1/* $OpenBSD: if_wpireg.h,v 1.28 2013/11/26 20:33:17 deraadt Exp $ */ 2 3/*- 4 * Copyright (c) 2006-2008 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#define WPI_TX_RING_COUNT 256 21#define WPI_TX_RING_LOMARK 192 22#define WPI_TX_RING_HIMARK 224 23#define WPI_RX_RING_COUNT_LOG 6 24#define WPI_RX_RING_COUNT (1 << WPI_RX_RING_COUNT_LOG) 25 26#define WPI_NTXQUEUES 8 27#define WPI_NDMACHNLS 6 28 29/* Maximum scatter/gather. */ 30#define WPI_MAX_SCATTER 4 31 32/* Maximum RX buffer size (larger than MCLBYTES.) */ 33#define WPI_RBUF_SIZE (3 * 1024) 34 35/* Base Address Register. */ 36#define WPI_PCI_BAR0 PCI_MAPREG_START 37 38/* 39 * Control and status registers. 40 */ 41#define WPI_HW_IF_CONFIG 0x000 42#define WPI_INT 0x008 43#define WPI_MASK 0x00c 44#define WPI_FH_INT 0x010 45#define WPI_GPIO_IN 0x018 46#define WPI_RESET 0x020 47#define WPI_GP_CNTRL 0x024 48#define WPI_EEPROM 0x02c 49#define WPI_EEPROM_GP 0x030 50#define WPI_UCODE_GP1_CLR 0x05c 51#define WPI_UCODE_GP2 0x060 52#define WPI_GIO_CHICKEN 0x100 53#define WPI_ANA_PLL 0x20c 54#define WPI_MEM_RADDR 0x40c 55#define WPI_MEM_WADDR 0x410 56#define WPI_MEM_WDATA 0x418 57#define WPI_MEM_RDATA 0x41c 58#define WPI_PRPH_WADDR 0x444 59#define WPI_PRPH_RADDR 0x448 60#define WPI_PRPH_WDATA 0x44c 61#define WPI_PRPH_RDATA 0x450 62#define WPI_HBUS_TARG_WRPTR 0x460 63#define WPI_FH_CBBC_CTRL(qid) (0x940 + (qid) * 8) 64#define WPI_FH_CBBC_BASE(qid) (0x944 + (qid) * 8) 65#define WPI_FH_RX_CONFIG 0xc00 66#define WPI_FH_RX_BASE 0xc04 67#define WPI_FH_RX_WPTR 0xc20 68#define WPI_FH_RX_RPTR_ADDR 0xc24 69#define WPI_FH_RSSR_TBL 0xcc0 70#define WPI_FH_RX_STATUS 0xcc4 71#define WPI_FH_TX_CONFIG(qid) (0xd00 + (qid) * 32) 72#define WPI_FH_TX_BASE 0xe80 73#define WPI_FH_MSG_CONFIG 0xe88 74#define WPI_FH_TX_STATUS 0xe90 75 76 77/* 78 * NIC internal memory offsets. 79 */ 80#define WPI_ALM_SCHED_MODE 0x2e00 81#define WPI_ALM_SCHED_ARASTAT 0x2e04 82#define WPI_ALM_SCHED_TXFACT 0x2e10 83#define WPI_ALM_SCHED_TXF4MF 0x2e14 84#define WPI_ALM_SCHED_TXF5MF 0x2e20 85#define WPI_ALM_SCHED_SBYPASS_MODE1 0x2e2c 86#define WPI_ALM_SCHED_SBYPASS_MODE2 0x2e30 87#define WPI_APMG_CLK_ENA 0x3004 88#define WPI_APMG_CLK_DIS 0x3008 89#define WPI_APMG_RFKILL 0x3014 90#define WPI_APMG_PS 0x300c 91#define WPI_APMG_PCI_STT 0x3010 92#define WPI_BSM_WR_CTRL 0x3400 93#define WPI_BSM_WR_MEM_SRC 0x3404 94#define WPI_BSM_WR_MEM_DST 0x3408 95#define WPI_BSM_WR_DWCOUNT 0x340c 96#define WPI_BSM_SRAM_BASE 0x3800 97#define WPI_BSM_DRAM_TEXT_ADDR 0x3490 98#define WPI_BSM_DRAM_TEXT_SIZE 0x3494 99#define WPI_BSM_DRAM_DATA_ADDR 0x3498 100#define WPI_BSM_DRAM_DATA_SIZE 0x349c 101 102 103/* Possible flags for register WPI_HW_IF_CONFIG. */ 104#define WPI_HW_IF_CONFIG_ALM_MB (1 << 8) 105#define WPI_HW_IF_CONFIG_ALM_MM (1 << 9) 106#define WPI_HW_IF_CONFIG_SKU_MRC (1 << 10) 107#define WPI_HW_IF_CONFIG_REV_D (1 << 11) 108#define WPI_HW_IF_CONFIG_TYPE_B (1 << 12) 109 110/* Possible flags for registers WPI_PRPH_RADDR/WPI_PRPH_WADDR. */ 111#define WPI_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 112 113/* Possible values for WPI_BSM_WR_MEM_DST. */ 114#define WPI_FW_TEXT_BASE 0x00000000 115#define WPI_FW_DATA_BASE 0x00800000 116 117/* Possible flags for WPI_GPIO_IN. */ 118#define WPI_GPIO_IN_VMAIN (1 << 9) 119 120/* Possible flags for register WPI_RESET. */ 121#define WPI_RESET_NEVO (1 << 0) 122#define WPI_RESET_SW (1 << 7) 123#define WPI_RESET_MASTER_DISABLED (1 << 8) 124#define WPI_RESET_STOP_MASTER (1 << 9) 125 126/* Possible flags for register WPI_GP_CNTRL. */ 127#define WPI_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 128#define WPI_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 129#define WPI_GP_CNTRL_INIT_DONE (1 << 2) 130#define WPI_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 131#define WPI_GP_CNTRL_SLEEP (1 << 4) 132#define WPI_GP_CNTRL_PS_MASK (7 << 24) 133#define WPI_GP_CNTRL_MAC_PS (4 << 24) 134#define WPI_GP_CNTRL_RFKILL (1 << 27) 135 136/* Possible flags for register WPI_GIO_CHICKEN. */ 137#define WPI_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 138 139/* Possible flags for register WPI_FH_RX_CONFIG. */ 140#define WPI_FH_RX_CONFIG_DMA_ENA (1U << 31) 141#define WPI_FH_RX_CONFIG_RDRBD_ENA (1U << 29) 142#define WPI_FH_RX_CONFIG_WRSTATUS_ENA (1U << 27) 143#define WPI_FH_RX_CONFIG_MAXFRAG (1U << 24) 144#define WPI_FH_RX_CONFIG_NRBD(x) ((x) << 20) 145#define WPI_FH_RX_CONFIG_IRQ_DST_HOST (1U << 12) 146#define WPI_FH_RX_CONFIG_IRQ_RBTH(x) ((x) << 4) 147 148/* Possible flags for register WPI_ANA_PLL. */ 149#define WPI_ANA_PLL_INIT (1 << 24) 150 151/* Possible flags for register WPI_UCODE_GP1_CLR. */ 152#define WPI_UCODE_GP1_RFKILL (1 << 1) 153#define WPI_UCODE_GP1_CMD_BLOCKED (1 << 2) 154 155/* Possible flags for WPI_FH_RX_STATUS. */ 156#define WPI_FH_RX_STATUS_IDLE (1 << 24) 157 158/* Possible flags for register WPI_BSM_WR_CTRL. */ 159#define WPI_BSM_WR_CTRL_START_EN (1U << 30) 160#define WPI_BSM_WR_CTRL_START (1U << 31) 161 162/* Possible flags for register WPI_INT. */ 163#define WPI_INT_ALIVE (1U << 0) 164#define WPI_INT_WAKEUP (1U << 1) 165#define WPI_INT_SW_RX (1U << 3) 166#define WPI_INT_RF_TOGGLED (1U << 7) 167#define WPI_INT_SW_ERR (1U << 25) 168#define WPI_INT_FH_TX (1U << 27) 169#define WPI_INT_HW_ERR (1U << 29) 170#define WPI_INT_FH_RX (1U << 31) 171 172/* Shortcut. */ 173#define WPI_INT_MASK \ 174 (WPI_INT_SW_ERR | WPI_INT_HW_ERR | WPI_INT_FH_TX | \ 175 WPI_INT_FH_RX | WPI_INT_ALIVE | WPI_INT_WAKEUP | \ 176 WPI_INT_SW_RX | WPI_INT_RF_TOGGLED) 177 178/* Possible flags for register WPI_FH_INT. */ 179#define WPI_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 180#define WPI_FH_INT_HI_PRIOR (1 << 30) 181/* Shortcuts for the above. */ 182#define WPI_FH_INT_RX \ 183 (WPI_FH_INT_RX_CHNL(0) | \ 184 WPI_FH_INT_RX_CHNL(1) | \ 185 WPI_FH_INT_RX_CHNL(2) | \ 186 WPI_FH_INT_HI_PRIOR) 187 188/* Possible flags for register WPI_FH_TX_STATUS. */ 189#define WPI_FH_TX_STATUS_IDLE(qid) \ 190 (1 << ((qid) + 24) | 1 << ((qid) + 16)) 191 192/* Possible flags for register WPI_EEPROM. */ 193#define WPI_EEPROM_READ_VALID (1 << 0) 194#define WPI_EEPROM_CMD (1 << 1) 195 196/* Possible flags for register WPI_EEPROM_GP. */ 197#define WPI_EEPROM_GP_IF_OWNER 0x00000180 198 199/* Possible flags for register WPI_APMG_PS. */ 200#define WPI_APMG_PS_PWR_SRC_MASK (3 << 24) 201 202/* Possible flags for register WPI_APMG_CLK_ENA/WPI_APMG_CLK_DIS. */ 203#define WPI_APMG_CLK_DMA_CLK_RQT (1 << 9) 204#define WPI_APMG_CLK_BSM_CLK_RQT (1 << 11) 205 206/* Possible flags for register WPI_APMG_PCI_STT. */ 207#define WPI_APMG_PCI_STT_L1A_DIS (1 << 11) 208 209struct wpi_shared { 210 uint32_t txbase[8]; 211 uint32_t next; 212 uint32_t reserved[2]; 213} __packed; 214 215#define WPI_MAX_SEG_LEN 65520 216struct wpi_tx_desc { 217 uint32_t flags; 218#define WPI_PAD32(x) ((((x) + 3) & ~3) - (x)) 219 220 struct { 221 uint32_t addr; 222 uint32_t len; 223 } __packed segs[WPI_MAX_SCATTER]; 224 uint8_t reserved[28]; 225} __packed; 226 227struct wpi_tx_stat { 228 uint8_t nrts; 229 uint8_t retrycnt; 230 uint8_t nkill; 231 uint8_t rate; 232 uint32_t duration; 233 uint32_t status; 234} __packed; 235 236struct wpi_rx_desc { 237 uint32_t len; 238 uint8_t type; 239#define WPI_UC_READY 1 240#define WPI_ADD_NODE_DONE 24 241#define WPI_RX_DONE 27 242#define WPI_TX_DONE 28 243#define WPI_START_SCAN 130 244#define WPI_STOP_SCAN 132 245#define WPI_STATE_CHANGED 161 246 247 uint8_t flags; 248 uint8_t idx; 249 uint8_t qid; 250} __packed; 251 252struct wpi_tx_cmd { 253 uint8_t code; 254#define WPI_CMD_RXON 16 255#define WPI_CMD_ASSOCIATE 17 256#define WPI_CMD_EDCA_PARAMS 19 257#define WPI_CMD_TIMING 20 258#define WPI_CMD_ADD_NODE 24 259#define WPI_CMD_TX_DATA 28 260#define WPI_CMD_MRR_SETUP 71 261#define WPI_CMD_SET_LED 72 262#define WPI_CMD_SET_POWER_MODE 119 263#define WPI_CMD_SCAN 128 264#define WPI_CMD_TXPOWER 151 265#define WPI_CMD_BT_COEX 155 266 267 uint8_t flags; 268 uint8_t idx; 269 uint8_t qid; 270 uint8_t data[124]; 271} __packed; 272 273/* Structure for command WPI_CMD_RXON. */ 274struct wpi_rxon { 275 uint8_t myaddr[IEEE80211_ADDR_LEN]; 276 uint16_t reserved1; 277 uint8_t bssid[IEEE80211_ADDR_LEN]; 278 uint16_t reserved2; 279 uint32_t reserved3[2]; 280 uint8_t mode; 281#define WPI_MODE_HOSTAP 1 282#define WPI_MODE_STA 3 283#define WPI_MODE_IBSS 4 284#define WPI_MODE_MONITOR 6 285 286 uint8_t reserved4[3]; 287 uint8_t ofdm_mask; 288 uint8_t cck_mask; 289 uint16_t associd; 290 uint32_t flags; 291#define WPI_RXON_24GHZ (1 << 0) 292#define WPI_RXON_CCK (1 << 1) 293#define WPI_RXON_AUTO (1 << 2) 294#define WPI_RXON_SHSLOT (1 << 4) 295#define WPI_RXON_SHPREAMBLE (1 << 5) 296#define WPI_RXON_NODIVERSITY (1 << 7) 297#define WPI_RXON_ANT_A (1 << 8) 298#define WPI_RXON_ANT_B (1 << 9) 299#define WPI_RXON_TSF (1 << 15) 300 301 uint32_t filter; 302#define WPI_FILTER_PROMISC (1 << 0) 303#define WPI_FILTER_CTL (1 << 1) 304#define WPI_FILTER_MULTICAST (1 << 2) 305#define WPI_FILTER_NODECRYPT (1 << 3) 306#define WPI_FILTER_BSS (1 << 5) 307 308 uint8_t chan; 309 uint8_t reserved6[3]; 310} __packed; 311 312/* Structure for command WPI_CMD_ASSOCIATE. */ 313struct wpi_assoc { 314 uint32_t flags; 315 uint32_t filter; 316 uint8_t ofdm_mask; 317 uint8_t cck_mask; 318 uint16_t reserved; 319} __packed; 320 321/* Structure for command WPI_CMD_EDCA_PARAMS. */ 322struct wpi_edca_params { 323 uint32_t flags; 324#define WPI_EDCA_UPDATE (1 << 0) 325#define WPI_EDCA_TXOP (1 << 4) 326 327 struct { 328 uint16_t cwmin; 329 uint16_t cwmax; 330 uint8_t aifsn; 331 uint8_t reserved; 332 uint16_t txoplimit; 333 } __packed ac[EDCA_NUM_AC]; 334} __packed; 335 336/* Structure for command WPI_CMD_TIMING. */ 337struct wpi_cmd_timing { 338 uint64_t tstamp; 339 uint16_t bintval; 340 uint16_t atim; 341 uint32_t binitval; 342 uint16_t lintval; 343 uint16_t reserved; 344} __packed; 345 346/* Structure for command WPI_CMD_ADD_NODE. */ 347struct wpi_node_info { 348 uint8_t control; 349#define WPI_NODE_UPDATE (1 << 0) 350 351 uint8_t reserved1[3]; 352 uint8_t macaddr[IEEE80211_ADDR_LEN]; 353 uint16_t reserved2; 354 uint8_t id; 355#define WPI_ID_BSS 0 356#define WPI_ID_BROADCAST 24 357 358 uint8_t flags; 359#define WPI_FLAG_SET_KEY (1 << 0) 360 361 uint16_t reserved3; 362 uint16_t kflags; 363#define WPI_KFLAG_CCMP (1 << 1) 364#define WPI_KFLAG_KID(kid) ((kid) << 8) 365 366 uint8_t tsc2; 367 uint8_t reserved4; 368 uint16_t ttak[5]; 369 uint16_t reserved5; 370 uint8_t key[16]; 371 372 uint32_t action; 373#define WPI_ACTION_SET_RATE (1 << 2) 374 375 uint32_t mask; 376 uint16_t tid; 377 uint8_t plcp; 378 uint8_t antenna; 379#define WPI_ANTENNA_A (1 << 6) 380#define WPI_ANTENNA_B (1 << 7) 381#define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B) 382 383 uint8_t add_imm; 384 uint8_t del_imm; 385 uint16_t add_imm_start; 386} __packed; 387 388/* Structure for command WPI_CMD_TX_DATA. */ 389struct wpi_cmd_data { 390 uint16_t len; 391 uint16_t lnext; 392 uint32_t flags; 393#define WPI_TX_NEED_RTS (1 << 1) 394#define WPI_TX_NEED_CTS (1 << 2) 395#define WPI_TX_NEED_ACK (1 << 3) 396#define WPI_TX_FULL_TXOP (1 << 7) 397#define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 398#define WPI_TX_AUTO_SEQ (1 << 13) 399#define WPI_TX_INSERT_TSTAMP (1 << 16) 400 401 uint8_t plcp; 402 uint8_t id; 403 uint8_t tid; 404 uint8_t security; 405#define WPI_CIPHER_WEP40 1 406#define WPI_CIPHER_CCMP 2 407#define WPI_CIPHER_TKIP 3 408#define WPI_CIPHER_WEP104 9 409 410 uint8_t key[IEEE80211_KEYBUF_SIZE]; 411 uint8_t tkip[IEEE80211_TKIP_MICLEN]; 412 uint32_t fnext; 413 uint32_t lifetime; 414#define WPI_LIFETIME_INFINITE 0xffffffff 415 416 uint8_t ofdm_mask; 417 uint8_t cck_mask; 418 uint8_t rts_ntries; 419 uint8_t data_ntries; 420 uint16_t timeout; 421 uint16_t txop; 422} __packed; 423 424/* Structure for command WPI_CMD_MRR_SETUP. */ 425#define WPI_RIDX_MAX 11 426struct wpi_mrr_setup { 427 uint32_t which; 428#define WPI_MRR_CTL 0 429#define WPI_MRR_DATA 1 430 431 struct { 432 uint8_t plcp; 433 uint8_t flags; 434 uint8_t ntries; 435 uint8_t next; 436 } __packed rates[WPI_RIDX_MAX + 1]; 437} __packed; 438 439/* Structure for command WPI_CMD_SET_LED. */ 440struct wpi_cmd_led { 441 uint32_t unit; /* multiplier (in usecs) */ 442 uint8_t which; 443#define WPI_LED_ACTIVITY 1 444#define WPI_LED_LINK 2 445 446 uint8_t off; 447 uint8_t on; 448 uint8_t reserved; 449} __packed; 450 451/* Structure for command WPI_CMD_SET_POWER_MODE. */ 452struct wpi_pmgt_cmd { 453 uint32_t flags; 454#define WPI_PS_ALLOW_SLEEP (1 << 0) 455#define WPI_PS_SLEEP_OVER_DTIM (1 << 2) 456#define WPI_PS_PCI_PMGT (1 << 3) 457 458 uint32_t rxtimeout; 459 uint32_t txtimeout; 460 uint32_t intval[5]; 461} __packed; 462 463/* Structures for command WPI_CMD_SCAN. */ 464struct wpi_scan_essid { 465 uint8_t id; 466 uint8_t len; 467 uint8_t data[IEEE80211_NWID_LEN]; 468} __packed; 469 470struct wpi_scan_hdr { 471 uint16_t len; 472 uint8_t reserved1; 473 uint8_t nchan; 474 uint16_t quiet_time; 475 uint16_t quiet_threshold; 476 uint16_t crc_threshold; 477 uint16_t reserved2; 478 uint32_t max_svc; /* background scans */ 479 uint32_t pause_svc; /* background scans */ 480 uint32_t flags; 481 uint32_t filter; 482 483 /* Followed by a struct wpi_cmd_data. */ 484 /* Followed by an array of 4 structq wpi_scan_essid. */ 485 /* Followed by probe request body. */ 486 /* Followed by an array of ``nchan'' structs wpi_scan_chan. */ 487} __packed; 488 489struct wpi_scan_chan { 490 uint8_t flags; 491#define WPI_CHAN_ACTIVE (1 << 0) 492#define WPI_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 493 494 uint8_t chan; 495 uint8_t rf_gain; 496 uint8_t dsp_gain; 497 uint16_t active; /* msecs */ 498 uint16_t passive; /* msecs */ 499} __packed; 500 501/* Maximum size of a scan command. */ 502#define WPI_SCAN_MAXSZ (MCLBYTES - 4) 503 504/* Structure for command WPI_CMD_TXPOWER. */ 505struct wpi_cmd_txpower { 506 uint8_t band; 507#define WPI_BAND_5GHZ 0 508#define WPI_BAND_2GHZ 1 509 510 uint8_t reserved; 511 uint16_t chan; 512 struct { 513 uint8_t plcp; 514 uint8_t rf_gain; 515 uint8_t dsp_gain; 516 uint8_t reserved; 517 } __packed rates[WPI_RIDX_MAX + 1]; 518} __packed; 519 520/* Structure for command WPI_CMD_BT_COEX. */ 521struct wpi_bluetooth { 522 uint8_t flags; 523#define WPI_BT_COEX_DISABLE 0 524#define WPI_BT_COEX_MODE_2WIRE 1 525#define WPI_BT_COEX_MODE_3WIRE 2 526#define WPI_BT_COEX_MODE_4WIRE 3 527 528 uint8_t lead_time; 529#define WPI_BT_LEAD_TIME_DEF 30 530 531 uint8_t max_kill; 532#define WPI_BT_MAX_KILL_DEF 5 533 534 uint8_t reserved; 535 uint32_t kill_ack; 536 uint32_t kill_cts; 537} __packed; 538 539/* Structures for WPI_RX_DONE notification. */ 540struct wpi_rx_stat { 541 uint8_t len; 542#define WPI_STAT_MAXLEN 20 543 544 uint8_t id; 545 uint8_t rssi; /* received signal strength */ 546#define WPI_RSSI_OFFSET 95 547 548 uint8_t agc; /* access gain control */ 549 uint16_t signal; 550 uint16_t noise; 551} __packed; 552 553struct wpi_rx_head { 554 uint16_t chan; 555 uint16_t flags; 556 uint8_t reserved; 557 uint8_t rate; 558 uint16_t len; 559} __packed; 560 561struct wpi_rx_tail { 562 uint32_t flags; 563#define WPI_RX_NO_CRC_ERR (1 << 0) 564#define WPI_RX_NO_OVFL_ERR (1 << 1) 565/* Shortcut for the above. */ 566#define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 567#define WPI_RX_CIPHER_MASK (7 << 8) 568#define WPI_RX_CIPHER_CCMP (2 << 8) 569#define WPI_RX_DECRYPT_MASK (3 << 11) 570#define WPI_RX_DECRYPT_OK (3 << 11) 571 572 uint64_t tstamp; 573 uint32_t tbeacon; 574} __packed; 575 576/* Structure for WPI_UC_READY notification. */ 577struct wpi_ucode_info { 578 uint32_t version; 579 uint8_t revision[8]; 580 uint8_t type; 581 uint8_t subtype; 582#define WPI_UCODE_INIT 9 583 584 uint16_t reserved; 585 uint32_t logptr; 586 uint32_t errptr; 587 uint32_t timestamp; 588 uint32_t valid; 589} __packed; 590 591/* Structure for WPI_START_SCAN notification. */ 592struct wpi_start_scan { 593 uint64_t tstamp; 594 uint32_t tbeacon; 595 uint8_t chan; 596 uint8_t band; 597 uint16_t reserved; 598 uint32_t status; 599} __packed; 600 601/* Structure for WPI_STOP_SCAN notification. */ 602struct wpi_stop_scan { 603 uint8_t nchan; 604 uint8_t status; 605 uint8_t reserved; 606 uint8_t chan; 607 uint64_t tsf; 608} __packed; 609 610 611/* Firmware error dump entry. */ 612struct wpi_fwdump { 613 uint32_t desc; 614 uint32_t time; 615 uint32_t blink[2]; 616 uint32_t ilink[2]; 617 uint32_t data; 618} __packed; 619 620/* Firmware image file header. */ 621struct wpi_firmware_hdr { 622 uint32_t version; 623 uint32_t main_textsz; 624 uint32_t main_datasz; 625 uint32_t init_textsz; 626 uint32_t init_datasz; 627 uint32_t boot_textsz; 628} __packed; 629 630#define WPI_FW_TEXT_MAXSZ (80 * 1024) 631#define WPI_FW_DATA_MAXSZ (32 * 1024) 632#define WPI_FW_BOOT_TEXT_MAXSZ 1024 633 634#define WPI_FW_UPDATED (1U << 31) 635 636/* 637 * Offsets into EEPROM. 638 */ 639#define WPI_EEPROM_MAC 0x015 640#define WPI_EEPROM_REVISION 0x035 641#define WPI_EEPROM_CAPABILITIES 0x045 642#define WPI_EEPROM_TYPE 0x04a 643#define WPI_EEPROM_DOMAIN 0x060 644#define WPI_EEPROM_BAND1 0x063 645#define WPI_EEPROM_BAND2 0x072 646#define WPI_EEPROM_BAND3 0x080 647#define WPI_EEPROM_BAND4 0x08d 648#define WPI_EEPROM_BAND5 0x099 649#define WPI_EEPROM_POWER_GRP 0x100 650 651struct wpi_eeprom_chan { 652 uint8_t flags; 653#define WPI_EEPROM_CHAN_VALID (1 << 0) 654#define WPI_EEPROM_CHAN_IBSS (1 << 1) 655#define WPI_EEPROM_CHAN_ACTIVE (1 << 3) 656#define WPI_EEPROM_CHAN_RADAR (1 << 4) 657 658 int8_t maxpwr; 659} __packed; 660 661struct wpi_eeprom_sample { 662 uint8_t index; 663 int8_t power; 664 uint16_t volt; 665} __packed; 666 667#define WPI_POWER_GROUPS_COUNT 5 668struct wpi_eeprom_group { 669 struct wpi_eeprom_sample samples[5]; 670 int32_t coef[5]; 671 int32_t corr[5]; 672 int8_t maxpwr; 673 uint8_t chan; 674 int16_t temp; 675} __packed; 676 677#define WPI_CHAN_BANDS_COUNT 5 678#define WPI_MAX_CHAN_PER_BAND 14 679static const struct wpi_chan_band { 680 uint32_t addr; /* offset in EEPROM */ 681 uint8_t nchan; 682 uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 683} wpi_bands[5] = { 684 { WPI_EEPROM_BAND1, 14, 685 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 686 { WPI_EEPROM_BAND2, 13, 687 { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 688 { WPI_EEPROM_BAND3, 12, 689 { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 690 { WPI_EEPROM_BAND4, 11, 691 { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 692 { WPI_EEPROM_BAND5, 6, 693 { 145, 149, 153, 157, 161, 165 } } 694}; 695 696/* HW rate indices. */ 697#define WPI_RIDX_OFDM6 0 698#define WPI_RIDX_OFDM36 5 699#define WPI_RIDX_OFDM48 6 700#define WPI_RIDX_OFDM54 7 701#define WPI_RIDX_CCK1 8 702#define WPI_RIDX_CCK2 9 703#define WPI_RIDX_CCK11 11 704 705static const struct wpi_rate { 706 uint8_t rate; 707 uint8_t plcp; 708} wpi_rates[WPI_RIDX_MAX + 1] = { 709 { 12, 0xd }, 710 { 18, 0xf }, 711 { 24, 0x5 }, 712 { 36, 0x7 }, 713 { 48, 0x9 }, 714 { 72, 0xb }, 715 { 96, 0x1 }, 716 { 108, 0x3 }, 717 { 2, 10 }, 718 { 4, 20 }, 719 { 11, 55 }, 720 { 22, 110 } 721}; 722 723#define WPI_MAX_PWR_INDEX 77 724/* 725 * RF Tx gain values from highest to lowest power (values obtained from 726 * the reference driver.) 727 */ 728static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 729 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 730 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 731 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 732 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 733 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 734 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 735 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 736 0x03 737}; 738 739static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 740 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 741 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 742 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 743 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 744 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 745 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 746 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 747 0x03 748}; 749 750/* 751 * DSP pre-DAC gain values from highest to lowest power (values obtained 752 * from the reference driver.) 753 */ 754static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 755 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 756 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 757 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 758 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 759 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 760 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 761 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 762 0x5f 763}; 764 765static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 766 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 767 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 768 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 769 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 770 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 771 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 772 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 773 0x78 774}; 775 776/* 777 * Power saving settings (values obtained from the reference driver.) 778 */ 779#define WPI_NDTIMRANGES 2 780#define WPI_NPOWERLEVELS 6 781static const struct wpi_pmgt { 782 uint32_t rxtimeout; 783 uint32_t txtimeout; 784 uint32_t intval[5]; 785 int skip_dtim; 786} wpi_pmgt[WPI_NDTIMRANGES][WPI_NPOWERLEVELS] = { 787 /* DTIM <= 10 */ 788 { 789 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 790 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 791 { 200, 300, { 2, 4, 6, 7, 7 }, 0 }, /* PS level 2 */ 792 { 50, 100, { 2, 6, 9, 9, 10 }, 0 }, /* PS level 3 */ 793 { 50, 25, { 2, 7, 9, 9, 10 }, 1 }, /* PS level 4 */ 794 { 25, 25, { 4, 7, 10, 10, 10 }, 1 } /* PS level 5 */ 795 }, 796 /* DTIM >= 11 */ 797 { 798 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 799 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 800 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 801 { 50, 100, { 2, 6, 9, 9, -1 }, 0 }, /* PS level 3 */ 802 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 803 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 804 } 805}; 806 807/* Firmware errors. */ 808static const char * const wpi_fw_errmsg[] = { 809 "OK", 810 "FAIL", 811 "BAD_PARAM", 812 "BAD_CHECKSUM", 813 "NMI_INTERRUPT", 814 "SYSASSERT", 815 "FATAL_ERROR" 816}; 817 818#define WPI_READ(sc, reg) \ 819 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 820 821#define WPI_WRITE(sc, reg, val) \ 822 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 823 824#define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 825 bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 826 (datap), (count)) 827 828#define WPI_SETBITS(sc, reg, mask) \ 829 WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask)) 830 831#define WPI_CLRBITS(sc, reg, mask) \ 832 WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask)) 833 834#define WPI_BARRIER_WRITE(sc) \ 835 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 836 BUS_SPACE_BARRIER_WRITE) 837 838#define WPI_BARRIER_READ_WRITE(sc) \ 839 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 840 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 841