if_wbreg.h revision 1.3
1/* $OpenBSD: if_wbreg.h,v 1.3 1999/09/27 18:17:01 jason Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_wbreg.h,v 1.4 1999/07/11 00:56:07 wpaul Exp $ 35 */ 36 37/* 38 * Winbond register definitions. 39 */ 40 41#define WB_BUSCTL 0x00 /* bus control */ 42#define WB_TXSTART 0x04 /* tx start demand */ 43#define WB_RXSTART 0x08 /* rx start demand */ 44#define WB_RXADDR 0x0C /* rx descriptor list start addr */ 45#define WB_TXADDR 0x10 /* tx descriptor list start addr */ 46#define WB_ISR 0x14 /* interrupt status register */ 47#define WB_NETCFG 0x18 /* network config register */ 48#define WB_IMR 0x1C /* interrupt mask */ 49#define WB_FRAMESDISCARDED 0x20 /* # of discarded frames */ 50#define WB_SIO 0x24 /* MII and ROM/EEPROM access */ 51#define WB_BOOTROMADDR 0x28 52#define WB_TIMER 0x2C /* general timer */ 53#define WB_CURRXCTL 0x30 /* current RX descriptor */ 54#define WB_CURRXBUF 0x34 /* current RX buffer */ 55#define WB_MAR0 0x38 /* multicast filter 0 */ 56#define WB_MAR1 0x3C /* multicast filter 1 */ 57#define WB_NODE0 0x40 /* station address 0 */ 58#define WB_NODE1 0x44 /* station address 1 */ 59#define WB_BOOTROMSIZE 0x48 /* boot ROM size */ 60#define WB_CURTXCTL 0x4C /* current TX descriptor */ 61#define WB_CURTXBUF 0x50 /* current TX buffer */ 62 63/* 64 * Bus control bits. 65 */ 66#define WB_BUSCTL_RESET 0x00000001 67#define WB_BUSCTL_ARBITRATION 0x00000002 68#define WB_BUSCTL_SKIPLEN 0x0000007C 69#define WB_BUSCTL_BUF_BIGENDIAN 0x00000080 70#define WB_BUSCTL_BURSTLEN 0x00003F00 71#define WB_BUSCTL_CACHEALIGN 0x0000C000 72#define WB_BUSCTL_DES_BIGENDIAN 0x00100000 73#define WB_BUSCTL_WAIT 0x00200000 74 75#define WB_SKIPLEN_1LONG 0x00000004 76#define WB_SKIPLEN_2LONG 0x00000008 77#define WB_SKIPLEN_3LONG 0x00000010 78#define WB_SKIPLEN_4LONG 0x00000020 79#define WB_SKIPLEN_5LONG 0x00000040 80 81#define WB_CACHEALIGN_8LONG 0x00004000 82#define WB_CACHEALIGN_16LONG 0x00008000 83#define WB_CACHEALIGN_32LONG 0x0000C000 84 85#define WB_BURSTLEN_USECA 0x00000000 86#define WB_BURSTLEN_1LONG 0x00000100 87#define WB_BURSTLEN_2LONG 0x00000200 88#define WB_BURSTLEN_4LONG 0x00000400 89#define WB_BURSTLEN_8LONG 0x00000800 90#define WB_BURSTLEN_16LONG 0x00001000 91#define WB_BURSTLEN_32LONG 0x00002000 92 93#define WB_BUSCTL_CONFIG (WB_CACHEALIGN_8LONG|WB_SKIPLEN_3LONG| \ 94 WB_BURSTLEN_8LONG) 95 96/* 97 * Interrupt status bits. 98 */ 99#define WB_ISR_TX_OK 0x00000001 100#define WB_ISR_TX_IDLE 0x00000002 101#define WB_ISR_TX_NOBUF 0x00000004 102#define WB_ISR_RX_EARLY 0x00000008 103#define WB_ISR_RX_ERR 0x00000010 104#define WB_ISR_TX_UNDERRUN 0x00000020 105#define WB_ISR_RX_OK 0x00000040 106#define WB_ISR_RX_NOBUF 0x00000080 107#define WB_ISR_RX_IDLE 0x00000100 108#define WB_ISR_TX_EARLY 0x00000400 109#define WB_ISR_TIMER_EXPIRED 0x00000800 110#define WB_ISR_BUS_ERR 0x00002000 111#define WB_ISR_ABNORMAL 0x00008000 112#define WB_ISR_NORMAL 0x00010000 113#define WB_ISR_RX_STATE 0x000E0000 114#define WB_ISR_TX_STATE 0x00700000 115#define WB_ISR_BUSERRTYPE 0x03800000 116 117/* 118 * The RX_STATE and TX_STATE fields are not described anywhere in the 119 * Winbond datasheet, however it appears that the Winbond chip is an 120 * attempt at a DEC 'tulip' clone, hence the ISR register is identical 121 * to that of the tulip chip and we can steal the bit definitions from 122 * the tulip documentation. 123 */ 124#define WB_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ 125#define WB_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ 126#define WB_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ 127#define WB_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ 128#define WB_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ 129#define WB_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ 130#define WB_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ 131#define WB_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ 132 133#define WB_TXSTATE_RESET 0x00000000 /* 000 - reset */ 134#define WB_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ 135#define WB_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ 136#define WB_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ 137#define WB_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ 138#define WB_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ 139#define WB_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ 140#define WB_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ 141 142/* 143 * Network config bits. 144 */ 145#define WB_NETCFG_RX_ON 0x00000002 146#define WB_NETCFG_RX_ALLPHYS 0x00000008 147#define WB_NETCFG_RX_MULTI 0x00000010 148#define WB_NETCFG_RX_BROAD 0x00000020 149#define WB_NETCFG_RX_RUNT 0x00000040 150#define WB_NETCFG_RX_ERR 0x00000080 151#define WB_NETCFG_FULLDUPLEX 0x00000200 152#define WB_NETCFG_LOOPBACK 0x00000C00 153#define WB_NETCFG_TX_ON 0x00002000 154#define WB_NETCFG_TX_THRESH 0x001FC000 155#define WB_NETCFG_RX_EARLYTHRSH 0x1FE00000 156#define WB_NETCFG_100MBPS 0x20000000 157#define WB_NETCFG_TX_EARLY_ON 0x40000000 158#define WB_NETCFG_RX_EARLY_ON 0x80000000 159 160/* 161 * The tx threshold can be adjusted in increments of 32 bytes. 162 */ 163#define WB_TXTHRESH(x) ((x >> 5) << 14) 164#define WB_TXTHRESH_CHUNK 32 165#define WB_TXTHRESH_INIT 0 /*72*/ 166 167/* 168 * Interrupt mask bits. 169 */ 170#define WB_IMR_TX_OK 0x00000001 171#define WB_IMR_TX_IDLE 0x00000002 172#define WB_IMR_TX_NOBUF 0x00000004 173#define WB_IMR_RX_EARLY 0x00000008 174#define WB_IMR_RX_ERR 0x00000010 175#define WB_IMR_TX_UNDERRUN 0x00000020 176#define WB_IMR_RX_OK 0x00000040 177#define WB_IMR_RX_NOBUF 0x00000080 178#define WB_IMR_RX_IDLE 0x00000100 179#define WB_IMR_TX_EARLY 0x00000400 180#define WB_IMR_TIMER_EXPIRED 0x00000800 181#define WB_IMR_BUS_ERR 0x00002000 182#define WB_IMR_ABNORMAL 0x00008000 183#define WB_IMR_NORMAL 0x00010000 184 185#define WB_INTRS \ 186 (WB_IMR_RX_OK|WB_IMR_TX_OK|WB_IMR_RX_NOBUF|WB_IMR_RX_ERR| \ 187 WB_IMR_TX_NOBUF|WB_IMR_TX_UNDERRUN|WB_IMR_BUS_ERR| \ 188 WB_IMR_ABNORMAL|WB_IMR_NORMAL|WB_IMR_TX_EARLY) 189/* 190 * Serial I/O (EEPROM/ROM) bits. 191 */ 192#define WB_SIO_EE_CS 0x00000001 /* EEPROM chip select */ 193#define WB_SIO_EE_CLK 0x00000002 /* EEPROM clock */ 194#define WB_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ 195#define WB_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ 196#define WB_SIO_ROMDATA4 0x00000010 197#define WB_SIO_ROMDATA5 0x00000020 198#define WB_SIO_ROMDATA6 0x00000040 199#define WB_SIO_ROMDATA7 0x00000080 200#define WB_SIO_ROMCTL_WRITE 0x00000200 201#define WB_SIO_ROMCTL_READ 0x00000400 202#define WB_SIO_EESEL 0x00000800 203#define WB_SIO_MII_CLK 0x00010000 /* MDIO clock */ 204#define WB_SIO_MII_DATAIN 0x00020000 /* MDIO data out */ 205#define WB_SIO_MII_DIR 0x00040000 /* MDIO dir */ 206#define WB_SIO_MII_DATAOUT 0x00080000 /* MDIO data in */ 207 208#define WB_EECMD_WRITE 0x140 209#define WB_EECMD_READ 0x180 210#define WB_EECMD_ERASE 0x1c0 211 212/* 213 * Winbond TX/RX descriptor structure. 214 */ 215 216struct wb_desc { 217 u_int32_t wb_status; 218 u_int32_t wb_ctl; 219 u_int32_t wb_ptr1; 220 u_int32_t wb_ptr2; 221}; 222 223#define wb_data wb_ptr1 224#define wb_next wb_ptr2 225 226#define WB_RXSTAT_CRCERR 0x00000002 227#define WB_RXSTAT_DRIBBLE 0x00000004 228#define WB_RXSTAT_MIIERR 0x00000008 229#define WB_RXSTAT_LATEEVENT 0x00000040 230#define WB_RXSTAT_GIANT 0x00000080 231#define WB_RXSTAT_LASTFRAG 0x00000100 232#define WB_RXSTAT_FIRSTFRAG 0x00000200 233#define WB_RXSTAT_MULTICAST 0x00000400 234#define WB_RXSTAT_RUNT 0x00000800 235#define WB_RXSTAT_RXTYPE 0x00003000 236#define WB_RXSTAT_RXERR 0x00008000 237#define WB_RXSTAT_RXLEN 0x3FFF0000 238#define WB_RXSTAT_RXCMP 0x40000000 239#define WB_RXSTAT_OWN 0x80000000 240 241#define WB_RXBYTES(x) ((x & WB_RXSTAT_RXLEN) >> 16) 242#define WB_RXSTAT (WB_RXSTAT_FIRSTFRAG|WB_RXSTAT_LASTFRAG|WB_RXSTAT_OWN) 243 244#define WB_RXCTL_BUFLEN1 0x00000FFF 245#define WB_RXCTL_BUFLEN2 0x00FFF000 246#define WB_RXCTL_RLINK 0x01000000 247#define WB_RXCTL_RLAST 0x02000000 248 249#define WB_TXSTAT_DEFER 0x00000001 250#define WB_TXSTAT_UNDERRUN 0x00000002 251#define WB_TXSTAT_COLLCNT 0x00000078 252#define WB_TXSTAT_SQE 0x00000080 253#define WB_TXSTAT_ABORT 0x00000100 254#define WB_TXSTAT_LATECOLL 0x00000200 255#define WB_TXSTAT_NOCARRIER 0x00000400 256#define WB_TXSTAT_CARRLOST 0x00000800 257#define WB_TXSTAT_TXERR 0x00001000 258#define WB_TXSTAT_OWN 0x80000000 259 260#define WB_TXCTL_BUFLEN1 0x000007FF 261#define WB_TXCTL_BUFLEN2 0x003FF800 262#define WB_TXCTL_PAD 0x00800000 263#define WB_TXCTL_TLINK 0x01000000 264#define WB_TXCTL_TLAST 0x02000000 265#define WB_TXCTL_NOCRC 0x08000000 266#define WB_TXCTL_FIRSTFRAG 0x20000000 267#define WB_TXCTL_LASTFRAG 0x40000000 268#define WB_TXCTL_FINT 0x80000000 269 270#define WB_MAXFRAGS 16 271#define WB_RX_LIST_CNT 64 272#define WB_TX_LIST_CNT 64 273#define WB_MIN_FRAMELEN 60 274 275/* 276 * A transmit 'super descriptor' is actually WB_MAXFRAGS regular 277 * descriptors clumped together. The idea here is to emulate the 278 * multi-fragment descriptor layout found in devices such as the 279 * Texas Instruments ThunderLAN and 3Com boomerang and cylone chips. 280 * The advantage to using this scheme is that it avoids buffer copies. 281 * The disadvantage is that there's a certain amount of overhead due 282 * to the fact that each 'fragment' is 16 bytes long. In my tests, 283 * this limits top speed to about 10.5MB/sec. It should be more like 284 * 11.5MB/sec. However, the upshot is that you can achieve better 285 * results on slower machines: a Pentium 200 can pump out packets at 286 * same speed as a PII 400. 287 */ 288struct wb_txdesc { 289 struct wb_desc wb_frag[WB_MAXFRAGS]; 290}; 291 292#define WB_TXNEXT(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_next 293#define WB_TXSTATUS(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_status 294#define WB_TXCTL(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_ctl 295#define WB_TXDATA(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_data 296 297#define WB_TXOWN(x) x->wb_ptr->wb_frag[0].wb_status 298 299#define WB_UNSENT 0x1234 300 301struct wb_list_data { 302 struct wb_desc wb_rx_list[WB_RX_LIST_CNT]; 303 struct wb_txdesc wb_tx_list[WB_TX_LIST_CNT]; 304}; 305 306struct wb_chain { 307 struct wb_txdesc *wb_ptr; 308 struct mbuf *wb_mbuf; 309 struct wb_chain *wb_nextdesc; 310 u_int8_t wb_lastdesc; 311}; 312 313struct wb_chain_onefrag { 314 struct wb_desc *wb_ptr; 315 struct mbuf *wb_mbuf; 316 struct wb_chain_onefrag *wb_nextdesc; 317 u_int8_t wb_rlast; 318}; 319 320struct wb_chain_data { 321 u_int8_t wb_pad[WB_MIN_FRAMELEN]; 322 struct wb_chain_onefrag wb_rx_chain[WB_RX_LIST_CNT]; 323 struct wb_chain wb_tx_chain[WB_TX_LIST_CNT]; 324 325 struct wb_chain_onefrag *wb_rx_head; 326 327 struct wb_chain *wb_tx_head; 328 struct wb_chain *wb_tx_tail; 329 struct wb_chain *wb_tx_free; 330}; 331 332struct wb_type { 333 u_int16_t wb_vid; 334 u_int16_t wb_did; 335 char *wb_name; 336}; 337 338struct wb_mii_frame { 339 u_int8_t mii_stdelim; 340 u_int8_t mii_opcode; 341 u_int8_t mii_phyaddr; 342 u_int8_t mii_regaddr; 343 u_int8_t mii_turnaround; 344 u_int16_t mii_data; 345}; 346 347/* 348 * MII constants 349 */ 350#define WB_MII_STARTDELIM 0x01 351#define WB_MII_READOP 0x02 352#define WB_MII_WRITEOP 0x01 353#define WB_MII_TURNAROUND 0x02 354 355#define WB_FLAG_FORCEDELAY 1 356#define WB_FLAG_SCHEDDELAY 2 357#define WB_FLAG_DELAYTIMEO 3 358 359struct wb_softc { 360 struct device sc_dev; /* generic device structure */ 361 void * sc_ih; /* interrupt handler cookie */ 362 struct arpcom arpcom; /* interface info */ 363 struct ifmedia ifmedia; /* media info */ 364 bus_space_handle_t wb_bhandle; 365 bus_space_tag_t wb_btag; 366 struct wb_type *wb_info; /* 3Com adapter info */ 367 struct wb_type *wb_pinfo; /* phy info */ 368 u_int8_t wb_type; 369 u_int8_t wb_phy_addr; /* PHY address */ 370 u_int8_t wb_tx_pend; /* TX pending */ 371 u_int8_t wb_want_auto; 372 u_int8_t wb_autoneg; 373 u_int16_t wb_txthresh; 374 caddr_t wb_ldata_ptr; 375 struct wb_list_data *wb_ldata; 376 struct wb_chain_data wb_cdata; 377}; 378 379/* 380 * register space access macros 381 */ 382#define CSR_WRITE_4(sc, reg, val) \ 383 bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val) 384#define CSR_WRITE_2(sc, reg, val) \ 385 bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val) 386#define CSR_WRITE_1(sc, reg, val) \ 387 bus_space_write_1(sc->wb_btag, sc->wb_bhandle, reg, val) 388 389#define CSR_READ_4(sc, reg) \ 390 bus_space_read_4(sc->wb_btag, sc->wb_bhandle, reg) 391#define CSR_READ_2(sc, reg) \ 392 bus_space_read_2(sc->wb_btag, sc->wb_bhandle, reg) 393#define CSR_READ_1(sc, reg) \ 394 bus_space_read_1(sc->wb_btag, sc->wb_bhandle, reg) 395 396#define WB_TIMEOUT 1000 397 398/* 399 * General constants that are fun to know. 400 * 401 * Winbond PCI vendor ID 402 */ 403#define WB_VENDORID 0x1050 404 405/* 406 * Winbond device IDs. 407 */ 408#define WB_DEVICEID_840F 0x0840 409 410/* 411 * Compex vendor ID. 412 */ 413#define CP_VENDORID 0x11F6 414 415/* 416 * Compex device IDs. 417 */ 418#define CP_DEVICEID_RL100 0x2011 419 420/* 421 * Texas Instruments PHY identifiers 422 */ 423#define TI_PHY_VENDORID 0x4000 424#define TI_PHY_10BT 0x501F 425#define TI_PHY_100VGPMI 0x502F 426 427/* 428 * These ID values are for the NS DP83840A 10/100 PHY 429 */ 430#define NS_PHY_VENDORID 0x2000 431#define NS_PHY_83840A 0x5C0F 432 433/* 434 * Level 1 10/100 PHY 435 */ 436#define LEVEL1_PHY_VENDORID 0x7810 437#define LEVEL1_PHY_LXT970 0x000F 438 439/* 440 * Intel 82555 10/100 PHY 441 */ 442#define INTEL_PHY_VENDORID 0x0A28 443#define INTEL_PHY_82555 0x015F 444 445/* 446 * SEEQ 80220 10/100 PHY 447 */ 448#define SEEQ_PHY_VENDORID 0x0016 449#define SEEQ_PHY_80220 0xF83F 450 451 452/* 453 * PCI low memory base and low I/O base register, and 454 * other PCI registers. Note: some are only available on 455 * the 3c905B, in particular those that related to power management. 456 */ 457 458#define WB_PCI_VENDOR_ID 0x00 459#define WB_PCI_DEVICE_ID 0x02 460#define WB_PCI_COMMAND 0x04 461#define WB_PCI_STATUS 0x06 462#define WB_PCI_CLASSCODE 0x09 463#define WB_PCI_LATENCY_TIMER 0x0D 464#define WB_PCI_HEADER_TYPE 0x0E 465#define WB_PCI_LOIO 0x10 466#define WB_PCI_LOMEM 0x14 467#define WB_PCI_BIOSROM 0x30 468#define WB_PCI_INTLINE 0x3C 469#define WB_PCI_INTPIN 0x3D 470#define WB_PCI_MINGNT 0x3E 471#define WB_PCI_MINLAT 0x0F 472#define WB_PCI_RESETOPT 0x48 473#define WB_PCI_EEPROM_DATA 0x4C 474 475/* power management registers */ 476#define WB_PCI_CAPID 0xDC /* 8 bits */ 477#define WB_PCI_NEXTPTR 0xDD /* 8 bits */ 478#define WB_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 479#define WB_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 480 481#define WB_PSTATE_MASK 0x0003 482#define WB_PSTATE_D0 0x0000 483#define WB_PSTATE_D1 0x0002 484#define WB_PSTATE_D2 0x0002 485#define WB_PSTATE_D3 0x0003 486#define WB_PME_EN 0x0010 487#define WB_PME_STATUS 0x8000 488 489#define PHY_UNKNOWN 6 490 491#define WB_PHYADDR_MIN 0x00 492#define WB_PHYADDR_MAX 0x1F 493 494#define PHY_BMCR 0x00 495#define PHY_BMSR 0x01 496#define PHY_VENID 0x02 497#define PHY_DEVID 0x03 498#define PHY_ANAR 0x04 499#define PHY_LPAR 0x05 500#define PHY_ANEXP 0x06 501 502#define PHY_ANAR_NEXTPAGE 0x8000 503#define PHY_ANAR_RSVD0 0x4000 504#define PHY_ANAR_TLRFLT 0x2000 505#define PHY_ANAR_RSVD1 0x1000 506#define PHY_ANAR_RSVD2 0x0800 507#define PHY_ANAR_RSVD3 0x0400 508#define PHY_ANAR_100BT4 0x0200 509#define PHY_ANAR_100BTXFULL 0x0100 510#define PHY_ANAR_100BTXHALF 0x0080 511#define PHY_ANAR_10BTFULL 0x0040 512#define PHY_ANAR_10BTHALF 0x0020 513#define PHY_ANAR_PROTO4 0x0010 514#define PHY_ANAR_PROTO3 0x0008 515#define PHY_ANAR_PROTO2 0x0004 516#define PHY_ANAR_PROTO1 0x0002 517#define PHY_ANAR_PROTO0 0x0001 518 519/* 520 * These are the register definitions for the PHY (physical layer 521 * interface chip). 522 */ 523/* 524 * PHY BMCR Basic Mode Control Register 525 */ 526#define PHY_BMCR_RESET 0x8000 527#define PHY_BMCR_LOOPBK 0x4000 528#define PHY_BMCR_SPEEDSEL 0x2000 529#define PHY_BMCR_AUTONEGENBL 0x1000 530#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 531#define PHY_BMCR_ISOLATE 0x0400 532#define PHY_BMCR_AUTONEGRSTR 0x0200 533#define PHY_BMCR_DUPLEX 0x0100 534#define PHY_BMCR_COLLTEST 0x0080 535#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 536#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 537#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 538#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 539#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 540#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 541#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 542/* 543 * RESET: 1 == software reset, 0 == normal operation 544 * Resets status and control registers to default values. 545 * Relatches all hardware config values. 546 * 547 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 548 * 549 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 550 * Link speed is selected byt his bit or if auto-negotiation if bit 551 * 12 (AUTONEGENBL) is set (in which case the value of this register 552 * is ignored). 553 * 554 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 555 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 556 * determine speed and mode. Should be cleared and then set if PHY configured 557 * for no autoneg on startup. 558 * 559 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 560 * 561 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 562 * 563 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 564 * 565 * COLLTEST: 1 == collision test enabled, 0 == normal operation 566 */ 567 568/* 569 * PHY, BMSR Basic Mode Status Register 570 */ 571#define PHY_BMSR_100BT4 0x8000 572#define PHY_BMSR_100BTXFULL 0x4000 573#define PHY_BMSR_100BTXHALF 0x2000 574#define PHY_BMSR_10BTFULL 0x1000 575#define PHY_BMSR_10BTHALF 0x0800 576#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 577#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 578#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 579#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 580#define PHY_BMSR_MFPRESUP 0x0040 581#define PHY_BMSR_AUTONEGCOMP 0x0020 582#define PHY_BMSR_REMFAULT 0x0010 583#define PHY_BMSR_CANAUTONEG 0x0008 584#define PHY_BMSR_LINKSTAT 0x0004 585#define PHY_BMSR_JABBER 0x0002 586#define PHY_BMSR_EXTENDED 0x0001 587 588#ifndef ETHER_CRC_LEN 589#define ETHER_CRC_LEN 4 590#endif 591#ifndef ETHER_ALIGN 592#define ETHER_ALIGN 2 593#endif 594 595#ifdef __alpha__ 596#undef vtophys 597#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 598#endif 599