if_wb.c revision 1.24
1/* $OpenBSD: if_wb.c,v 1.24 2004/09/23 17:45:16 brad Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26 1999/09/25 17:29:02 wpaul Exp $ 35 */ 36 37/* 38 * Winbond fast ethernet PCI NIC driver 39 * 40 * Supports various cheap network adapters based on the Winbond W89C840F 41 * fast ethernet controller chip. This includes adapters manufactured by 42 * Winbond itself and some made by Linksys. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49/* 50 * The Winbond W89C840F chip is a bus master; in some ways it resembles 51 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 52 * one major difference which is that while the registers do many of 53 * the same things as a tulip adapter, the offsets are different: where 54 * tulip registers are typically spaced 8 bytes apart, the Winbond 55 * registers are spaced 4 bytes apart. The receiver filter is also 56 * programmed differently. 57 * 58 * Like the tulip, the Winbond chip uses small descriptors containing 59 * a status word, a control word and 32-bit areas that can either be used 60 * to point to two external data blocks, or to point to a single block 61 * and another descriptor in a linked list. Descriptors can be grouped 62 * together in blocks to form fixed length rings or can be chained 63 * together in linked lists. A single packet may be spread out over 64 * several descriptors if necessary. 65 * 66 * For the receive ring, this driver uses a linked list of descriptors, 67 * each pointing to a single mbuf cluster buffer, which us large enough 68 * to hold an entire packet. The link list is looped back to created a 69 * closed ring. 70 * 71 * For transmission, the driver creates a linked list of 'super descriptors' 72 * which each contain several individual descriptors linked toghether. 73 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 74 * abuse as fragment pointers. This allows us to use a buffer management 75 * scheme very similar to that used in the ThunderLAN and Etherlink XL 76 * drivers. 77 * 78 * Autonegotiation is performed using the external PHY via the MII bus. 79 * The sample boards I have all use a Davicom PHY. 80 * 81 * Note: the author of the Linux driver for the Winbond chip alludes 82 * to some sort of flaw in the chip's design that seems to mandate some 83 * drastic workaround which signigicantly impairs transmit performance. 84 * I have no idea what he's on about: transmit performance with all 85 * three of my test boards seems fine. 86 */ 87 88#include "bpfilter.h" 89 90#include <sys/param.h> 91#include <sys/systm.h> 92#include <sys/sockio.h> 93#include <sys/mbuf.h> 94#include <sys/malloc.h> 95#include <sys/kernel.h> 96#include <sys/socket.h> 97#include <sys/device.h> 98#include <sys/queue.h> 99#include <sys/timeout.h> 100 101#include <net/if.h> 102#include <net/if_dl.h> 103#include <net/if_types.h> 104 105#ifdef INET 106#include <netinet/in.h> 107#include <netinet/in_systm.h> 108#include <netinet/in_var.h> 109#include <netinet/ip.h> 110#include <netinet/if_ether.h> 111#endif 112 113#include <net/if_media.h> 114 115#if NBPFILTER > 0 116#include <net/bpf.h> 117#endif 118 119#include <uvm/uvm_extern.h> /* for vtophys */ 120 121#include <dev/mii/mii.h> 122#include <dev/mii/miivar.h> 123#include <dev/pci/pcireg.h> 124#include <dev/pci/pcivar.h> 125#include <dev/pci/pcidevs.h> 126 127#define WB_USEIOSPACE 128 129/* #define WB_BACKGROUND_AUTONEG */ 130 131#include <dev/pci/if_wbreg.h> 132 133int wb_probe(struct device *, void *, void *); 134void wb_attach(struct device *, struct device *, void *); 135 136void wb_bfree(caddr_t, u_int, void *); 137int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 138 struct mbuf *); 139int wb_encap(struct wb_softc *, struct wb_chain *, 140 struct mbuf *); 141 142void wb_rxeof(struct wb_softc *); 143void wb_rxeoc(struct wb_softc *); 144void wb_txeof(struct wb_softc *); 145void wb_txeoc(struct wb_softc *); 146int wb_intr(void *); 147void wb_tick(void *); 148void wb_start(struct ifnet *); 149int wb_ioctl(struct ifnet *, u_long, caddr_t); 150void wb_init(void *); 151void wb_stop(struct wb_softc *); 152void wb_watchdog(struct ifnet *); 153void wb_shutdown(void *); 154int wb_ifmedia_upd(struct ifnet *); 155void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 156 157void wb_eeprom_putbyte(struct wb_softc *, int); 158void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 159void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 160void wb_mii_sync(struct wb_softc *); 161void wb_mii_send(struct wb_softc *, u_int32_t, int); 162int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 163int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 164 165void wb_setcfg(struct wb_softc *, u_int32_t); 166u_int8_t wb_calchash(caddr_t); 167void wb_setmulti(struct wb_softc *); 168void wb_reset(struct wb_softc *); 169void wb_fixmedia(struct wb_softc *); 170int wb_list_rx_init(struct wb_softc *); 171int wb_list_tx_init(struct wb_softc *); 172 173int wb_miibus_readreg(struct device *, int, int); 174void wb_miibus_writereg(struct device *, int, int, int); 175void wb_miibus_statchg(struct device *); 176 177#define WB_SETBIT(sc, reg, x) \ 178 CSR_WRITE_4(sc, reg, \ 179 CSR_READ_4(sc, reg) | x) 180 181#define WB_CLRBIT(sc, reg, x) \ 182 CSR_WRITE_4(sc, reg, \ 183 CSR_READ_4(sc, reg) & ~x) 184 185#define SIO_SET(x) \ 186 CSR_WRITE_4(sc, WB_SIO, \ 187 CSR_READ_4(sc, WB_SIO) | x) 188 189#define SIO_CLR(x) \ 190 CSR_WRITE_4(sc, WB_SIO, \ 191 CSR_READ_4(sc, WB_SIO) & ~x) 192 193/* 194 * Send a read command and address to the EEPROM, check for ACK. 195 */ 196void wb_eeprom_putbyte(sc, addr) 197 struct wb_softc *sc; 198 int addr; 199{ 200 register int d, i; 201 202 d = addr | WB_EECMD_READ; 203 204 /* 205 * Feed in each bit and strobe the clock. 206 */ 207 for (i = 0x400; i; i >>= 1) { 208 if (d & i) { 209 SIO_SET(WB_SIO_EE_DATAIN); 210 } else { 211 SIO_CLR(WB_SIO_EE_DATAIN); 212 } 213 DELAY(100); 214 SIO_SET(WB_SIO_EE_CLK); 215 DELAY(150); 216 SIO_CLR(WB_SIO_EE_CLK); 217 DELAY(100); 218 } 219 220 return; 221} 222 223/* 224 * Read a word of data stored in the EEPROM at address 'addr.' 225 */ 226void wb_eeprom_getword(sc, addr, dest) 227 struct wb_softc *sc; 228 int addr; 229 u_int16_t *dest; 230{ 231 register int i; 232 u_int16_t word = 0; 233 234 /* Enter EEPROM access mode. */ 235 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 236 237 /* 238 * Send address of word we want to read. 239 */ 240 wb_eeprom_putbyte(sc, addr); 241 242 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 243 244 /* 245 * Start reading bits from EEPROM. 246 */ 247 for (i = 0x8000; i; i >>= 1) { 248 SIO_SET(WB_SIO_EE_CLK); 249 DELAY(100); 250 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 251 word |= i; 252 SIO_CLR(WB_SIO_EE_CLK); 253 DELAY(100); 254 } 255 256 /* Turn off EEPROM access mode. */ 257 CSR_WRITE_4(sc, WB_SIO, 0); 258 259 *dest = word; 260 261 return; 262} 263 264/* 265 * Read a sequence of words from the EEPROM. 266 */ 267void wb_read_eeprom(sc, dest, off, cnt, swap) 268 struct wb_softc *sc; 269 caddr_t dest; 270 int off; 271 int cnt; 272 int swap; 273{ 274 int i; 275 u_int16_t word = 0, *ptr; 276 277 for (i = 0; i < cnt; i++) { 278 wb_eeprom_getword(sc, off + i, &word); 279 ptr = (u_int16_t *)(dest + (i * 2)); 280 if (swap) 281 *ptr = ntohs(word); 282 else 283 *ptr = word; 284 } 285 286 return; 287} 288 289/* 290 * Sync the PHYs by setting data bit and strobing the clock 32 times. 291 */ 292void wb_mii_sync(sc) 293 struct wb_softc *sc; 294{ 295 register int i; 296 297 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 298 299 for (i = 0; i < 32; i++) { 300 SIO_SET(WB_SIO_MII_CLK); 301 DELAY(1); 302 SIO_CLR(WB_SIO_MII_CLK); 303 DELAY(1); 304 } 305 306 return; 307} 308 309/* 310 * Clock a series of bits through the MII. 311 */ 312void wb_mii_send(sc, bits, cnt) 313 struct wb_softc *sc; 314 u_int32_t bits; 315 int cnt; 316{ 317 int i; 318 319 SIO_CLR(WB_SIO_MII_CLK); 320 321 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 322 if (bits & i) { 323 SIO_SET(WB_SIO_MII_DATAIN); 324 } else { 325 SIO_CLR(WB_SIO_MII_DATAIN); 326 } 327 DELAY(1); 328 SIO_CLR(WB_SIO_MII_CLK); 329 DELAY(1); 330 SIO_SET(WB_SIO_MII_CLK); 331 } 332} 333 334/* 335 * Read an PHY register through the MII. 336 */ 337int wb_mii_readreg(sc, frame) 338 struct wb_softc *sc; 339 struct wb_mii_frame *frame; 340 341{ 342 int i, ack, s; 343 344 s = splimp(); 345 346 /* 347 * Set up frame for RX. 348 */ 349 frame->mii_stdelim = WB_MII_STARTDELIM; 350 frame->mii_opcode = WB_MII_READOP; 351 frame->mii_turnaround = 0; 352 frame->mii_data = 0; 353 354 CSR_WRITE_4(sc, WB_SIO, 0); 355 356 /* 357 * Turn on data xmit. 358 */ 359 SIO_SET(WB_SIO_MII_DIR); 360 361 wb_mii_sync(sc); 362 363 /* 364 * Send command/address info. 365 */ 366 wb_mii_send(sc, frame->mii_stdelim, 2); 367 wb_mii_send(sc, frame->mii_opcode, 2); 368 wb_mii_send(sc, frame->mii_phyaddr, 5); 369 wb_mii_send(sc, frame->mii_regaddr, 5); 370 371 /* Idle bit */ 372 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 373 DELAY(1); 374 SIO_SET(WB_SIO_MII_CLK); 375 DELAY(1); 376 377 /* Turn off xmit. */ 378 SIO_CLR(WB_SIO_MII_DIR); 379 /* Check for ack */ 380 SIO_CLR(WB_SIO_MII_CLK); 381 DELAY(1); 382 SIO_SET(WB_SIO_MII_CLK); 383 DELAY(1); 384 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 385 SIO_CLR(WB_SIO_MII_CLK); 386 DELAY(1); 387 SIO_SET(WB_SIO_MII_CLK); 388 DELAY(1); 389 390 /* 391 * Now try reading data bits. If the ack failed, we still 392 * need to clock through 16 cycles to keep the PHY(s) in sync. 393 */ 394 if (ack) { 395 for(i = 0; i < 16; i++) { 396 SIO_CLR(WB_SIO_MII_CLK); 397 DELAY(1); 398 SIO_SET(WB_SIO_MII_CLK); 399 DELAY(1); 400 } 401 goto fail; 402 } 403 404 for (i = 0x8000; i; i >>= 1) { 405 SIO_CLR(WB_SIO_MII_CLK); 406 DELAY(1); 407 if (!ack) { 408 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 409 frame->mii_data |= i; 410 DELAY(1); 411 } 412 SIO_SET(WB_SIO_MII_CLK); 413 DELAY(1); 414 } 415 416fail: 417 418 SIO_CLR(WB_SIO_MII_CLK); 419 DELAY(1); 420 SIO_SET(WB_SIO_MII_CLK); 421 DELAY(1); 422 423 splx(s); 424 425 if (ack) 426 return(1); 427 return(0); 428} 429 430/* 431 * Write to a PHY register through the MII. 432 */ 433int wb_mii_writereg(sc, frame) 434 struct wb_softc *sc; 435 struct wb_mii_frame *frame; 436 437{ 438 int s; 439 440 s = splimp(); 441 /* 442 * Set up frame for TX. 443 */ 444 445 frame->mii_stdelim = WB_MII_STARTDELIM; 446 frame->mii_opcode = WB_MII_WRITEOP; 447 frame->mii_turnaround = WB_MII_TURNAROUND; 448 449 /* 450 * Turn on data output. 451 */ 452 SIO_SET(WB_SIO_MII_DIR); 453 454 wb_mii_sync(sc); 455 456 wb_mii_send(sc, frame->mii_stdelim, 2); 457 wb_mii_send(sc, frame->mii_opcode, 2); 458 wb_mii_send(sc, frame->mii_phyaddr, 5); 459 wb_mii_send(sc, frame->mii_regaddr, 5); 460 wb_mii_send(sc, frame->mii_turnaround, 2); 461 wb_mii_send(sc, frame->mii_data, 16); 462 463 /* Idle bit. */ 464 SIO_SET(WB_SIO_MII_CLK); 465 DELAY(1); 466 SIO_CLR(WB_SIO_MII_CLK); 467 DELAY(1); 468 469 /* 470 * Turn off xmit. 471 */ 472 SIO_CLR(WB_SIO_MII_DIR); 473 474 splx(s); 475 476 return(0); 477} 478 479int 480wb_miibus_readreg(dev, phy, reg) 481 struct device *dev; 482 int phy, reg; 483{ 484 struct wb_softc *sc = (struct wb_softc *)dev; 485 struct wb_mii_frame frame; 486 487 bzero((char *)&frame, sizeof(frame)); 488 489 frame.mii_phyaddr = phy; 490 frame.mii_regaddr = reg; 491 wb_mii_readreg(sc, &frame); 492 493 return(frame.mii_data); 494} 495 496void 497wb_miibus_writereg(dev, phy, reg, data) 498 struct device *dev; 499 int phy, reg, data; 500{ 501 struct wb_softc *sc = (struct wb_softc *)dev; 502 struct wb_mii_frame frame; 503 504 bzero((char *)&frame, sizeof(frame)); 505 506 frame.mii_phyaddr = phy; 507 frame.mii_regaddr = reg; 508 frame.mii_data = data; 509 510 wb_mii_writereg(sc, &frame); 511 512 return; 513} 514 515void 516wb_miibus_statchg(dev) 517 struct device *dev; 518{ 519 struct wb_softc *sc = (struct wb_softc *)dev; 520 521 wb_setcfg(sc, sc->sc_mii.mii_media_active); 522} 523 524/* 525 * Program the 64-bit multicast hash filter. 526 */ 527void wb_setmulti(sc) 528 struct wb_softc *sc; 529{ 530 struct ifnet *ifp; 531 int h = 0; 532 u_int32_t hashes[2] = { 0, 0 }; 533 struct arpcom *ac = &sc->arpcom; 534 struct ether_multi *enm; 535 struct ether_multistep step; 536 u_int32_t rxfilt; 537 int mcnt = 0; 538 539 ifp = &sc->arpcom.ac_if; 540 541 rxfilt = CSR_READ_4(sc, WB_NETCFG); 542 543allmulti: 544 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 545 rxfilt |= WB_NETCFG_RX_MULTI; 546 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 547 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 548 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 549 return; 550 } 551 552 /* first, zot all the existing hash bits */ 553 CSR_WRITE_4(sc, WB_MAR0, 0); 554 CSR_WRITE_4(sc, WB_MAR1, 0); 555 556 /* now program new ones */ 557 ETHER_FIRST_MULTI(step, ac, enm); 558 while (enm != NULL) { 559 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 560 ifp->if_flags |= IFF_ALLMULTI; 561 goto allmulti; 562 } 563 h = ~(ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26); 564 if (h < 32) 565 hashes[0] |= (1 << h); 566 else 567 hashes[1] |= (1 << (h - 32)); 568 mcnt++; 569 ETHER_NEXT_MULTI(step, enm); 570 } 571 572 if (mcnt) 573 rxfilt |= WB_NETCFG_RX_MULTI; 574 else 575 rxfilt &= ~WB_NETCFG_RX_MULTI; 576 577 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 578 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 579 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 580 581 return; 582} 583 584/* 585 * The Winbond manual states that in order to fiddle with the 586 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 587 * first have to put the transmit and/or receive logic in the idle state. 588 */ 589void 590wb_setcfg(sc, media) 591 struct wb_softc *sc; 592 u_int32_t media; 593{ 594 int i, restart = 0; 595 596 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 597 restart = 1; 598 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 599 600 for (i = 0; i < WB_TIMEOUT; i++) { 601 DELAY(10); 602 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 603 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 604 break; 605 } 606 607 if (i == WB_TIMEOUT) 608 printf("%s: failed to force tx and " 609 "rx to idle state\n", sc->sc_dev.dv_xname); 610 } 611 612 if (IFM_SUBTYPE(media) == IFM_10_T) 613 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 614 else 615 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 616 617 if ((media & IFM_GMASK) == IFM_FDX) 618 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 619 else 620 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 621 622 if (restart) 623 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 624 625 return; 626} 627 628void 629wb_reset(sc) 630 struct wb_softc *sc; 631{ 632 register int i; 633 struct mii_data *mii = &sc->sc_mii; 634 635 CSR_WRITE_4(sc, WB_NETCFG, 0); 636 CSR_WRITE_4(sc, WB_BUSCTL, 0); 637 CSR_WRITE_4(sc, WB_TXADDR, 0); 638 CSR_WRITE_4(sc, WB_RXADDR, 0); 639 640 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 641 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 642 643 for (i = 0; i < WB_TIMEOUT; i++) { 644 DELAY(10); 645 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 646 break; 647 } 648 if (i == WB_TIMEOUT) 649 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 650 651 /* Wait a little while for the chip to get its brains in order. */ 652 DELAY(1000); 653 654 if (mii->mii_instance) { 655 struct mii_softc *miisc; 656 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 657 miisc = LIST_NEXT(miisc, mii_list)) 658 mii_phy_reset(miisc); 659 } 660} 661 662void 663wb_fixmedia(sc) 664 struct wb_softc *sc; 665{ 666 struct mii_data *mii = &sc->sc_mii; 667 u_int32_t media; 668 669 if (LIST_FIRST(&mii->mii_phys) == NULL) 670 return; 671 672 mii_pollstat(mii); 673 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 674 media = mii->mii_media_active & ~IFM_10_T; 675 media |= IFM_100_TX; 676 } if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 677 media = mii->mii_media_active & ~IFM_100_TX; 678 media |= IFM_10_T; 679 } else 680 return; 681 682 ifmedia_set(&mii->mii_media, media); 683} 684 685const struct pci_matchid wb_devices[] = { 686 { PCI_VENDOR_WINBOND, PCI_PRODUCT_WINBOND_W89C840F }, 687 { PCI_VENDOR_COMPEX, PCI_PRODUCT_COMPEX_RL100ATX }, 688}; 689 690/* 691 * Probe for a Winbond chip. Check the PCI vendor and device 692 * IDs against our list and return a device name if we find a match. 693 */ 694int 695wb_probe(parent, match, aux) 696 struct device *parent; 697 void *match, *aux; 698{ 699 return (pci_matchbyid((struct pci_attach_args *)aux, wb_devices, 700 sizeof(wb_devices)/sizeof(wb_devices[0]))); 701} 702 703/* 704 * Attach the interface. Allocate softc structures, do ifmedia 705 * setup and ethernet/BPF attach. 706 */ 707void 708wb_attach(parent, self, aux) 709 struct device *parent, *self; 710 void *aux; 711{ 712 struct wb_softc *sc = (struct wb_softc *)self; 713 struct pci_attach_args *pa = aux; 714 pci_chipset_tag_t pc = pa->pa_pc; 715 pci_intr_handle_t ih; 716 const char *intrstr = NULL; 717 struct ifnet *ifp = &sc->arpcom.ac_if; 718 bus_addr_t iobase; 719 bus_size_t iosize; 720 int s, rseg; 721 u_int32_t command; 722 bus_dma_segment_t seg; 723 bus_dmamap_t dmamap; 724 caddr_t kva; 725 726 s = splimp(); 727 728 /* 729 * Handle power management nonsense. 730 */ 731 732 command = pci_conf_read(pc, pa->pa_tag, WB_PCI_CAPID) & 0x000000FF; 733 if (command == 0x01) { 734 735 command = pci_conf_read(pc, pa->pa_tag, WB_PCI_PWRMGMTCTRL); 736 if (command & WB_PSTATE_MASK) { 737 u_int32_t io, mem, irq; 738 739 /* Save important PCI config data. */ 740 io = pci_conf_read(pc, pa->pa_tag, WB_PCI_LOIO); 741 mem = pci_conf_read(pc, pa->pa_tag, WB_PCI_LOMEM); 742 irq = pci_conf_read(pc, pa->pa_tag, WB_PCI_INTLINE); 743 744 /* Reset the power state. */ 745 printf("%s: chip is in D%d power mode " 746 "-- setting to D0\n", sc->sc_dev.dv_xname, 747 command & WB_PSTATE_MASK); 748 command &= 0xFFFFFFFC; 749 pci_conf_write(pc, pa->pa_tag, WB_PCI_PWRMGMTCTRL, 750 command); 751 752 /* Restore PCI config data. */ 753 pci_conf_write(pc, pa->pa_tag, WB_PCI_LOIO, io); 754 pci_conf_write(pc, pa->pa_tag, WB_PCI_LOMEM, mem); 755 pci_conf_write(pc, pa->pa_tag, WB_PCI_INTLINE, irq); 756 } 757 } 758 759 /* 760 * Map control/status registers. 761 */ 762 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 763 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 764 PCI_COMMAND_MASTER_ENABLE; 765 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 766 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 767 768#ifdef WB_USEIOSPACE 769 if (!(command & PCI_COMMAND_IO_ENABLE)) { 770 printf(": failed to enable I/O ports!\n"); 771 goto fail; 772 } 773 if (pci_io_find(pc, pa->pa_tag, WB_PCI_LOIO, &iobase, &iosize)) { 774 printf(": can't find i/o space\n"); 775 goto fail; 776 } 777 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->wb_bhandle)) { 778 printf(": can't map i/o space\n"); 779 goto fail; 780 } 781 sc->wb_btag = pa->pa_iot; 782#else 783 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 784 printf(": failed to enable memory mapping!\n"); 785 goto fail; 786 } 787 if (pci_mem_find(pc, pa->pa_tag, WB_PCI_LOMEM, &iobase, &iosize, NULL)){ 788 printf(": can't find mem space\n"); 789 goto fail; 790 } 791 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->wb_bhandle)) { 792 printf(": can't map mem space\n"); 793 goto fail; 794 } 795 sc->wb_btag = pa->pa_memt; 796#endif 797 798 /* Allocate interrupt */ 799 if (pci_intr_map(pa, &ih)) { 800 printf(": couldn't map interrupt\n"); 801 goto fail; 802 } 803 intrstr = pci_intr_string(pc, ih); 804 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wb_intr, sc, 805 self->dv_xname); 806 if (sc->sc_ih == NULL) { 807 printf(": couldn't establish interrupt"); 808 if (intrstr != NULL) 809 printf(" at %s", intrstr); 810 printf("\n"); 811 goto fail; 812 } 813 printf(": %s", intrstr); 814 815 sc->wb_cachesize = pci_conf_read(pc, pa->pa_tag, WB_PCI_CACHELEN)&0xff; 816 817 /* Reset the adapter. */ 818 wb_reset(sc); 819 820 /* 821 * Get station address from the EEPROM. 822 */ 823 wb_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0, 3, 0); 824 printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); 825 826 if (bus_dmamem_alloc(pa->pa_dmat, sizeof(struct wb_list_data), 827 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 828 printf("%s: can't alloc list data\n", sc->sc_dev.dv_xname); 829 goto fail; 830 } 831 if (bus_dmamem_map(pa->pa_dmat, &seg, rseg, 832 sizeof(struct wb_list_data), &kva, BUS_DMA_NOWAIT)) { 833 printf("%s: can't map list data, size %d\n", 834 sc->sc_dev.dv_xname, sizeof(struct wb_list_data)); 835 bus_dmamem_free(pa->pa_dmat, &seg, rseg); 836 goto fail; 837 } 838 if (bus_dmamap_create(pa->pa_dmat, sizeof(struct wb_list_data), 1, 839 sizeof(struct wb_list_data), 0, BUS_DMA_NOWAIT, &dmamap)) { 840 printf("%s: can't create dma map\n", sc->sc_dev.dv_xname); 841 bus_dmamem_unmap(pa->pa_dmat, kva, 842 sizeof(struct wb_list_data)); 843 bus_dmamem_free(pa->pa_dmat, &seg, rseg); 844 goto fail; 845 } 846 if (bus_dmamap_load(pa->pa_dmat, dmamap, kva, 847 sizeof(struct wb_list_data), NULL, BUS_DMA_NOWAIT)) { 848 printf("%s: can't load dma map\n", sc->sc_dev.dv_xname); 849 bus_dmamap_destroy(pa->pa_dmat, dmamap); 850 bus_dmamem_unmap(pa->pa_dmat, kva, 851 sizeof(struct wb_list_data)); 852 bus_dmamem_free(pa->pa_dmat, &seg, rseg); 853 goto fail; 854 } 855 sc->wb_ldata = (struct wb_list_data *)kva; 856 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 857 858 ifp->if_softc = sc; 859 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 860 ifp->if_ioctl = wb_ioctl; 861 ifp->if_start = wb_start; 862 ifp->if_watchdog = wb_watchdog; 863 ifp->if_baudrate = 10000000; 864 IFQ_SET_MAXLEN(&ifp->if_snd, WB_TX_LIST_CNT - 1); 865 IFQ_SET_READY(&ifp->if_snd); 866 867 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 868 869 /* 870 * Do ifmedia setup. 871 */ 872 wb_stop(sc); 873 874 ifmedia_init(&sc->sc_mii.mii_media, 0, wb_ifmedia_upd, wb_ifmedia_sts); 875 sc->sc_mii.mii_ifp = ifp; 876 sc->sc_mii.mii_readreg = wb_miibus_readreg; 877 sc->sc_mii.mii_writereg = wb_miibus_writereg; 878 sc->sc_mii.mii_statchg = wb_miibus_statchg; 879 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 880 0); 881 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 882 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE,0,NULL); 883 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 884 } else 885 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 886 887 /* 888 * Call MI attach routines. 889 */ 890 if_attach(ifp); 891 ether_ifattach(ifp); 892 893 shutdownhook_establish(wb_shutdown, sc); 894 895fail: 896 splx(s); 897 return; 898} 899 900/* 901 * Initialize the transmit descriptors. 902 */ 903int wb_list_tx_init(sc) 904 struct wb_softc *sc; 905{ 906 struct wb_chain_data *cd; 907 struct wb_list_data *ld; 908 int i; 909 910 cd = &sc->wb_cdata; 911 ld = sc->wb_ldata; 912 913 for (i = 0; i < WB_TX_LIST_CNT; i++) { 914 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 915 if (i == (WB_TX_LIST_CNT - 1)) { 916 cd->wb_tx_chain[i].wb_nextdesc = 917 &cd->wb_tx_chain[0]; 918 } else { 919 cd->wb_tx_chain[i].wb_nextdesc = 920 &cd->wb_tx_chain[i + 1]; 921 } 922 } 923 924 cd->wb_tx_free = &cd->wb_tx_chain[0]; 925 cd->wb_tx_tail = cd->wb_tx_head = NULL; 926 927 return(0); 928} 929 930 931/* 932 * Initialize the RX descriptors and allocate mbufs for them. Note that 933 * we arrange the descriptors in a closed ring, so that the last descriptor 934 * points back to the first. 935 */ 936int wb_list_rx_init(sc) 937 struct wb_softc *sc; 938{ 939 struct wb_chain_data *cd; 940 struct wb_list_data *ld; 941 int i; 942 943 cd = &sc->wb_cdata; 944 ld = sc->wb_ldata; 945 946 for (i = 0; i < WB_RX_LIST_CNT; i++) { 947 cd->wb_rx_chain[i].wb_ptr = 948 (struct wb_desc *)&ld->wb_rx_list[i]; 949 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 950 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 951 return(ENOBUFS); 952 if (i == (WB_RX_LIST_CNT - 1)) { 953 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 954 ld->wb_rx_list[i].wb_next = 955 vtophys(&ld->wb_rx_list[0]); 956 } else { 957 cd->wb_rx_chain[i].wb_nextdesc = 958 &cd->wb_rx_chain[i + 1]; 959 ld->wb_rx_list[i].wb_next = 960 vtophys(&ld->wb_rx_list[i + 1]); 961 } 962 } 963 964 cd->wb_rx_head = &cd->wb_rx_chain[0]; 965 966 return(0); 967} 968 969void 970wb_bfree(buf, size, arg) 971 caddr_t buf; 972 u_int size; 973 void *arg; 974{ 975} 976 977/* 978 * Initialize an RX descriptor and attach an MBUF cluster. 979 */ 980int 981wb_newbuf(sc, c, m) 982 struct wb_softc *sc; 983 struct wb_chain_onefrag *c; 984 struct mbuf *m; 985{ 986 struct mbuf *m_new = NULL; 987 988 if (m == NULL) { 989 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 990 if (m_new == NULL) 991 return(ENOBUFS); 992 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf; 993 m_new->m_flags |= M_EXT; 994 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 995 m_new->m_len = WB_BUFBYTES; 996 m_new->m_ext.ext_free = wb_bfree; 997 m_new->m_ext.ext_arg = NULL; 998 MCLINITREFERENCE(m_new); 999 } else { 1000 m_new = m; 1001 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1002 m_new->m_data = m_new->m_ext.ext_buf; 1003 } 1004 1005 m_adj(m_new, sizeof(u_int64_t)); 1006 1007 c->wb_mbuf = m_new; 1008 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1009 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1010 c->wb_ptr->wb_status = WB_RXSTAT; 1011 1012 return(0); 1013} 1014 1015/* 1016 * A frame has been uploaded: pass the resulting mbuf chain up to 1017 * the higher level protocols. 1018 */ 1019void wb_rxeof(sc) 1020 struct wb_softc *sc; 1021{ 1022 struct mbuf *m = NULL; 1023 struct ifnet *ifp; 1024 struct wb_chain_onefrag *cur_rx; 1025 int total_len = 0; 1026 u_int32_t rxstat; 1027 1028 ifp = &sc->arpcom.ac_if; 1029 1030 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1031 WB_RXSTAT_OWN)) { 1032 struct mbuf *m0 = NULL; 1033 1034 cur_rx = sc->wb_cdata.wb_rx_head; 1035 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1036 1037 m = cur_rx->wb_mbuf; 1038 1039 if ((rxstat & WB_RXSTAT_MIIERR) || 1040 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1041 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1042 !(rxstat & WB_RXSTAT_LASTFRAG) || 1043 !(rxstat & WB_RXSTAT_RXCMP)) { 1044 ifp->if_ierrors++; 1045 wb_newbuf(sc, cur_rx, m); 1046 printf("%s: receiver babbling: possible chip " 1047 "bug, forcing reset\n", sc->sc_dev.dv_xname); 1048 wb_fixmedia(sc); 1049 wb_reset(sc); 1050 wb_init(sc); 1051 return; 1052 } 1053 1054 if (rxstat & WB_RXSTAT_RXERR) { 1055 ifp->if_ierrors++; 1056 wb_newbuf(sc, cur_rx, m); 1057 break; 1058 } 1059 1060 /* No errors; receive the packet. */ 1061 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1062 1063 /* 1064 * XXX The Winbond chip includes the CRC with every 1065 * received frame, and there's no way to turn this 1066 * behavior off (at least, I can't find anything in 1067 * the manual that explains how to do it) so we have 1068 * to trim off the CRC manually. 1069 */ 1070 total_len -= ETHER_CRC_LEN; 1071 1072 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1073 total_len + ETHER_ALIGN, 0, ifp, NULL); 1074 wb_newbuf(sc, cur_rx, m); 1075 if (m0 == NULL) { 1076 ifp->if_ierrors++; 1077 break; 1078 } 1079 m_adj(m0, ETHER_ALIGN); 1080 m = m0; 1081 1082 ifp->if_ipackets++; 1083 1084#if NBPFILTER > 0 1085 /* 1086 * Handle BPF listeners. Let the BPF user see the packet. 1087 */ 1088 if (ifp->if_bpf) 1089 bpf_mtap(ifp->if_bpf, m); 1090#endif 1091 /* pass it on. */ 1092 ether_input_mbuf(ifp, m); 1093 } 1094 1095 return; 1096} 1097 1098void wb_rxeoc(sc) 1099 struct wb_softc *sc; 1100{ 1101 wb_rxeof(sc); 1102 1103 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1104 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1105 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1106 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1107 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1108 1109 return; 1110} 1111 1112/* 1113 * A frame was downloaded to the chip. It's safe for us to clean up 1114 * the list buffers. 1115 */ 1116void wb_txeof(sc) 1117 struct wb_softc *sc; 1118{ 1119 struct wb_chain *cur_tx; 1120 struct ifnet *ifp; 1121 1122 ifp = &sc->arpcom.ac_if; 1123 1124 /* Clear the timeout timer. */ 1125 ifp->if_timer = 0; 1126 1127 if (sc->wb_cdata.wb_tx_head == NULL) 1128 return; 1129 1130 /* 1131 * Go through our tx list and free mbufs for those 1132 * frames that have been transmitted. 1133 */ 1134 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1135 u_int32_t txstat; 1136 1137 cur_tx = sc->wb_cdata.wb_tx_head; 1138 txstat = WB_TXSTATUS(cur_tx); 1139 1140 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1141 break; 1142 1143 if (txstat & WB_TXSTAT_TXERR) { 1144 ifp->if_oerrors++; 1145 if (txstat & WB_TXSTAT_ABORT) 1146 ifp->if_collisions++; 1147 if (txstat & WB_TXSTAT_LATECOLL) 1148 ifp->if_collisions++; 1149 } 1150 1151 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1152 1153 ifp->if_opackets++; 1154 m_freem(cur_tx->wb_mbuf); 1155 cur_tx->wb_mbuf = NULL; 1156 1157 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1158 sc->wb_cdata.wb_tx_head = NULL; 1159 sc->wb_cdata.wb_tx_tail = NULL; 1160 break; 1161 } 1162 1163 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1164 } 1165 1166 return; 1167} 1168 1169/* 1170 * TX 'end of channel' interrupt handler. 1171 */ 1172void wb_txeoc(sc) 1173 struct wb_softc *sc; 1174{ 1175 struct ifnet *ifp; 1176 1177 ifp = &sc->arpcom.ac_if; 1178 1179 ifp->if_timer = 0; 1180 1181 if (sc->wb_cdata.wb_tx_head == NULL) { 1182 ifp->if_flags &= ~IFF_OACTIVE; 1183 sc->wb_cdata.wb_tx_tail = NULL; 1184 } else { 1185 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1186 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1187 ifp->if_timer = 5; 1188 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1189 } 1190 } 1191 1192 return; 1193} 1194 1195int wb_intr(arg) 1196 void *arg; 1197{ 1198 struct wb_softc *sc; 1199 struct ifnet *ifp; 1200 u_int32_t status; 1201 int r = 0; 1202 1203 sc = arg; 1204 ifp = &sc->arpcom.ac_if; 1205 1206 if (!(ifp->if_flags & IFF_UP)) 1207 return (r); 1208 1209 /* Disable interrupts. */ 1210 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1211 1212 for (;;) { 1213 1214 status = CSR_READ_4(sc, WB_ISR); 1215 if (status) 1216 CSR_WRITE_4(sc, WB_ISR, status); 1217 1218 if ((status & WB_INTRS) == 0) 1219 break; 1220 1221 r = 1; 1222 1223 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1224 ifp->if_ierrors++; 1225 wb_reset(sc); 1226 if (status & WB_ISR_RX_ERR) 1227 wb_fixmedia(sc); 1228 wb_init(sc); 1229 continue; 1230 } 1231 1232 if (status & WB_ISR_RX_OK) 1233 wb_rxeof(sc); 1234 1235 if (status & WB_ISR_RX_IDLE) 1236 wb_rxeoc(sc); 1237 1238 if (status & WB_ISR_TX_OK) 1239 wb_txeof(sc); 1240 1241 if (status & WB_ISR_TX_NOBUF) 1242 wb_txeoc(sc); 1243 1244 if (status & WB_ISR_TX_IDLE) { 1245 wb_txeof(sc); 1246 if (sc->wb_cdata.wb_tx_head != NULL) { 1247 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1248 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1249 } 1250 } 1251 1252 if (status & WB_ISR_TX_UNDERRUN) { 1253 ifp->if_oerrors++; 1254 wb_txeof(sc); 1255 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1256 /* Jack up TX threshold */ 1257 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1258 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1259 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1260 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1261 } 1262 1263 if (status & WB_ISR_BUS_ERR) { 1264 wb_reset(sc); 1265 wb_init(sc); 1266 } 1267 1268 } 1269 1270 /* Re-enable interrupts. */ 1271 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1272 1273 if (!IFQ_IS_EMPTY(&ifp->if_snd)) { 1274 wb_start(ifp); 1275 } 1276 1277 return (r); 1278} 1279 1280void 1281wb_tick(xsc) 1282 void *xsc; 1283{ 1284 struct wb_softc *sc = xsc; 1285 int s; 1286 1287 s = splimp(); 1288 mii_tick(&sc->sc_mii); 1289 splx(s); 1290 timeout_add(&sc->wb_tick_tmo, hz); 1291} 1292 1293/* 1294 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1295 * pointers to the fragment pointers. 1296 */ 1297int wb_encap(sc, c, m_head) 1298 struct wb_softc *sc; 1299 struct wb_chain *c; 1300 struct mbuf *m_head; 1301{ 1302 int frag = 0; 1303 struct wb_desc *f = NULL; 1304 int total_len; 1305 struct mbuf *m; 1306 1307 /* 1308 * Start packing the mbufs in this chain into 1309 * the fragment pointers. Stop when we run out 1310 * of fragments or hit the end of the mbuf chain. 1311 */ 1312 m = m_head; 1313 total_len = 0; 1314 1315 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1316 if (m->m_len != 0) { 1317 if (frag == WB_MAXFRAGS) 1318 break; 1319 total_len += m->m_len; 1320 f = &c->wb_ptr->wb_frag[frag]; 1321 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1322 if (frag == 0) { 1323 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1324 f->wb_status = 0; 1325 } else 1326 f->wb_status = WB_TXSTAT_OWN; 1327 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1328 f->wb_data = vtophys(mtod(m, vaddr_t)); 1329 frag++; 1330 } 1331 } 1332 1333 /* 1334 * Handle special case: we used up all 16 fragments, 1335 * but we have more mbufs left in the chain. Copy the 1336 * data into an mbuf cluster. Note that we don't 1337 * bother clearing the values in the other fragment 1338 * pointers/counters; it wouldn't gain us anything, 1339 * and would waste cycles. 1340 */ 1341 if (m != NULL) { 1342 struct mbuf *m_new = NULL; 1343 1344 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1345 if (m_new == NULL) 1346 return(1); 1347 if (m_head->m_pkthdr.len > MHLEN) { 1348 MCLGET(m_new, M_DONTWAIT); 1349 if (!(m_new->m_flags & M_EXT)) { 1350 m_freem(m_new); 1351 return(1); 1352 } 1353 } 1354 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1355 mtod(m_new, caddr_t)); 1356 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1357 m_freem(m_head); 1358 m_head = m_new; 1359 f = &c->wb_ptr->wb_frag[0]; 1360 f->wb_status = 0; 1361 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1362 f->wb_ctl = total_len = m_new->m_len; 1363 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1364 frag = 1; 1365 } 1366 1367 if (total_len < WB_MIN_FRAMELEN) { 1368 f = &c->wb_ptr->wb_frag[frag]; 1369 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1370 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1371 f->wb_ctl |= WB_TXCTL_TLINK; 1372 f->wb_status = WB_TXSTAT_OWN; 1373 frag++; 1374 } 1375 1376 c->wb_mbuf = m_head; 1377 c->wb_lastdesc = frag - 1; 1378 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1379 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1380 1381 return(0); 1382} 1383 1384/* 1385 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1386 * to the mbuf data regions directly in the transmit lists. We also save a 1387 * copy of the pointers since the transmit list fragment pointers are 1388 * physical addresses. 1389 */ 1390 1391void wb_start(ifp) 1392 struct ifnet *ifp; 1393{ 1394 struct wb_softc *sc; 1395 struct mbuf *m_head = NULL; 1396 struct wb_chain *cur_tx = NULL, *start_tx; 1397 1398 sc = ifp->if_softc; 1399 1400 /* 1401 * Check for an available queue slot. If there are none, 1402 * punt. 1403 */ 1404 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1405 ifp->if_flags |= IFF_OACTIVE; 1406 return; 1407 } 1408 1409 start_tx = sc->wb_cdata.wb_tx_free; 1410 1411 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1412 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1413 if (m_head == NULL) 1414 break; 1415 1416 /* Pick a descriptor off the free list. */ 1417 cur_tx = sc->wb_cdata.wb_tx_free; 1418 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1419 1420 /* Pack the data into the descriptor. */ 1421 wb_encap(sc, cur_tx, m_head); 1422 1423 if (cur_tx != start_tx) 1424 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1425 1426#if NBPFILTER > 0 1427 /* 1428 * If there's a BPF listener, bounce a copy of this frame 1429 * to him. 1430 */ 1431 if (ifp->if_bpf) 1432 bpf_mtap(ifp->if_bpf, cur_tx->wb_mbuf); 1433#endif 1434 } 1435 1436 /* 1437 * If there are no packets queued, bail. 1438 */ 1439 if (cur_tx == NULL) 1440 return; 1441 1442 /* 1443 * Place the request for the upload interrupt 1444 * in the last descriptor in the chain. This way, if 1445 * we're chaining several packets at once, we'll only 1446 * get an interupt once for the whole chain rather than 1447 * once for each packet. 1448 */ 1449 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1450 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1451 sc->wb_cdata.wb_tx_tail = cur_tx; 1452 1453 if (sc->wb_cdata.wb_tx_head == NULL) { 1454 sc->wb_cdata.wb_tx_head = start_tx; 1455 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1456 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1457 } else { 1458 /* 1459 * We need to distinguish between the case where 1460 * the own bit is clear because the chip cleared it 1461 * and where the own bit is clear because we haven't 1462 * set it yet. The magic value WB_UNSET is just some 1463 * ramdomly chosen number which doesn't have the own 1464 * bit set. When we actually transmit the frame, the 1465 * status word will have _only_ the own bit set, so 1466 * the txeoc handler will be able to tell if it needs 1467 * to initiate another transmission to flush out pending 1468 * frames. 1469 */ 1470 WB_TXOWN(start_tx) = WB_UNSENT; 1471 } 1472 1473 /* 1474 * Set a timeout in case the chip goes out to lunch. 1475 */ 1476 ifp->if_timer = 5; 1477 1478 return; 1479} 1480 1481void wb_init(xsc) 1482 void *xsc; 1483{ 1484 struct wb_softc *sc = xsc; 1485 struct ifnet *ifp = &sc->arpcom.ac_if; 1486 int s, i; 1487 1488 s = splimp(); 1489 1490 /* 1491 * Cancel pending I/O and free all RX/TX buffers. 1492 */ 1493 wb_stop(sc); 1494 wb_reset(sc); 1495 1496 sc->wb_txthresh = WB_TXTHRESH_INIT; 1497 1498 /* 1499 * Set cache alignment and burst length. 1500 */ 1501#ifdef foo 1502 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1503 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1504 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1505#endif 1506 1507 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1508 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1509 switch(sc->wb_cachesize) { 1510 case 32: 1511 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1512 break; 1513 case 16: 1514 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1515 break; 1516 case 8: 1517 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1518 break; 1519 case 0: 1520 default: 1521 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1522 break; 1523 } 1524 1525 /* This doesn't tend to work too well at 100Mbps. */ 1526 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1527 1528 /* Init our MAC address */ 1529 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1530 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1531 } 1532 1533 /* Init circular RX list. */ 1534 if (wb_list_rx_init(sc) == ENOBUFS) { 1535 printf("%s: initialization failed: no " 1536 "memory for rx buffers\n", sc->sc_dev.dv_xname); 1537 wb_stop(sc); 1538 splx(s); 1539 return; 1540 } 1541 1542 /* Init TX descriptors. */ 1543 wb_list_tx_init(sc); 1544 1545 /* If we want promiscuous mode, set the allframes bit. */ 1546 if (ifp->if_flags & IFF_PROMISC) { 1547 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1548 } else { 1549 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1550 } 1551 1552 /* 1553 * Set capture broadcast bit to capture broadcast frames. 1554 */ 1555 if (ifp->if_flags & IFF_BROADCAST) { 1556 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1557 } else { 1558 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1559 } 1560 1561 /* 1562 * Program the multicast filter, if necessary. 1563 */ 1564 wb_setmulti(sc); 1565 1566 /* 1567 * Load the address of the RX list. 1568 */ 1569 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1570 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1571 1572 /* 1573 * Enable interrupts. 1574 */ 1575 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1576 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1577 1578 /* Enable receiver and transmitter. */ 1579 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1580 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1581 1582 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1583 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1584 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1585 1586 ifp->if_flags |= IFF_RUNNING; 1587 ifp->if_flags &= ~IFF_OACTIVE; 1588 1589 splx(s); 1590 1591 timeout_set(&sc->wb_tick_tmo, wb_tick, sc); 1592 timeout_add(&sc->wb_tick_tmo, hz); 1593 1594 return; 1595} 1596 1597/* 1598 * Set media options. 1599 */ 1600int 1601wb_ifmedia_upd(ifp) 1602 struct ifnet *ifp; 1603{ 1604 struct wb_softc *sc = ifp->if_softc; 1605 1606 if (ifp->if_flags & IFF_UP) 1607 wb_init(sc); 1608 1609 return(0); 1610} 1611 1612/* 1613 * Report current media status. 1614 */ 1615void 1616wb_ifmedia_sts(ifp, ifmr) 1617 struct ifnet *ifp; 1618 struct ifmediareq *ifmr; 1619{ 1620 struct wb_softc *sc = ifp->if_softc; 1621 struct mii_data *mii = &sc->sc_mii; 1622 1623 mii_pollstat(mii); 1624 ifmr->ifm_active = mii->mii_media_active; 1625 ifmr->ifm_status = mii->mii_media_status; 1626} 1627 1628int wb_ioctl(ifp, command, data) 1629 struct ifnet *ifp; 1630 u_long command; 1631 caddr_t data; 1632{ 1633 struct wb_softc *sc = ifp->if_softc; 1634 struct ifreq *ifr = (struct ifreq *) data; 1635 struct ifaddr *ifa = (struct ifaddr *)data; 1636 int s, error = 0; 1637 1638 s = splimp(); 1639 1640 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 1641 splx(s); 1642 return (error); 1643 } 1644 1645 switch(command) { 1646 case SIOCSIFADDR: 1647 ifp->if_flags |= IFF_UP; 1648 switch (ifa->ifa_addr->sa_family) { 1649#ifdef INET 1650 case AF_INET: 1651 wb_init(sc); 1652 arp_ifinit(&sc->arpcom, ifa); 1653 break; 1654#endif /* INET */ 1655 default: 1656 wb_init(sc); 1657 } 1658 break; 1659 case SIOCSIFFLAGS: 1660 if (ifp->if_flags & IFF_UP) { 1661 wb_init(sc); 1662 } else { 1663 if (ifp->if_flags & IFF_RUNNING) 1664 wb_stop(sc); 1665 } 1666 error = 0; 1667 break; 1668 case SIOCADDMULTI: 1669 case SIOCDELMULTI: 1670 error = (command == SIOCADDMULTI) ? 1671 ether_addmulti(ifr, &sc->arpcom) : 1672 ether_delmulti(ifr, &sc->arpcom); 1673 1674 if (error == ENETRESET) { 1675 /* 1676 * Multicast list has changed; set the hardware 1677 * filter accordingly. 1678 */ 1679 wb_setmulti(sc); 1680 error = 0; 1681 } 1682 break; 1683 case SIOCGIFMEDIA: 1684 case SIOCSIFMEDIA: 1685 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1686 break; 1687 default: 1688 error = EINVAL; 1689 break; 1690 } 1691 1692 splx(s); 1693 1694 return(error); 1695} 1696 1697void wb_watchdog(ifp) 1698 struct ifnet *ifp; 1699{ 1700 struct wb_softc *sc; 1701 1702 sc = ifp->if_softc; 1703 1704 ifp->if_oerrors++; 1705 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1706 1707#ifdef foo 1708 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1709 printf("%s: no carrier - transceiver cable problem?\n", 1710 sc->sc_dev.dv_xname); 1711#endif 1712 wb_stop(sc); 1713 wb_reset(sc); 1714 wb_init(sc); 1715 1716 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1717 wb_start(ifp); 1718 1719 return; 1720} 1721 1722/* 1723 * Stop the adapter and free any mbufs allocated to the 1724 * RX and TX lists. 1725 */ 1726void wb_stop(sc) 1727 struct wb_softc *sc; 1728{ 1729 register int i; 1730 struct ifnet *ifp; 1731 1732 ifp = &sc->arpcom.ac_if; 1733 ifp->if_timer = 0; 1734 1735 timeout_del(&sc->wb_tick_tmo); 1736 1737 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1738 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1739 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1740 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1741 1742 /* 1743 * Free data in the RX lists. 1744 */ 1745 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1746 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1747 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1748 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1749 } 1750 } 1751 bzero((char *)&sc->wb_ldata->wb_rx_list, 1752 sizeof(sc->wb_ldata->wb_rx_list)); 1753 1754 /* 1755 * Free the TX list buffers. 1756 */ 1757 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1758 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1759 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1760 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1761 } 1762 } 1763 1764 bzero((char *)&sc->wb_ldata->wb_tx_list, 1765 sizeof(sc->wb_ldata->wb_tx_list)); 1766 1767 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1768 1769 return; 1770} 1771 1772/* 1773 * Stop all chip I/O so that the kernel's probe routines don't 1774 * get confused by errant DMAs when rebooting. 1775 */ 1776void wb_shutdown(arg) 1777 void *arg; 1778{ 1779 struct wb_softc *sc = (struct wb_softc *)arg; 1780 1781 wb_stop(sc); 1782 1783 return; 1784} 1785 1786struct cfattach wb_ca = { 1787 sizeof(struct wb_softc), wb_probe, wb_attach 1788}; 1789 1790struct cfdriver wb_cd = { 1791 0, "wb", DV_IFNET 1792}; 1793