1/* $OpenBSD: if_vtereg.h,v 1.2 2011/05/28 08:31:51 kevlo Exp $ */ 2/*- 3 * Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/vte/if_vtereg.h 216829 2010-12-31 00:21:41Z yongari $ 29 */ 30 31#ifndef _IF_VTEREG_H 32#define _IF_VTEREG_H 33 34/* PCI low memory base and low I/O base register */ 35#define VTE_PCI_LOIO 0x10 36#define VTE_PCI_LOMEM 0x14 37 38/* MAC control register 0 */ 39#define VTE_MCR0 0x00 40#define MCR0_ACCPT_ERR 0x0001 41#define MCR0_RX_ENB 0x0002 42#define MCR0_ACCPT_RUNT 0x0004 43#define MCR0_ACCPT_LONG_PKT 0x0008 44#define MCR0_ACCPT_DRIBBLE 0x0010 45#define MCR0_PROMISC 0x0020 46#define MCR0_BROADCAST_DIS 0x0040 47#define MCR0_RX_EARLY_INTR 0x0080 48#define MCR0_MULTICAST 0x0100 49#define MCR0_FC_ENB 0x0200 50#define MCR0_TX_ENB 0x1000 51#define MCR0_TX_EARLY_INTR 0x4000 52#define MCR0_FULL_DUPLEX 0x8000 53 54/* MAC control register 1 */ 55#define VTE_MCR1 0x04 56#define MCR1_MAC_RESET 0x0001 57#define MCR1_MAC_LOOPBACK 0x0002 58#define MCR1_EXCESS_COL_RETRANS_DIS 0x0004 59#define MCR1_AUTO_CHG_DUPLEX 0x0008 60#define MCR1_PKT_LENGTH_1518 0x0010 61#define MCR1_PKT_LENGTH_1522 0x0020 62#define MCR1_PKT_LENGTH_1534 0x0030 63#define MCR1_PKT_LENGTH_1537 0x0000 64#define MCR1_EARLY_INTR_THRESH_1129 0x0000 65#define MCR1_EARLY_INTR_THRESH_1257 0x0040 66#define MCR1_EARLY_INTR_THRESH_1385 0x0080 67#define MCR1_EARLY_INTR_THRESH_1513 0x00C0 68#define MCR1_EXCESS_COL_RETRY_16 0x0000 69#define MCR1_EXCESS_COL_RETRY_32 0x0100 70#define MCR1_FC_ACTIVE 0x0200 71#define MCR1_RX_DESC_HASH_IDX 0x4000 72#define MCR1_RX_UNICAST_HASH 0x8000 73 74#define MCR1_PKT_LENGTH_MASK 0x0030 75#define MCR1_EARLY_INTR_THRESH_MASK 0x00C0 76 77/* MAC bus control register */ 78#define VTE_MBCR 0x08 79#define MBCR_FIFO_XFER_LENGTH_4 0x0000 80#define MBCR_FIFO_XFER_LENGTH_8 0x0001 81#define MBCR_FIFO_XFER_LENGTH_16 0x0002 82#define MBCR_FIFO_XFER_LENGTH_32 0x0003 83#define MBCR_TX_FIFO_THRESH_16 0x0000 84#define MBCR_TX_FIFO_THRESH_32 0x0004 85#define MBCR_TX_FIFO_THRESH_64 0x0008 86#define MBCR_TX_FIFO_THRESH_96 0x000C 87#define MBCR_RX_FIFO_THRESH_8 0x0000 88#define MBCR_RX_FIFO_THRESH_16 0x0010 89#define MBCR_RX_FIFO_THRESH_32 0x0020 90#define MBCR_RX_FIFO_THRESH_64 0x0030 91#define MBCR_SDRAM_BUS_REQ_TIMER_MASK 0x1F00 92#define MBCR_SDRAM_BUS_REQ_TIMER_SHIFT 8 93#define MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT 0x1F00 94 95/* MAC TX interrupt control register */ 96#define VTE_MTICR 0x0C 97#define MTICR_TX_TIMER_MASK 0x001F 98#define MTICR_TX_BUNDLE_MASK 0x0F00 99#define VTE_IM_TX_TIMER_DEFAULT 0x7F 100#define VTE_IM_TX_BUNDLE_DEFAULT 15 101 102#define VTE_IM_TIMER_MIN 0 103#define VTE_IM_TIMER_MAX 82 104#define VTE_IM_TIMER_MASK 0x001F 105#define VTE_IM_TIMER_SHIFT 0 106#define VTE_IM_BUNDLE_MIN 1 107#define VTE_IM_BUNDLE_MAX 15 108#define VTE_IM_BUNDLE_SHIFT 8 109 110/* MAC RX interrupt control register */ 111#define VTE_MRICR 0x10 112#define MRICR_RX_TIMER_MASK 0x001F 113#define MRICR_RX_BUNDLE_MASK 0x0F00 114#define VTE_IM_RX_TIMER_DEFAULT 0x7F 115#define VTE_IM_RX_BUNDLE_DEFAULT 15 116 117/* MAC TX poll command register */ 118#define VTE_TX_POLL 0x14 119#define TX_POLL_START 0x0001 120 121/* MAC RX buffer size register */ 122#define VTE_MRBSR 0x18 123#define VTE_MRBSR_SIZE_MASK 0x03FF 124 125/* MAC RX descriptor control register */ 126#define VTE_MRDCR 0x1A 127#define VTE_MRDCR_RESIDUE_MASK 0x00FF 128#define VTE_MRDCR_RX_PAUSE_THRESH_MASK 0xFF00 129#define VTE_MRDCR_RX_PAUSE_THRESH_SHIFT 8 130 131/* MAC Last status register */ 132#define VTE_MLSR 0x1C 133#define MLSR_MULTICAST 0x0001 134#define MLSR_BROADCAST 0x0002 135#define MLSR_CRC_ERR 0x0004 136#define MLSR_RUNT 0x0008 137#define MLSR_LONG_PKT 0x0010 138#define MLSR_TRUNC 0x0020 139#define MLSR_DRIBBLE 0x0040 140#define MLSR_PHY_ERR 0x0080 141#define MLSR_TX_FIFO_UNDERRUN 0x0200 142#define MLSR_RX_DESC_UNAVAIL 0x0400 143#define MLSR_TX_EXCESS_COL 0x2000 144#define MLSR_TX_LATE_COL 0x4000 145#define MLSR_RX_FIFO_OVERRUN 0x8000 146 147/* MAC MDIO control register */ 148#define VTE_MMDIO 0x20 149#define MMDIO_REG_ADDR_MASK 0x001F 150#define MMDIO_PHY_ADDR_MASK 0x1F00 151#define MMDIO_READ 0x2000 152#define MMDIO_WRITE 0x4000 153#define MMDIO_REG_ADDR_SHIFT 0 154#define MMDIO_PHY_ADDR_SHIFT 8 155 156/* MAC MDIO read data register */ 157#define VTE_MMRD 0x24 158#define MMRD_DATA_MASK 0xFFFF 159 160/* MAC MDIO write data register */ 161#define VTE_MMWD 0x28 162#define MMWD_DATA_MASK 0xFFFF 163 164/* MAC TX descriptor start address 0 */ 165#define VTE_MTDSA0 0x2C 166 167/* MAC TX descriptor start address 1 */ 168#define VTE_MTDSA1 0x30 169 170/* MAC RX descriptor start address 0 */ 171#define VTE_MRDSA0 0x34 172 173/* MAC RX descriptor start address 1 */ 174#define VTE_MRDSA1 0x38 175 176/* MAC Interrupt status register */ 177#define VTE_MISR 0x3C 178#define MISR_RX_DONE 0x0001 179#define MISR_RX_DESC_UNAVAIL 0x0002 180#define MISR_RX_FIFO_FULL 0x0004 181#define MISR_RX_EARLY_INTR 0x0008 182#define MISR_TX_DONE 0x0010 183#define MISR_TX_EARLY_INTR 0x0080 184#define MISR_EVENT_CNT_OFLOW 0x0100 185#define MISR_PHY_MEDIA_CHG 0x0200 186 187/* MAC Interrupt enable register */ 188#define VTE_MIER 0x40 189 190#define VTE_INTRS \ 191 (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | MISR_RX_FIFO_FULL | \ 192 MISR_TX_DONE | MISR_EVENT_CNT_OFLOW) 193 194/* MAC Event counter interrupt status register */ 195#define VTE_MECISR 0x44 196#define MECISR_EC_RX_DONE 0x0001 197#define MECISR_EC_MULTICAST 0x0002 198#define MECISR_EC_BROADCAST 0x0004 199#define MECISR_EC_CRC_ERR 0x0008 200#define MECISR_EC_RUNT 0x0010 201#define MESCIR_EC_LONG_PKT 0x0020 202#define MESCIR_EC_RX_DESC_UNAVAIL 0x0080 203#define MESCIR_EC_RX_FIFO_FULL 0x0100 204#define MESCIR_EC_TX_DONE 0x0200 205#define MESCIR_EC_LATE_COL 0x0400 206#define MESCIR_EC_TX_UNDERRUN 0x0800 207 208/* MAC Event counter interrupt enable register */ 209#define VTE_MECIER 0x48 210#define VTE_MECIER_INTRS \ 211 (MECISR_EC_RX_DONE | MECISR_EC_MULTICAST | MECISR_EC_BROADCAST | \ 212 MECISR_EC_CRC_ERR | MECISR_EC_RUNT | MESCIR_EC_LONG_PKT | \ 213 MESCIR_EC_RX_DESC_UNAVAIL | MESCIR_EC_RX_FIFO_FULL | \ 214 MESCIR_EC_TX_DONE | MESCIR_EC_LATE_COL | MESCIR_EC_TX_UNDERRUN) 215 216#define VTE_CNT_RX_DONE 0x50 217 218#define VTE_CNT_MECNT0 0x52 219 220#define VTE_CNT_MECNT1 0x54 221 222#define VTE_CNT_MECNT2 0x56 223 224#define VTE_CNT_MECNT3 0x58 225 226#define VTE_CNT_TX_DONE 0x5A 227 228#define VTE_CNT_MECNT4 0x5C 229 230#define VTE_CNT_PAUSE 0x5E 231 232/* MAC Hash table register */ 233#define VTE_MAR0 0x60 234#define VTE_MAR1 0x62 235#define VTE_MAR2 0x64 236#define VTE_MAR3 0x66 237 238/* MAC station address and multicast address register */ 239#define VTE_MID0L 0x68 240#define VTE_MID0M 0x6A 241#define VTE_MID0H 0x6C 242#define VTE_MID1L 0x70 243#define VTE_MID1M 0x72 244#define VTE_MID1H 0x74 245#define VTE_MID2L 0x78 246#define VTE_MID2M 0x7A 247#define VTE_MID2H 0x7C 248#define VTE_MID3L 0x80 249#define VTE_MID3M 0x82 250#define VTE_MID3H 0x84 251 252#define VTE_RXFILTER_PEEFECT_BASE VTE_MID1L 253#define VTE_RXFILT_PERFECT_CNT 3 254 255/* MAC PHY status change configuration register */ 256#define VTE_MPSCCR 0x88 257#define MPSCCR_TIMER_DIVIDER_MASK 0x0007 258#define MPSCCR_PHY_ADDR_MASK 0x1F00 259#define MPSCCR_PHY_STS_CHG_ENB 0x8000 260#define MPSCCR_PHY_ADDR_SHIFT 8 261 262/* MAC PHY status register2 */ 263#define VTE_MPSR 0x8A 264#define MPSR_LINK_UP 0x0001 265#define MPSR_SPEED_100 0x0002 266#define MPSR_FULL_DUPLEX 0x0004 267 268/* MAC Status machine(undocumented). */ 269#define VTE_MACSM 0xAC 270 271/* MDC Speed control register */ 272#define VTE_MDCSC 0xB6 273#define MDCSC_DEFAULT 0x0030 274 275/* MAC Identifier and revision register */ 276#define VTE_MACID_REV 0xBC 277#define VTE_MACID_REV_MASK 0x00FF 278#define VTE_MACID_MASK 0xFF00 279#define VTE_MACID_REV_SHIFT 0 280#define VTE_MACID_SHIFT 8 281 282/* MAC Identifier register */ 283#define VTE_MACID 0xBE 284 285/* 286 * RX descriptor 287 * - Added one more uint16_t member to align it 4 on bytes boundary. 288 * This does not affect operation of controller since it includes 289 * next pointer address. 290 */ 291struct vte_rx_desc { 292 uint16_t drst; 293 uint16_t drlen; 294 uint32_t drbp; 295 uint32_t drnp; 296 uint16_t hidx; 297 uint16_t rsvd2; 298 uint16_t rsvd3; 299 uint16_t __pad; /* Not actual descriptor member. */ 300}; 301 302#define VTE_DRST_MID_MASK 0x0003 303#define VTE_DRST_MID_HIT 0x0004 304#define VTE_DRST_MULTICAST_HIT 0x0008 305#define VTE_DRST_MULTICAST 0x0010 306#define VTE_DRST_BROADCAST 0x0020 307#define VTE_DRST_CRC_ERR 0x0040 308#define VTE_DRST_RUNT 0x0080 309#define VTE_DRST_LONG 0x0100 310#define VTE_DRST_TRUNC 0x0200 311#define VTE_DRST_DRIBBLE 0x0400 312#define VTE_DRST_PHY_ERR 0x0800 313#define VTE_DRST_RX_OK 0x4000 314#define VTE_DRST_RX_OWN 0x8000 315 316#define VTE_RX_LEN(x) ((x) & 0x7FF) 317 318#define VTE_RX_HIDX(x) ((x) & 0x3F) 319 320/* 321 * TX descriptor 322 * - Added one more uint32_t member to align it on 16 bytes boundary. 323 */ 324struct vte_tx_desc { 325 uint16_t dtst; 326 uint16_t dtlen; 327 uint32_t dtbp; 328 uint32_t dtnp; 329 uint32_t __pad; /* Not actual descriptor member. */ 330}; 331 332#define VTE_DTST_EXCESS_COL 0x0010 333#define VTE_DTST_LATE_COL 0x0020 334#define VTE_DTST_UNDERRUN 0x0040 335#define VTE_DTST_NO_CRC 0x2000 336#define VTE_DTST_TX_OK 0x4000 337#define VTE_DTST_TX_OWN 0x8000 338 339#define VTE_TX_LEN(x) ((x) & 0x7FF) 340 341#define VTE_TX_RING_CNT 64 342#define VTE_TX_RING_ALIGN 16 343/* 344 * The TX/RX descriptor format has no limitation for number of 345 * descriptors in TX/RX ring. However, the maximum number of 346 * descriptors that could be set as RX descriptor ring residue 347 * counter is 255. This effectively limits number of RX 348 * descriptors available to be less than or equal to 255. 349 */ 350#define VTE_RX_RING_CNT 128 351#define VTE_RX_RING_ALIGN 16 352#define VTE_RX_BUF_ALIGN 4 353 354#define VTE_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 355 356#define VTE_TX_RING_SZ \ 357 (sizeof(struct vte_tx_desc) * VTE_TX_RING_CNT) 358#define VTE_RX_RING_SZ \ 359 (sizeof(struct vte_rx_desc) * VTE_RX_RING_CNT) 360 361#define VTE_RX_BUF_SIZE_MAX (MCLBYTES - sizeof(uint32_t)) 362 363#define VTE_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 364 365struct vte_rxdesc { 366 struct mbuf *rx_m; 367 bus_dmamap_t rx_dmamap; 368 struct vte_rx_desc *rx_desc; 369}; 370 371struct vte_txdesc { 372 struct mbuf *tx_m; 373 bus_dmamap_t tx_dmamap; 374 struct vte_tx_desc *tx_desc; 375 int tx_flags; 376#define VTE_TXMBUF 0x0001 377}; 378 379struct vte_chain_data { 380 struct vte_txdesc vte_txdesc[VTE_TX_RING_CNT]; 381 struct mbuf *vte_txmbufs[VTE_TX_RING_CNT]; 382 struct vte_rxdesc vte_rxdesc[VTE_RX_RING_CNT]; 383 bus_dmamap_t vte_tx_ring_map; 384 bus_dma_segment_t vte_tx_ring_seg; 385 bus_dmamap_t vte_rx_ring_map; 386 bus_dma_segment_t vte_rx_ring_seg; 387 bus_dmamap_t vte_rr_ring_map; 388 bus_dma_segment_t vte_rr_ring_seg; 389 bus_dmamap_t vte_rx_sparemap; 390 bus_dmamap_t vte_cmb_map; 391 bus_dma_segment_t vte_cmb_seg; 392 bus_dmamap_t vte_smb_map; 393 bus_dma_segment_t vte_smb_seg; 394 struct vte_tx_desc *vte_tx_ring; 395 bus_addr_t vte_tx_ring_paddr; 396 struct vte_rx_desc *vte_rx_ring; 397 bus_addr_t vte_rx_ring_paddr; 398 399 int vte_tx_prod; 400 int vte_tx_cons; 401 int vte_tx_cnt; 402 int vte_rx_cons; 403}; 404 405struct vte_hw_stats { 406 /* RX stats. */ 407 uint32_t rx_frames; 408 uint32_t rx_bcast_frames; 409 uint32_t rx_mcast_frames; 410 uint32_t rx_runts; 411 uint32_t rx_crcerrs; 412 uint32_t rx_long_frames; 413 uint32_t rx_fifo_full; 414 uint32_t rx_desc_unavail; 415 uint32_t rx_pause_frames; 416 417 /* TX stats. */ 418 uint32_t tx_frames; 419 uint32_t tx_underruns; 420 uint32_t tx_late_colls; 421 uint32_t tx_pause_frames; 422}; 423 424/* 425 * Software state per device. 426 */ 427struct vte_softc { 428 struct device sc_dev; 429 struct arpcom sc_arpcom; 430 bus_space_tag_t sc_mem_bt; 431 bus_space_handle_t sc_mem_bh; 432 bus_size_t sc_mem_size; 433 bus_dma_tag_t sc_dmat; 434 pci_chipset_tag_t sc_pct; 435 pcitag_t sc_pcitag; 436 void *sc_irq_handle; 437 struct mii_data sc_miibus; 438 uint8_t vte_eaddr[ETHER_ADDR_LEN]; 439 int vte_flags; 440#define VTE_FLAG_LINK 0x8000 441 442 struct timeout vte_tick_ch; 443 struct vte_hw_stats vte_stats; 444 struct vte_chain_data vte_cdata; 445 int vte_int_rx_mod; 446 int vte_int_tx_mod; 447}; 448 449/* Register access macros. */ 450#define CSR_WRITE_2(_sc, reg, val) \ 451 bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 452#define CSR_READ_2(_sc, reg) \ 453 bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 454 455#define VTE_TX_TIMEOUT 5 456#define VTE_RESET_TIMEOUT 100 457#define VTE_TIMEOUT 1000 458#define VTE_PHY_TIMEOUT 1000 459 460#endif /* _IF_VTEREG_H */ 461