if_skreg.h revision 1.41
1/* $OpenBSD: if_skreg.h,v 1.41 2006/11/23 21:56:32 kettenis Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_skreg.h,v 1.9 2000/04/22 02:16:37 wpaul Exp $ 35 * $FreeBSD: /c/ncvs/src/sys/pci/xmaciireg.h,v 1.3 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38/* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54/* 55 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 56 * but internally it has a 16K register space. This 16K space is 57 * divided into 128-byte blocks. The first 128 bytes of the I/O 58 * window represent the first block, which is permanently mapped 59 * at the start of the window. The other 127 blocks can be mapped 60 * to the second 128 bytes of the I/O window by setting the desired 61 * block value in the RAP register in block 0. Not all of the 127 62 * blocks are actually used. Most registers are 32 bits wide, but 63 * there are a few 16-bit and 8-bit ones as well. 64 */ 65 66/* Start of remappable register window. */ 67#define SK_WIN_BASE 0x0080 68 69/* Size of a window */ 70#define SK_WIN_LEN 0x80 71 72#define SK_WIN_MASK 0x3F80 73#define SK_REG_MASK 0x7F 74 75/* Compute the window of a given register (for the RAP register) */ 76#define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 77 78/* Compute the relative offset of a register within the window */ 79#define SK_REG(reg) ((reg) & SK_REG_MASK) 80 81#define SK_PORT_A 0 82#define SK_PORT_B 1 83 84/* 85 * Compute offset of port-specific register. Since there are two 86 * ports, there are two of some GEnesis modules (e.g. two sets of 87 * DMA queues, two sets of FIFO control registers, etc...). Normally, 88 * the block for port 0 is at offset 0x0 and the block for port 1 is 89 * at offset 0x80 (i.e. the next page over). However for the transmit 90 * BMUs and RAMbuffers, there are two blocks for each port: one for 91 * the sync transmit queue and one for the async queue (which we don't 92 * use). However instead of ordering them like this: 93 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 94 * SysKonnect has instead ordered them like this: 95 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 96 * This means that when referencing the TX BMU and RAMbuffer registers, 97 * we have to double the block offset (0x80 * 2) in order to reach the 98 * second queue. This prevents us from using the same formula 99 * (sk_port * 0x80) to compute the offsets for all of the port-specific 100 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 101 * The simplest thing is to provide an extra argument to these macros: 102 * the 'skip' parameter. The 'skip' value is the number of extra pages 103 * for skip when computing the port0/port1 offsets. For most registers, 104 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 105 */ 106#define SK_IF_READ_4(sc_if, skip, reg) \ 107 sk_win_read_4(sc_if->sk_softc, reg + \ 108 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 109#define SK_IF_READ_2(sc_if, skip, reg) \ 110 sk_win_read_2(sc_if->sk_softc, reg + \ 111 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 112#define SK_IF_READ_1(sc_if, skip, reg) \ 113 sk_win_read_1(sc_if->sk_softc, reg + \ 114 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 115 116#define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 117 sk_win_write_4(sc_if->sk_softc, \ 118 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 119#define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 120 sk_win_write_2(sc_if->sk_softc, \ 121 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 122#define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 123 sk_win_write_1(sc_if->sk_softc, \ 124 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 125 126/* Block 0 registers, permanently mapped at iobase. */ 127#define SK_RAP 0x0000 128#define SK_CSR 0x0004 129#define SK_LED 0x0006 130#define SK_ISR 0x0008 /* interrupt source */ 131#define SK_IMR 0x000C /* interrupt mask */ 132#define SK_IESR 0x0010 /* interrupt hardware error source */ 133#define SK_IEMR 0x0014 /* interrupt hardware error mask */ 134#define SK_ISSR 0x0018 /* special interrupt source */ 135#define SK_Y2_ISSR2 0x001C 136#define SK_Y2_ISSR3 0x0020 137#define SK_Y2_EISR 0x0024 138#define SK_Y2_LISR 0x0028 139#define SK_Y2_ICR 0x002C 140#define SK_XM_IMR0 0x0020 141#define SK_XM_ISR0 0x0028 142#define SK_XM_PHYADDR0 0x0030 143#define SK_XM_PHYDATA0 0x0034 144#define SK_XM_IMR1 0x0040 145#define SK_XM_ISR1 0x0048 146#define SK_XM_PHYADDR1 0x0050 147#define SK_XM_PHYDATA1 0x0054 148#define SK_BMU_RX_CSR0 0x0060 149#define SK_BMU_RX_CSR1 0x0064 150#define SK_BMU_TXS_CSR0 0x0068 151#define SK_BMU_TXA_CSR0 0x006C 152#define SK_BMU_TXS_CSR1 0x0070 153#define SK_BMU_TXA_CSR1 0x0074 154 155/* SK_CSR register */ 156#define SK_CSR_SW_RESET 0x0001 157#define SK_CSR_SW_UNRESET 0x0002 158#define SK_CSR_MASTER_RESET 0x0004 159#define SK_CSR_MASTER_UNRESET 0x0008 160#define SK_CSR_MASTER_STOP 0x0010 161#define SK_CSR_MASTER_DONE 0x0020 162#define SK_CSR_SW_IRQ_CLEAR 0x0040 163#define SK_CSR_SW_IRQ_SET 0x0080 164#define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 165#define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 MHz, = 33 */ 166#define SK_CSR_ASF_OFF 0x1000 167#define SK_CSR_ASF_ON 0x2000 168 169/* SK_LED register */ 170#define SK_LED_GREEN_OFF 0x01 171#define SK_LED_GREEN_ON 0x02 172 173/* SK_ISR register */ 174#define SK_ISR_TX2_AS_CHECK 0x00000001 175#define SK_ISR_TX2_AS_EOF 0x00000002 176#define SK_ISR_TX2_AS_EOB 0x00000004 177#define SK_ISR_TX2_S_CHECK 0x00000008 178#define SK_ISR_TX2_S_EOF 0x00000010 179#define SK_ISR_TX2_S_EOB 0x00000020 180#define SK_ISR_TX1_AS_CHECK 0x00000040 181#define SK_ISR_TX1_AS_EOF 0x00000080 182#define SK_ISR_TX1_AS_EOB 0x00000100 183#define SK_ISR_TX1_S_CHECK 0x00000200 184#define SK_ISR_TX1_S_EOF 0x00000400 185#define SK_ISR_TX1_S_EOB 0x00000800 186#define SK_ISR_RX2_CHECK 0x00001000 187#define SK_ISR_RX2_EOF 0x00002000 188#define SK_ISR_RX2_EOB 0x00004000 189#define SK_ISR_RX1_CHECK 0x00008000 190#define SK_ISR_RX1_EOF 0x00010000 191#define SK_ISR_RX1_EOB 0x00020000 192#define SK_ISR_LINK2_OFLOW 0x00040000 193#define SK_ISR_MAC2 0x00080000 194#define SK_ISR_LINK1_OFLOW 0x00100000 195#define SK_ISR_MAC1 0x00200000 196#define SK_ISR_TIMER 0x00400000 197#define SK_ISR_EXTERNAL_REG 0x00800000 198#define SK_ISR_SW 0x01000000 199#define SK_ISR_I2C_RDY 0x02000000 200#define SK_ISR_TX2_TIMEO 0x04000000 201#define SK_ISR_TX1_TIMEO 0x08000000 202#define SK_ISR_RX2_TIMEO 0x10000000 203#define SK_ISR_RX1_TIMEO 0x20000000 204#define SK_ISR_RSVD 0x40000000 205#define SK_ISR_HWERR 0x80000000 206 207/* SK_IMR register */ 208#define SK_IMR_TX2_AS_CHECK 0x00000001 209#define SK_IMR_TX2_AS_EOF 0x00000002 210#define SK_IMR_TX2_AS_EOB 0x00000004 211#define SK_IMR_TX2_S_CHECK 0x00000008 212#define SK_IMR_TX2_S_EOF 0x00000010 213#define SK_IMR_TX2_S_EOB 0x00000020 214#define SK_IMR_TX1_AS_CHECK 0x00000040 215#define SK_IMR_TX1_AS_EOF 0x00000080 216#define SK_IMR_TX1_AS_EOB 0x00000100 217#define SK_IMR_TX1_S_CHECK 0x00000200 218#define SK_IMR_TX1_S_EOF 0x00000400 219#define SK_IMR_TX1_S_EOB 0x00000800 220#define SK_IMR_RX2_CHECK 0x00001000 221#define SK_IMR_RX2_EOF 0x00002000 222#define SK_IMR_RX2_EOB 0x00004000 223#define SK_IMR_RX1_CHECK 0x00008000 224#define SK_IMR_RX1_EOF 0x00010000 225#define SK_IMR_RX1_EOB 0x00020000 226#define SK_IMR_LINK2_OFLOW 0x00040000 227#define SK_IMR_MAC2 0x00080000 228#define SK_IMR_LINK1_OFLOW 0x00100000 229#define SK_IMR_MAC1 0x00200000 230#define SK_IMR_TIMER 0x00400000 231#define SK_IMR_EXTERNAL_REG 0x00800000 232#define SK_IMR_SW 0x01000000 233#define SK_IMR_I2C_RDY 0x02000000 234#define SK_IMR_TX2_TIMEO 0x04000000 235#define SK_IMR_TX1_TIMEO 0x08000000 236#define SK_IMR_RX2_TIMEO 0x10000000 237#define SK_IMR_RX1_TIMEO 0x20000000 238#define SK_IMR_RSVD 0x40000000 239#define SK_IMR_HWERR 0x80000000 240 241#define SK_INTRS1 \ 242 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 243 244#define SK_INTRS2 \ 245 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 246 247#define SK_Y2_IMR_TX1_AS_CHECK 0x00000001 248#define SK_Y2_IMR_TX1_S_CHECK 0x00000002 249#define SK_Y2_IMR_RX1_CHECK 0x00000004 250#define SK_Y2_IMR_MAC1 0x00000008 251#define SK_Y2_IMR_PHY1 0x00000010 252#define SK_Y2_IMR_TX2_AS_CHECK 0x00000100 253#define SK_Y2_IMR_TX2_S_CHECK 0x00000200 254#define SK_Y2_IMR_RX2_CHECK 0x00000400 255#define SK_Y2_IMR_MAC2 0x00000800 256#define SK_Y2_IMR_PHY2 0x00001000 257#define SK_Y2_IMR_TIMER 0x01000000 258#define SK_Y2_IMR_SW 0x02000000 259#define SK_Y2_IMR_ASF 0x20000000 260#define SK_Y2_IMR_BMU 0x40000000 261#define SK_Y2_IMR_HWERR 0x80000000 262 263#define SK_Y2_INTRS1 \ 264 (SK_Y2_IMR_RX1_CHECK|SK_Y2_IMR_TX1_AS_CHECK \ 265 |SK_Y2_IMR_MAC1|SK_Y2_IMR_PHY1) 266 267#define SK_Y2_INTRS2 \ 268 (SK_Y2_IMR_RX2_CHECK|SK_Y2_IMR_TX2_AS_CHECK \ 269 |SK_Y2_IMR_MAC2|SK_Y2_IMR_PHY2) 270 271/* SK_IESR register */ 272#define SK_IESR_PAR_RX2 0x00000001 273#define SK_IESR_PAR_RX1 0x00000002 274#define SK_IESR_PAR_MAC2 0x00000004 275#define SK_IESR_PAR_MAC1 0x00000008 276#define SK_IESR_PAR_WR_RAM 0x00000010 277#define SK_IESR_PAR_RD_RAM 0x00000020 278#define SK_IESR_NO_TSTAMP_MAC2 0x00000040 279#define SK_IESR_NO_TSTAMO_MAC1 0x00000080 280#define SK_IESR_NO_STS_MAC2 0x00000100 281#define SK_IESR_NO_STS_MAC1 0x00000200 282#define SK_IESR_IRQ_STS 0x00000400 283#define SK_IESR_MASTERERR 0x00000800 284 285/* SK_IEMR register */ 286#define SK_IEMR_PAR_RX2 0x00000001 287#define SK_IEMR_PAR_RX1 0x00000002 288#define SK_IEMR_PAR_MAC2 0x00000004 289#define SK_IEMR_PAR_MAC1 0x00000008 290#define SK_IEMR_PAR_WR_RAM 0x00000010 291#define SK_IEMR_PAR_RD_RAM 0x00000020 292#define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 293#define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 294#define SK_IEMR_NO_STS_MAC2 0x00000100 295#define SK_IEMR_NO_STS_MAC1 0x00000200 296#define SK_IEMR_IRQ_STS 0x00000400 297#define SK_IEMR_MASTERERR 0x00000800 298 299/* Block 2 */ 300#define SK_MAC0_0 0x0100 301#define SK_MAC0_1 0x0104 302#define SK_MAC1_0 0x0108 303#define SK_MAC1_1 0x010C 304#define SK_MAC2_0 0x0110 305#define SK_MAC2_1 0x0114 306#define SK_CONNTYPE 0x0118 307#define SK_PMDTYPE 0x0119 308#define SK_CONFIG 0x011A 309#define SK_CHIPVER 0x011B 310#define SK_EPROM0 0x011C 311#define SK_EPROM1 0x011D /* yukon/genesis */ 312#define SK_Y2_CLKGATE 0x011D /* yukon 2 */ 313#define SK_EPROM2 0x011E /* yukon/genesis */ 314#define SK_Y2_HWRES 0x011E /* yukon 2 */ 315#define SK_EPROM3 0x011F 316#define SK_EP_ADDR 0x0120 317#define SK_EP_DATA 0x0124 318#define SK_EP_LOADCTL 0x0128 319#define SK_EP_LOADTST 0x0129 320#define SK_TIMERINIT 0x0130 321#define SK_TIMER 0x0134 322#define SK_TIMERCTL 0x0138 323#define SK_TIMERTST 0x0139 324#define SK_IMTIMERINIT 0x0140 325#define SK_IMTIMER 0x0144 326#define SK_IMTIMERCTL 0x0148 327#define SK_IMTIMERTST 0x0149 328#define SK_IMMR 0x014C 329#define SK_IHWEMR 0x0150 330#define SK_TESTCTL1 0x0158 331#define SK_TESTCTL2 0x0159 332#define SK_GPIO 0x015C 333#define SK_I2CHWCTL 0x0160 334#define SK_I2CHWDATA 0x0164 335#define SK_I2CHWIRQ 0x0168 336#define SK_I2CSW 0x016C 337#define SK_BLNKINIT 0x0170 338#define SK_BLNKCOUNT 0x0174 339#define SK_BLNKCTL 0x0178 340#define SK_BLNKSTS 0x0179 341#define SK_BLNKTST 0x017A 342 343/* Values for SK_CHIPVER */ 344#define SK_GENESIS 0x0A 345#define SK_YUKON 0xB0 346#define SK_YUKON_LITE 0xB1 347#define SK_YUKON_LP 0xB2 348#define SK_YUKON_XL 0xB3 349#define SK_YUKON_EC_U 0xB4 350#define SK_YUKON_EC 0xB6 351#define SK_YUKON_FE 0xB7 352 353#define SK_IS_GENESIS(sc) \ 354 ((sc)->sk_type == SK_GENESIS) 355#define SK_IS_YUKON(sc) \ 356 ((sc)->sk_type >= SK_YUKON && (sc)->sk_type <= SK_YUKON_LP) 357#define SK_IS_YUKON2(sc) \ 358 ((sc)->sk_type >= SK_YUKON_XL && (sc)->sk_type <= SK_YUKON_FE) 359 360/* Known revisions in SK_CONFIG */ 361#define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach */ 362#define SK_YUKON_LITE_REV_A1 0x3 363#define SK_YUKON_LITE_REV_A3 0x7 364 365#define SK_YUKON_XL_REV_A0 0x0 366#define SK_YUKON_XL_REV_A1 0x1 367#define SK_YUKON_XL_REV_A2 0x2 368#define SK_YUKON_XL_REV_A3 0x3 369 370#define SK_YUKON_EC_REV_A1 0x0 371#define SK_YUKON_EC_REV_A2 0x1 372#define SK_YUKON_EC_REV_A3 0x2 373 374#define SK_YUKON_EC_U_REV_A0 0x1 375#define SK_YUKON_EC_U_REV_A1 0x2 376 377#define SK_IMCTL_IRQ_CLEAR 0x01 378#define SK_IMCTL_STOP 0x02 379#define SK_IMCTL_START 0x04 380 381/* Number of ticks per usec for interrupt moderation */ 382#define SK_IMTIMER_TICKS_GENESIS 53 383#define SK_IMTIMER_TICKS_YUKON 78 384#define SK_IMTIMER_TICKS_YUKON_EC 125 385#define SK_IM_USECS(x) ((x) * imtimer_ticks) 386 387/* 388 * The SK_EPROM0 register contains a byte that describes the 389 * amount of SRAM mounted on the NIC. The value also tells if 390 * the chips are 64K or 128K. This affects the RAMbuffer address 391 * offset that we need to use. 392 */ 393#define SK_RAMSIZE_512K_64 0x1 394#define SK_RAMSIZE_1024K_128 0x2 395#define SK_RAMSIZE_1024K_64 0x3 396#define SK_RAMSIZE_2048K_128 0x4 397 398#define SK_RBOFF_0 0x0 399#define SK_RBOFF_80000 0x80000 400 401/* 402 * SK_EEPROM1 contains the PHY type, which may be XMAC for 403 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 404 * PHY. 405 */ 406#define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 407#define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 408#define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 409#define SK_PHYTYPE_NAT 3 /* National DP83891 */ 410#define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ 411#define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ 412 413/* 414 * PHY addresses. 415 */ 416#define SK_PHYADDR_XMAC 0x0 417#define SK_PHYADDR_BCOM 0x1 418#define SK_PHYADDR_LONE 0x3 419#define SK_PHYADDR_NAT 0x0 420#define SK_PHYADDR_MARV 0x0 421 422#define SK_CONFIG_SINGLEMAC 0x01 423#define SK_CONFIG_DIS_DSL_CLK 0x02 424 425#define SK_PMD_1000BASETX_ALT 0x31 426#define SK_PMD_1000BASECX 0x43 427#define SK_PMD_1000BASELX 0x4C 428#define SK_PMD_1000BASESX 0x53 429#define SK_PMD_1000BASETX 0x54 430 431/* GPIO bits */ 432#define SK_GPIO_DAT0 0x00000001 433#define SK_GPIO_DAT1 0x00000002 434#define SK_GPIO_DAT2 0x00000004 435#define SK_GPIO_DAT3 0x00000008 436#define SK_GPIO_DAT4 0x00000010 437#define SK_GPIO_DAT5 0x00000020 438#define SK_GPIO_DAT6 0x00000040 439#define SK_GPIO_DAT7 0x00000080 440#define SK_GPIO_DAT8 0x00000100 441#define SK_GPIO_DAT9 0x00000200 442#define SK_GPIO_DIR0 0x00010000 443#define SK_GPIO_DIR1 0x00020000 444#define SK_GPIO_DIR2 0x00040000 445#define SK_GPIO_DIR3 0x00080000 446#define SK_GPIO_DIR4 0x00100000 447#define SK_GPIO_DIR5 0x00200000 448#define SK_GPIO_DIR6 0x00400000 449#define SK_GPIO_DIR7 0x00800000 450#define SK_GPIO_DIR8 0x01000000 451#define SK_GPIO_DIR9 0x02000000 452 453#define SK_Y2_CLKGATE_LINK2_INACTIVE 0x80 /* port 2 inactive */ 454#define SK_Y2_CLKGATE_LINK2_GATE_DIS 0x40 /* disable clock gate, 2 */ 455#define SK_Y2_CLKGATE_LINK2_CORE_DIS 0x20 /* disable core clock, 2 */ 456#define SK_Y2_CLKGATE_LINK2_PCI_DIS 0x10 /* disable pci clock, 2 */ 457#define SK_Y2_CLKGATE_LINK1_INACTIVE 0x08 /* port 1 inactive */ 458#define SK_Y2_CLKGATE_LINK1_GATE_DIS 0x04 /* disable clock gate, 1 */ 459#define SK_Y2_CLKGATE_LINK1_CORE_DIS 0x02 /* disable core clock, 1 */ 460#define SK_Y2_CLKGATE_LINK1_PCI_DIS 0x01 /* disable pci clock, 1 */ 461 462#define SK_Y2_HWRES_LINK_1 0x01 463#define SK_Y2_HWRES_LINK_2 0x02 464#define SK_Y2_HWRES_LINK_MASK (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2) 465#define SK_Y2_HWRES_LINK_DUAL (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2) 466 467/* Block 3 Ram interface and MAC arbiter registers */ 468#define SK_RAMADDR 0x0180 469#define SK_RAMDATA0 0x0184 470#define SK_RAMDATA1 0x0188 471#define SK_TO0 0x0190 472#define SK_TO1 0x0191 473#define SK_TO2 0x0192 474#define SK_TO3 0x0193 475#define SK_TO4 0x0194 476#define SK_TO5 0x0195 477#define SK_TO6 0x0196 478#define SK_TO7 0x0197 479#define SK_TO8 0x0198 480#define SK_TO9 0x0199 481#define SK_TO10 0x019A 482#define SK_TO11 0x019B 483#define SK_RITIMEO_TMR 0x019C 484#define SK_RAMCTL 0x01A0 485#define SK_RITIMER_TST 0x01A2 486 487#define SK_RAMCTL_RESET 0x0001 488#define SK_RAMCTL_UNRESET 0x0002 489#define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 490#define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 491 492/* Mac arbiter registers */ 493#define SK_MINIT_RX1 0x01B0 494#define SK_MINIT_RX2 0x01B1 495#define SK_MINIT_TX1 0x01B2 496#define SK_MINIT_TX2 0x01B3 497#define SK_MTIMEO_RX1 0x01B4 498#define SK_MTIMEO_RX2 0x01B5 499#define SK_MTIMEO_TX1 0x01B6 500#define SK_MTIEMO_TX2 0x01B7 501#define SK_MACARB_CTL 0x01B8 502#define SK_MTIMER_TST 0x01BA 503#define SK_RCINIT_RX1 0x01C0 504#define SK_RCINIT_RX2 0x01C1 505#define SK_RCINIT_TX1 0x01C2 506#define SK_RCINIT_TX2 0x01C3 507#define SK_RCTIMEO_RX1 0x01C4 508#define SK_RCTIMEO_RX2 0x01C5 509#define SK_RCTIMEO_TX1 0x01C6 510#define SK_RCTIMEO_TX2 0x01C7 511#define SK_RECOVERY_CTL 0x01C8 512#define SK_RCTIMER_TST 0x01CA 513 514/* Packet arbiter registers */ 515#define SK_RXPA1_TINIT 0x01D0 516#define SK_RXPA2_TINIT 0x01D4 517#define SK_TXPA1_TINIT 0x01D8 518#define SK_TXPA2_TINIT 0x01DC 519#define SK_RXPA1_TIMEO 0x01E0 520#define SK_RXPA2_TIMEO 0x01E4 521#define SK_TXPA1_TIMEO 0x01E8 522#define SK_TXPA2_TIMEO 0x01EC 523#define SK_PKTARB_CTL 0x01F0 524#define SK_PKTATB_TST 0x01F2 525 526#define SK_PKTARB_TIMEOUT 0x2000 527 528#define SK_PKTARBCTL_RESET 0x0001 529#define SK_PKTARBCTL_UNRESET 0x0002 530#define SK_PKTARBCTL_RXTO1_OFF 0x0004 531#define SK_PKTARBCTL_RXTO1_ON 0x0008 532#define SK_PKTARBCTL_RXTO2_OFF 0x0010 533#define SK_PKTARBCTL_RXTO2_ON 0x0020 534#define SK_PKTARBCTL_TXTO1_OFF 0x0040 535#define SK_PKTARBCTL_TXTO1_ON 0x0080 536#define SK_PKTARBCTL_TXTO2_OFF 0x0100 537#define SK_PKTARBCTL_TXTO2_ON 0x0200 538#define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 539#define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 540#define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 541#define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 542 543#define SK_MINIT_XMAC_B2 54 544#define SK_MINIT_XMAC_C1 63 545 546#define SK_MACARBCTL_RESET 0x0001 547#define SK_MACARBCTL_UNRESET 0x0002 548#define SK_MACARBCTL_FASTOE_OFF 0x0004 549#define SK_MACARBCRL_FASTOE_ON 0x0008 550 551#define SK_RCINIT_XMAC_B2 54 552#define SK_RCINIT_XMAC_C1 0 553 554#define SK_RECOVERYCTL_RX1_OFF 0x0001 555#define SK_RECOVERYCTL_RX1_ON 0x0002 556#define SK_RECOVERYCTL_RX2_OFF 0x0004 557#define SK_RECOVERYCTL_RX2_ON 0x0008 558#define SK_RECOVERYCTL_TX1_OFF 0x0010 559#define SK_RECOVERYCTL_TX1_ON 0x0020 560#define SK_RECOVERYCTL_TX2_OFF 0x0040 561#define SK_RECOVERYCTL_TX2_ON 0x0080 562 563#define SK_RECOVERY_XMAC_B2 \ 564 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 565 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 566 567#define SK_RECOVERY_XMAC_C1 \ 568 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 569 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 570 571/* Block 4 -- TX Arbiter MAC 1 */ 572#define SK_TXAR1_TIMERINIT 0x0200 573#define SK_TXAR1_TIMERVAL 0x0204 574#define SK_TXAR1_LIMITINIT 0x0208 575#define SK_TXAR1_LIMITCNT 0x020C 576#define SK_TXAR1_COUNTERCTL 0x0210 577#define SK_TXAR1_COUNTERTST 0x0212 578#define SK_TXAR1_COUNTERSTS 0x0212 579 580/* Block 5 -- TX Arbiter MAC 2 */ 581#define SK_TXAR2_TIMERINIT 0x0280 582#define SK_TXAR2_TIMERVAL 0x0284 583#define SK_TXAR2_LIMITINIT 0x0288 584#define SK_TXAR2_LIMITCNT 0x028C 585#define SK_TXAR2_COUNTERCTL 0x0290 586#define SK_TXAR2_COUNTERTST 0x0291 587#define SK_TXAR2_COUNTERSTS 0x0292 588 589#define SK_TXARCTL_OFF 0x01 590#define SK_TXARCTL_ON 0x02 591#define SK_TXARCTL_RATECTL_OFF 0x04 592#define SK_TXARCTL_RATECTL_ON 0x08 593#define SK_TXARCTL_ALLOC_OFF 0x10 594#define SK_TXARCTL_ALLOC_ON 0x20 595#define SK_TXARCTL_FSYNC_OFF 0x40 596#define SK_TXARCTL_FSYNC_ON 0x80 597 598/* Block 6 -- External registers */ 599#define SK_EXTREG_BASE 0x300 600#define SK_EXTREG_END 0x37C 601 602/* Block 7 -- PCI config registers */ 603#define SK_PCI_BASE 0x0380 604#define SK_PCI_END 0x03FC 605 606/* Compute offset of mirrored PCI register */ 607#define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 608 609/* Block 8 -- RX queue 1 */ 610#define SK_RXQ1_BUFCNT 0x0400 611#define SK_RXQ1_BUFCTL 0x0402 612#define SK_RXQ1_NEXTDESC 0x0404 613#define SK_RXQ1_RXBUF_LO 0x0408 614#define SK_RXQ1_RXBUF_HI 0x040C 615#define SK_RXQ1_RXSTAT 0x0410 616#define SK_RXQ1_TIMESTAMP 0x0414 617#define SK_RXQ1_CSUM1 0x0418 618#define SK_RXQ1_CSUM2 0x041A 619#define SK_RXQ1_CSUM1_START 0x041C 620#define SK_RXQ1_CSUM2_START 0x041E 621#define SK_RXQ1_CURADDR_LO 0x0420 622#define SK_RXQ1_CURADDR_HI 0x0424 623#define SK_RXQ1_CURCNT_LO 0x0428 624#define SK_RXQ1_CURCNT_HI 0x042C 625#define SK_RXQ1_CURBYTES 0x0430 626#define SK_RXQ1_BMU_CSR 0x0434 627#define SK_RXQ1_WATERMARK 0x0438 628#define SK_RXQ1_FLAG 0x043A 629#define SK_RXQ1_TEST1 0x043C 630#define SK_RXQ1_TEST2 0x0440 631#define SK_RXQ1_TEST3 0x0444 632/* yukon-2 only */ 633#define SK_RXQ1_Y2_WM 0x0440 634#define SK_RXQ1_Y2_AL 0x0442 635#define SK_RXQ1_Y2_RSP 0x0444 636#define SK_RXQ1_Y2_RSL 0x0446 637#define SK_RXQ1_Y2_RP 0x0448 638#define SK_RXQ1_Y2_RL 0x044A 639#define SK_RXQ1_Y2_WP 0x044C 640#define SK_RXQ1_Y2_WSP 0x044D 641#define SK_RXQ1_Y2_WL 0x044E 642#define SK_RXQ1_Y2_WSL 0x044F 643/* yukon-2 only (prefetch unit) */ 644#define SK_RXQ1_Y2_PREF_CSR 0x0450 645#define SK_RXQ1_Y2_PREF_LIDX 0x0454 646#define SK_RXQ1_Y2_PREF_ADDRLO 0x0458 647#define SK_RXQ1_Y2_PREF_ADDRHI 0x045C 648#define SK_RXQ1_Y2_PREF_GETIDX 0x0460 649#define SK_RXQ1_Y2_PREF_PUTIDX 0x0464 650#define SK_RXQ1_Y2_PREF_FIFOWP 0x0470 651#define SK_RXQ1_Y2_PREF_FIFORP 0x0474 652#define SK_RXQ1_Y2_PREF_FIFOWM 0x0478 653#define SK_RXQ1_Y2_PREF_FIFOLV 0x047C 654 655/* Block 9 -- RX queue 2 */ 656#define SK_RXQ2_BUFCNT 0x0480 657#define SK_RXQ2_BUFCTL 0x0482 658#define SK_RXQ2_NEXTDESC 0x0484 659#define SK_RXQ2_RXBUF_LO 0x0488 660#define SK_RXQ2_RXBUF_HI 0x048C 661#define SK_RXQ2_RXSTAT 0x0490 662#define SK_RXQ2_TIMESTAMP 0x0494 663#define SK_RXQ2_CSUM1 0x0498 664#define SK_RXQ2_CSUM2 0x049A 665#define SK_RXQ2_CSUM1_START 0x049C 666#define SK_RXQ2_CSUM2_START 0x049E 667#define SK_RXQ2_CURADDR_LO 0x04A0 668#define SK_RXQ2_CURADDR_HI 0x04A4 669#define SK_RXQ2_CURCNT_LO 0x04A8 670#define SK_RXQ2_CURCNT_HI 0x04AC 671#define SK_RXQ2_CURBYTES 0x04B0 672#define SK_RXQ2_BMU_CSR 0x04B4 673#define SK_RXQ2_WATERMARK 0x04B8 674#define SK_RXQ2_FLAG 0x04BA 675#define SK_RXQ2_TEST1 0x04BC 676#define SK_RXQ2_TEST2 0x04C0 677#define SK_RXQ2_TEST3 0x04C4 678/* yukon-2 only */ 679#define SK_RXQ2_Y2_WM 0x04C0 680#define SK_RXQ2_Y2_AL 0x04C2 681#define SK_RXQ2_Y2_RSP 0x04C4 682#define SK_RXQ2_Y2_RSL 0x04C6 683#define SK_RXQ2_Y2_RP 0x04C8 684#define SK_RXQ2_Y2_RL 0x04CA 685#define SK_RXQ2_Y2_WP 0x04CC 686#define SK_RXQ2_Y2_WSP 0x04CD 687#define SK_RXQ2_Y2_WL 0x04CE 688#define SK_RXQ2_Y2_WSL 0x04CF 689/* yukon-2 only (prefetch unit) */ 690#define SK_RXQ2_Y2_PREF_CSR 0x04D0 691#define SK_RXQ2_Y2_PREF_LIDX 0x04D4 692#define SK_RXQ2_Y2_PREF_ADDRLO 0x04D8 693#define SK_RXQ2_Y2_PREF_ADDRHI 0x04DC 694#define SK_RXQ2_Y2_PREF_GETIDX 0x04E0 695#define SK_RXQ2_Y2_PREF_PUTIDX 0x04E4 696#define SK_RXQ2_Y2_PREF_FIFOWP 0x04F0 697#define SK_RXQ2_Y2_PREF_FIFORP 0x04F4 698#define SK_RXQ2_Y2_PREF_FIFOWM 0x04F8 699#define SK_RXQ2_Y2_PREF_FIFOLV 0x04FC 700 701#define SK_RXBMU_CLR_IRQ_ERR 0x00000001 702#define SK_RXBMU_CLR_IRQ_EOF 0x00000002 703#define SK_RXBMU_CLR_IRQ_EOB 0x00000004 704#define SK_RXBMU_CLR_IRQ_PAR 0x00000008 705#define SK_RXBMU_RX_START 0x00000010 706#define SK_RXBMU_RX_STOP 0x00000020 707#define SK_RXBMU_POLL_OFF 0x00000040 708#define SK_RXBMU_POLL_ON 0x00000080 709#define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 710#define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 711#define SK_RXBMU_DESCWR_SM_RESET 0x00000400 712#define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 713#define SK_RXBMU_DESCRD_SM_RESET 0x00001000 714#define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 715#define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 716#define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 717#define SK_RXBMU_PFI_SM_RESET 0x00010000 718#define SK_RXBMU_PFI_SM_UNRESET 0x00020000 719#define SK_RXBMU_FIFO_RESET 0x00040000 720#define SK_RXBMU_FIFO_UNRESET 0x00080000 721#define SK_RXBMU_DESC_RESET 0x00100000 722#define SK_RXBMU_DESC_UNRESET 0x00200000 723#define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 724 725#define SK_RXBMU_ONLINE \ 726 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 727 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 728 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 729 SK_RXBMU_DESC_UNRESET) 730 731#define SK_RXBMU_OFFLINE \ 732 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 733 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 734 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 735 SK_RXBMU_DESC_RESET) 736 737/* Block 12 -- TX sync queue 1 */ 738#define SK_TXQS1_BUFCNT 0x0600 739#define SK_TXQS1_BUFCTL 0x0602 740#define SK_TXQS1_NEXTDESC 0x0604 741#define SK_TXQS1_RXBUF_LO 0x0608 742#define SK_TXQS1_RXBUF_HI 0x060C 743#define SK_TXQS1_RXSTAT 0x0610 744#define SK_TXQS1_CSUM_STARTVAL 0x0614 745#define SK_TXQS1_CSUM_STARTPOS 0x0618 746#define SK_TXQS1_CSUM_WRITEPOS 0x061A 747#define SK_TXQS1_CURADDR_LO 0x0620 748#define SK_TXQS1_CURADDR_HI 0x0624 749#define SK_TXQS1_CURCNT_LO 0x0628 750#define SK_TXQS1_CURCNT_HI 0x062C 751#define SK_TXQS1_CURBYTES 0x0630 752#define SK_TXQS1_BMU_CSR 0x0634 753#define SK_TXQS1_WATERMARK 0x0638 754#define SK_TXQS1_FLAG 0x063A 755#define SK_TXQS1_TEST1 0x063C 756#define SK_TXQS1_TEST2 0x0640 757#define SK_TXQS1_TEST3 0x0644 758/* yukon-2 only */ 759#define SK_TXQS1_Y2_WM 0x0640 760#define SK_TXQS1_Y2_AL 0x0642 761#define SK_TXQS1_Y2_RSP 0x0644 762#define SK_TXQS1_Y2_RSL 0x0646 763#define SK_TXQS1_Y2_RP 0x0648 764#define SK_TXQS1_Y2_RL 0x064A 765#define SK_TXQS1_Y2_WP 0x064C 766#define SK_TXQS1_Y2_WSP 0x064D 767#define SK_TXQS1_Y2_WL 0x064E 768#define SK_TXQS1_Y2_WSL 0x064F 769/* yukon-2 only (prefetch unit) */ 770#define SK_TXQS1_Y2_PREF_CSR 0x0650 771#define SK_TXQS1_Y2_PREF_LIDX 0x0654 772#define SK_TXQS1_Y2_PREF_ADDRLO 0x0658 773#define SK_TXQS1_Y2_PREF_ADDRHI 0x065C 774#define SK_TXQS1_Y2_PREF_GETIDX 0x0660 775#define SK_TXQS1_Y2_PREF_PUTIDX 0x0664 776#define SK_TXQS1_Y2_PREF_FIFOWP 0x0670 777#define SK_TXQS1_Y2_PREF_FIFORP 0x0674 778#define SK_TXQS1_Y2_PREF_FIFOWM 0x0678 779#define SK_TXQS1_Y2_PREF_FIFOLV 0x067C 780 781/* Block 13 -- TX async queue 1 */ 782#define SK_TXQA1_BUFCNT 0x0680 783#define SK_TXQA1_BUFCTL 0x0682 784#define SK_TXQA1_NEXTDESC 0x0684 785#define SK_TXQA1_RXBUF_LO 0x0688 786#define SK_TXQA1_RXBUF_HI 0x068C 787#define SK_TXQA1_RXSTAT 0x0690 788#define SK_TXQA1_CSUM_STARTVAL 0x0694 789#define SK_TXQA1_CSUM_STARTPOS 0x0698 790#define SK_TXQA1_CSUM_WRITEPOS 0x069A 791#define SK_TXQA1_CURADDR_LO 0x06A0 792#define SK_TXQA1_CURADDR_HI 0x06A4 793#define SK_TXQA1_CURCNT_LO 0x06A8 794#define SK_TXQA1_CURCNT_HI 0x06AC 795#define SK_TXQA1_CURBYTES 0x06B0 796#define SK_TXQA1_BMU_CSR 0x06B4 797#define SK_TXQA1_WATERMARK 0x06B8 798#define SK_TXQA1_FLAG 0x06BA 799#define SK_TXQA1_TEST1 0x06BC 800#define SK_TXQA1_TEST2 0x06C0 801#define SK_TXQA1_TEST3 0x06C4 802/* yukon-2 only */ 803#define SK_TXQA1_Y2_WM 0x06C0 804#define SK_TXQA1_Y2_AL 0x06C2 805#define SK_TXQA1_Y2_RSP 0x06C4 806#define SK_TXQA1_Y2_RSL 0x06C6 807#define SK_TXQA1_Y2_RP 0x06C8 808#define SK_TXQA1_Y2_RL 0x06CA 809#define SK_TXQA1_Y2_WP 0x06CC 810#define SK_TXQA1_Y2_WSP 0x06CD 811#define SK_TXQA1_Y2_WL 0x06CE 812#define SK_TXQA1_Y2_WSL 0x06CF 813/* yukon-2 only (prefetch unit) */ 814#define SK_TXQA1_Y2_PREF_CSR 0x06D0 815#define SK_TXQA1_Y2_PREF_LIDX 0x06D4 816#define SK_TXQA1_Y2_PREF_ADDRLO 0x06D8 817#define SK_TXQA1_Y2_PREF_ADDRHI 0x06DC 818#define SK_TXQA1_Y2_PREF_GETIDX 0x06E0 819#define SK_TXQA1_Y2_PREF_PUTIDX 0x06E4 820#define SK_TXQA1_Y2_PREF_FIFOWP 0x06F0 821#define SK_TXQA1_Y2_PREF_FIFORP 0x06F4 822#define SK_TXQA1_Y2_PREF_FIFOWM 0x06F8 823#define SK_TXQA1_Y2_PREF_FIFOLV 0x06FC 824 825/* Block 14 -- TX sync queue 2 */ 826#define SK_TXQS2_BUFCNT 0x0700 827#define SK_TXQS2_BUFCTL 0x0702 828#define SK_TXQS2_NEXTDESC 0x0704 829#define SK_TXQS2_RXBUF_LO 0x0708 830#define SK_TXQS2_RXBUF_HI 0x070C 831#define SK_TXQS2_RXSTAT 0x0710 832#define SK_TXQS2_CSUM_STARTVAL 0x0714 833#define SK_TXQS2_CSUM_STARTPOS 0x0718 834#define SK_TXQS2_CSUM_WRITEPOS 0x071A 835#define SK_TXQS2_CURADDR_LO 0x0720 836#define SK_TXQS2_CURADDR_HI 0x0724 837#define SK_TXQS2_CURCNT_LO 0x0728 838#define SK_TXQS2_CURCNT_HI 0x072C 839#define SK_TXQS2_CURBYTES 0x0730 840#define SK_TXQS2_BMU_CSR 0x0734 841#define SK_TXQS2_WATERMARK 0x0738 842#define SK_TXQS2_FLAG 0x073A 843#define SK_TXQS2_TEST1 0x073C 844#define SK_TXQS2_TEST2 0x0740 845#define SK_TXQS2_TEST3 0x0744 846/* yukon-2 only */ 847#define SK_TXQS2_Y2_WM 0x0740 848#define SK_TXQS2_Y2_AL 0x0742 849#define SK_TXQS2_Y2_RSP 0x0744 850#define SK_TXQS2_Y2_RSL 0x0746 851#define SK_TXQS2_Y2_RP 0x0748 852#define SK_TXQS2_Y2_RL 0x074A 853#define SK_TXQS2_Y2_WP 0x074C 854#define SK_TXQS2_Y2_WSP 0x074D 855#define SK_TXQS2_Y2_WL 0x074E 856#define SK_TXQS2_Y2_WSL 0x074F 857/* yukon-2 only (prefetch unit) */ 858#define SK_TXQS2_Y2_PREF_CSR 0x0750 859#define SK_TXQS2_Y2_PREF_LIDX 0x0754 860#define SK_TXQS2_Y2_PREF_ADDRLO 0x0758 861#define SK_TXQS2_Y2_PREF_ADDRHI 0x075C 862#define SK_TXQS2_Y2_PREF_GETIDX 0x0760 863#define SK_TXQS2_Y2_PREF_PUTIDX 0x0764 864#define SK_TXQS2_Y2_PREF_FIFOWP 0x0770 865#define SK_TXQS2_Y2_PREF_FIFORP 0x0774 866#define SK_TXQS2_Y2_PREF_FIFOWM 0x0778 867#define SK_TXQS2_Y2_PREF_FIFOLV 0x077C 868 869/* Block 15 -- TX async queue 2 */ 870#define SK_TXQA2_BUFCNT 0x0780 871#define SK_TXQA2_BUFCTL 0x0782 872#define SK_TXQA2_NEXTDESC 0x0784 873#define SK_TXQA2_RXBUF_LO 0x0788 874#define SK_TXQA2_RXBUF_HI 0x078C 875#define SK_TXQA2_RXSTAT 0x0790 876#define SK_TXQA2_CSUM_STARTVAL 0x0794 877#define SK_TXQA2_CSUM_STARTPOS 0x0798 878#define SK_TXQA2_CSUM_WRITEPOS 0x079A 879#define SK_TXQA2_CURADDR_LO 0x07A0 880#define SK_TXQA2_CURADDR_HI 0x07A4 881#define SK_TXQA2_CURCNT_LO 0x07A8 882#define SK_TXQA2_CURCNT_HI 0x07AC 883#define SK_TXQA2_CURBYTES 0x07B0 884#define SK_TXQA2_BMU_CSR 0x07B4 885#define SK_TXQA2_WATERMARK 0x07B8 886#define SK_TXQA2_FLAG 0x07BA 887#define SK_TXQA2_TEST1 0x07BC 888#define SK_TXQA2_TEST2 0x07C0 889#define SK_TXQA2_TEST3 0x07C4 890/* yukon-2 only */ 891#define SK_TXQA2_Y2_WM 0x07C0 892#define SK_TXQA2_Y2_AL 0x07C2 893#define SK_TXQA2_Y2_RSP 0x07C4 894#define SK_TXQA2_Y2_RSL 0x07C6 895#define SK_TXQA2_Y2_RP 0x07C8 896#define SK_TXQA2_Y2_RL 0x07CA 897#define SK_TXQA2_Y2_WP 0x07CC 898#define SK_TXQA2_Y2_WSP 0x07CD 899#define SK_TXQA2_Y2_WL 0x07CE 900#define SK_TXQA2_Y2_WSL 0x07CF 901/* yukon-2 only (prefetch unit) */ 902#define SK_TXQA2_Y2_PREF_CSR 0x07D0 903#define SK_TXQA2_Y2_PREF_LIDX 0x07D4 904#define SK_TXQA2_Y2_PREF_ADDRLO 0x07D8 905#define SK_TXQA2_Y2_PREF_ADDRHI 0x07DC 906#define SK_TXQA2_Y2_PREF_GETIDX 0x07E0 907#define SK_TXQA2_Y2_PREF_PUTIDX 0x07E4 908#define SK_TXQA2_Y2_PREF_FIFOWP 0x07F0 909#define SK_TXQA2_Y2_PREF_FIFORP 0x07F4 910#define SK_TXQA2_Y2_PREF_FIFOWM 0x07F8 911#define SK_TXQA2_Y2_PREF_FIFOLV 0x07FC 912 913#define SK_TXBMU_CLR_IRQ_ERR 0x00000001 914#define SK_TXBMU_CLR_IRQ_EOF 0x00000002 915#define SK_TXBMU_CLR_IRQ_EOB 0x00000004 916#define SK_TXBMU_TX_START 0x00000010 917#define SK_TXBMU_TX_STOP 0x00000020 918#define SK_TXBMU_POLL_OFF 0x00000040 919#define SK_TXBMU_POLL_ON 0x00000080 920#define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 921#define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 922#define SK_TXBMU_DESCWR_SM_RESET 0x00000400 923#define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 924#define SK_TXBMU_DESCRD_SM_RESET 0x00001000 925#define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 926#define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 927#define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 928#define SK_TXBMU_PFI_SM_RESET 0x00010000 929#define SK_TXBMU_PFI_SM_UNRESET 0x00020000 930#define SK_TXBMU_FIFO_RESET 0x00040000 931#define SK_TXBMU_FIFO_UNRESET 0x00080000 932#define SK_TXBMU_DESC_RESET 0x00100000 933#define SK_TXBMU_DESC_UNRESET 0x00200000 934#define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 935 936#define SK_TXBMU_ONLINE \ 937 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 938 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 939 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 940 SK_TXBMU_DESC_UNRESET|SK_TXBMU_POLL_ON) 941 942#define SK_TXBMU_OFFLINE \ 943 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 944 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 945 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 946 SK_TXBMU_DESC_RESET|SK_TXBMU_POLL_OFF) 947 948/* Block 16 -- Receive RAMbuffer 1 */ 949#define SK_RXRB1_START 0x0800 950#define SK_RXRB1_END 0x0804 951#define SK_RXRB1_WR_PTR 0x0808 952#define SK_RXRB1_RD_PTR 0x080C 953#define SK_RXRB1_UTHR_PAUSE 0x0810 954#define SK_RXRB1_LTHR_PAUSE 0x0814 955#define SK_RXRB1_UTHR_HIPRIO 0x0818 956#define SK_RXRB1_UTHR_LOPRIO 0x081C 957#define SK_RXRB1_PKTCNT 0x0820 958#define SK_RXRB1_LVL 0x0824 959#define SK_RXRB1_CTLTST 0x0828 960 961/* Block 17 -- Receive RAMbuffer 2 */ 962#define SK_RXRB2_START 0x0880 963#define SK_RXRB2_END 0x0884 964#define SK_RXRB2_WR_PTR 0x0888 965#define SK_RXRB2_RD_PTR 0x088C 966#define SK_RXRB2_UTHR_PAUSE 0x0890 967#define SK_RXRB2_LTHR_PAUSE 0x0894 968#define SK_RXRB2_UTHR_HIPRIO 0x0898 969#define SK_RXRB2_UTHR_LOPRIO 0x089C 970#define SK_RXRB2_PKTCNT 0x08A0 971#define SK_RXRB2_LVL 0x08A4 972#define SK_RXRB2_CTLTST 0x08A8 973 974/* Block 20 -- Sync. Transmit RAMbuffer 1 */ 975#define SK_TXRBS1_START 0x0A00 976#define SK_TXRBS1_END 0x0A04 977#define SK_TXRBS1_WR_PTR 0x0A08 978#define SK_TXRBS1_RD_PTR 0x0A0C 979#define SK_TXRBS1_PKTCNT 0x0A20 980#define SK_TXRBS1_LVL 0x0A24 981#define SK_TXRBS1_CTLTST 0x0A28 982 983/* Block 21 -- Async. Transmit RAMbuffer 1 */ 984#define SK_TXRBA1_START 0x0A80 985#define SK_TXRBA1_END 0x0A84 986#define SK_TXRBA1_WR_PTR 0x0A88 987#define SK_TXRBA1_RD_PTR 0x0A8C 988#define SK_TXRBA1_PKTCNT 0x0AA0 989#define SK_TXRBA1_LVL 0x0AA4 990#define SK_TXRBA1_CTLTST 0x0AA8 991 992/* Block 22 -- Sync. Transmit RAMbuffer 2 */ 993#define SK_TXRBS2_START 0x0B00 994#define SK_TXRBS2_END 0x0B04 995#define SK_TXRBS2_WR_PTR 0x0B08 996#define SK_TXRBS2_RD_PTR 0x0B0C 997#define SK_TXRBS2_PKTCNT 0x0B20 998#define SK_TXRBS2_LVL 0x0B24 999#define SK_TXRBS2_CTLTST 0x0B28 1000 1001/* Block 23 -- Async. Transmit RAMbuffer 2 */ 1002#define SK_TXRBA2_START 0x0B80 1003#define SK_TXRBA2_END 0x0B84 1004#define SK_TXRBA2_WR_PTR 0x0B88 1005#define SK_TXRBA2_RD_PTR 0x0B8C 1006#define SK_TXRBA2_PKTCNT 0x0BA0 1007#define SK_TXRBA2_LVL 0x0BA4 1008#define SK_TXRBA2_CTLTST 0x0BA8 1009 1010#define SK_RBCTL_RESET 0x00000001 1011#define SK_RBCTL_UNRESET 0x00000002 1012#define SK_RBCTL_OFF 0x00000004 1013#define SK_RBCTL_ON 0x00000008 1014#define SK_RBCTL_STORENFWD_OFF 0x00000010 1015#define SK_RBCTL_STORENFWD_ON 0x00000020 1016 1017/* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 1018#define SK_RXF1_END 0x0C00 1019#define SK_RXF1_WPTR 0x0C04 1020#define SK_RXF1_RPTR 0x0C0C 1021#define SK_RXF1_PKTCNT 0x0C10 1022#define SK_RXF1_LVL 0x0C14 1023#define SK_RXF1_MACCTL 0x0C18 1024#define SK_RXF1_CTL 0x0C1C 1025#define SK_RXLED1_CNTINIT 0x0C20 1026#define SK_RXLED1_COUNTER 0x0C24 1027#define SK_RXLED1_CTL 0x0C28 1028#define SK_RXLED1_TST 0x0C29 1029#define SK_LINK_SYNC1_CINIT 0x0C30 1030#define SK_LINK_SYNC1_COUNTER 0x0C34 1031#define SK_LINK_SYNC1_CTL 0x0C38 1032#define SK_LINK_SYNC1_TST 0x0C39 1033#define SK_LINKLED1_CTL 0x0C3C 1034 1035#define SK_FIFO_END 0x3F 1036 1037/* Receive MAC FIFO 1 (Yukon Only) */ 1038#define SK_RXMF1_END 0x0C40 1039#define SK_RXMF1_THRESHOLD 0x0C44 1040#define SK_RXMF1_CTRL_TEST 0x0C48 1041#define SK_RXMF1_FLUSH_MASK 0x0C4C 1042#define SK_RXMF1_FLUSH_THRESHOLD 0x0C50 1043#define SK_RXMF1_WRITE_PTR 0x0C60 1044#define SK_RXMF1_WRITE_LEVEL 0x0C68 1045#define SK_RXMF1_READ_PTR 0x0C70 1046#define SK_RXMF1_READ_LEVEL 0x0C78 1047 1048/* Receive MAC FIFO 1 Control/Test */ 1049#define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 1050#define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 1051#define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 1052#define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 1053#define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 1054#define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 1055#define SK_RFCTL_FIFO_FLUSH_OFF 0x00000080 /* RX FIFO Flsuh mode off */ 1056#define SK_RFCTL_FIFO_FLUSH_ON 0x00000040 /* RX FIFO Flush mode on */ 1057#define SK_RFCTL_RX_FIFO_OVER 0x00000020 /* Clear IRQ RX FIFO Overrun */ 1058#define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ 1059#define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 1060#define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 1061#define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 1062#define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 1063 1064#define SK_RFCTL_FIFO_THRESHOLD 0x0a /* flush threshold (default) */ 1065 1066/* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 1067#define SK_RXF2_END 0x0C80 1068#define SK_RXF2_WPTR 0x0C84 1069#define SK_RXF2_RPTR 0x0C8C 1070#define SK_RXF2_PKTCNT 0x0C90 1071#define SK_RXF2_LVL 0x0C94 1072#define SK_RXF2_MACCTL 0x0C98 1073#define SK_RXF2_CTL 0x0C9C 1074#define SK_RXLED2_CNTINIT 0x0CA0 1075#define SK_RXLED2_COUNTER 0x0CA4 1076#define SK_RXLED2_CTL 0x0CA8 1077#define SK_RXLED2_TST 0x0CA9 1078#define SK_LINK_SYNC2_CINIT 0x0CB0 1079#define SK_LINK_SYNC2_COUNTER 0x0CB4 1080#define SK_LINK_SYNC2_CTL 0x0CB8 1081#define SK_LINK_SYNC2_TST 0x0CB9 1082#define SK_LINKLED2_CTL 0x0CBC 1083 1084#define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 1085#define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 1086#define SK_RXMACCTL_TSTAMP_OFF 0x00000004 1087#define SK_RXMACCTL_RSTAMP_ON 0x00000008 1088#define SK_RXMACCTL_FLUSH_OFF 0x00000010 1089#define SK_RXMACCTL_FLUSH_ON 0x00000020 1090#define SK_RXMACCTL_PAUSE_OFF 0x00000040 1091#define SK_RXMACCTL_PAUSE_ON 0x00000080 1092#define SK_RXMACCTL_AFULL_OFF 0x00000100 1093#define SK_RXMACCTL_AFULL_ON 0x00000200 1094#define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 1095#define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 1096#define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 1097#define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 1098#define SK_RXMACCTL_STS_TIMEO 0x00FF0000 1099#define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 1100 1101#define SK_RXLEDCTL_ENABLE 0x0001 1102#define SK_RXLEDCTL_COUNTER_STOP 0x0002 1103#define SK_RXLEDCTL_COUNTER_START 0x0004 1104 1105#define SK_LINKLED_OFF 0x0001 1106#define SK_LINKLED_ON 0x0002 1107#define SK_LINKLED_LINKSYNC_OFF 0x0004 1108#define SK_LINKLED_LINKSYNC_ON 0x0008 1109#define SK_LINKLED_BLINK_OFF 0x0010 1110#define SK_LINKLED_BLINK_ON 0x0020 1111 1112/* Block 26 -- TX MAC FIFO 1 regisrers */ 1113#define SK_TXF1_END 0x0D00 1114#define SK_TXF1_WPTR 0x0D04 1115#define SK_TXF1_RPTR 0x0D0C 1116#define SK_TXF1_PKTCNT 0x0D10 1117#define SK_TXF1_LVL 0x0D14 1118#define SK_TXF1_MACCTL 0x0D18 1119#define SK_TXF1_CTL 0x0D1C 1120#define SK_TXLED1_CNTINIT 0x0D20 1121#define SK_TXLED1_COUNTER 0x0D24 1122#define SK_TXLED1_CTL 0x0D28 1123#define SK_TXLED1_TST 0x0D29 1124 1125/* Transmit MAC FIFO 1 (Yukon Only) */ 1126#define SK_TXMF1_END 0x0D40 1127#define SK_TXMF1_THRESHOLD 0x0D44 1128#define SK_TXMF1_CTRL_TEST 0x0D48 1129#define SK_TXMF1_WRITE_PTR 0x0D60 1130#define SK_TXMF1_WRITE_SHADOW 0x0D64 1131#define SK_TXMF1_WRITE_LEVEL 0x0D68 1132#define SK_TXMF1_READ_PTR 0x0D70 1133#define SK_TXMF1_RESTART_PTR 0x0D74 1134#define SK_TXMF1_READ_LEVEL 0x0D78 1135 1136/* Transmit MAC FIFO Control/Test */ 1137#define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 1138#define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 1139#define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 1140#define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 1141#define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 1142#define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 1143#define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ 1144#define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ 1145#define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ 1146#define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 1147#define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 1148#define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 1149#define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 1150 1151/* Block 27 -- TX MAC FIFO 2 regisrers */ 1152#define SK_TXF2_END 0x0D80 1153#define SK_TXF2_WPTR 0x0D84 1154#define SK_TXF2_RPTR 0x0D8C 1155#define SK_TXF2_PKTCNT 0x0D90 1156#define SK_TXF2_LVL 0x0D94 1157#define SK_TXF2_MACCTL 0x0D98 1158#define SK_TXF2_CTL 0x0D9C 1159#define SK_TXLED2_CNTINIT 0x0DA0 1160#define SK_TXLED2_COUNTER 0x0DA4 1161#define SK_TXLED2_CTL 0x0DA8 1162#define SK_TXLED2_TST 0x0DA9 1163 1164#define SK_TXMACCTL_XMAC_RESET 0x00000001 1165#define SK_TXMACCTL_XMAC_UNRESET 0x00000002 1166#define SK_TXMACCTL_LOOP_OFF 0x00000004 1167#define SK_TXMACCTL_LOOP_ON 0x00000008 1168#define SK_TXMACCTL_FLUSH_OFF 0x00000010 1169#define SK_TXMACCTL_FLUSH_ON 0x00000020 1170#define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 1171#define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 1172#define SK_TXMACCTL_AFULL_OFF 0x00000100 1173#define SK_TXMACCTL_AFULL_ON 0x00000200 1174#define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 1175#define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 1176#define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 1177#define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 1178#define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 1179#define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 1180 1181#define SK_TXLEDCTL_ENABLE 0x0001 1182#define SK_TXLEDCTL_COUNTER_STOP 0x0002 1183#define SK_TXLEDCTL_COUNTER_START 0x0004 1184 1185#define SK_FIFO_RESET 0x00000001 1186#define SK_FIFO_UNRESET 0x00000002 1187#define SK_FIFO_OFF 0x00000004 1188#define SK_FIFO_ON 0x00000008 1189 1190/* Block 28 -- Descriptor Poll Timer */ 1191#define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ 1192#define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ 1193 1194#define SK_DPT_TIMER_MAX 0x00ffffffff /* 214.75ms at 78.125MHz */ 1195 1196#define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */ 1197#define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */ 1198#define SK_DPT_TCTL_START 0x0002 /* Start Timer */ 1199 1200#define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ 1201#define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ 1202#define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ 1203#define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ 1204 1205#define SK_TSTAMP_COUNT 0x0e14 1206#define SK_TSTAMP_CTL 0x0e18 1207 1208#define SK_TSTAMP_IRQ_CLEAR 0x01 1209#define SK_TSTAMP_STOP 0x02 1210#define SK_TSTAMP_START 0x04 1211 1212#define SK_Y2_ASF_CSR 0x0e68 1213 1214#define SK_Y2_ASF_RESET 0x08 1215 1216#define SK_Y2_LEV_ITIMERINIT 0x0eb0 1217#define SK_Y2_LEV_ITIMERCTL 0x0eb8 1218#define SK_Y2_TX_ITIMERINIT 0x0ec0 1219#define SK_Y2_TX_ITIMERCTL 0x0ec8 1220#define SK_Y2_ISR_ITIMERINIT 0x0ed0 1221#define SK_Y2_ISR_ITIMERCTL 0x0ed8 1222 1223/* Block 29 -- Status BMU (Yukon-2 only) */ 1224#define SK_STAT_BMU_CSR 0x0e80 1225#define SK_STAT_BMU_LIDX 0x0e84 1226#define SK_STAT_BMU_ADDRLO 0x0e88 1227#define SK_STAT_BMU_ADDRHI 0x0e8c 1228#define SK_STAT_BMU_TXA1_RIDX 0x0e90 1229#define SK_STAT_BMU_TXS1_RIDX 0x0e92 1230#define SK_STAT_BMU_TXA2_RIDX 0x0e94 1231#define SK_STAT_BMU_TXS2_RIDX 0x0e96 1232#define SK_STAT_BMU_TX_THRESH 0x0e98 1233#define SK_STAT_BMU_PUTIDX 0x0e9c 1234#define SK_STAT_BMU_FIFOWP 0x0ea0 1235#define SK_STAT_BMU_FIFORP 0x0ea4 1236#define SK_STAT_BMU_FIFORSP 0x0ea6 1237#define SK_STAT_BMU_FIFOLV 0x0ea8 1238#define SK_STAT_BMU_FIFOSLV 0x0eaa 1239#define SK_STAT_BMU_FIFOWM 0x0eac 1240#define SK_STAT_BMU_FIFOIWM 0x0ead 1241 1242#define SK_STAT_BMU_RESET 0x00000001 1243#define SK_STAT_BMU_UNRESET 0x00000002 1244#define SK_STAT_BMU_OFF 0x00000004 1245#define SK_STAT_BMU_ON 0x00000008 1246#define SK_STAT_BMU_IRQ_CLEAR 0x00000010 1247 1248/* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ 1249#define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ 1250#define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ 1251#define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ 1252#define SK_GMAC_IMR 0x0f0c /* GMAC Interrupt Mask Register */ 1253#define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ 1254#define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ 1255#define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ 1256#define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ 1257#define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ 1258#define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ 1259#define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ 1260#define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ 1261#define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ 1262#define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ 1263#define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ 1264#define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ 1265#define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ 1266#define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ 1267#define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ 1268#define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ 1269#define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ 1270#define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ 1271#define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ 1272#define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ 1273#define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ 1274#define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ 1275#define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ 1276#define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ 1277#define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ 1278 1279#define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ 1280#define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ 1281#define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ 1282#define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ 1283#define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ 1284#define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ 1285 1286#define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ 1287#define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ 1288#define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ 1289#define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ 1290#define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ 1291#define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ 1292#define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ 1293#define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ 1294#define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ 1295#define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ 1296#define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ 1297#define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ 1298#define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ 1299#define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ 1300#define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ 1301#define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ 1302#define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ 1303#define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ 1304#define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ 1305#define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ 1306#define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ 1307#define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ 1308#define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ 1309 1310#define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1311 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) 1312#define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1313 SK_GPHY_HWCFG_M_2 ) 1314#define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ 1315 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) 1316 1317#define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ 1318#define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ 1319#define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ 1320#define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ 1321#define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ 1322#define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ 1323 1324#define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ 1325#define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ 1326 1327/* Block 31 -- reserved */ 1328 1329/* Block 32-33 -- Pattern Ram */ 1330#define SK_WOL_PRAM 0x1000 1331 1332/* Block 0x22 - 0x37 -- reserved */ 1333 1334/* Block 0x38 -- Y2 PCI config registers */ 1335#define SK_Y2_PCI_BASE 0x1c00 1336 1337/* Compute offset of mirrored PCI register */ 1338#define SK_Y2_PCI_REG(reg) ((reg) + SK_Y2_PCI_BASE) 1339 1340/* Block 0x39 - 0x3f -- reserved */ 1341 1342/* Block 0x40 to 0x4F -- XMAC 1 registers */ 1343#define SK_XMAC1_BASE 0x2000 1344 1345/* Block 0x50 to 0x5F -- MARV 1 registers */ 1346#define SK_MARV1_BASE 0x2800 1347 1348/* Block 0x60 to 0x6F -- XMAC 2 registers */ 1349#define SK_XMAC2_BASE 0x3000 1350 1351/* Block 0x70 to 0x7F -- MARV 2 registers */ 1352#define SK_MARV2_BASE 0x3800 1353 1354/* Compute relative offset of an XMAC register in the XMAC window(s). */ 1355#define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ 1356 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 1357 1358#if 0 1359#define SK_XM_READ_4(sc, reg) \ 1360 ((sk_win_read_2(sc->sk_softc, \ 1361 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ 1362 ((sk_win_read_2(sc->sk_softc, \ 1363 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) 1364 1365#define SK_XM_WRITE_4(sc, reg, val) \ 1366 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ 1367 ((val) & 0xFFFF)); \ 1368 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ 1369 ((val) >> 16) & 0xFFFF) 1370#else 1371#define SK_XM_READ_4(sc, reg) \ 1372 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1373 1374#define SK_XM_WRITE_4(sc, reg, val) \ 1375 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) 1376#endif 1377 1378#define SK_XM_READ_2(sc, reg) \ 1379 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1380 1381#define SK_XM_WRITE_2(sc, reg, val) \ 1382 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) 1383 1384#define SK_XM_SETBIT_4(sc, reg, x) \ 1385 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1386 1387#define SK_XM_CLRBIT_4(sc, reg, x) \ 1388 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1389 1390#define SK_XM_SETBIT_2(sc, reg, x) \ 1391 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1392 1393#define SK_XM_CLRBIT_2(sc, reg, x) \ 1394 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1395 1396/* Compute relative offset of an MARV register in the MARV window(s). */ 1397#define SK_YU_REG(sc, reg) \ 1398 ((reg) + SK_MARV1_BASE + \ 1399 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) 1400 1401#define SK_YU_READ_4(sc, reg) \ 1402 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1403 1404#define SK_YU_READ_2(sc, reg) \ 1405 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1406 1407#define SK_YU_WRITE_4(sc, reg, val) \ 1408 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1409 1410#define SK_YU_WRITE_2(sc, reg, val) \ 1411 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1412 1413#define SK_YU_SETBIT_4(sc, reg, x) \ 1414 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1415 1416#define SK_YU_CLRBIT_4(sc, reg, x) \ 1417 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1418 1419#define SK_YU_SETBIT_2(sc, reg, x) \ 1420 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) 1421 1422#define SK_YU_CLRBIT_2(sc, reg, x) \ 1423 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) 1424 1425/* 1426 * The default FIFO threshold on the XMAC II is 4 bytes. On 1427 * dual port NICs, this often leads to transmit underruns, so we 1428 * bump the threshold a little. 1429 */ 1430#define SK_XM_TX_FIFOTHRESH 512 1431 1432#define SK_PCI_VENDOR_ID 0x0000 1433#define SK_PCI_DEVICE_ID 0x0002 1434#define SK_PCI_COMMAND 0x0004 1435#define SK_PCI_STATUS 0x0006 1436#define SK_PCI_REVID 0x0008 1437#define SK_PCI_CLASSCODE 0x0009 1438#define SK_PCI_CACHELEN 0x000C 1439#define SK_PCI_LATENCY_TIMER 0x000D 1440#define SK_PCI_HEADER_TYPE 0x000E 1441#define SK_PCI_LOMEM 0x0010 1442#define SK_PCI_LOIO 0x0014 1443#define SK_PCI_SUBVEN_ID 0x002C 1444#define SK_PCI_SYBSYS_ID 0x002E 1445#define SK_PCI_BIOSROM 0x0030 1446#define SK_PCI_INTLINE 0x003C 1447#define SK_PCI_INTPIN 0x003D 1448#define SK_PCI_MINGNT 0x003E 1449#define SK_PCI_MINLAT 0x003F 1450 1451/* device specific PCI registers */ 1452#define SK_PCI_OURREG1 0x0040 1453#define SK_PCI_OURREG2 0x0044 1454#define SK_PCI_CAPID 0x0048 /* 8 bits */ 1455#define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 1456#define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 1457#define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 1458#define SK_PCI_PME_EVENT 0x004F 1459 1460#define SK_Y2_REG1_PHY1_COMA 0x10000000 1461#define SK_Y2_REG1_PHY2_COMA 0x20000000 1462 1463#define SK_PSTATE_MASK 0x0003 1464#define SK_PSTATE_D0 0x0000 1465#define SK_PSTATE_D1 0x0001 1466#define SK_PSTATE_D2 0x0002 1467#define SK_PSTATE_D3 0x0003 1468#define SK_PME_EN 0x0010 1469#define SK_PME_STATUS 0x8000 1470 1471#define CSR_WRITE_4(sc, reg, val) \ 1472 bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1473#define CSR_WRITE_2(sc, reg, val) \ 1474 bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1475#define CSR_WRITE_1(sc, reg, val) \ 1476 bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1477 1478#define CSR_READ_4(sc, reg) \ 1479 bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1480#define CSR_READ_2(sc, reg) \ 1481 bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1482#define CSR_READ_1(sc, reg) \ 1483 bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1484 1485struct sk_type { 1486 u_int16_t sk_vid; 1487 u_int16_t sk_did; 1488 char *sk_name; 1489}; 1490 1491#define SK_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) 1492#define SK_ADDR_HI(x) ((u_int64_t) (x) >> 32) 1493 1494#define SK_RING_ALIGN 64 1495 1496/* RX queue descriptor data structure */ 1497struct sk_rx_desc { 1498 u_int32_t sk_ctl; 1499 u_int32_t sk_next; 1500 u_int32_t sk_data_lo; 1501 u_int32_t sk_data_hi; 1502 u_int32_t sk_xmac_rxstat; 1503 u_int32_t sk_timestamp; 1504 u_int16_t sk_csum2; 1505 u_int16_t sk_csum1; 1506 u_int16_t sk_csum2_start; 1507 u_int16_t sk_csum1_start; 1508}; 1509 1510#define SK_OPCODE_DEFAULT 0x00550000 1511#define SK_OPCODE_CSUM 0x00560000 1512 1513#define SK_RXCTL_LEN 0x0000FFFF 1514#define SK_RXCTL_OPCODE 0x00FF0000 1515#define SK_RXCTL_TSTAMP_VALID 0x01000000 1516#define SK_RXCTL_STATUS_VALID 0x02000000 1517#define SK_RXCTL_DEV0 0x04000000 1518#define SK_RXCTL_EOF_INTR 0x08000000 1519#define SK_RXCTL_EOB_INTR 0x10000000 1520#define SK_RXCTL_LASTFRAG 0x20000000 1521#define SK_RXCTL_FIRSTFRAG 0x40000000 1522#define SK_RXCTL_OWN 0x80000000 1523 1524#define SK_RXSTAT \ 1525 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \ 1526 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1527 1528struct sk_tx_desc { 1529 u_int32_t sk_ctl; 1530 u_int32_t sk_next; 1531 u_int32_t sk_data_lo; 1532 u_int32_t sk_data_hi; 1533 u_int32_t sk_xmac_txstat; 1534 u_int16_t sk_rsvd0; 1535 u_int16_t sk_csum_startval; 1536 u_int16_t sk_csum_startpos; 1537 u_int16_t sk_csum_writepos; 1538 u_int32_t sk_rsvd1; 1539}; 1540 1541#define SK_TXCTL_LEN 0x0000FFFF 1542#define SK_TXCTL_OPCODE 0x00FF0000 1543#define SK_TXCTL_SW 0x01000000 1544#define SK_TXCTL_NOCRC 0x02000000 1545#define SK_TXCTL_STORENFWD 0x04000000 1546#define SK_TXCTL_EOF_INTR 0x08000000 1547#define SK_TXCTL_EOB_INTR 0x10000000 1548#define SK_TXCTL_LASTFRAG 0x20000000 1549#define SK_TXCTL_FIRSTFRAG 0x40000000 1550#define SK_TXCTL_OWN 0x80000000 1551 1552#define SK_TXSTAT \ 1553 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1554 1555#define SK_RXBYTES(x) ((x) & 0x0000FFFF); 1556#define SK_TXBYTES SK_RXBYTES 1557 1558#define SK_TX_RING_CNT 512 1559#define SK_RX_RING_CNT 256 1560 1561struct msk_rx_desc { 1562 u_int32_t sk_addr; 1563 u_int16_t sk_len; 1564 u_int8_t sk_ctl; 1565 u_int8_t sk_opcode; 1566} __packed; 1567 1568#define SK_Y2_RXOPC_BUFFER 0x40 1569#define SK_Y2_RXOPC_PACKET 0x41 1570#define SK_Y2_RXOPC_OWN 0x80 1571 1572struct msk_tx_desc { 1573 u_int32_t sk_addr; 1574 u_int16_t sk_len; 1575 u_int8_t sk_ctl; 1576 u_int8_t sk_opcode; 1577} __packed; 1578 1579#define SK_Y2_TXCTL_LASTFRAG 0x80 1580 1581#define SK_Y2_TXOPC_BUFFER 0x40 1582#define SK_Y2_TXOPC_PACKET 0x41 1583#define SK_Y2_TXOPC_OWN 0x80 1584 1585struct msk_status_desc { 1586 u_int32_t sk_status; 1587 u_int16_t sk_len; 1588 u_int8_t sk_link; 1589 u_int8_t sk_opcode; 1590} __packed; 1591 1592#define SK_Y2_STOPC_RXSTAT 0x60 1593#define SK_Y2_STOPC_TXSTAT 0x68 1594#define SK_Y2_STOPC_OWN 0x80 1595 1596#define MSK_TX_RING_CNT 512 1597#define MSK_RX_RING_CNT 512 1598#define MSK_STATUS_RING_CNT 2048 1599 1600/* 1601 * Jumbo buffer stuff. Note that we must allocate more jumbo 1602 * buffers than there are descriptors in the receive ring. This 1603 * is because we don't know how long it will take for a packet 1604 * to be released after we hand it off to the upper protocol 1605 * layers. To be safe, we allocate 1.5 times the number of 1606 * receive descriptors. 1607 */ 1608#define SK_JUMBO_FRAMELEN 9018 1609#define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 1610#define SK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 1611#define SK_JSLOTS ((SK_RX_RING_CNT / 2) * 3) 1612 1613#define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN) 1614#define SK_JLEN SK_JRAWLEN 1615#define SK_MCLBYTES SK_JLEN 1616#define SK_JPAGESZ PAGE_SIZE 1617#define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) 1618#define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) 1619 1620#define MSK_JSLOTS ((MSK_RX_RING_CNT / 2) * 3) 1621 1622#define MSK_RESID (SK_JPAGESZ - (SK_JLEN * MSK_JSLOTS) % SK_JPAGESZ) 1623#define MSK_JMEM ((SK_JLEN * MSK_JSLOTS) + MSK_RESID) 1624 1625#define SK_MAXUNIT 256 1626#define SK_TIMEOUT 1000 1627 1628/* YUKON registers */ 1629 1630/* General Purpose Status Register (GPSR) */ 1631#define YUKON_GPSR 0x0000 1632 1633#define YU_GPSR_SPEED 0x8000 /* speed 0 - 10Mbps, 1 - 100Mbps */ 1634#define YU_GPSR_DUPLEX 0x4000 /* 0 - half duplex, 1 - full duplex */ 1635#define YU_GPSR_FCTL_TX 0x2000 /* Tx flow control, 1 - disabled */ 1636#define YU_GPSR_LINK 0x1000 /* link status (down/up) */ 1637#define YU_GPSR_PAUSE 0x0800 /* flow control enable/disable */ 1638#define YU_GPSR_TX_IN_PROG 0x0400 /* transmit in progress */ 1639#define YU_GPSR_EXCESS_COL 0x0200 /* excessive collisions occurred */ 1640#define YU_GPSR_LATE_COL 0x0100 /* late collision occurred */ 1641#define YU_GPSR_MII_PHY_STC 0x0020 /* MII PHY status change */ 1642#define YU_GPSR_GIG_SPEED 0x0010 /* Gigabit Speed (0 - use speed bit) */ 1643#define YU_GPSR_PARTITION 0x0008 /* partition mode */ 1644#define YU_GPSR_FCTL_RX 0x0004 /* Rx flow control, 1 - disabled */ 1645#define YU_GPSR_PROMS_EN 0x0002 /* promiscuous mode, 1 - enabled */ 1646 1647/* General Purpose Control Register (GPCR) */ 1648#define YUKON_GPCR 0x0004 1649 1650#define YU_GPCR_FCTL_TX_DIS 0x2000 /* Disable Tx flow control 802.3x */ 1651#define YU_GPCR_TXEN 0x1000 /* Transmit Enable */ 1652#define YU_GPCR_RXEN 0x0800 /* Receive Enable */ 1653#define YU_GPCR_BURSTEN 0x0400 /* Burst Mode Enable */ 1654#define YU_GPCR_LPBK 0x0200 /* MAC Loopback Enable */ 1655#define YU_GPCR_PAR 0x0100 /* Partition Enable */ 1656#define YU_GPCR_GIG 0x0080 /* Gigabit Speed 1000Mbps */ 1657#define YU_GPCR_FLP 0x0040 /* Force Link Pass */ 1658#define YU_GPCR_DUPLEX 0x0020 /* Duplex Enable */ 1659#define YU_GPCR_FCTL_RX_DIS 0x0010 /* Disable Rx flow control 802.3x */ 1660#define YU_GPCR_SPEED 0x0008 /* Port Speed 100Mbps */ 1661#define YU_GPCR_DPLX_DIS 0x0004 /* Disable Auto-Update for duplex */ 1662#define YU_GPCR_FCTL_DIS 0x0002 /* Disable Auto-Update for 802.3x */ 1663#define YU_GPCR_SPEED_DIS 0x0001 /* Disable Auto-Update for speed */ 1664 1665/* Transmit Control Register (TCR) */ 1666#define YUKON_TCR 0x0008 1667 1668#define YU_TCR_FJ 0x8000 /* force jam / flow control */ 1669#define YU_TCR_CRCD 0x4000 /* insert CRC (0 - enable) */ 1670#define YU_TCR_PADD 0x2000 /* pad packets to 64b (0 - enable) */ 1671#define YU_TCR_COLTH 0x1c00 /* collision threshold */ 1672 1673/* Receive Control Register (RCR) */ 1674#define YUKON_RCR 0x000c 1675 1676#define YU_RCR_UFLEN 0x8000 /* unicast filter enable */ 1677#define YU_RCR_MUFLEN 0x4000 /* multicast filter enable */ 1678#define YU_RCR_CRCR 0x2000 /* remove CRC */ 1679#define YU_RCR_PASSFC 0x1000 /* pass flow control packets */ 1680 1681/* Transmit Flow Control Register (TFCR) */ 1682#define YUKON_TFCR 0x0010 /* Pause Time */ 1683 1684/* Transmit Parameter Register (TPR) */ 1685#define YUKON_TPR 0x0014 1686 1687#define YU_TPR_JAM_LEN(x) (((x) & 0x3) << 14) 1688#define YU_TPR_JAM_IPG(x) (((x) & 0x1f) << 9) 1689#define YU_TPR_JAM2DATA_IPG(x) (((x) & 0x1f) << 4) 1690 1691/* Serial Mode Register (SMR) */ 1692#define YUKON_SMR 0x0018 1693 1694#define YU_SMR_DATA_BLIND(x) (((x) & 0x1f) << 11) 1695#define YU_SMR_LIMIT4 0x0400 /* reset after 16 / 4 collisions */ 1696#define YU_SMR_MFL_JUMBO 0x0100 /* max frame length for jumbo frames */ 1697#define YU_SMR_MFL_VLAN 0x0200 /* max frame length + vlan tag */ 1698#define YU_SMR_IPG_DATA(x) ((x) & 0x1f) 1699 1700/* Source Address Low #1 (SAL1) */ 1701#define YUKON_SAL1 0x001c /* SA1[15:0] */ 1702 1703/* Source Address Middle #1 (SAM1) */ 1704#define YUKON_SAM1 0x0020 /* SA1[31:16] */ 1705 1706/* Source Address High #1 (SAH1) */ 1707#define YUKON_SAH1 0x0024 /* SA1[47:32] */ 1708 1709/* Source Address Low #2 (SAL2) */ 1710#define YUKON_SAL2 0x0028 /* SA2[15:0] */ 1711 1712/* Source Address Middle #2 (SAM2) */ 1713#define YUKON_SAM2 0x002c /* SA2[31:16] */ 1714 1715/* Source Address High #2 (SAH2) */ 1716#define YUKON_SAH2 0x0030 /* SA2[47:32] */ 1717 1718/* Multicatst Address Hash Register 1 (MCAH1) */ 1719#define YUKON_MCAH1 0x0034 1720 1721/* Multicatst Address Hash Register 2 (MCAH2) */ 1722#define YUKON_MCAH2 0x0038 1723 1724/* Multicatst Address Hash Register 3 (MCAH3) */ 1725#define YUKON_MCAH3 0x003c 1726 1727/* Multicatst Address Hash Register 4 (MCAH4) */ 1728#define YUKON_MCAH4 0x0040 1729 1730/* Transmit Interrupt Register (TIR) */ 1731#define YUKON_TIR 0x0044 1732 1733#define YU_TIR_OUT_UNICAST 0x0001 /* Num Unicast Packets Transmitted */ 1734#define YU_TIR_OUT_BROADCAST 0x0002 /* Num Broadcast Packets Transmitted */ 1735#define YU_TIR_OUT_PAUSE 0x0004 /* Num Pause Packets Transmitted */ 1736#define YU_TIR_OUT_MULTICAST 0x0008 /* Num Multicast Packets Transmitted */ 1737#define YU_TIR_OUT_OCTETS 0x0030 /* Num Bytes Transmitted */ 1738#define YU_TIR_OUT_64_OCTETS 0x0000 /* Num Packets Transmitted */ 1739#define YU_TIR_OUT_127_OCTETS 0x0000 /* Num Packets Transmitted */ 1740#define YU_TIR_OUT_255_OCTETS 0x0000 /* Num Packets Transmitted */ 1741#define YU_TIR_OUT_511_OCTETS 0x0000 /* Num Packets Transmitted */ 1742#define YU_TIR_OUT_1023_OCTETS 0x0000 /* Num Packets Transmitted */ 1743#define YU_TIR_OUT_1518_OCTETS 0x0000 /* Num Packets Transmitted */ 1744#define YU_TIR_OUT_MAX_OCTETS 0x0000 /* Num Packets Transmitted */ 1745#define YU_TIR_OUT_SPARE 0x0000 /* Num Packets Transmitted */ 1746#define YU_TIR_OUT_COLLISIONS 0x0000 /* Num Packets Transmitted */ 1747#define YU_TIR_OUT_LATE 0x0000 /* Num Packets Transmitted */ 1748 1749/* Receive Interrupt Register (RIR) */ 1750#define YUKON_RIR 0x0048 1751 1752/* Transmit and Receive Interrupt Register (TRIR) */ 1753#define YUKON_TRIR 0x004c 1754 1755/* Transmit Interrupt Mask Register (TIMR) */ 1756#define YUKON_TIMR 0x0050 1757 1758/* Receive Interrupt Mask Register (RIMR) */ 1759#define YUKON_RIMR 0x0054 1760 1761/* Transmit and Receive Interrupt Mask Register (TRIMR) */ 1762#define YUKON_TRIMR 0x0058 1763 1764/* SMI Control Register (SMICR) */ 1765#define YUKON_SMICR 0x0080 1766 1767#define YU_SMICR_PHYAD(x) (((x) & 0x1f) << 11) 1768#define YU_SMICR_REGAD(x) (((x) & 0x1f) << 6) 1769#define YU_SMICR_OPCODE 0x0020 /* opcode (0 - write, 1 - read) */ 1770#define YU_SMICR_OP_READ 0x0020 /* opcode read */ 1771#define YU_SMICR_OP_WRITE 0x0000 /* opcode write */ 1772#define YU_SMICR_READ_VALID 0x0010 /* read valid */ 1773#define YU_SMICR_BUSY 0x0008 /* busy (writing) */ 1774 1775/* SMI Data Register (SMIDR) */ 1776#define YUKON_SMIDR 0x0084 1777 1778/* PHY Addres Register (PAR) */ 1779#define YUKON_PAR 0x0088 1780 1781#define YU_PAR_MIB_CLR 0x0020 /* MIB Counters Clear Mode */ 1782#define YU_PAR_LOAD_TSTCNT 0x0010 /* Load count 0xfffffff0 into cntr */ 1783 1784/* Receive status */ 1785#define YU_RXSTAT_FOFL 0x00000001 /* Rx FIFO overflow */ 1786#define YU_RXSTAT_CRCERR 0x00000002 /* CRC error */ 1787#define YU_RXSTAT_FRAGMENT 0x00000008 /* fragment */ 1788#define YU_RXSTAT_LONGERR 0x00000010 /* too long packet */ 1789#define YU_RXSTAT_MIIERR 0x00000020 /* MII error */ 1790#define YU_RXSTAT_BADFC 0x00000040 /* bad flow-control packet */ 1791#define YU_RXSTAT_GOODFC 0x00000080 /* good flow-control packet */ 1792#define YU_RXSTAT_RXOK 0x00000100 /* receice OK (Good packet) */ 1793#define YU_RXSTAT_BROADCAST 0x00000200 /* broadcast packet */ 1794#define YU_RXSTAT_MULTICAST 0x00000400 /* multicast packet */ 1795#define YU_RXSTAT_RUNT 0x00000800 /* undersize packet */ 1796#define YU_RXSTAT_JABBER 0x00001000 /* jabber packet */ 1797#define YU_RXSTAT_VLAN 0x00002000 /* VLAN packet */ 1798#define YU_RXSTAT_LENSHIFT 16 1799 1800#define YU_RXSTAT_BYTES(x) ((x) >> YU_RXSTAT_LENSHIFT) 1801 1802/* 1803 * Registers and data structures for the XaQti Corporation XMAC II 1804 * Gigabit Ethernet MAC. Datasheet is available from http://www.xaqti.com. 1805 * The XMAC can be programmed for 16-bit or 32-bit register access modes. 1806 * The SysKonnect gigabit ethernet adapters use 16-bit mode, so that's 1807 * how the registers are laid out here. 1808 */ 1809 1810#define XM_DEVICEID 0x00E0AE20 1811#define XM_XAQTI_OUI 0x00E0AE 1812 1813#define XM_XMAC_REV(x) (((x) & 0x000000E0) >> 5) 1814 1815#define XM_XMAC_REV_B2 0x0 1816#define XM_XMAC_REV_C1 0x1 1817 1818#define XM_MMUCMD 0x0000 1819#define XM_POFF 0x0008 1820#define XM_BURST 0x000C 1821#define XM_VLAN_TAGLEV1 0x0010 1822#define XM_VLAN_TAGLEV2 0x0014 1823#define XM_TXCMD 0x0020 1824#define XM_TX_RETRYLIMIT 0x0024 1825#define XM_TX_SLOTTIME 0x0028 1826#define XM_TX_IPG 0x003C 1827#define XM_RXCMD 0x0030 1828#define XM_PHY_ADDR 0x0034 1829#define XM_PHY_DATA 0x0038 1830#define XM_GPIO 0x0040 1831#define XM_IMR 0x0044 1832#define XM_ISR 0x0048 1833#define XM_HWCFG 0x004C 1834#define XM_TX_LOWAT 0x0060 1835#define XM_TX_HIWAT 0x0062 1836#define XM_TX_REQTHRESH_LO 0x0064 1837#define XM_TX_REQTHRESH_HI 0x0066 1838#define XM_TX_REQTHRESH XM_TX_REQTHRESH_LO 1839#define XM_PAUSEDST0 0x0068 1840#define XM_PAUSEDST1 0x006A 1841#define XM_PAUSEDST2 0x006C 1842#define XM_CTLPARM_LO 0x0070 1843#define XM_CTLPARM_HI 0x0072 1844#define XM_CTLPARM XM_CTLPARM_LO 1845#define XM_OPCODE_PAUSE_TIMER 0x0074 1846#define XM_TXSTAT_LIFO 0x0078 1847 1848/* 1849 * Perfect filter registers. The XMAC has a table of 16 perfect 1850 * filter entries, spaced 8 bytes apart. This is in addition to 1851 * the station address registers, which appear below. 1852 */ 1853#define XM_RXFILT_BASE 0x0080 1854#define XM_RXFILT_END 0x0107 1855#define XM_RXFILT_MAX 16 1856#define XM_RXFILT_ENTRY(ent) (XM_RXFILT_BASE + ((ent * 8))) 1857 1858/* Primary station address. */ 1859#define XM_PAR0 0x0108 1860#define XM_PAR1 0x010A 1861#define XM_PAR2 0x010C 1862 1863/* 64-bit multicast hash table registers */ 1864#define XM_MAR0 0x0110 1865#define XM_MAR1 0x0112 1866#define XM_MAR2 0x0114 1867#define XM_MAR3 0x0116 1868#define XM_RX_LOWAT 0x0118 1869#define XM_RX_HIWAT 0x011A 1870#define XM_RX_REQTHRESH_LO 0x011C 1871#define XM_RX_REQTHRESH_HI 0x011E 1872#define XM_RX_REQTHRESH XM_RX_REQTHRESH_LO 1873#define XM_DEVID_LO 0x0120 1874#define XM_DEVID_HI 0x0122 1875#define XM_DEVID XM_DEVID_LO 1876#define XM_MODE_LO 0x0124 1877#define XM_MODE_HI 0x0126 1878#define XM_MODE XM_MODE_LO 1879#define XM_LASTSRC0 0x0128 1880#define XM_LASTSRC1 0x012A 1881#define XM_LASTSRC2 0x012C 1882#define XM_TSTAMP_READ 0x0130 1883#define XM_TSTAMP_LOAD 0x0134 1884#define XM_STATS_CMD 0x0200 1885#define XM_RXCNT_EVENT_LO 0x0204 1886#define XM_RXCNT_EVENT_HI 0x0206 1887#define XM_RXCNT_EVENT XM_RXCNT_EVENT_LO 1888#define XM_TXCNT_EVENT_LO 0x0208 1889#define XM_TXCNT_EVENT_HI 0x020A 1890#define XM_TXCNT_EVENT XM_TXCNT_EVENT_LO 1891#define XM_RXCNT_EVMASK_LO 0x020C 1892#define XM_RXCNT_EVMASK_HI 0x020E 1893#define XM_RXCNT_EVMASK XM_RXCNT_EVMASK_LO 1894#define XM_TXCNT_EVMASK_LO 0x0210 1895#define XM_TXCNT_EVMASK_HI 0x0212 1896#define XM_TXCNT_EVMASK XM_TXCNT_EVMASK_LO 1897 1898/* Statistics command register */ 1899#define XM_STATCMD_CLR_TX 0x0001 1900#define XM_STATCMD_CLR_RX 0x0002 1901#define XM_STATCMD_COPY_TX 0x0004 1902#define XM_STATCMD_COPY_RX 0x0008 1903#define XM_STATCMD_SNAP_TX 0x0010 1904#define XM_STATCMD_SNAP_RX 0x0020 1905 1906/* TX statistics registers */ 1907#define XM_TXSTATS_PKTSOK 0x280 1908#define XM_TXSTATS_BYTESOK_HI 0x284 1909#define XM_TXSTATS_BYTESOK_LO 0x288 1910#define XM_TXSTATS_BCASTSOK 0x28C 1911#define XM_TXSTATS_MCASTSOK 0x290 1912#define XM_TXSTATS_UCASTSOK 0x294 1913#define XM_TXSTATS_GIANTS 0x298 1914#define XM_TXSTATS_BURSTCNT 0x29C 1915#define XM_TXSTATS_PAUSEPKTS 0x2A0 1916#define XM_TXSTATS_MACCTLPKTS 0x2A4 1917#define XM_TXSTATS_SINGLECOLS 0x2A8 1918#define XM_TXSTATS_MULTICOLS 0x2AC 1919#define XM_TXSTATS_EXCESSCOLS 0x2B0 1920#define XM_TXSTATS_LATECOLS 0x2B4 1921#define XM_TXSTATS_DEFER 0x2B8 1922#define XM_TXSTATS_EXCESSDEFER 0x2BC 1923#define XM_TXSTATS_UNDERRUN 0x2C0 1924#define XM_TXSTATS_CARRIERSENSE 0x2C4 1925#define XM_TXSTATS_UTILIZATION 0x2C8 1926#define XM_TXSTATS_64 0x2D0 1927#define XM_TXSTATS_65_127 0x2D4 1928#define XM_TXSTATS_128_255 0x2D8 1929#define XM_TXSTATS_256_511 0x2DC 1930#define XM_TXSTATS_512_1023 0x2E0 1931#define XM_TXSTATS_1024_MAX 0x2E4 1932 1933/* RX statistics registers */ 1934#define XM_RXSTATS_PKTSOK 0x300 1935#define XM_RXSTATS_BYTESOK_HI 0x304 1936#define XM_RXSTATS_BYTESOK_LO 0x308 1937#define XM_RXSTATS_BCASTSOK 0x30C 1938#define XM_RXSTATS_MCASTSOK 0x310 1939#define XM_RXSTATS_UCASTSOK 0x314 1940#define XM_RXSTATS_PAUSEPKTS 0x318 1941#define XM_RXSTATS_MACCTLPKTS 0x31C 1942#define XM_RXSTATS_BADPAUSEPKTS 0x320 1943#define XM_RXSTATS_BADMACCTLPKTS 0x324 1944#define XM_RXSTATS_BURSTCNT 0x328 1945#define XM_RXSTATS_MISSEDPKTS 0x32C 1946#define XM_RXSTATS_FRAMEERRS 0x330 1947#define XM_RXSTATS_OVERRUN 0x334 1948#define XM_RXSTATS_JABBER 0x338 1949#define XM_RXSTATS_CARRLOSS 0x33C 1950#define XM_RXSTATS_INRNGLENERR 0x340 1951#define XM_RXSTATS_SYMERR 0x344 1952#define XM_RXSTATS_SHORTEVENT 0x348 1953#define XM_RXSTATS_RUNTS 0x34C 1954#define XM_RXSTATS_GIANTS 0x350 1955#define XM_RXSTATS_CRCERRS 0x354 1956#define XM_RXSTATS_CEXTERRS 0x35C 1957#define XM_RXSTATS_UTILIZATION 0x360 1958#define XM_RXSTATS_64 0x368 1959#define XM_RXSTATS_65_127 0x36C 1960#define XM_RXSTATS_128_255 0x370 1961#define XM_RXSTATS_256_511 0x374 1962#define XM_RXSTATS_512_1023 0x378 1963#define XM_RXSTATS_1024_MAX 0x37C 1964 1965#define XM_MMUCMD_TX_ENB 0x0001 1966#define XM_MMUCMD_RX_ENB 0x0002 1967#define XM_MMUCMD_GMIILOOP 0x0004 1968#define XM_MMUCMD_RATECTL 0x0008 1969#define XM_MMUCMD_GMIIFDX 0x0010 1970#define XM_MMUCMD_NO_MGMT_PRMB 0x0020 1971#define XM_MMUCMD_SIMCOL 0x0040 1972#define XM_MMUCMD_FORCETX 0x0080 1973#define XM_MMUCMD_LOOPENB 0x0200 1974#define XM_MMUCMD_IGNPAUSE 0x0400 1975#define XM_MMUCMD_PHYBUSY 0x0800 1976#define XM_MMUCMD_PHYDATARDY 0x1000 1977 1978#define XM_TXCMD_AUTOPAD 0x0001 1979#define XM_TXCMD_NOCRC 0x0002 1980#define XM_TXCMD_NOPREAMBLE 0x0004 1981#define XM_TXCMD_NOGIGAMODE 0x0008 1982#define XM_TXCMD_SAMPLELINE 0x0010 1983#define XM_TXCMD_ENCBYPASS 0x0020 1984#define XM_TXCMD_XMITBK2BK 0x0040 1985#define XM_TXCMD_FAIRSHARE 0x0080 1986 1987#define XM_RXCMD_DISABLE_CEXT 0x0001 1988#define XM_RXCMD_STRIPPAD 0x0002 1989#define XM_RXCMD_SAMPLELINE 0x0004 1990#define XM_RXCMD_SELFRX 0x0008 1991#define XM_RXCMD_STRIPFCS 0x0010 1992#define XM_RXCMD_TRANSPARENT 0x0020 1993#define XM_RXCMD_IPGCAPTURE 0x0040 1994#define XM_RXCMD_BIGPKTOK 0x0080 1995#define XM_RXCMD_LENERROK 0x0100 1996 1997#define XM_GPIO_GP0_SET 0x0001 1998#define XM_GPIO_RESETSTATS 0x0004 1999#define XM_GPIO_RESETMAC 0x0008 2000#define XM_GPIO_FORCEINT 0x0020 2001#define XM_GPIO_ANEGINPROG 0x0040 2002 2003#define XM_IMR_RX_EOF 0x0001 2004#define XM_IMR_TX_EOF 0x0002 2005#define XM_IMR_TX_UNDERRUN 0x0004 2006#define XM_IMR_RX_OVERRUN 0x0008 2007#define XM_IMR_TX_STATS_OFLOW 0x0010 2008#define XM_IMR_RX_STATS_OFLOW 0x0020 2009#define XM_IMR_TSTAMP_OFLOW 0x0040 2010#define XM_IMR_AUTONEG_DONE 0x0080 2011#define XM_IMR_NEXTPAGE_RDY 0x0100 2012#define XM_IMR_PAGE_RECEIVED 0x0200 2013#define XM_IMR_LP_REQCFG 0x0400 2014#define XM_IMR_GP0_SET 0x0800 2015#define XM_IMR_FORCEINTR 0x1000 2016#define XM_IMR_TX_ABORT 0x2000 2017#define XM_IMR_LINKEVENT 0x4000 2018 2019#define XM_INTRS \ 2020 (~(XM_IMR_GP0_SET|XM_IMR_AUTONEG_DONE|XM_IMR_TX_UNDERRUN)) 2021 2022#define XM_ISR_RX_EOF 0x0001 2023#define XM_ISR_TX_EOF 0x0002 2024#define XM_ISR_TX_UNDERRUN 0x0004 2025#define XM_ISR_RX_OVERRUN 0x0008 2026#define XM_ISR_TX_STATS_OFLOW 0x0010 2027#define XM_ISR_RX_STATS_OFLOW 0x0020 2028#define XM_ISR_TSTAMP_OFLOW 0x0040 2029#define XM_ISR_AUTONEG_DONE 0x0080 2030#define XM_ISR_NEXTPAGE_RDY 0x0100 2031#define XM_ISR_PAGE_RECEIVED 0x0200 2032#define XM_ISR_LP_REQCFG 0x0400 2033#define XM_ISR_GP0_SET 0x0800 2034#define XM_ISR_FORCEINTR 0x1000 2035#define XM_ISR_TX_ABORT 0x2000 2036#define XM_ISR_LINKEVENT 0x4000 2037 2038#define XM_HWCFG_GENEOP 0x0008 2039#define XM_HWCFG_SIGSTATCKH 0x0004 2040#define XM_HWCFG_GMIIMODE 0x0001 2041 2042#define XM_MODE_FLUSH_RXFIFO 0x00000001 2043#define XM_MODE_FLUSH_TXFIFO 0x00000002 2044#define XM_MODE_BIGENDIAN 0x00000004 2045#define XM_MODE_RX_PROMISC 0x00000008 2046#define XM_MODE_RX_NOBROAD 0x00000010 2047#define XM_MODE_RX_NOMULTI 0x00000020 2048#define XM_MODE_RX_NOUNI 0x00000040 2049#define XM_MODE_RX_BADFRAMES 0x00000080 2050#define XM_MODE_RX_CRCERRS 0x00000100 2051#define XM_MODE_RX_GIANTS 0x00000200 2052#define XM_MODE_RX_INRANGELEN 0x00000400 2053#define XM_MODE_RX_RUNTS 0x00000800 2054#define XM_MODE_RX_MACCTL 0x00001000 2055#define XM_MODE_RX_USE_PERFECT 0x00002000 2056#define XM_MODE_RX_USE_STATION 0x00004000 2057#define XM_MODE_RX_USE_HASH 0x00008000 2058#define XM_MODE_RX_ADDRPAIR 0x00010000 2059#define XM_MODE_PAUSEONHI 0x00020000 2060#define XM_MODE_PAUSEONLO 0x00040000 2061#define XM_MODE_TIMESTAMP 0x00080000 2062#define XM_MODE_SENDPAUSE 0x00100000 2063#define XM_MODE_SENDCONTINUOUS 0x00200000 2064#define XM_MODE_LE_STATUSWORD 0x00400000 2065#define XM_MODE_AUTOFIFOPAUSE 0x00800000 2066#define XM_MODE_EXPAUSEGEN 0x02000000 2067#define XM_MODE_RX_INVERSE 0x04000000 2068 2069#define XM_RXSTAT_MACCTL 0x00000001 2070#define XM_RXSTAT_ERRFRAME 0x00000002 2071#define XM_RXSTAT_CRCERR 0x00000004 2072#define XM_RXSTAT_GIANT 0x00000008 2073#define XM_RXSTAT_RUNT 0x00000010 2074#define XM_RXSTAT_FRAMEERR 0x00000020 2075#define XM_RXSTAT_INRANGEERR 0x00000040 2076#define XM_RXSTAT_CARRIERERR 0x00000080 2077#define XM_RXSTAT_COLLERR 0x00000100 2078#define XM_RXSTAT_802_3 0x00000200 2079#define XM_RXSTAT_CARREXTERR 0x00000400 2080#define XM_RXSTAT_BURSTMODE 0x00000800 2081#define XM_RXSTAT_UNICAST 0x00002000 2082#define XM_RXSTAT_MULTICAST 0x00004000 2083#define XM_RXSTAT_BROADCAST 0x00008000 2084#define XM_RXSTAT_VLAN_LEV1 0x00010000 2085#define XM_RXSTAT_VLAN_LEV2 0x00020000 2086#define XM_RXSTAT_LEN 0xFFFC0000 2087#define XM_RXSTAT_LENSHIFT 18 2088 2089#define XM_RXSTAT_BYTES(x) ((x) >> XM_RXSTAT_LENSHIFT) 2090 2091/* 2092 * XMAC PHY registers, indirectly accessed through 2093 * XM_PHY_ADDR and XM_PHY_REG. 2094 */ 2095 2096#define XM_PHY_BMCR 0x0000 /* control */ 2097#define XM_PHY_BMSR 0x0001 /* status */ 2098#define XM_PHY_VENID 0x0002 /* vendor id */ 2099#define XM_PHY_DEVID 0x0003 /* device id */ 2100#define XM_PHY_ANAR 0x0004 /* autoneg advertisenemt */ 2101#define XM_PHY_LPAR 0x0005 /* link partner ability */ 2102#define XM_PHY_ANEXP 0x0006 /* autoneg expansion */ 2103#define XM_PHY_NEXTP 0x0007 /* nextpage */ 2104#define XM_PHY_LPNEXTP 0x0008 /* link partner's nextpage */ 2105#define XM_PHY_EXTSTS 0x000F /* extented status */ 2106#define XM_PHY_RESAB 0x0010 /* resolved ability */ 2107 2108#define XM_BMCR_DUPLEX 0x0100 2109#define XM_BMCR_RENEGOTIATE 0x0200 2110#define XM_BMCR_AUTONEGENBL 0x1000 2111#define XM_BMCR_LOOPBACK 0x4000 2112#define XM_BMCR_RESET 0x8000 2113 2114#define XM_BMSR_EXTCAP 0x0001 2115#define XM_BMSR_LINKSTAT 0x0004 2116#define XM_BMSR_AUTONEGABLE 0x0008 2117#define XM_BMSR_REMFAULT 0x0010 2118#define XM_BMSR_AUTONEGDONE 0x0020 2119#define XM_BMSR_EXTSTAT 0x0100 2120 2121#define XM_VENID_XAQTI 0xD14C 2122#define XM_DEVID_XMAC 0x0002 2123 2124#define XM_ANAR_FULLDUPLEX 0x0020 2125#define XM_ANAR_HALFDUPLEX 0x0040 2126#define XM_ANAR_PAUSEBITS 0x0180 2127#define XM_ANAR_REMFAULTBITS 0x1800 2128#define XM_ANAR_ACK 0x4000 2129#define XM_ANAR_NEXTPAGE 0x8000 2130 2131#define XM_LPAR_FULLDUPLEX 0x0020 2132#define XM_LPAR_HALFDUPLEX 0x0040 2133#define XM_LPAR_PAUSEBITS 0x0180 2134#define XM_LPAR_REMFAULTBITS 0x1800 2135#define XM_LPAR_ACK 0x4000 2136#define XM_LPAR_NEXTPAGE 0x8000 2137 2138#define XM_PAUSE_NOPAUSE 0x0000 2139#define XM_PAUSE_SYMPAUSE 0x0080 2140#define XM_PAUSE_ASYMPAUSE 0x0100 2141#define XM_PAUSE_BOTH 0x0180 2142 2143#define XM_REMFAULT_LINKOK 0x0000 2144#define XM_REMFAULT_LINKFAIL 0x0800 2145#define XM_REMFAULT_OFFLINE 0x1000 2146#define XM_REMFAULT_ANEGERR 0x1800 2147 2148#define XM_ANEXP_GOTPAGE 0x0002 2149#define XM_ANEXP_NEXTPAGE_SELF 0x0004 2150#define XM_ANEXP_NEXTPAGE_LP 0x0008 2151 2152#define XM_NEXTP_MESSAGE 0x07FF 2153#define XM_NEXTP_TOGGLE 0x0800 2154#define XM_NEXTP_ACK2 0x1000 2155#define XM_NEXTP_MPAGE 0x2000 2156#define XM_NEXTP_ACK1 0x4000 2157#define XM_NEXTP_NPAGE 0x8000 2158 2159#define XM_LPNEXTP_MESSAGE 0x07FF 2160#define XM_LPNEXTP_TOGGLE 0x0800 2161#define XM_LPNEXTP_ACK2 0x1000 2162#define XM_LPNEXTP_MPAGE 0x2000 2163#define XM_LPNEXTP_ACK1 0x4000 2164#define XM_LPNEXTP_NPAGE 0x8000 2165 2166#define XM_EXTSTS_HALFDUPLEX 0x4000 2167#define XM_EXTSTS_FULLDUPLEX 0x8000 2168 2169#define XM_RESAB_PAUSEMISMATCH 0x0008 2170#define XM_RESAB_ABLMISMATCH 0x0010 2171#define XM_RESAB_FDMODESEL 0x0020 2172#define XM_RESAB_HDMODESEL 0x0040 2173#define XM_RESAB_PAUSEBITS 0x0180 2174