if_sk.c revision 1.88
1/* $OpenBSD: if_sk.c,v 1.88 2005/11/26 19:16:28 brad Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37/* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53/* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72/* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89#include "bpfilter.h" 90 91#include <sys/param.h> 92#include <sys/systm.h> 93#include <sys/sockio.h> 94#include <sys/mbuf.h> 95#include <sys/malloc.h> 96#include <sys/kernel.h> 97#include <sys/socket.h> 98#include <sys/device.h> 99#include <sys/queue.h> 100 101#include <net/if.h> 102#include <net/if_dl.h> 103#include <net/if_types.h> 104 105#ifdef INET 106#include <netinet/in.h> 107#include <netinet/in_systm.h> 108#include <netinet/in_var.h> 109#include <netinet/ip.h> 110#include <netinet/udp.h> 111#include <netinet/tcp.h> 112#include <netinet/if_ether.h> 113#endif 114 115#include <net/if_media.h> 116#include <net/if_vlan_var.h> 117 118#if NBPFILTER > 0 119#include <net/bpf.h> 120#endif 121 122#include <dev/mii/mii.h> 123#include <dev/mii/miivar.h> 124#include <dev/mii/brgphyreg.h> 125 126#include <dev/pci/pcireg.h> 127#include <dev/pci/pcivar.h> 128#include <dev/pci/pcidevs.h> 129 130#define SK_VERBOSE 131/* #define SK_USEIOSPACE */ 132 133#include <dev/pci/if_skreg.h> 134#include <dev/pci/if_skvar.h> 135 136int skc_probe(struct device *, void *, void *); 137void skc_attach(struct device *, struct device *self, void *aux); 138int sk_probe(struct device *, void *, void *); 139void sk_attach(struct device *, struct device *self, void *aux); 140int skcprint(void *, const char *); 141int sk_intr(void *); 142void sk_intr_bcom(struct sk_if_softc *); 143void sk_intr_xmac(struct sk_if_softc *); 144void sk_intr_yukon(struct sk_if_softc *); 145void sk_rxeof(struct sk_if_softc *); 146void sk_txeof(struct sk_if_softc *); 147int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 148void sk_start(struct ifnet *); 149int sk_ioctl(struct ifnet *, u_long, caddr_t); 150void sk_init(void *); 151void sk_init_xmac(struct sk_if_softc *); 152void sk_init_yukon(struct sk_if_softc *); 153void sk_stop(struct sk_if_softc *); 154void sk_watchdog(struct ifnet *); 155void sk_shutdown(void *); 156int sk_ifmedia_upd(struct ifnet *); 157void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 158void sk_reset(struct sk_softc *); 159int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 160int sk_alloc_jumbo_mem(struct sk_if_softc *); 161void *sk_jalloc(struct sk_if_softc *); 162void sk_jfree(caddr_t, u_int, void *); 163int sk_init_rx_ring(struct sk_if_softc *); 164int sk_init_tx_ring(struct sk_if_softc *); 165 166int sk_xmac_miibus_readreg(struct device *, int, int); 167void sk_xmac_miibus_writereg(struct device *, int, int, int); 168void sk_xmac_miibus_statchg(struct device *); 169 170int sk_marv_miibus_readreg(struct device *, int, int); 171void sk_marv_miibus_writereg(struct device *, int, int, int); 172void sk_marv_miibus_statchg(struct device *); 173 174u_int32_t sk_xmac_hash(caddr_t); 175u_int32_t sk_yukon_hash(caddr_t); 176void sk_setfilt(struct sk_if_softc *, caddr_t, int); 177void sk_setmulti(struct sk_if_softc *); 178void sk_tick(void *); 179void sk_rxcsum(struct ifnet *, struct mbuf *, const u_int16_t, const u_int16_t); 180 181#ifdef SK_DEBUG 182#define DPRINTF(x) if (skdebug) printf x 183#define DPRINTFN(n,x) if (skdebug >= (n)) printf x 184int skdebug = 0; 185 186void sk_dump_txdesc(struct sk_tx_desc *, int); 187void sk_dump_mbuf(struct mbuf *); 188void sk_dump_bytes(const char *, int); 189#else 190#define DPRINTF(x) 191#define DPRINTFN(n,x) 192#endif 193 194#define SK_SETBIT(sc, reg, x) \ 195 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 196 197#define SK_CLRBIT(sc, reg, x) \ 198 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 199 200#define SK_WIN_SETBIT_4(sc, reg, x) \ 201 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 202 203#define SK_WIN_CLRBIT_4(sc, reg, x) \ 204 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 205 206#define SK_WIN_SETBIT_2(sc, reg, x) \ 207 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 208 209#define SK_WIN_CLRBIT_2(sc, reg, x) \ 210 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 211 212/* supported device vendors */ 213const struct pci_matchid skc_devices[] = { 214 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940 }, 215 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940B }, 216 { PCI_VENDOR_CNET, PCI_PRODUCT_CNET_GIGACARD }, 217 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T }, 218 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 219 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2 }, 220 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064 }, 221 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON }, 222 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_BELKIN }, 223 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_2 }, 224 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_3 }, 225 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 226 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 227 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 228 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 229 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 230 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 231 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 232 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 233 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 234 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 235 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 236 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 237 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 238 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK98XX }, 239 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK98XX2 }, 240 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Sxx }, 241 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Exx }, 242}; 243 244#define SK_LINKSYS_EG1032_SUBID 0x00151737 245 246static inline u_int32_t 247sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 248{ 249#ifdef SK_USEIOSPACE 250 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 251 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 252#else 253 return CSR_READ_4(sc, reg); 254#endif 255} 256 257static inline u_int16_t 258sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 259{ 260#ifdef SK_USEIOSPACE 261 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 262 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 263#else 264 return CSR_READ_2(sc, reg); 265#endif 266} 267 268static inline u_int8_t 269sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 270{ 271#ifdef SK_USEIOSPACE 272 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 273 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 274#else 275 return CSR_READ_1(sc, reg); 276#endif 277} 278 279static inline void 280sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 281{ 282#ifdef SK_USEIOSPACE 283 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 284 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 285#else 286 CSR_WRITE_4(sc, reg, x); 287#endif 288} 289 290static inline void 291sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 292{ 293#ifdef SK_USEIOSPACE 294 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 295 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 296#else 297 CSR_WRITE_2(sc, reg, x); 298#endif 299} 300 301static inline void 302sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 303{ 304#ifdef SK_USEIOSPACE 305 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 306 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 307#else 308 CSR_WRITE_1(sc, reg, x); 309#endif 310} 311 312int 313sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 314{ 315 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 316 int i; 317 318 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 319 320 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 321 return(0); 322 323 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 324 SK_XM_READ_2(sc_if, XM_PHY_DATA); 325 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 326 for (i = 0; i < SK_TIMEOUT; i++) { 327 DELAY(1); 328 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 329 XM_MMUCMD_PHYDATARDY) 330 break; 331 } 332 333 if (i == SK_TIMEOUT) { 334 printf("%s: phy failed to come ready\n", 335 sc_if->sk_dev.dv_xname); 336 return(0); 337 } 338 } 339 DELAY(1); 340 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 341} 342 343void 344sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 345{ 346 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 347 int i; 348 349 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 350 351 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 352 for (i = 0; i < SK_TIMEOUT; i++) { 353 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 354 break; 355 } 356 357 if (i == SK_TIMEOUT) { 358 printf("%s: phy failed to come ready\n", 359 sc_if->sk_dev.dv_xname); 360 return; 361 } 362 363 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 364 for (i = 0; i < SK_TIMEOUT; i++) { 365 DELAY(1); 366 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 367 break; 368 } 369 370 if (i == SK_TIMEOUT) 371 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 372} 373 374void 375sk_xmac_miibus_statchg(struct device *dev) 376{ 377 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 378 struct mii_data *mii = &sc_if->sk_mii; 379 380 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 381 382 /* 383 * If this is a GMII PHY, manually set the XMAC's 384 * duplex mode accordingly. 385 */ 386 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 387 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 388 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 389 } else { 390 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 391 } 392 } 393} 394 395int 396sk_marv_miibus_readreg(dev, phy, reg) 397 struct device *dev; 398 int phy, reg; 399{ 400 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 401 u_int16_t val; 402 int i; 403 404 if (phy != 0 || 405 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 406 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 407 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 408 phy, reg)); 409 return(0); 410 } 411 412 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 413 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 414 415 for (i = 0; i < SK_TIMEOUT; i++) { 416 DELAY(1); 417 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 418 if (val & YU_SMICR_READ_VALID) 419 break; 420 } 421 422 if (i == SK_TIMEOUT) { 423 printf("%s: phy failed to come ready\n", 424 sc_if->sk_dev.dv_xname); 425 return 0; 426 } 427 428 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 429 SK_TIMEOUT)); 430 431 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 432 433 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 434 phy, reg, val)); 435 436 return val; 437} 438 439void 440sk_marv_miibus_writereg(dev, phy, reg, val) 441 struct device *dev; 442 int phy, reg, val; 443{ 444 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 445 int i; 446 447 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 448 phy, reg, val)); 449 450 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 451 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 452 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 453 454 for (i = 0; i < SK_TIMEOUT; i++) { 455 DELAY(1); 456 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 457 break; 458 } 459} 460 461void 462sk_marv_miibus_statchg(dev) 463 struct device *dev; 464{ 465 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 466 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 467} 468 469#define HASH_BITS 6 470 471u_int32_t 472sk_xmac_hash(caddr_t addr) 473{ 474 u_int32_t crc; 475 476 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 477 return (~crc & ((1 << HASH_BITS) - 1)); 478} 479 480u_int32_t 481sk_yukon_hash(caddr_t addr) 482{ 483 u_int32_t crc; 484 485 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 486 return (crc & ((1 << HASH_BITS) - 1)); 487} 488 489void 490sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 491{ 492 int base = XM_RXFILT_ENTRY(slot); 493 494 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 495 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 496 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 497} 498 499void 500sk_setmulti(struct sk_if_softc *sc_if) 501{ 502 struct sk_softc *sc = sc_if->sk_softc; 503 struct ifnet *ifp= &sc_if->arpcom.ac_if; 504 u_int32_t hashes[2] = { 0, 0 }; 505 int h, i; 506 struct arpcom *ac = &sc_if->arpcom; 507 struct ether_multi *enm; 508 struct ether_multistep step; 509 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 510 511 /* First, zot all the existing filters. */ 512 switch(sc->sk_type) { 513 case SK_GENESIS: 514 for (i = 1; i < XM_RXFILT_MAX; i++) 515 sk_setfilt(sc_if, (caddr_t)&dummy, i); 516 517 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 518 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 519 break; 520 case SK_YUKON: 521 case SK_YUKON_LITE: 522 case SK_YUKON_LP: 523 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 524 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 525 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 526 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 527 break; 528 } 529 530 /* Now program new ones. */ 531allmulti: 532 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 533 hashes[0] = 0xFFFFFFFF; 534 hashes[1] = 0xFFFFFFFF; 535 } else { 536 i = 1; 537 /* First find the tail of the list. */ 538 ETHER_FIRST_MULTI(step, ac, enm); 539 while (enm != NULL) { 540 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 541 ETHER_ADDR_LEN)) { 542 ifp->if_flags |= IFF_ALLMULTI; 543 goto allmulti; 544 } 545 /* 546 * Program the first XM_RXFILT_MAX multicast groups 547 * into the perfect filter. For all others, 548 * use the hash table. 549 */ 550 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 551 sk_setfilt(sc_if, enm->enm_addrlo, i); 552 i++; 553 } 554 else { 555 switch(sc->sk_type) { 556 case SK_GENESIS: 557 h = sk_xmac_hash(enm->enm_addrlo); 558 break; 559 560 case SK_YUKON: 561 case SK_YUKON_LITE: 562 case SK_YUKON_LP: 563 h = sk_yukon_hash(enm->enm_addrlo); 564 break; 565 } 566 if (h < 32) 567 hashes[0] |= (1 << h); 568 else 569 hashes[1] |= (1 << (h - 32)); 570 } 571 572 ETHER_NEXT_MULTI(step, enm); 573 } 574 } 575 576 switch(sc->sk_type) { 577 case SK_GENESIS: 578 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 579 XM_MODE_RX_USE_PERFECT); 580 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 581 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 582 break; 583 case SK_YUKON: 584 case SK_YUKON_LITE: 585 case SK_YUKON_LP: 586 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 587 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 588 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 589 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 590 break; 591 } 592} 593 594int 595sk_init_rx_ring(struct sk_if_softc *sc_if) 596{ 597 struct sk_chain_data *cd = &sc_if->sk_cdata; 598 struct sk_ring_data *rd = sc_if->sk_rdata; 599 int i; 600 601 bzero((char *)rd->sk_rx_ring, 602 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 603 604 for (i = 0; i < SK_RX_RING_CNT; i++) { 605 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 606 if (i == (SK_RX_RING_CNT - 1)) { 607 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 608 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 609 } else { 610 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 611 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 612 } 613 rd->sk_rx_ring[i].sk_csum1_start = ETHER_HDR_LEN; 614 rd->sk_rx_ring[i].sk_csum2_start = ETHER_HDR_LEN + 615 sizeof(struct ip); 616 } 617 618 for (i = 0; i < SK_RX_RING_CNT; i++) { 619 if (sk_newbuf(sc_if, i, NULL, 620 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 621 printf("%s: failed alloc of %dth mbuf\n", 622 sc_if->sk_dev.dv_xname, i); 623 return(ENOBUFS); 624 } 625 } 626 627 sc_if->sk_cdata.sk_rx_prod = 0; 628 sc_if->sk_cdata.sk_rx_cons = 0; 629 630 return(0); 631} 632 633int 634sk_init_tx_ring(struct sk_if_softc *sc_if) 635{ 636 struct sk_softc *sc = sc_if->sk_softc; 637 struct sk_chain_data *cd = &sc_if->sk_cdata; 638 struct sk_ring_data *rd = sc_if->sk_rdata; 639 bus_dmamap_t dmamap; 640 struct sk_txmap_entry *entry; 641 int i; 642 643 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 644 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 645 646 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 647 for (i = 0; i < SK_TX_RING_CNT; i++) { 648 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 649 if (i == (SK_TX_RING_CNT - 1)) { 650 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 651 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 652 } else { 653 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 654 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 655 } 656 657 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 658 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 659 return (ENOBUFS); 660 661 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 662 if (!entry) { 663 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 664 return (ENOBUFS); 665 } 666 entry->dmamap = dmamap; 667 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 668 } 669 670 sc_if->sk_cdata.sk_tx_prod = 0; 671 sc_if->sk_cdata.sk_tx_cons = 0; 672 sc_if->sk_cdata.sk_tx_cnt = 0; 673 674 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 675 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 676 677 return (0); 678} 679 680int 681sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 682 bus_dmamap_t dmamap) 683{ 684 struct mbuf *m_new = NULL; 685 struct sk_chain *c; 686 struct sk_rx_desc *r; 687 688 if (m == NULL) { 689 caddr_t buf = NULL; 690 691 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 692 if (m_new == NULL) 693 return(ENOBUFS); 694 695 /* Allocate the jumbo buffer */ 696 buf = sk_jalloc(sc_if); 697 if (buf == NULL) { 698 m_freem(m_new); 699 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 700 "dropped!\n", sc_if->arpcom.ac_if.if_xname)); 701 return(ENOBUFS); 702 } 703 704 /* Attach the buffer to the mbuf */ 705 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 706 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 707 } else { 708 /* 709 * We're re-using a previously allocated mbuf; 710 * be sure to re-init pointers and lengths to 711 * default values. 712 */ 713 m_new = m; 714 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 715 m_new->m_data = m_new->m_ext.ext_buf; 716 } 717 m_adj(m_new, ETHER_ALIGN); 718 719 c = &sc_if->sk_cdata.sk_rx_chain[i]; 720 r = c->sk_desc; 721 c->sk_mbuf = m_new; 722 r->sk_data_lo = dmamap->dm_segs[0].ds_addr + 723 (((vaddr_t)m_new->m_data 724 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf)); 725 r->sk_ctl = SK_JLEN | SK_RXSTAT; 726 727 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 728 729 return(0); 730} 731 732/* 733 * Memory management for jumbo frames. 734 */ 735 736int 737sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 738{ 739 struct sk_softc *sc = sc_if->sk_softc; 740 caddr_t ptr, kva; 741 bus_dma_segment_t seg; 742 int i, rseg, state, error; 743 struct sk_jpool_entry *entry; 744 745 state = error = 0; 746 747 /* Grab a big chunk o' storage. */ 748 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 749 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 750 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 751 return (ENOBUFS); 752 } 753 754 state = 1; 755 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, &kva, 756 BUS_DMA_NOWAIT)) { 757 printf("%s: can't map dma buffers (%d bytes)\n", 758 sc->sk_dev.dv_xname, SK_JMEM); 759 error = ENOBUFS; 760 goto out; 761 } 762 763 state = 2; 764 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 765 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 766 printf("%s: can't create dma map\n", sc->sk_dev.dv_xname); 767 error = ENOBUFS; 768 goto out; 769 } 770 771 state = 3; 772 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 773 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 774 printf("%s: can't load dma map\n", sc->sk_dev.dv_xname); 775 error = ENOBUFS; 776 goto out; 777 } 778 779 state = 4; 780 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 781 DPRINTFN(1,("sk_jumbo_buf = 0x%08X\n", sc_if->sk_cdata.sk_jumbo_buf)); 782 783 LIST_INIT(&sc_if->sk_jfree_listhead); 784 LIST_INIT(&sc_if->sk_jinuse_listhead); 785 786 /* 787 * Now divide it up into 9K pieces and save the addresses 788 * in an array. 789 */ 790 ptr = sc_if->sk_cdata.sk_jumbo_buf; 791 for (i = 0; i < SK_JSLOTS; i++) { 792 sc_if->sk_cdata.sk_jslots[i] = ptr; 793 ptr += SK_JLEN; 794 entry = malloc(sizeof(struct sk_jpool_entry), 795 M_DEVBUF, M_NOWAIT); 796 if (entry == NULL) { 797 printf("%s: no memory for jumbo buffer queue!\n", 798 sc->sk_dev.dv_xname); 799 error = ENOBUFS; 800 goto out; 801 } 802 entry->slot = i; 803 if (i) 804 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 805 entry, jpool_entries); 806 else 807 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 808 entry, jpool_entries); 809 } 810out: 811 if (error != 0) { 812 switch (state) { 813 case 4: 814 bus_dmamap_unload(sc->sc_dmatag, 815 sc_if->sk_cdata.sk_rx_jumbo_map); 816 case 3: 817 bus_dmamap_destroy(sc->sc_dmatag, 818 sc_if->sk_cdata.sk_rx_jumbo_map); 819 case 2: 820 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 821 case 1: 822 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 823 break; 824 default: 825 break; 826 } 827 } 828 829 return (error); 830} 831 832/* 833 * Allocate a jumbo buffer. 834 */ 835void * 836sk_jalloc(struct sk_if_softc *sc_if) 837{ 838 struct sk_jpool_entry *entry; 839 840 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 841 842 if (entry == NULL) 843 return (NULL); 844 845 LIST_REMOVE(entry, jpool_entries); 846 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 847 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 848} 849 850/* 851 * Release a jumbo buffer. 852 */ 853void 854sk_jfree(caddr_t buf, u_int size, void *arg) 855{ 856 struct sk_jpool_entry *entry; 857 struct sk_if_softc *sc; 858 int i; 859 860 /* Extract the softc struct pointer. */ 861 sc = (struct sk_if_softc *)arg; 862 863 if (sc == NULL) 864 panic("sk_jfree: can't find softc pointer!"); 865 866 /* calculate the slot this buffer belongs to */ 867 868 i = ((vaddr_t)buf 869 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 870 871 if ((i < 0) || (i >= SK_JSLOTS)) 872 panic("sk_jfree: asked to free buffer that we don't manage!"); 873 874 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 875 if (entry == NULL) 876 panic("sk_jfree: buffer not in use!"); 877 entry->slot = i; 878 LIST_REMOVE(entry, jpool_entries); 879 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 880} 881 882/* 883 * Set media options. 884 */ 885int 886sk_ifmedia_upd(struct ifnet *ifp) 887{ 888 struct sk_if_softc *sc_if = ifp->if_softc; 889 890 sk_init(sc_if); 891 mii_mediachg(&sc_if->sk_mii); 892 return(0); 893} 894 895/* 896 * Report current media status. 897 */ 898void 899sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 900{ 901 struct sk_if_softc *sc_if = ifp->if_softc; 902 903 mii_pollstat(&sc_if->sk_mii); 904 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 905 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 906} 907 908int 909sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 910{ 911 struct sk_if_softc *sc_if = ifp->if_softc; 912 struct sk_softc *sc = sc_if->sk_softc; 913 struct ifreq *ifr = (struct ifreq *) data; 914 struct ifaddr *ifa = (struct ifaddr *) data; 915 struct mii_data *mii; 916 int s, error = 0; 917 918 s = splnet(); 919 920 if ((error = ether_ioctl(ifp, &sc_if->arpcom, command, data)) > 0) { 921 splx(s); 922 return error; 923 } 924 925 switch(command) { 926 case SIOCSIFADDR: 927 ifp->if_flags |= IFF_UP; 928 switch (ifa->ifa_addr->sa_family) { 929#ifdef INET 930 case AF_INET: 931 sk_init(sc_if); 932 arp_ifinit(&sc_if->arpcom, ifa); 933 break; 934#endif /* INET */ 935 default: 936 sk_init(sc_if); 937 break; 938 } 939 break; 940 case SIOCSIFMTU: 941 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 942 error = EINVAL; 943 else if (ifp->if_mtu != ifr->ifr_mtu) 944 ifp->if_mtu = ifr->ifr_mtu; 945 break; 946 case SIOCSIFFLAGS: 947 if (ifp->if_flags & IFF_UP) { 948 if (ifp->if_flags & IFF_RUNNING && 949 ifp->if_flags & IFF_PROMISC && 950 !(sc_if->sk_if_flags & IFF_PROMISC)) { 951 switch(sc->sk_type) { 952 case SK_GENESIS: 953 SK_XM_SETBIT_4(sc_if, XM_MODE, 954 XM_MODE_RX_PROMISC); 955 break; 956 case SK_YUKON: 957 case SK_YUKON_LITE: 958 case SK_YUKON_LP: 959 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 960 YU_RCR_UFLEN | YU_RCR_MUFLEN); 961 break; 962 } 963 sk_setmulti(sc_if); 964 } else if (ifp->if_flags & IFF_RUNNING && 965 !(ifp->if_flags & IFF_PROMISC) && 966 sc_if->sk_if_flags & IFF_PROMISC) { 967 switch(sc->sk_type) { 968 case SK_GENESIS: 969 SK_XM_CLRBIT_4(sc_if, XM_MODE, 970 XM_MODE_RX_PROMISC); 971 break; 972 case SK_YUKON: 973 case SK_YUKON_LITE: 974 case SK_YUKON_LP: 975 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 976 YU_RCR_UFLEN | YU_RCR_MUFLEN); 977 break; 978 } 979 980 sk_setmulti(sc_if); 981 } else 982 sk_init(sc_if); 983 } else { 984 if (ifp->if_flags & IFF_RUNNING) 985 sk_stop(sc_if); 986 } 987 sc_if->sk_if_flags = ifp->if_flags; 988 error = 0; 989 break; 990 case SIOCADDMULTI: 991 case SIOCDELMULTI: 992 error = (command == SIOCADDMULTI) ? 993 ether_addmulti(ifr, &sc_if->arpcom) : 994 ether_delmulti(ifr, &sc_if->arpcom); 995 996 if (error == ENETRESET) { 997 /* 998 * Multicast list has changed; set the hardware 999 * filter accordingly. 1000 */ 1001 if (ifp->if_flags & IFF_RUNNING) 1002 sk_setmulti(sc_if); 1003 error = 0; 1004 } 1005 break; 1006 case SIOCGIFMEDIA: 1007 case SIOCSIFMEDIA: 1008 mii = &sc_if->sk_mii; 1009 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1010 break; 1011 default: 1012 error = EINVAL; 1013 break; 1014 } 1015 1016 splx(s); 1017 1018 return(error); 1019} 1020 1021/* 1022 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1023 * IDs against our list and return a device name if we find a match. 1024 */ 1025int 1026skc_probe(struct device *parent, void *match, void *aux) 1027{ 1028 struct pci_attach_args *pa = aux; 1029 pci_chipset_tag_t pc = pa->pa_pc; 1030 pcireg_t subid; 1031 1032 subid = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1033 1034 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1035 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1036 subid == SK_LINKSYS_EG1032_SUBID) 1037 return (1); 1038 1039 return (pci_matchbyid((struct pci_attach_args *)aux, skc_devices, 1040 sizeof(skc_devices)/sizeof(skc_devices[0]))); 1041} 1042 1043/* 1044 * Force the GEnesis into reset, then bring it out of reset. 1045 */ 1046void sk_reset(struct sk_softc *sc) 1047{ 1048 u_int32_t imtimer_ticks; 1049 1050 DPRINTFN(2, ("sk_reset\n")); 1051 1052 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1053 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1054 if (SK_YUKON_FAMILY(sc->sk_type)) 1055 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1056 1057 DELAY(1000); 1058 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1059 DELAY(2); 1060 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1061 if (SK_YUKON_FAMILY(sc->sk_type)) 1062 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1063 1064 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1065 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1066 CSR_READ_2(sc, SK_LINK_CTRL))); 1067 1068 if (sc->sk_type == SK_GENESIS) { 1069 /* Configure packet arbiter */ 1070 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1071 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1072 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1073 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1074 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1075 } 1076 1077 /* Enable RAM interface */ 1078 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1079 1080 /* 1081 * Configure interrupt moderation. The moderation timer 1082 * defers interrupts specified in the interrupt moderation 1083 * timer mask based on the timeout specified in the interrupt 1084 * moderation timer init register. Each bit in the timer 1085 * register represents one tick, so to specify a timeout in 1086 * microseconds, we have to multiply by the correct number of 1087 * ticks-per-microsecond. 1088 */ 1089 switch (sc->sk_type) { 1090 case SK_GENESIS: 1091 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1092 break; 1093 case SK_YUKON_EC: 1094 case SK_YUKON_XL: 1095 case SK_YUKON_FE: 1096 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1097 break; 1098 default: 1099 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1100 } 1101 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(100)); 1102 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1103 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1104 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1105} 1106 1107int 1108sk_probe(struct device *parent, void *match, void *aux) 1109{ 1110 struct skc_attach_args *sa = aux; 1111 1112 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1113 return(0); 1114 1115 switch (sa->skc_type) { 1116 case SK_GENESIS: 1117 case SK_YUKON: 1118 case SK_YUKON_LITE: 1119 case SK_YUKON_LP: 1120#ifdef not_quite_yet 1121 case SK_YUKON_XL: 1122 case SK_YUKON_EC_U: 1123 case SK_YUKON_EC: 1124 case SK_YUKON_FE: 1125#endif 1126 return (1); 1127 } 1128 1129 return (0); 1130} 1131 1132/* 1133 * Each XMAC chip is attached as a separate logical IP interface. 1134 * Single port cards will have only one logical interface of course. 1135 */ 1136void 1137sk_attach(struct device *parent, struct device *self, void *aux) 1138{ 1139 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1140 struct sk_softc *sc = (struct sk_softc *)parent; 1141 struct skc_attach_args *sa = aux; 1142 struct ifnet *ifp; 1143 caddr_t kva; 1144 bus_dma_segment_t seg; 1145 int i, rseg; 1146 1147 sc_if->sk_port = sa->skc_port; 1148 sc_if->sk_softc = sc; 1149 sc->sk_if[sa->skc_port] = sc_if; 1150 1151 if (sa->skc_port == SK_PORT_A) 1152 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1153 if (sa->skc_port == SK_PORT_B) 1154 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1155 1156 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1157 1158 /* 1159 * Get station address for this interface. Note that 1160 * dual port cards actually come with three station 1161 * addresses: one for each port, plus an extra. The 1162 * extra one is used by the SysKonnect driver software 1163 * as a 'virtual' station address for when both ports 1164 * are operating in failover mode. Currently we don't 1165 * use this extra address. 1166 */ 1167 for (i = 0; i < ETHER_ADDR_LEN; i++) 1168 sc_if->arpcom.ac_enaddr[i] = 1169 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1170 1171 1172 printf(": address %s\n", 1173 ether_sprintf(sc_if->arpcom.ac_enaddr)); 1174 1175 /* 1176 * Set up RAM buffer addresses. The NIC will have a certain 1177 * amount of SRAM on it, somewhere between 512K and 2MB. We 1178 * need to divide this up a) between the transmitter and 1179 * receiver and b) between the two XMACs, if this is a 1180 * dual port NIC. Our algorithm is to divide up the memory 1181 * evenly so that everyone gets a fair share. 1182 * 1183 * Just to be contrary, Yukon2 appears to have separate memory 1184 * for each MAC. 1185 */ 1186 if (SK_IS_YUKON2(sc) || 1187 sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1188 u_int32_t chunk, val; 1189 1190 chunk = sc->sk_ramsize / 2; 1191 val = sc->sk_rboff / sizeof(u_int64_t); 1192 sc_if->sk_rx_ramstart = val; 1193 val += (chunk / sizeof(u_int64_t)); 1194 sc_if->sk_rx_ramend = val - 1; 1195 sc_if->sk_tx_ramstart = val; 1196 val += (chunk / sizeof(u_int64_t)); 1197 sc_if->sk_tx_ramend = val - 1; 1198 } else { 1199 u_int32_t chunk, val; 1200 1201 chunk = sc->sk_ramsize / 4; 1202 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1203 sizeof(u_int64_t); 1204 sc_if->sk_rx_ramstart = val; 1205 val += (chunk / sizeof(u_int64_t)); 1206 sc_if->sk_rx_ramend = val - 1; 1207 sc_if->sk_tx_ramstart = val; 1208 val += (chunk / sizeof(u_int64_t)); 1209 sc_if->sk_tx_ramend = val - 1; 1210 } 1211 1212 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1213 " tx_ramstart=%#x tx_ramend=%#x\n", 1214 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1215 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1216 1217 /* Read and save PHY type and set PHY address */ 1218 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1219 switch (sc_if->sk_phytype) { 1220 case SK_PHYTYPE_XMAC: 1221 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1222 break; 1223 case SK_PHYTYPE_BCOM: 1224 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1225 break; 1226 case SK_PHYTYPE_MARV_COPPER: 1227 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1228 break; 1229 default: 1230 printf("%s: unsupported PHY type: %d\n", 1231 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1232 return; 1233 } 1234 if (SK_IS_YUKON2(sc) && sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1235 sc->sk_pmd != IFM_1000_SX && sc->sk_pmd != IFM_1000_LX) { 1236 /* not initialized, punt */ 1237 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1238 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1239 } 1240 1241 /* Allocate the descriptor queues. */ 1242 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1243 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1244 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 1245 goto fail; 1246 } 1247 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1248 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1249 printf("%s: can't map dma buffers (%d bytes)\n", 1250 sc_if->sk_dev.dv_xname, sizeof(struct sk_ring_data)); 1251 goto fail_1; 1252 } 1253 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1254 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1255 &sc_if->sk_ring_map)) { 1256 printf("%s: can't create dma map\n", sc_if->sk_dev.dv_xname); 1257 goto fail_2; 1258 } 1259 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1260 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1261 printf("%s: can't load dma map\n", sc_if->sk_dev.dv_xname); 1262 goto fail_3; 1263 } 1264 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1265 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1266 1267 /* Try to allocate memory for jumbo buffers. */ 1268 if (sk_alloc_jumbo_mem(sc_if)) { 1269 printf("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1270 goto fail_3; 1271 } 1272 1273 ifp = &sc_if->arpcom.ac_if; 1274 ifp->if_softc = sc_if; 1275 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1276 ifp->if_ioctl = sk_ioctl; 1277 ifp->if_start = sk_start; 1278 ifp->if_watchdog = sk_watchdog; 1279 ifp->if_baudrate = 1000000000; 1280 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1281 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1282 IFQ_SET_READY(&ifp->if_snd); 1283 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1284 1285 /* 1286 * Do miibus setup. 1287 */ 1288 switch (sc->sk_type) { 1289 case SK_GENESIS: 1290 sk_init_xmac(sc_if); 1291 break; 1292 case SK_YUKON: 1293 case SK_YUKON_LITE: 1294 case SK_YUKON_LP: 1295 case SK_YUKON_XL: 1296 case SK_YUKON_EC_U: 1297 case SK_YUKON_EC: 1298 case SK_YUKON_FE: 1299 sk_init_yukon(sc_if); 1300 break; 1301 default: 1302 printf("%s: unknown device type %d\n", sc->sk_dev.dv_xname, 1303 sc->sk_type); 1304 /* dealloc jumbo on error */ 1305 goto fail_3; 1306 } 1307 1308 DPRINTFN(2, ("sk_attach: 1\n")); 1309 1310 sc_if->sk_mii.mii_ifp = ifp; 1311 if (sc->sk_type == SK_GENESIS) { 1312 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1313 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1314 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1315 } else { 1316 /* yukon/yukon2 */ 1317 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1318 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1319 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1320 } 1321 1322 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1323 sk_ifmedia_upd, sk_ifmedia_sts); 1324 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1325 MII_OFFSET_ANY, 0); 1326 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1327 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1328 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1329 0, NULL); 1330 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1331 } 1332 else 1333 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1334 1335 timeout_set(&sc_if->sk_tick_ch, sk_tick, sc_if); 1336 timeout_add(&sc_if->sk_tick_ch, hz); 1337 1338 DPRINTFN(2, ("sk_attach: 1\n")); 1339 1340 /* 1341 * Call MI attach routines. 1342 */ 1343 if_attach(ifp); 1344 ether_ifattach(ifp); 1345 1346 DPRINTFN(2, ("sk_attach: end\n")); 1347 1348 return; 1349 1350fail_3: 1351 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1352fail_2: 1353 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct sk_ring_data)); 1354fail_1: 1355 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1356fail: 1357 sc->sk_if[sa->skc_port] = NULL; 1358} 1359 1360int 1361skcprint(void *aux, const char *pnp) 1362{ 1363 struct skc_attach_args *sa = aux; 1364 1365 if (pnp) 1366 printf("sk port %c at %s", 1367 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1368 else 1369 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1370 return (UNCONF); 1371} 1372 1373/* 1374 * Attach the interface. Allocate softc structures, do ifmedia 1375 * setup and ethernet/BPF attach. 1376 */ 1377void 1378skc_attach(struct device *parent, struct device *self, void *aux) 1379{ 1380 struct sk_softc *sc = (struct sk_softc *)self; 1381 struct pci_attach_args *pa = aux; 1382 struct skc_attach_args skca; 1383 pci_chipset_tag_t pc = pa->pa_pc; 1384 pcireg_t command, memtype; 1385 pci_intr_handle_t ih; 1386 const char *intrstr = NULL; 1387 bus_size_t size; 1388 u_int8_t skrs; 1389 char *revstr = NULL; 1390 1391 DPRINTFN(2, ("begin skc_attach\n")); 1392 1393 /* 1394 * Handle power management nonsense. 1395 */ 1396 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1397 1398 if (command == 0x01) { 1399 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1400 if (command & SK_PSTATE_MASK) { 1401 u_int32_t iobase, membase, irq; 1402 1403 /* Save important PCI config data. */ 1404 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1405 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1406 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1407 1408 /* Reset the power state. */ 1409 printf("%s chip is in D%d power mode " 1410 "-- setting to D0\n", sc->sk_dev.dv_xname, 1411 command & SK_PSTATE_MASK); 1412 command &= 0xFFFFFFFC; 1413 pci_conf_write(pc, pa->pa_tag, 1414 SK_PCI_PWRMGMTCTRL, command); 1415 1416 /* Restore PCI config data. */ 1417 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1418 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1419 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1420 } 1421 } 1422 1423 /* 1424 * Map control/status registers. 1425 */ 1426 1427#ifdef SK_USEIOSPACE 1428 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1429 &sc->sk_btag, &sc->sk_bhandle, NULL, &size, 0)) { 1430 printf(": can't map i/o space\n"); 1431 return; 1432 } 1433#else 1434 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1435 switch (memtype) { 1436 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1437 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1438 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1439 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1440 NULL, &size, 0) == 0) 1441 break; 1442 default: 1443 printf(": can't map mem space\n"); 1444 return; 1445 } 1446#endif 1447 sc->sc_dmatag = pa->pa_dmat; 1448 1449 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1450 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1451 1452 /* bail out here if chip is not recognized */ 1453 if (sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1454 printf("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1455 goto fail_1; 1456 } 1457 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1458 1459 /* Allocate interrupt */ 1460 if (pci_intr_map(pa, &ih)) { 1461 printf(": couldn't map interrupt\n"); 1462 goto fail_1; 1463 } 1464 1465 intrstr = pci_intr_string(pc, ih); 1466 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc, 1467 self->dv_xname); 1468 if (sc->sk_intrhand == NULL) { 1469 printf(": couldn't establish interrupt"); 1470 if (intrstr != NULL) 1471 printf(" at %s", intrstr); 1472 printf("\n"); 1473 goto fail_1; 1474 } 1475 printf(": %s\n", intrstr); 1476 1477 /* Reset the adapter. */ 1478 sk_reset(sc); 1479 1480 skrs = sk_win_read_1(sc, SK_EPROM0); 1481 if (sc->sk_type == SK_GENESIS) { 1482 /* Read and save RAM size and RAMbuffer offset */ 1483 switch(skrs) { 1484 case SK_RAMSIZE_512K_64: 1485 sc->sk_ramsize = 0x80000; 1486 sc->sk_rboff = SK_RBOFF_0; 1487 break; 1488 case SK_RAMSIZE_1024K_64: 1489 sc->sk_ramsize = 0x100000; 1490 sc->sk_rboff = SK_RBOFF_80000; 1491 break; 1492 case SK_RAMSIZE_1024K_128: 1493 sc->sk_ramsize = 0x100000; 1494 sc->sk_rboff = SK_RBOFF_0; 1495 break; 1496 case SK_RAMSIZE_2048K_128: 1497 sc->sk_ramsize = 0x200000; 1498 sc->sk_rboff = SK_RBOFF_0; 1499 break; 1500 default: 1501 printf("%s: unknown ram size: %d\n", 1502 sc->sk_dev.dv_xname, skrs); 1503 goto fail_2; 1504 break; 1505 } 1506 } else { 1507 if (skrs == 0x00) 1508 sc->sk_ramsize = 0x20000; 1509 else 1510 sc->sk_ramsize = skrs * (1<<12); 1511 sc->sk_rboff = SK_RBOFF_0; 1512 } 1513 1514 DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n", 1515 sc->sk_ramsize, sc->sk_ramsize / 1024, 1516 sc->sk_rboff)); 1517 1518 /* Read and save physical media type */ 1519 skrs = sk_win_read_1(sc, SK_PMDTYPE); 1520 if (SK_IS_YUKON2(sc)) { 1521 switch (skrs) { 1522 case 'L': 1523 sc->sk_pmd = IFM_1000_LX; 1524 break; 1525 case 'S': 1526 sc->sk_pmd = IFM_1000_SX; 1527 break; 1528 case SK_PMD_1000BASETX: 1529 case SK_PMD_1000BASETX_ALT: 1530 default: 1531 sc->sk_pmd = IFM_1000_T; 1532 break; 1533 } 1534 } else { 1535 switch (skrs) { 1536 case SK_PMD_1000BASESX: 1537 sc->sk_pmd = IFM_1000_SX; 1538 break; 1539 case SK_PMD_1000BASELX: 1540 sc->sk_pmd = IFM_1000_LX; 1541 break; 1542 case SK_PMD_1000BASECX: 1543 sc->sk_pmd = IFM_1000_CX; 1544 break; 1545 case SK_PMD_1000BASETX: 1546 case SK_PMD_1000BASETX_ALT: 1547 sc->sk_pmd = IFM_1000_T; 1548 break; 1549 default: 1550 printf("%s: unknown media type: 0x%x\n", 1551 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1552 goto fail_2; 1553 } 1554 } 1555 1556 switch (sc->sk_type) { 1557 case SK_GENESIS: 1558 sc->sk_name = "SysKonnect GEnesis"; 1559 break; 1560 case SK_YUKON: 1561 sc->sk_name = "Marvell Yukon"; 1562 break; 1563 case SK_YUKON_LITE: 1564 sc->sk_name = "Marvell Yukon Lite"; 1565 break; 1566 case SK_YUKON_LP: 1567 sc->sk_name = "Marvell Yukon LP"; 1568 break; 1569 case SK_YUKON_XL: 1570 sc->sk_name = "Marvell Yukon-2 XL"; 1571 break; 1572 case SK_YUKON_EC_U: 1573 sc->sk_name = "Marvell Yukon-2 EC Ultra"; 1574 break; 1575 case SK_YUKON_EC: 1576 sc->sk_name = "Marvell Yukon-2 EC"; 1577 break; 1578 case SK_YUKON_FE: 1579 sc->sk_name = "Marvell Yukon-2 FE"; 1580 break; 1581 default: 1582 sc->sk_name = "Marvell Yukon (Unknown)"; 1583 } 1584 1585 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1586 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1587 uint32_t flashaddr; 1588 uint8_t testbyte; 1589 1590 flashaddr = sk_win_read_4(sc, SK_EP_ADDR); 1591 1592 /* test Flash-Address Register */ 1593 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff); 1594 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1595 1596 if (testbyte != 0) { 1597 /* This is a Yukon Lite Rev A0 */ 1598 sc->sk_type = SK_YUKON_LITE; 1599 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1600 /* restore Flash-Address Register */ 1601 sk_win_write_4(sc, SK_EP_ADDR, flashaddr); 1602 } 1603 } 1604 1605 if (sc->sk_type == SK_YUKON_LITE) { 1606 switch (sc->sk_rev) { 1607 case SK_YUKON_LITE_REV_A0: 1608 revstr = "A0"; 1609 break; 1610 case SK_YUKON_LITE_REV_A1: 1611 revstr = "A1"; 1612 break; 1613 case SK_YUKON_LITE_REV_A3: 1614 revstr = "A3"; 1615 break; 1616 default: 1617 ; 1618 } 1619 } 1620 1621 /* Announce the product name. */ 1622 printf("%s: %s", sc->sk_dev.dv_xname, sc->sk_name); 1623 if (revstr != NULL) 1624 printf(" rev. %s", revstr); 1625 printf(" (0x%x)\n", sc->sk_rev); 1626 1627 skca.skc_port = SK_PORT_A; 1628 skca.skc_type = sc->sk_type; 1629 skca.skc_rev = sc->sk_rev; 1630 (void)config_found(&sc->sk_dev, &skca, skcprint); 1631 1632 if (SK_IS_YUKON2(sc)) { 1633 u_int8_t hw; 1634 1635 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1636 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1637 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1638 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) { 1639 skca.skc_port = SK_PORT_B; 1640 skca.skc_type = sc->sk_type; 1641 skca.skc_rev = sc->sk_rev; 1642 (void)config_found(&sc->sk_dev, &skca, 1643 skcprint); 1644 } 1645 } 1646 } else { 1647 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1648 skca.skc_port = SK_PORT_B; 1649 skca.skc_type = sc->sk_type; 1650 skca.skc_rev = sc->sk_rev; 1651 (void)config_found(&sc->sk_dev, &skca, skcprint); 1652 } 1653 } 1654 1655 /* Turn on the 'driver is loaded' LED. */ 1656 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1657 1658 return; 1659 1660fail_2: 1661 pci_intr_disestablish(pc, sc->sk_intrhand); 1662fail_1: 1663 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1664} 1665 1666int 1667sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1668{ 1669 struct sk_softc *sc = sc_if->sk_softc; 1670 struct sk_tx_desc *f = NULL; 1671 u_int32_t frag, cur, cnt = 0; 1672 int i; 1673 struct sk_txmap_entry *entry; 1674 bus_dmamap_t txmap; 1675 1676 DPRINTFN(2, ("sk_encap\n")); 1677 1678 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1679 if (entry == NULL) { 1680 DPRINTFN(2, ("sk_encap: no txmap available\n")); 1681 return ENOBUFS; 1682 } 1683 txmap = entry->dmamap; 1684 1685 cur = frag = *txidx; 1686 1687#ifdef SK_DEBUG 1688 if (skdebug >= 2) 1689 sk_dump_mbuf(m_head); 1690#endif 1691 1692 /* 1693 * Start packing the mbufs in this chain into 1694 * the fragment pointers. Stop when we run out 1695 * of fragments or hit the end of the mbuf chain. 1696 */ 1697 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1698 BUS_DMA_NOWAIT)) { 1699 DPRINTFN(2, ("sk_encap: dmamap failed\n")); 1700 return(ENOBUFS); 1701 } 1702 1703 DPRINTFN(2, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1704 1705 /* Sync the DMA map. */ 1706 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1707 BUS_DMASYNC_PREWRITE); 1708 1709 for (i = 0; i < txmap->dm_nsegs; i++) { 1710 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1711 DPRINTFN(2, ("sk_encap: too few descriptors free\n")); 1712 return(ENOBUFS); 1713 } 1714 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1715 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1716 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1717 if (cnt == 0) 1718 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1719 else 1720 f->sk_ctl |= SK_TXCTL_OWN; 1721 1722 cur = frag; 1723 SK_INC(frag, SK_TX_RING_CNT); 1724 cnt++; 1725 } 1726 1727 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1728 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1729 1730 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1731 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1732 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1733 1734 /* Sync descriptors before handing to chip */ 1735 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1736 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1737 1738 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1739 1740 /* Sync first descriptor to hand it off */ 1741 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1742 1743 sc_if->sk_cdata.sk_tx_cnt += cnt; 1744 1745#ifdef SK_DEBUG 1746 if (skdebug >= 2) { 1747 struct sk_tx_desc *desc; 1748 u_int32_t idx; 1749 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1750 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1751 sk_dump_txdesc(desc, idx); 1752 } 1753 } 1754#endif 1755 1756 *txidx = frag; 1757 1758 DPRINTFN(2, ("sk_encap: completed successfully\n")); 1759 1760 return(0); 1761} 1762 1763void 1764sk_start(struct ifnet *ifp) 1765{ 1766 struct sk_if_softc *sc_if = ifp->if_softc; 1767 struct sk_softc *sc = sc_if->sk_softc; 1768 struct mbuf *m_head = NULL; 1769 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1770 int pkts = 0; 1771 1772 DPRINTFN(2, ("sk_start\n")); 1773 1774 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1775 IFQ_POLL(&ifp->if_snd, m_head); 1776 if (m_head == NULL) 1777 break; 1778 1779 /* 1780 * Pack the data into the transmit ring. If we 1781 * don't have room, set the OACTIVE flag and wait 1782 * for the NIC to drain the ring. 1783 */ 1784 if (sk_encap(sc_if, m_head, &idx)) { 1785 ifp->if_flags |= IFF_OACTIVE; 1786 break; 1787 } 1788 1789 /* now we are committed to transmit the packet */ 1790 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1791 pkts++; 1792 1793 /* 1794 * If there's a BPF listener, bounce a copy of this frame 1795 * to him. 1796 */ 1797#if NBPFILTER > 0 1798 if (ifp->if_bpf) 1799 bpf_mtap(ifp->if_bpf, m_head); 1800#endif 1801 } 1802 if (pkts == 0) 1803 return; 1804 1805 /* Transmit */ 1806 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1807 sc_if->sk_cdata.sk_tx_prod = idx; 1808 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1809 1810 /* Set a timeout in case the chip goes out to lunch. */ 1811 ifp->if_timer = 5; 1812 } 1813} 1814 1815 1816void 1817sk_watchdog(struct ifnet *ifp) 1818{ 1819 struct sk_if_softc *sc_if = ifp->if_softc; 1820 1821 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1822 ifp->if_flags &= ~IFF_RUNNING; 1823 sk_init(sc_if); 1824} 1825 1826void 1827sk_shutdown(void *v) 1828{ 1829 struct sk_softc *sc = v; 1830 1831 DPRINTFN(2, ("sk_shutdown\n")); 1832 1833 /* Turn off the 'driver is loaded' LED. */ 1834 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1835 1836 /* 1837 * Reset the GEnesis controller. Doing this should also 1838 * assert the resets on the attached XMAC(s). 1839 */ 1840 sk_reset(sc); 1841} 1842 1843void 1844sk_rxeof(struct sk_if_softc *sc_if) 1845{ 1846 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1847 struct mbuf *m; 1848 struct sk_chain *cur_rx; 1849 struct sk_rx_desc *cur_desc; 1850 int i, cur, total_len = 0; 1851 u_int32_t rxstat; 1852 bus_dmamap_t dmamap; 1853 u_int16_t csum1, csum2; 1854 1855 DPRINTFN(2, ("sk_rxeof\n")); 1856 1857 i = sc_if->sk_cdata.sk_rx_prod; 1858 1859 for (;;) { 1860 cur = i; 1861 1862 /* Sync the descriptor */ 1863 SK_CDRXSYNC(sc_if, cur, 1864 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1865 1866 if (sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN) { 1867 /* Invalidate the descriptor -- it's not ready yet */ 1868 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 1869 sc_if->sk_cdata.sk_rx_prod = i; 1870 break; 1871 } 1872 1873 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1874 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1875 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1876 1877 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1878 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1879 1880 rxstat = cur_desc->sk_xmac_rxstat; 1881 m = cur_rx->sk_mbuf; 1882 cur_rx->sk_mbuf = NULL; 1883 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1884 1885 csum1 = sc_if->sk_rdata->sk_rx_ring[i].sk_csum1; 1886 csum2 = sc_if->sk_rdata->sk_rx_ring[i].sk_csum2; 1887 1888 SK_INC(i, SK_RX_RING_CNT); 1889 1890 if (rxstat & XM_RXSTAT_ERRFRAME) { 1891 ifp->if_ierrors++; 1892 sk_newbuf(sc_if, cur, m, dmamap); 1893 continue; 1894 } 1895 1896 /* 1897 * Try to allocate a new jumbo buffer. If that 1898 * fails, copy the packet to mbufs and put the 1899 * jumbo buffer back in the ring so it can be 1900 * re-used. If allocating mbufs fails, then we 1901 * have to drop the packet. 1902 */ 1903 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1904 struct mbuf *m0; 1905 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1906 total_len + ETHER_ALIGN, 0, ifp, NULL); 1907 sk_newbuf(sc_if, cur, m, dmamap); 1908 if (m0 == NULL) { 1909 ifp->if_ierrors++; 1910 continue; 1911 } 1912 m_adj(m0, ETHER_ALIGN); 1913 m = m0; 1914 } else { 1915 m->m_pkthdr.rcvif = ifp; 1916 m->m_pkthdr.len = m->m_len = total_len; 1917 } 1918 1919 ifp->if_ipackets++; 1920 1921 sk_rxcsum(ifp, m, csum1, csum2); 1922 1923#if NBPFILTER > 0 1924 if (ifp->if_bpf) 1925 bpf_mtap(ifp->if_bpf, m); 1926#endif 1927 1928 /* pass it on. */ 1929 ether_input_mbuf(ifp, m); 1930 } 1931} 1932 1933void 1934sk_rxcsum(struct ifnet *ifp, struct mbuf *m, const u_int16_t csum1, const u_int16_t csum2) 1935{ 1936 struct ether_header *eh; 1937 struct ip *ip; 1938 u_int8_t *pp; 1939 int hlen, len, plen; 1940 u_int16_t iph_csum, ipo_csum, ipd_csum, csum; 1941 1942 pp = mtod(m, u_int8_t *); 1943 plen = m->m_pkthdr.len; 1944 if (plen < sizeof(*eh)) 1945 return; 1946 eh = (struct ether_header *)pp; 1947 iph_csum = in_cksum_addword(csum1, (~csum2 & 0xffff)); 1948 1949 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1950 u_int16_t *xp = (u_int16_t *)pp; 1951 1952 xp = (u_int16_t *)pp; 1953 if (xp[1] != htons(ETHERTYPE_IP)) 1954 return; 1955 iph_csum = in_cksum_addword(iph_csum, (~xp[0] & 0xffff)); 1956 iph_csum = in_cksum_addword(iph_csum, (~xp[1] & 0xffff)); 1957 xp = (u_int16_t *)(pp + sizeof(struct ip)); 1958 iph_csum = in_cksum_addword(iph_csum, xp[0]); 1959 iph_csum = in_cksum_addword(iph_csum, xp[1]); 1960 pp += EVL_ENCAPLEN; 1961 } else if (eh->ether_type != htons(ETHERTYPE_IP)) 1962 return; 1963 1964 pp += sizeof(*eh); 1965 plen -= sizeof(*eh); 1966 1967 ip = (struct ip *)pp; 1968 1969 if (ip->ip_v != IPVERSION) 1970 return; 1971 1972 hlen = ip->ip_hl << 2; 1973 if (hlen < sizeof(struct ip)) 1974 return; 1975 if (hlen > ntohs(ip->ip_len)) 1976 return; 1977 1978 /* Don't deal with truncated or padded packets. */ 1979 if (plen != ntohs(ip->ip_len)) 1980 return; 1981 1982 len = hlen - sizeof(struct ip); 1983 if (len > 0) { 1984 u_int16_t *p; 1985 1986 p = (u_int16_t *)(ip + 1); 1987 ipo_csum = 0; 1988 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++) 1989 ipo_csum = in_cksum_addword(ipo_csum, *p); 1990 iph_csum = in_cksum_addword(iph_csum, ipo_csum); 1991 ipd_csum = in_cksum_addword(csum2, (~ipo_csum & 0xffff)); 1992 } else 1993 ipd_csum = csum2; 1994 1995 if (iph_csum != 0xffff) 1996 return; 1997 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1998 1999 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 2000 return; /* ip frag, we're done for now */ 2001 2002 pp += hlen; 2003 2004 /* Only know checksum protocol for udp/tcp */ 2005 if (ip->ip_p == IPPROTO_UDP) { 2006 struct udphdr *uh = (struct udphdr *)pp; 2007 2008 if (uh->uh_sum == 0) /* udp with no checksum */ 2009 return; 2010 } else if (ip->ip_p != IPPROTO_TCP) 2011 return; 2012 2013 csum = in_cksum_phdr(ip->ip_src.s_addr, ip->ip_dst.s_addr, 2014 htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum); 2015 if (csum == 0xffff) { 2016 m->m_pkthdr.csum_flags |= (ip->ip_p == IPPROTO_TCP) ? 2017 M_TCP_CSUM_IN_OK : M_UDP_CSUM_IN_OK; 2018 } 2019} 2020 2021void 2022sk_txeof(struct sk_if_softc *sc_if) 2023{ 2024 struct sk_softc *sc = sc_if->sk_softc; 2025 struct sk_tx_desc *cur_tx; 2026 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2027 u_int32_t idx; 2028 struct sk_txmap_entry *entry; 2029 2030 DPRINTFN(2, ("sk_txeof\n")); 2031 2032 /* 2033 * Go through our tx ring and free mbufs for those 2034 * frames that have been sent. 2035 */ 2036 idx = sc_if->sk_cdata.sk_tx_cons; 2037 while(idx != sc_if->sk_cdata.sk_tx_prod) { 2038 SK_CDTXSYNC(sc_if, idx, 1, 2039 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2040 2041 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2042#ifdef SK_DEBUG 2043 if (skdebug >= 2) 2044 sk_dump_txdesc(cur_tx, idx); 2045#endif 2046 if (cur_tx->sk_ctl & SK_TXCTL_OWN) { 2047 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2048 break; 2049 } 2050 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 2051 ifp->if_opackets++; 2052 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2053 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2054 2055 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2056 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2057 2058 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2059 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2060 2061 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2062 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2063 link); 2064 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2065 } 2066 sc_if->sk_cdata.sk_tx_cnt--; 2067 SK_INC(idx, SK_TX_RING_CNT); 2068 } 2069 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2070 ifp->if_timer = 0; 2071 else /* nudge chip to keep tx ring moving */ 2072 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2073 2074 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2075 ifp->if_flags &= ~IFF_OACTIVE; 2076 2077 sc_if->sk_cdata.sk_tx_cons = idx; 2078} 2079 2080void 2081sk_tick(void *xsc_if) 2082{ 2083 struct sk_if_softc *sc_if = xsc_if; 2084 struct mii_data *mii = &sc_if->sk_mii; 2085 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2086 int i; 2087 2088 DPRINTFN(2, ("sk_tick\n")); 2089 2090 if (!(ifp->if_flags & IFF_UP)) 2091 return; 2092 2093 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2094 sk_intr_bcom(sc_if); 2095 return; 2096 } 2097 2098 /* 2099 * According to SysKonnect, the correct way to verify that 2100 * the link has come back up is to poll bit 0 of the GPIO 2101 * register three times. This pin has the signal from the 2102 * link sync pin connected to it; if we read the same link 2103 * state 3 times in a row, we know the link is up. 2104 */ 2105 for (i = 0; i < 3; i++) { 2106 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2107 break; 2108 } 2109 2110 if (i != 3) { 2111 timeout_add(&sc_if->sk_tick_ch, hz); 2112 return; 2113 } 2114 2115 /* Turn the GP0 interrupt back on. */ 2116 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2117 SK_XM_READ_2(sc_if, XM_ISR); 2118 mii_tick(mii); 2119 timeout_del(&sc_if->sk_tick_ch); 2120} 2121 2122void 2123sk_intr_bcom(struct sk_if_softc *sc_if) 2124{ 2125 struct mii_data *mii = &sc_if->sk_mii; 2126 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2127 int status; 2128 2129 DPRINTFN(2, ("sk_intr_bcom\n")); 2130 2131 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2132 2133 /* 2134 * Read the PHY interrupt register to make sure 2135 * we clear any pending interrupts. 2136 */ 2137 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2138 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2139 2140 if (!(ifp->if_flags & IFF_RUNNING)) { 2141 sk_init_xmac(sc_if); 2142 return; 2143 } 2144 2145 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2146 int lstat; 2147 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2148 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2149 2150 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2151 mii_mediachg(mii); 2152 /* Turn off the link LED. */ 2153 SK_IF_WRITE_1(sc_if, 0, 2154 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2155 sc_if->sk_link = 0; 2156 } else if (status & BRGPHY_ISR_LNK_CHG) { 2157 sk_xmac_miibus_writereg((struct device *)sc_if, 2158 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2159 mii_tick(mii); 2160 sc_if->sk_link = 1; 2161 /* Turn on the link LED. */ 2162 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2163 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2164 SK_LINKLED_BLINK_OFF); 2165 } else { 2166 mii_tick(mii); 2167 timeout_add(&sc_if->sk_tick_ch, hz); 2168 } 2169 } 2170 2171 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2172} 2173 2174void 2175sk_intr_xmac(struct sk_if_softc *sc_if) 2176{ 2177 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2178 2179 DPRINTFN(2, ("sk_intr_xmac\n")); 2180 2181 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2182 if (status & XM_ISR_GP0_SET) { 2183 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2184 timeout_add(&sc_if->sk_tick_ch, hz); 2185 } 2186 2187 if (status & XM_ISR_AUTONEG_DONE) { 2188 timeout_add(&sc_if->sk_tick_ch, hz); 2189 } 2190 } 2191 2192 if (status & XM_IMR_TX_UNDERRUN) 2193 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2194 2195 if (status & XM_IMR_RX_OVERRUN) 2196 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2197} 2198 2199void 2200sk_intr_yukon(sc_if) 2201 struct sk_if_softc *sc_if; 2202{ 2203 int status; 2204 2205 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2206 2207 DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status)); 2208} 2209 2210int 2211sk_intr(void *xsc) 2212{ 2213 struct sk_softc *sc = xsc; 2214 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2215 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2216 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2217 u_int32_t status; 2218 int claimed = 0; 2219 2220 if (sc_if0 != NULL) 2221 ifp0 = &sc_if0->arpcom.ac_if; 2222 if (sc_if1 != NULL) 2223 ifp1 = &sc_if1->arpcom.ac_if; 2224 2225 for (;;) { 2226 status = CSR_READ_4(sc, SK_ISSR); 2227 DPRINTFN(2, ("sk_intr: status=%#x\n", status)); 2228 2229 if (!(status & sc->sk_intrmask)) 2230 break; 2231 2232 claimed = 1; 2233 2234 /* Handle receive interrupts first. */ 2235 if (status & SK_ISR_RX1_EOF) { 2236 sk_rxeof(sc_if0); 2237 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2238 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2239 } 2240 if (status & SK_ISR_RX2_EOF) { 2241 sk_rxeof(sc_if1); 2242 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2243 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2244 } 2245 2246 /* Then transmit interrupts. */ 2247 if (status & SK_ISR_TX1_S_EOF) { 2248 sk_txeof(sc_if0); 2249 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2250 SK_TXBMU_CLR_IRQ_EOF); 2251 } 2252 if (status & SK_ISR_TX2_S_EOF) { 2253 sk_txeof(sc_if1); 2254 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2255 SK_TXBMU_CLR_IRQ_EOF); 2256 } 2257 2258 /* Then MAC interrupts. */ 2259 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 2260 if (sc->sk_type == SK_GENESIS) 2261 sk_intr_xmac(sc_if0); 2262 else 2263 sk_intr_yukon(sc_if0); 2264 } 2265 2266 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 2267 if (sc->sk_type == SK_GENESIS) 2268 sk_intr_xmac(sc_if1); 2269 else 2270 sk_intr_yukon(sc_if1); 2271 2272 } 2273 2274 if (status & SK_ISR_EXTERNAL_REG) { 2275 if (ifp0 != NULL && 2276 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2277 sk_intr_bcom(sc_if0); 2278 2279 if (ifp1 != NULL && 2280 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2281 sk_intr_bcom(sc_if1); 2282 } 2283 } 2284 2285 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2286 2287 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2288 sk_start(ifp0); 2289 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2290 sk_start(ifp1); 2291 2292 return (claimed); 2293} 2294 2295void 2296sk_init_xmac(struct sk_if_softc *sc_if) 2297{ 2298 struct sk_softc *sc = sc_if->sk_softc; 2299 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2300 struct sk_bcom_hack bhack[] = { 2301 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2302 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2303 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2304 { 0, 0 } }; 2305 2306 DPRINTFN(2, ("sk_init_xmac\n")); 2307 2308 /* Unreset the XMAC. */ 2309 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2310 DELAY(1000); 2311 2312 /* Reset the XMAC's internal state. */ 2313 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2314 2315 /* Save the XMAC II revision */ 2316 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2317 2318 /* 2319 * Perform additional initialization for external PHYs, 2320 * namely for the 1000baseTX cards that use the XMAC's 2321 * GMII mode. 2322 */ 2323 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2324 int i = 0; 2325 u_int32_t val; 2326 2327 /* Take PHY out of reset. */ 2328 val = sk_win_read_4(sc, SK_GPIO); 2329 if (sc_if->sk_port == SK_PORT_A) 2330 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2331 else 2332 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2333 sk_win_write_4(sc, SK_GPIO, val); 2334 2335 /* Enable GMII mode on the XMAC. */ 2336 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2337 2338 sk_xmac_miibus_writereg((struct device *)sc_if, 2339 SK_PHYADDR_BCOM, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2340 DELAY(10000); 2341 sk_xmac_miibus_writereg((struct device *)sc_if, 2342 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2343 2344 /* 2345 * Early versions of the BCM5400 apparently have 2346 * a bug that requires them to have their reserved 2347 * registers initialized to some magic values. I don't 2348 * know what the numbers do, I'm just the messenger. 2349 */ 2350 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2351 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2352 while(bhack[i].reg) { 2353 sk_xmac_miibus_writereg((struct device *)sc_if, 2354 SK_PHYADDR_BCOM, bhack[i].reg, 2355 bhack[i].val); 2356 i++; 2357 } 2358 } 2359 } 2360 2361 /* Set station address */ 2362 SK_XM_WRITE_2(sc_if, XM_PAR0, 2363 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2364 SK_XM_WRITE_2(sc_if, XM_PAR1, 2365 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2366 SK_XM_WRITE_2(sc_if, XM_PAR2, 2367 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2368 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2369 2370 if (ifp->if_flags & IFF_PROMISC) { 2371 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2372 } else { 2373 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2374 } 2375 2376 if (ifp->if_flags & IFF_BROADCAST) { 2377 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2378 } else { 2379 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2380 } 2381 2382 /* We don't need the FCS appended to the packet. */ 2383 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2384 2385 /* We want short frames padded to 60 bytes. */ 2386 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2387 2388 /* 2389 * Enable the reception of all error frames. This is is 2390 * a necessary evil due to the design of the XMAC. The 2391 * XMAC's receive FIFO is only 8K in size, however jumbo 2392 * frames can be up to 9000 bytes in length. When bad 2393 * frame filtering is enabled, the XMAC's RX FIFO operates 2394 * in 'store and forward' mode. For this to work, the 2395 * entire frame has to fit into the FIFO, but that means 2396 * that jumbo frames larger than 8192 bytes will be 2397 * truncated. Disabling all bad frame filtering causes 2398 * the RX FIFO to operate in streaming mode, in which 2399 * case the XMAC will start transfering frames out of the 2400 * RX FIFO as soon as the FIFO threshold is reached. 2401 */ 2402 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2403 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2404 XM_MODE_RX_INRANGELEN); 2405 2406 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2407 2408 /* 2409 * Bump up the transmit threshold. This helps hold off transmit 2410 * underruns when we're blasting traffic from both ports at once. 2411 */ 2412 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2413 2414 /* Set multicast filter */ 2415 sk_setmulti(sc_if); 2416 2417 /* Clear and enable interrupts */ 2418 SK_XM_READ_2(sc_if, XM_ISR); 2419 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2420 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2421 else 2422 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2423 2424 /* Configure MAC arbiter */ 2425 switch(sc_if->sk_xmac_rev) { 2426 case XM_XMAC_REV_B2: 2427 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2428 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2429 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2430 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2431 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2432 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2433 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2434 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2435 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2436 break; 2437 case XM_XMAC_REV_C1: 2438 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2439 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2440 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2441 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2442 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2443 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2444 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2445 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2446 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2447 break; 2448 default: 2449 break; 2450 } 2451 sk_win_write_2(sc, SK_MACARB_CTL, 2452 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2453 2454 sc_if->sk_link = 1; 2455} 2456 2457void sk_init_yukon(sc_if) 2458 struct sk_if_softc *sc_if; 2459{ 2460 u_int32_t phy; 2461 u_int16_t reg; 2462 struct sk_softc *sc; 2463 int i; 2464 2465 sc = sc_if->sk_softc; 2466 2467 DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n", 2468 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2469 2470 if (sc->sk_type == SK_YUKON_LITE && 2471 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2472 /* Take PHY out of reset. */ 2473 sk_win_write_4(sc, SK_GPIO, 2474 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2475 } 2476 2477 /* GMAC and GPHY Reset */ 2478 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2479 2480 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2481 2482 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2483 DELAY(1000); 2484 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2485 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2486 DELAY(1000); 2487 2488 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2489 2490 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2491 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2492 2493 switch(sc_if->sk_softc->sk_pmd) { 2494 case IFM_1000_SX: 2495 case IFM_1000_LX: 2496 phy |= SK_GPHY_FIBER; 2497 break; 2498 2499 case IFM_1000_CX: 2500 case IFM_1000_T: 2501 phy |= SK_GPHY_COPPER; 2502 break; 2503 } 2504 2505 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2506 2507 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2508 DELAY(1000); 2509 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2510 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2511 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2512 2513 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2514 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2515 2516 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2517 2518 /* unused read of the interrupt source register */ 2519 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2520 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2521 2522 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2523 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2524 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2525 2526 /* MIB Counter Clear Mode set */ 2527 reg |= YU_PAR_MIB_CLR; 2528 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2529 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2530 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2531 2532 /* MIB Counter Clear Mode clear */ 2533 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2534 reg &= ~YU_PAR_MIB_CLR; 2535 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2536 2537 /* receive control reg */ 2538 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2539 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2540 YU_RCR_CRCR); 2541 2542 /* transmit parameter register */ 2543 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2544 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2545 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2546 2547 /* serial mode register */ 2548 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2549 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2550 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2551 YU_SMR_IPG_DATA(0x1e)); 2552 2553 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2554 /* Setup Yukon's address */ 2555 for (i = 0; i < 3; i++) { 2556 /* Write Source Address 1 (unicast filter) */ 2557 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2558 sc_if->arpcom.ac_enaddr[i * 2] | 2559 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2560 } 2561 2562 for (i = 0; i < 3; i++) { 2563 reg = sk_win_read_2(sc_if->sk_softc, 2564 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2565 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2566 } 2567 2568 /* Set multicast filter */ 2569 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2570 sk_setmulti(sc_if); 2571 2572 /* enable interrupt mask for counter overflows */ 2573 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2574 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2575 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2576 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2577 2578 /* Configure RX MAC FIFO */ 2579 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2580 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2581 2582 /* Configure TX MAC FIFO */ 2583 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2584 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2585 2586 DPRINTFN(6, ("sk_init_yukon: end\n")); 2587} 2588 2589/* 2590 * Note that to properly initialize any part of the GEnesis chip, 2591 * you first have to take it out of reset mode. 2592 */ 2593void 2594sk_init(void *xsc_if) 2595{ 2596 struct sk_if_softc *sc_if = xsc_if; 2597 struct sk_softc *sc = sc_if->sk_softc; 2598 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2599 struct mii_data *mii = &sc_if->sk_mii; 2600 int s; 2601 2602 DPRINTFN(2, ("sk_init\n")); 2603 2604 s = splnet(); 2605 2606 if (ifp->if_flags & IFF_RUNNING) { 2607 splx(s); 2608 return; 2609 } 2610 2611 /* Cancel pending I/O and free all RX/TX buffers. */ 2612 sk_stop(sc_if); 2613 2614 if (sc->sk_type == SK_GENESIS) { 2615 /* Configure LINK_SYNC LED */ 2616 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2617 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2618 SK_LINKLED_LINKSYNC_ON); 2619 2620 /* Configure RX LED */ 2621 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2622 SK_RXLEDCTL_COUNTER_START); 2623 2624 /* Configure TX LED */ 2625 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2626 SK_TXLEDCTL_COUNTER_START); 2627 } 2628 2629 /* Configure I2C registers */ 2630 2631 /* Configure XMAC(s) */ 2632 switch (sc->sk_type) { 2633 case SK_GENESIS: 2634 sk_init_xmac(sc_if); 2635 break; 2636 case SK_YUKON: 2637 case SK_YUKON_LITE: 2638 case SK_YUKON_LP: 2639 sk_init_yukon(sc_if); 2640 break; 2641 } 2642 mii_mediachg(mii); 2643 2644 if (sc->sk_type == SK_GENESIS) { 2645 /* Configure MAC FIFOs */ 2646 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2647 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2648 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2649 2650 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2651 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2652 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2653 } 2654 2655 /* Configure transmit arbiter(s) */ 2656 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2657 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2658 2659 /* Configure RAMbuffers */ 2660 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2661 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2662 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2663 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2664 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2665 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2666 2667 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2668 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2669 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2670 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2671 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2672 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2673 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2674 2675 /* Configure BMUs */ 2676 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2677 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2678 SK_RX_RING_ADDR(sc_if, 0)); 2679 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2680 2681 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2682 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2683 SK_TX_RING_ADDR(sc_if, 0)); 2684 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2685 2686 /* Init descriptors */ 2687 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2688 printf("%s: initialization failed: no " 2689 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2690 sk_stop(sc_if); 2691 splx(s); 2692 return; 2693 } 2694 2695 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2696 printf("%s: initialization failed: no " 2697 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2698 sk_stop(sc_if); 2699 splx(s); 2700 return; 2701 } 2702 2703 /* Configure interrupt handling */ 2704 CSR_READ_4(sc, SK_ISSR); 2705 if (sc_if->sk_port == SK_PORT_A) 2706 sc->sk_intrmask |= SK_INTRS1; 2707 else 2708 sc->sk_intrmask |= SK_INTRS2; 2709 2710 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2711 2712 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2713 2714 /* Start BMUs. */ 2715 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2716 2717 if (sc->sk_type == SK_GENESIS) { 2718 /* Enable XMACs TX and RX state machines */ 2719 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2720 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2721 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2722 } 2723 2724 if (SK_YUKON_FAMILY(sc->sk_type)) { 2725 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2726 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2727 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2728 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2729 } 2730 2731 2732 ifp->if_flags |= IFF_RUNNING; 2733 ifp->if_flags &= ~IFF_OACTIVE; 2734 2735 splx(s); 2736} 2737 2738void 2739sk_stop(struct sk_if_softc *sc_if) 2740{ 2741 struct sk_softc *sc = sc_if->sk_softc; 2742 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2743 struct sk_txmap_entry *dma; 2744 int i; 2745 2746 DPRINTFN(2, ("sk_stop\n")); 2747 2748 timeout_del(&sc_if->sk_tick_ch); 2749 2750 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2751 2752 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2753 u_int32_t val; 2754 2755 /* Put PHY back into reset. */ 2756 val = sk_win_read_4(sc, SK_GPIO); 2757 if (sc_if->sk_port == SK_PORT_A) { 2758 val |= SK_GPIO_DIR0; 2759 val &= ~SK_GPIO_DAT0; 2760 } else { 2761 val |= SK_GPIO_DIR2; 2762 val &= ~SK_GPIO_DAT2; 2763 } 2764 sk_win_write_4(sc, SK_GPIO, val); 2765 } 2766 2767 /* Turn off various components of this interface. */ 2768 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2769 switch (sc->sk_type) { 2770 case SK_GENESIS: 2771 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2772 SK_TXMACCTL_XMAC_RESET); 2773 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2774 break; 2775 case SK_YUKON: 2776 case SK_YUKON_LITE: 2777 case SK_YUKON_LP: 2778 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2779 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2780 break; 2781 } 2782 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2783 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2784 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2785 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2786 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2787 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2788 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2789 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2790 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2791 2792 /* Disable interrupts */ 2793 if (sc_if->sk_port == SK_PORT_A) 2794 sc->sk_intrmask &= ~SK_INTRS1; 2795 else 2796 sc->sk_intrmask &= ~SK_INTRS2; 2797 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2798 2799 SK_XM_READ_2(sc_if, XM_ISR); 2800 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2801 2802 /* Free RX and TX mbufs still in the queues. */ 2803 for (i = 0; i < SK_RX_RING_CNT; i++) { 2804 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2805 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2806 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2807 } 2808 } 2809 2810 for (i = 0; i < SK_TX_RING_CNT; i++) { 2811 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2812 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2813 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2814 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2815 sc_if->sk_cdata.sk_tx_map[i], link); 2816 sc_if->sk_cdata.sk_tx_map[i] = 0; 2817 } 2818 } 2819 2820 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2821 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2822 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2823 free(dma, M_DEVBUF); 2824 } 2825} 2826 2827struct cfattach skc_ca = { 2828 sizeof(struct sk_softc), skc_probe, skc_attach, 2829}; 2830 2831struct cfdriver skc_cd = { 2832 0, "skc", DV_DULL 2833}; 2834 2835struct cfattach sk_ca = { 2836 sizeof(struct sk_if_softc), sk_probe, sk_attach, 2837}; 2838 2839struct cfdriver sk_cd = { 2840 0, "sk", DV_IFNET 2841}; 2842 2843#ifdef SK_DEBUG 2844void 2845sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2846{ 2847#define DESC_PRINT(X) \ 2848 if (desc->X) \ 2849 printf("txdesc[%d]." #X "=%#x\n", \ 2850 idx, desc->X); 2851 2852 DESC_PRINT(sk_ctl); 2853 DESC_PRINT(sk_next); 2854 DESC_PRINT(sk_data_lo); 2855 DESC_PRINT(sk_data_hi); 2856 DESC_PRINT(sk_xmac_txstat); 2857 DESC_PRINT(sk_rsvd0); 2858 DESC_PRINT(sk_csum_startval); 2859 DESC_PRINT(sk_csum_startpos); 2860 DESC_PRINT(sk_csum_writepos); 2861 DESC_PRINT(sk_rsvd1); 2862#undef PRINT 2863} 2864 2865void 2866sk_dump_bytes(const char *data, int len) 2867{ 2868 int c, i, j; 2869 2870 for (i = 0; i < len; i += 16) { 2871 printf("%08x ", i); 2872 c = len - i; 2873 if (c > 16) c = 16; 2874 2875 for (j = 0; j < c; j++) { 2876 printf("%02x ", data[i + j] & 0xff); 2877 if ((j & 0xf) == 7 && j > 0) 2878 printf(" "); 2879 } 2880 2881 for (; j < 16; j++) 2882 printf(" "); 2883 printf(" "); 2884 2885 for (j = 0; j < c; j++) { 2886 int ch = data[i + j] & 0xff; 2887 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2888 } 2889 2890 printf("\n"); 2891 2892 if (c < 16) 2893 break; 2894 } 2895} 2896 2897void 2898sk_dump_mbuf(struct mbuf *m) 2899{ 2900 int count = m->m_pkthdr.len; 2901 2902 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2903 2904 while (count > 0 && m) { 2905 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2906 m, m->m_data, m->m_len); 2907 sk_dump_bytes(mtod(m, char *), m->m_len); 2908 2909 count -= m->m_len; 2910 m = m->m_next; 2911 } 2912} 2913#endif 2914