if_sk.c revision 1.87
1/* $OpenBSD: if_sk.c,v 1.87 2005/11/15 20:32:04 brad Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37/* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53/* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72/* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89#include "bpfilter.h" 90 91#include <sys/param.h> 92#include <sys/systm.h> 93#include <sys/sockio.h> 94#include <sys/mbuf.h> 95#include <sys/malloc.h> 96#include <sys/kernel.h> 97#include <sys/socket.h> 98#include <sys/device.h> 99#include <sys/queue.h> 100 101#include <net/if.h> 102#include <net/if_dl.h> 103#include <net/if_types.h> 104 105#ifdef INET 106#include <netinet/in.h> 107#include <netinet/in_systm.h> 108#include <netinet/in_var.h> 109#include <netinet/ip.h> 110#include <netinet/udp.h> 111#include <netinet/tcp.h> 112#include <netinet/if_ether.h> 113#endif 114 115#include <net/if_media.h> 116#include <net/if_vlan_var.h> 117 118#if NBPFILTER > 0 119#include <net/bpf.h> 120#endif 121 122#include <dev/mii/mii.h> 123#include <dev/mii/miivar.h> 124#include <dev/mii/brgphyreg.h> 125 126#include <dev/pci/pcireg.h> 127#include <dev/pci/pcivar.h> 128#include <dev/pci/pcidevs.h> 129 130#define SK_VERBOSE 131/* #define SK_USEIOSPACE */ 132 133#include <dev/pci/if_skreg.h> 134#include <dev/pci/if_skvar.h> 135 136int skc_probe(struct device *, void *, void *); 137void skc_attach(struct device *, struct device *self, void *aux); 138int sk_probe(struct device *, void *, void *); 139void sk_attach(struct device *, struct device *self, void *aux); 140int skcprint(void *, const char *); 141int sk_intr(void *); 142void sk_intr_bcom(struct sk_if_softc *); 143void sk_intr_xmac(struct sk_if_softc *); 144void sk_intr_yukon(struct sk_if_softc *); 145void sk_rxeof(struct sk_if_softc *); 146void sk_txeof(struct sk_if_softc *); 147int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 148void sk_start(struct ifnet *); 149int sk_ioctl(struct ifnet *, u_long, caddr_t); 150void sk_init(void *); 151void sk_init_xmac(struct sk_if_softc *); 152void sk_init_yukon(struct sk_if_softc *); 153void sk_stop(struct sk_if_softc *); 154void sk_watchdog(struct ifnet *); 155void sk_shutdown(void *); 156int sk_ifmedia_upd(struct ifnet *); 157void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 158void sk_reset(struct sk_softc *); 159int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 160int sk_alloc_jumbo_mem(struct sk_if_softc *); 161void *sk_jalloc(struct sk_if_softc *); 162void sk_jfree(caddr_t, u_int, void *); 163int sk_init_rx_ring(struct sk_if_softc *); 164int sk_init_tx_ring(struct sk_if_softc *); 165 166int sk_xmac_miibus_readreg(struct device *, int, int); 167void sk_xmac_miibus_writereg(struct device *, int, int, int); 168void sk_xmac_miibus_statchg(struct device *); 169 170int sk_marv_miibus_readreg(struct device *, int, int); 171void sk_marv_miibus_writereg(struct device *, int, int, int); 172void sk_marv_miibus_statchg(struct device *); 173 174u_int32_t sk_xmac_hash(caddr_t); 175u_int32_t sk_yukon_hash(caddr_t); 176void sk_setfilt(struct sk_if_softc *, caddr_t, int); 177void sk_setmulti(struct sk_if_softc *); 178void sk_tick(void *); 179void sk_rxcsum(struct ifnet *, struct mbuf *, const u_int16_t, const u_int16_t); 180 181#ifdef SK_DEBUG 182#define DPRINTF(x) if (skdebug) printf x 183#define DPRINTFN(n,x) if (skdebug >= (n)) printf x 184int skdebug = 0; 185 186void sk_dump_txdesc(struct sk_tx_desc *, int); 187void sk_dump_mbuf(struct mbuf *); 188void sk_dump_bytes(const char *, int); 189#else 190#define DPRINTF(x) 191#define DPRINTFN(n,x) 192#endif 193 194#define SK_SETBIT(sc, reg, x) \ 195 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 196 197#define SK_CLRBIT(sc, reg, x) \ 198 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 199 200#define SK_WIN_SETBIT_4(sc, reg, x) \ 201 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 202 203#define SK_WIN_CLRBIT_4(sc, reg, x) \ 204 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 205 206#define SK_WIN_SETBIT_2(sc, reg, x) \ 207 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 208 209#define SK_WIN_CLRBIT_2(sc, reg, x) \ 210 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 211 212/* supported device vendors */ 213const struct pci_matchid skc_devices[] = { 214 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940 }, 215 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940B }, 216 { PCI_VENDOR_CNET, PCI_PRODUCT_CNET_GIGACARD }, 217 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T }, 218 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 219 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2 }, 220 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064 }, 221 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON }, 222 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_BELKIN }, 223 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_2 }, 224 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_3 }, 225 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 226 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 227 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 228 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 229 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 230 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 231 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 232 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 233 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 234 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 235 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 236 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 237 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 238 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK98XX }, 239 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK98XX2 }, 240 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Sxx }, 241 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Exx }, 242}; 243 244#define SK_LINKSYS_EG1032_SUBID 0x00151737 245 246static inline u_int32_t 247sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 248{ 249#ifdef SK_USEIOSPACE 250 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 251 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 252#else 253 return CSR_READ_4(sc, reg); 254#endif 255} 256 257static inline u_int16_t 258sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 259{ 260#ifdef SK_USEIOSPACE 261 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 262 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 263#else 264 return CSR_READ_2(sc, reg); 265#endif 266} 267 268static inline u_int8_t 269sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 270{ 271#ifdef SK_USEIOSPACE 272 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 273 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 274#else 275 return CSR_READ_1(sc, reg); 276#endif 277} 278 279static inline void 280sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 281{ 282#ifdef SK_USEIOSPACE 283 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 284 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 285#else 286 CSR_WRITE_4(sc, reg, x); 287#endif 288} 289 290static inline void 291sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 292{ 293#ifdef SK_USEIOSPACE 294 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 295 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 296#else 297 CSR_WRITE_2(sc, reg, x); 298#endif 299} 300 301static inline void 302sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 303{ 304#ifdef SK_USEIOSPACE 305 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 306 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 307#else 308 CSR_WRITE_1(sc, reg, x); 309#endif 310} 311 312int 313sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 314{ 315 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 316 int i; 317 318 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 319 320 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 321 return(0); 322 323 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 324 SK_XM_READ_2(sc_if, XM_PHY_DATA); 325 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 326 for (i = 0; i < SK_TIMEOUT; i++) { 327 DELAY(1); 328 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 329 XM_MMUCMD_PHYDATARDY) 330 break; 331 } 332 333 if (i == SK_TIMEOUT) { 334 printf("%s: phy failed to come ready\n", 335 sc_if->sk_dev.dv_xname); 336 return(0); 337 } 338 } 339 DELAY(1); 340 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 341} 342 343void 344sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 345{ 346 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 347 int i; 348 349 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 350 351 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 352 for (i = 0; i < SK_TIMEOUT; i++) { 353 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 354 break; 355 } 356 357 if (i == SK_TIMEOUT) { 358 printf("%s: phy failed to come ready\n", 359 sc_if->sk_dev.dv_xname); 360 return; 361 } 362 363 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 364 for (i = 0; i < SK_TIMEOUT; i++) { 365 DELAY(1); 366 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 367 break; 368 } 369 370 if (i == SK_TIMEOUT) 371 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 372} 373 374void 375sk_xmac_miibus_statchg(struct device *dev) 376{ 377 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 378 struct mii_data *mii = &sc_if->sk_mii; 379 380 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 381 382 /* 383 * If this is a GMII PHY, manually set the XMAC's 384 * duplex mode accordingly. 385 */ 386 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 387 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 388 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 389 } else { 390 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 391 } 392 } 393} 394 395int 396sk_marv_miibus_readreg(dev, phy, reg) 397 struct device *dev; 398 int phy, reg; 399{ 400 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 401 u_int16_t val; 402 int i; 403 404 if (phy != 0 || 405 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 406 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 407 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 408 phy, reg)); 409 return(0); 410 } 411 412 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 413 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 414 415 for (i = 0; i < SK_TIMEOUT; i++) { 416 DELAY(1); 417 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 418 if (val & YU_SMICR_READ_VALID) 419 break; 420 } 421 422 if (i == SK_TIMEOUT) { 423 printf("%s: phy failed to come ready\n", 424 sc_if->sk_dev.dv_xname); 425 return 0; 426 } 427 428 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 429 SK_TIMEOUT)); 430 431 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 432 433 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 434 phy, reg, val)); 435 436 return val; 437} 438 439void 440sk_marv_miibus_writereg(dev, phy, reg, val) 441 struct device *dev; 442 int phy, reg, val; 443{ 444 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 445 int i; 446 447 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 448 phy, reg, val)); 449 450 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 451 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 452 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 453 454 for (i = 0; i < SK_TIMEOUT; i++) { 455 DELAY(1); 456 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 457 break; 458 } 459} 460 461void 462sk_marv_miibus_statchg(dev) 463 struct device *dev; 464{ 465 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 466 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 467} 468 469#define HASH_BITS 6 470 471u_int32_t 472sk_xmac_hash(caddr_t addr) 473{ 474 u_int32_t crc; 475 476 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 477 return (~crc & ((1 << HASH_BITS) - 1)); 478} 479 480u_int32_t 481sk_yukon_hash(caddr_t addr) 482{ 483 u_int32_t crc; 484 485 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 486 return (crc & ((1 << HASH_BITS) - 1)); 487} 488 489void 490sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 491{ 492 int base = XM_RXFILT_ENTRY(slot); 493 494 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 495 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 496 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 497} 498 499void 500sk_setmulti(struct sk_if_softc *sc_if) 501{ 502 struct sk_softc *sc = sc_if->sk_softc; 503 struct ifnet *ifp= &sc_if->arpcom.ac_if; 504 u_int32_t hashes[2] = { 0, 0 }; 505 int h, i; 506 struct arpcom *ac = &sc_if->arpcom; 507 struct ether_multi *enm; 508 struct ether_multistep step; 509 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 510 511 /* First, zot all the existing filters. */ 512 switch(sc->sk_type) { 513 case SK_GENESIS: 514 for (i = 1; i < XM_RXFILT_MAX; i++) 515 sk_setfilt(sc_if, (caddr_t)&dummy, i); 516 517 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 518 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 519 break; 520 case SK_YUKON: 521 case SK_YUKON_LITE: 522 case SK_YUKON_LP: 523 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 524 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 525 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 526 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 527 break; 528 } 529 530 /* Now program new ones. */ 531allmulti: 532 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 533 hashes[0] = 0xFFFFFFFF; 534 hashes[1] = 0xFFFFFFFF; 535 } else { 536 i = 1; 537 /* First find the tail of the list. */ 538 ETHER_FIRST_MULTI(step, ac, enm); 539 while (enm != NULL) { 540 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 541 ETHER_ADDR_LEN)) { 542 ifp->if_flags |= IFF_ALLMULTI; 543 goto allmulti; 544 } 545 /* 546 * Program the first XM_RXFILT_MAX multicast groups 547 * into the perfect filter. For all others, 548 * use the hash table. 549 */ 550 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 551 sk_setfilt(sc_if, enm->enm_addrlo, i); 552 i++; 553 } 554 else { 555 switch(sc->sk_type) { 556 case SK_GENESIS: 557 h = sk_xmac_hash(enm->enm_addrlo); 558 break; 559 560 case SK_YUKON: 561 case SK_YUKON_LITE: 562 case SK_YUKON_LP: 563 h = sk_yukon_hash(enm->enm_addrlo); 564 break; 565 } 566 if (h < 32) 567 hashes[0] |= (1 << h); 568 else 569 hashes[1] |= (1 << (h - 32)); 570 } 571 572 ETHER_NEXT_MULTI(step, enm); 573 } 574 } 575 576 switch(sc->sk_type) { 577 case SK_GENESIS: 578 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 579 XM_MODE_RX_USE_PERFECT); 580 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 581 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 582 break; 583 case SK_YUKON: 584 case SK_YUKON_LITE: 585 case SK_YUKON_LP: 586 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 587 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 588 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 589 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 590 break; 591 } 592} 593 594int 595sk_init_rx_ring(struct sk_if_softc *sc_if) 596{ 597 struct sk_chain_data *cd = &sc_if->sk_cdata; 598 struct sk_ring_data *rd = sc_if->sk_rdata; 599 int i; 600 601 bzero((char *)rd->sk_rx_ring, 602 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 603 604 for (i = 0; i < SK_RX_RING_CNT; i++) { 605 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 606 if (i == (SK_RX_RING_CNT - 1)) { 607 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 608 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 609 } else { 610 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 611 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 612 } 613 rd->sk_rx_ring[i].sk_csum1_start = ETHER_HDR_LEN; 614 rd->sk_rx_ring[i].sk_csum2_start = ETHER_HDR_LEN + 615 sizeof(struct ip); 616 } 617 618 for (i = 0; i < SK_RX_RING_CNT; i++) { 619 if (sk_newbuf(sc_if, i, NULL, 620 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 621 printf("%s: failed alloc of %dth mbuf\n", 622 sc_if->sk_dev.dv_xname, i); 623 return(ENOBUFS); 624 } 625 } 626 627 sc_if->sk_cdata.sk_rx_prod = 0; 628 sc_if->sk_cdata.sk_rx_cons = 0; 629 630 return(0); 631} 632 633int 634sk_init_tx_ring(struct sk_if_softc *sc_if) 635{ 636 struct sk_softc *sc = sc_if->sk_softc; 637 struct sk_chain_data *cd = &sc_if->sk_cdata; 638 struct sk_ring_data *rd = sc_if->sk_rdata; 639 bus_dmamap_t dmamap; 640 struct sk_txmap_entry *entry; 641 int i; 642 643 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 644 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 645 646 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 647 for (i = 0; i < SK_TX_RING_CNT; i++) { 648 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 649 if (i == (SK_TX_RING_CNT - 1)) { 650 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 651 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 652 } else { 653 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 654 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 655 } 656 657 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 658 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 659 return (ENOBUFS); 660 661 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 662 if (!entry) { 663 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 664 return (ENOBUFS); 665 } 666 entry->dmamap = dmamap; 667 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 668 } 669 670 sc_if->sk_cdata.sk_tx_prod = 0; 671 sc_if->sk_cdata.sk_tx_cons = 0; 672 sc_if->sk_cdata.sk_tx_cnt = 0; 673 674 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 675 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 676 677 return (0); 678} 679 680int 681sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 682 bus_dmamap_t dmamap) 683{ 684 struct mbuf *m_new = NULL; 685 struct sk_chain *c; 686 struct sk_rx_desc *r; 687 688 if (m == NULL) { 689 caddr_t buf = NULL; 690 691 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 692 if (m_new == NULL) 693 return(ENOBUFS); 694 695 /* Allocate the jumbo buffer */ 696 buf = sk_jalloc(sc_if); 697 if (buf == NULL) { 698 m_freem(m_new); 699 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 700 "dropped!\n", sc_if->arpcom.ac_if.if_xname)); 701 return(ENOBUFS); 702 } 703 704 /* Attach the buffer to the mbuf */ 705 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 706 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 707 } else { 708 /* 709 * We're re-using a previously allocated mbuf; 710 * be sure to re-init pointers and lengths to 711 * default values. 712 */ 713 m_new = m; 714 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 715 m_new->m_data = m_new->m_ext.ext_buf; 716 } 717 m_adj(m_new, ETHER_ALIGN); 718 719 c = &sc_if->sk_cdata.sk_rx_chain[i]; 720 r = c->sk_desc; 721 c->sk_mbuf = m_new; 722 r->sk_data_lo = dmamap->dm_segs[0].ds_addr + 723 (((vaddr_t)m_new->m_data 724 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf)); 725 r->sk_ctl = SK_JLEN | SK_RXSTAT; 726 727 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 728 729 return(0); 730} 731 732/* 733 * Memory management for jumbo frames. 734 */ 735 736int 737sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 738{ 739 struct sk_softc *sc = sc_if->sk_softc; 740 caddr_t ptr, kva; 741 bus_dma_segment_t seg; 742 int i, rseg, state, error; 743 struct sk_jpool_entry *entry; 744 745 state = error = 0; 746 747 /* Grab a big chunk o' storage. */ 748 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 749 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 750 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 751 return (ENOBUFS); 752 } 753 754 state = 1; 755 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, &kva, 756 BUS_DMA_NOWAIT)) { 757 printf("%s: can't map dma buffers (%d bytes)\n", 758 sc->sk_dev.dv_xname, SK_JMEM); 759 error = ENOBUFS; 760 goto out; 761 } 762 763 state = 2; 764 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 765 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 766 printf("%s: can't create dma map\n", sc->sk_dev.dv_xname); 767 error = ENOBUFS; 768 goto out; 769 } 770 771 state = 3; 772 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 773 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 774 printf("%s: can't load dma map\n", sc->sk_dev.dv_xname); 775 error = ENOBUFS; 776 goto out; 777 } 778 779 state = 4; 780 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 781 DPRINTFN(1,("sk_jumbo_buf = 0x%08X\n", sc_if->sk_cdata.sk_jumbo_buf)); 782 783 LIST_INIT(&sc_if->sk_jfree_listhead); 784 LIST_INIT(&sc_if->sk_jinuse_listhead); 785 786 /* 787 * Now divide it up into 9K pieces and save the addresses 788 * in an array. 789 */ 790 ptr = sc_if->sk_cdata.sk_jumbo_buf; 791 for (i = 0; i < SK_JSLOTS; i++) { 792 sc_if->sk_cdata.sk_jslots[i] = ptr; 793 ptr += SK_JLEN; 794 entry = malloc(sizeof(struct sk_jpool_entry), 795 M_DEVBUF, M_NOWAIT); 796 if (entry == NULL) { 797 printf("%s: no memory for jumbo buffer queue!\n", 798 sc->sk_dev.dv_xname); 799 error = ENOBUFS; 800 goto out; 801 } 802 entry->slot = i; 803 if (i) 804 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 805 entry, jpool_entries); 806 else 807 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 808 entry, jpool_entries); 809 } 810out: 811 if (error != 0) { 812 switch (state) { 813 case 4: 814 bus_dmamap_unload(sc->sc_dmatag, 815 sc_if->sk_cdata.sk_rx_jumbo_map); 816 case 3: 817 bus_dmamap_destroy(sc->sc_dmatag, 818 sc_if->sk_cdata.sk_rx_jumbo_map); 819 case 2: 820 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 821 case 1: 822 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 823 break; 824 default: 825 break; 826 } 827 } 828 829 return (error); 830} 831 832/* 833 * Allocate a jumbo buffer. 834 */ 835void * 836sk_jalloc(struct sk_if_softc *sc_if) 837{ 838 struct sk_jpool_entry *entry; 839 840 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 841 842 if (entry == NULL) 843 return (NULL); 844 845 LIST_REMOVE(entry, jpool_entries); 846 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 847 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 848} 849 850/* 851 * Release a jumbo buffer. 852 */ 853void 854sk_jfree(caddr_t buf, u_int size, void *arg) 855{ 856 struct sk_jpool_entry *entry; 857 struct sk_if_softc *sc; 858 int i; 859 860 /* Extract the softc struct pointer. */ 861 sc = (struct sk_if_softc *)arg; 862 863 if (sc == NULL) 864 panic("sk_jfree: can't find softc pointer!"); 865 866 /* calculate the slot this buffer belongs to */ 867 868 i = ((vaddr_t)buf 869 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 870 871 if ((i < 0) || (i >= SK_JSLOTS)) 872 panic("sk_jfree: asked to free buffer that we don't manage!"); 873 874 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 875 if (entry == NULL) 876 panic("sk_jfree: buffer not in use!"); 877 entry->slot = i; 878 LIST_REMOVE(entry, jpool_entries); 879 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 880} 881 882/* 883 * Set media options. 884 */ 885int 886sk_ifmedia_upd(struct ifnet *ifp) 887{ 888 struct sk_if_softc *sc_if = ifp->if_softc; 889 890 sk_init(sc_if); 891 mii_mediachg(&sc_if->sk_mii); 892 return(0); 893} 894 895/* 896 * Report current media status. 897 */ 898void 899sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 900{ 901 struct sk_if_softc *sc_if = ifp->if_softc; 902 903 mii_pollstat(&sc_if->sk_mii); 904 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 905 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 906} 907 908int 909sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 910{ 911 struct sk_if_softc *sc_if = ifp->if_softc; 912 struct sk_softc *sc = sc_if->sk_softc; 913 struct ifreq *ifr = (struct ifreq *) data; 914 struct ifaddr *ifa = (struct ifaddr *) data; 915 struct mii_data *mii; 916 int s, error = 0; 917 918 s = splnet(); 919 920 if ((error = ether_ioctl(ifp, &sc_if->arpcom, command, data)) > 0) { 921 splx(s); 922 return error; 923 } 924 925 switch(command) { 926 case SIOCSIFADDR: 927 ifp->if_flags |= IFF_UP; 928 switch (ifa->ifa_addr->sa_family) { 929#ifdef INET 930 case AF_INET: 931 sk_init(sc_if); 932 arp_ifinit(&sc_if->arpcom, ifa); 933 break; 934#endif /* INET */ 935 default: 936 sk_init(sc_if); 937 break; 938 } 939 break; 940 case SIOCSIFMTU: 941 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 942 error = EINVAL; 943 else if (ifp->if_mtu != ifr->ifr_mtu) 944 ifp->if_mtu = ifr->ifr_mtu; 945 break; 946 case SIOCSIFFLAGS: 947 if (ifp->if_flags & IFF_UP) { 948 if (ifp->if_flags & IFF_RUNNING && 949 ifp->if_flags & IFF_PROMISC && 950 !(sc_if->sk_if_flags & IFF_PROMISC)) { 951 switch(sc->sk_type) { 952 case SK_GENESIS: 953 SK_XM_SETBIT_4(sc_if, XM_MODE, 954 XM_MODE_RX_PROMISC); 955 break; 956 case SK_YUKON: 957 case SK_YUKON_LITE: 958 case SK_YUKON_LP: 959 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 960 YU_RCR_UFLEN | YU_RCR_MUFLEN); 961 break; 962 } 963 sk_setmulti(sc_if); 964 } else if (ifp->if_flags & IFF_RUNNING && 965 !(ifp->if_flags & IFF_PROMISC) && 966 sc_if->sk_if_flags & IFF_PROMISC) { 967 switch(sc->sk_type) { 968 case SK_GENESIS: 969 SK_XM_CLRBIT_4(sc_if, XM_MODE, 970 XM_MODE_RX_PROMISC); 971 break; 972 case SK_YUKON: 973 case SK_YUKON_LITE: 974 case SK_YUKON_LP: 975 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 976 YU_RCR_UFLEN | YU_RCR_MUFLEN); 977 break; 978 } 979 980 sk_setmulti(sc_if); 981 } else 982 sk_init(sc_if); 983 } else { 984 if (ifp->if_flags & IFF_RUNNING) 985 sk_stop(sc_if); 986 } 987 sc_if->sk_if_flags = ifp->if_flags; 988 error = 0; 989 break; 990 case SIOCADDMULTI: 991 case SIOCDELMULTI: 992 error = (command == SIOCADDMULTI) ? 993 ether_addmulti(ifr, &sc_if->arpcom) : 994 ether_delmulti(ifr, &sc_if->arpcom); 995 996 if (error == ENETRESET) { 997 /* 998 * Multicast list has changed; set the hardware 999 * filter accordingly. 1000 */ 1001 if (ifp->if_flags & IFF_RUNNING) 1002 sk_setmulti(sc_if); 1003 error = 0; 1004 } 1005 break; 1006 case SIOCGIFMEDIA: 1007 case SIOCSIFMEDIA: 1008 mii = &sc_if->sk_mii; 1009 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1010 break; 1011 default: 1012 error = EINVAL; 1013 break; 1014 } 1015 1016 splx(s); 1017 1018 return(error); 1019} 1020 1021/* 1022 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1023 * IDs against our list and return a device name if we find a match. 1024 */ 1025int 1026skc_probe(struct device *parent, void *match, void *aux) 1027{ 1028 struct pci_attach_args *pa = aux; 1029 pci_chipset_tag_t pc = pa->pa_pc; 1030 pcireg_t subid; 1031 1032 subid = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1033 1034 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1035 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1036 subid == SK_LINKSYS_EG1032_SUBID) 1037 return (1); 1038 1039 return (pci_matchbyid((struct pci_attach_args *)aux, skc_devices, 1040 sizeof(skc_devices)/sizeof(skc_devices[0]))); 1041} 1042 1043/* 1044 * Force the GEnesis into reset, then bring it out of reset. 1045 */ 1046void sk_reset(struct sk_softc *sc) 1047{ 1048 DPRINTFN(2, ("sk_reset\n")); 1049 1050 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1051 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1052 if (SK_YUKON_FAMILY(sc->sk_type)) 1053 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1054 1055 DELAY(1000); 1056 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1057 DELAY(2); 1058 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1059 if (SK_YUKON_FAMILY(sc->sk_type)) 1060 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1061 1062 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1063 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1064 CSR_READ_2(sc, SK_LINK_CTRL))); 1065 1066 if (sc->sk_type == SK_GENESIS) { 1067 /* Configure packet arbiter */ 1068 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1069 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1070 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1071 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1072 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1073 } 1074 1075 /* Enable RAM interface */ 1076 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1077 1078 /* 1079 * Configure interrupt moderation. The moderation timer 1080 * defers interrupts specified in the interrupt moderation 1081 * timer mask based on the timeout specified in the interrupt 1082 * moderation timer init register. Each bit in the timer 1083 * register represents 18.825ns, so to specify a timeout in 1084 * microseconds, we have to multiply by 54. 1085 */ 1086 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(100)); 1087 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1088 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1089 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1090} 1091 1092int 1093sk_probe(struct device *parent, void *match, void *aux) 1094{ 1095 struct skc_attach_args *sa = aux; 1096 1097 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1098 return(0); 1099 1100 switch (sa->skc_type) { 1101 case SK_GENESIS: 1102 case SK_YUKON: 1103 case SK_YUKON_LITE: 1104 case SK_YUKON_LP: 1105#ifdef not_quite_yet 1106 case SK_YUKON_XL: 1107 case SK_YUKON_EC_U: 1108 case SK_YUKON_EC: 1109 case SK_YUKON_FE: 1110#endif 1111 return (1); 1112 } 1113 1114 return (0); 1115} 1116 1117/* 1118 * Each XMAC chip is attached as a separate logical IP interface. 1119 * Single port cards will have only one logical interface of course. 1120 */ 1121void 1122sk_attach(struct device *parent, struct device *self, void *aux) 1123{ 1124 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1125 struct sk_softc *sc = (struct sk_softc *)parent; 1126 struct skc_attach_args *sa = aux; 1127 struct ifnet *ifp; 1128 caddr_t kva; 1129 bus_dma_segment_t seg; 1130 int i, rseg; 1131 1132 sc_if->sk_port = sa->skc_port; 1133 sc_if->sk_softc = sc; 1134 sc->sk_if[sa->skc_port] = sc_if; 1135 1136 if (sa->skc_port == SK_PORT_A) 1137 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1138 if (sa->skc_port == SK_PORT_B) 1139 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1140 1141 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1142 1143 /* 1144 * Get station address for this interface. Note that 1145 * dual port cards actually come with three station 1146 * addresses: one for each port, plus an extra. The 1147 * extra one is used by the SysKonnect driver software 1148 * as a 'virtual' station address for when both ports 1149 * are operating in failover mode. Currently we don't 1150 * use this extra address. 1151 */ 1152 for (i = 0; i < ETHER_ADDR_LEN; i++) 1153 sc_if->arpcom.ac_enaddr[i] = 1154 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1155 1156 1157 printf(": address %s\n", 1158 ether_sprintf(sc_if->arpcom.ac_enaddr)); 1159 1160 /* 1161 * Set up RAM buffer addresses. The NIC will have a certain 1162 * amount of SRAM on it, somewhere between 512K and 2MB. We 1163 * need to divide this up a) between the transmitter and 1164 * receiver and b) between the two XMACs, if this is a 1165 * dual port NIC. Our algorithm is to divide up the memory 1166 * evenly so that everyone gets a fair share. 1167 * 1168 * Just to be contrary, Yukon2 appears to have separate memory 1169 * for each MAC. 1170 */ 1171 if (SK_IS_YUKON2(sc) || 1172 sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1173 u_int32_t chunk, val; 1174 1175 chunk = sc->sk_ramsize / 2; 1176 val = sc->sk_rboff / sizeof(u_int64_t); 1177 sc_if->sk_rx_ramstart = val; 1178 val += (chunk / sizeof(u_int64_t)); 1179 sc_if->sk_rx_ramend = val - 1; 1180 sc_if->sk_tx_ramstart = val; 1181 val += (chunk / sizeof(u_int64_t)); 1182 sc_if->sk_tx_ramend = val - 1; 1183 } else { 1184 u_int32_t chunk, val; 1185 1186 chunk = sc->sk_ramsize / 4; 1187 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1188 sizeof(u_int64_t); 1189 sc_if->sk_rx_ramstart = val; 1190 val += (chunk / sizeof(u_int64_t)); 1191 sc_if->sk_rx_ramend = val - 1; 1192 sc_if->sk_tx_ramstart = val; 1193 val += (chunk / sizeof(u_int64_t)); 1194 sc_if->sk_tx_ramend = val - 1; 1195 } 1196 1197 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1198 " tx_ramstart=%#x tx_ramend=%#x\n", 1199 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1200 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1201 1202 /* Read and save PHY type and set PHY address */ 1203 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1204 switch (sc_if->sk_phytype) { 1205 case SK_PHYTYPE_XMAC: 1206 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1207 break; 1208 case SK_PHYTYPE_BCOM: 1209 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1210 break; 1211 case SK_PHYTYPE_MARV_COPPER: 1212 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1213 break; 1214 default: 1215 printf("%s: unsupported PHY type: %d\n", 1216 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1217 return; 1218 } 1219 if (SK_IS_YUKON2(sc) && sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1220 sc->sk_pmd != IFM_1000_SX && sc->sk_pmd != IFM_1000_LX) { 1221 /* not initialized, punt */ 1222 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1223 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1224 } 1225 1226 /* Allocate the descriptor queues. */ 1227 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1228 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1229 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 1230 goto fail; 1231 } 1232 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1233 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1234 printf("%s: can't map dma buffers (%d bytes)\n", 1235 sc_if->sk_dev.dv_xname, sizeof(struct sk_ring_data)); 1236 goto fail_1; 1237 } 1238 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1239 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1240 &sc_if->sk_ring_map)) { 1241 printf("%s: can't create dma map\n", sc_if->sk_dev.dv_xname); 1242 goto fail_2; 1243 } 1244 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1245 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1246 printf("%s: can't load dma map\n", sc_if->sk_dev.dv_xname); 1247 goto fail_3; 1248 } 1249 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1250 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1251 1252 /* Try to allocate memory for jumbo buffers. */ 1253 if (sk_alloc_jumbo_mem(sc_if)) { 1254 printf("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1255 goto fail_3; 1256 } 1257 1258 ifp = &sc_if->arpcom.ac_if; 1259 ifp->if_softc = sc_if; 1260 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1261 ifp->if_ioctl = sk_ioctl; 1262 ifp->if_start = sk_start; 1263 ifp->if_watchdog = sk_watchdog; 1264 ifp->if_baudrate = 1000000000; 1265 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1266 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1267 IFQ_SET_READY(&ifp->if_snd); 1268 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1269 1270 /* 1271 * Do miibus setup. 1272 */ 1273 switch (sc->sk_type) { 1274 case SK_GENESIS: 1275 sk_init_xmac(sc_if); 1276 break; 1277 case SK_YUKON: 1278 case SK_YUKON_LITE: 1279 case SK_YUKON_LP: 1280 case SK_YUKON_XL: 1281 case SK_YUKON_EC_U: 1282 case SK_YUKON_EC: 1283 case SK_YUKON_FE: 1284 sk_init_yukon(sc_if); 1285 break; 1286 default: 1287 printf("%s: unknown device type %d\n", sc->sk_dev.dv_xname, 1288 sc->sk_type); 1289 /* dealloc jumbo on error */ 1290 goto fail_3; 1291 } 1292 1293 DPRINTFN(2, ("sk_attach: 1\n")); 1294 1295 sc_if->sk_mii.mii_ifp = ifp; 1296 if (sc->sk_type == SK_GENESIS) { 1297 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1298 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1299 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1300 } else { 1301 /* yukon/yukon2 */ 1302 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1303 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1304 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1305 } 1306 1307 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1308 sk_ifmedia_upd, sk_ifmedia_sts); 1309 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1310 MII_OFFSET_ANY, 0); 1311 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1312 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1313 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1314 0, NULL); 1315 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1316 } 1317 else 1318 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1319 1320 timeout_set(&sc_if->sk_tick_ch, sk_tick, sc_if); 1321 timeout_add(&sc_if->sk_tick_ch, hz); 1322 1323 DPRINTFN(2, ("sk_attach: 1\n")); 1324 1325 /* 1326 * Call MI attach routines. 1327 */ 1328 if_attach(ifp); 1329 ether_ifattach(ifp); 1330 1331 DPRINTFN(2, ("sk_attach: end\n")); 1332 1333 return; 1334 1335fail_3: 1336 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1337fail_2: 1338 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct sk_ring_data)); 1339fail_1: 1340 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1341fail: 1342 sc->sk_if[sa->skc_port] = NULL; 1343} 1344 1345int 1346skcprint(void *aux, const char *pnp) 1347{ 1348 struct skc_attach_args *sa = aux; 1349 1350 if (pnp) 1351 printf("sk port %c at %s", 1352 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1353 else 1354 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1355 return (UNCONF); 1356} 1357 1358/* 1359 * Attach the interface. Allocate softc structures, do ifmedia 1360 * setup and ethernet/BPF attach. 1361 */ 1362void 1363skc_attach(struct device *parent, struct device *self, void *aux) 1364{ 1365 struct sk_softc *sc = (struct sk_softc *)self; 1366 struct pci_attach_args *pa = aux; 1367 struct skc_attach_args skca; 1368 pci_chipset_tag_t pc = pa->pa_pc; 1369 pcireg_t command, memtype; 1370 pci_intr_handle_t ih; 1371 const char *intrstr = NULL; 1372 bus_size_t size; 1373 u_int8_t skrs; 1374 char *revstr = NULL; 1375 1376 DPRINTFN(2, ("begin skc_attach\n")); 1377 1378 /* 1379 * Handle power management nonsense. 1380 */ 1381 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1382 1383 if (command == 0x01) { 1384 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1385 if (command & SK_PSTATE_MASK) { 1386 u_int32_t iobase, membase, irq; 1387 1388 /* Save important PCI config data. */ 1389 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1390 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1391 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1392 1393 /* Reset the power state. */ 1394 printf("%s chip is in D%d power mode " 1395 "-- setting to D0\n", sc->sk_dev.dv_xname, 1396 command & SK_PSTATE_MASK); 1397 command &= 0xFFFFFFFC; 1398 pci_conf_write(pc, pa->pa_tag, 1399 SK_PCI_PWRMGMTCTRL, command); 1400 1401 /* Restore PCI config data. */ 1402 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1403 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1404 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1405 } 1406 } 1407 1408 /* 1409 * Map control/status registers. 1410 */ 1411 1412#ifdef SK_USEIOSPACE 1413 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1414 &sc->sk_btag, &sc->sk_bhandle, NULL, &size, 0)) { 1415 printf(": can't map i/o space\n"); 1416 return; 1417 } 1418#else 1419 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1420 switch (memtype) { 1421 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1422 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1423 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1424 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1425 NULL, &size, 0) == 0) 1426 break; 1427 default: 1428 printf(": can't map mem space\n"); 1429 return; 1430 } 1431#endif 1432 sc->sc_dmatag = pa->pa_dmat; 1433 1434 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1435 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1436 1437 /* bail out here if chip is not recognized */ 1438 if (sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1439 printf("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1440 goto fail_1; 1441 } 1442 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1443 1444 /* Allocate interrupt */ 1445 if (pci_intr_map(pa, &ih)) { 1446 printf(": couldn't map interrupt\n"); 1447 goto fail_1; 1448 } 1449 1450 intrstr = pci_intr_string(pc, ih); 1451 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc, 1452 self->dv_xname); 1453 if (sc->sk_intrhand == NULL) { 1454 printf(": couldn't establish interrupt"); 1455 if (intrstr != NULL) 1456 printf(" at %s", intrstr); 1457 printf("\n"); 1458 goto fail_1; 1459 } 1460 printf(": %s\n", intrstr); 1461 1462 /* Reset the adapter. */ 1463 sk_reset(sc); 1464 1465 skrs = sk_win_read_1(sc, SK_EPROM0); 1466 if (sc->sk_type == SK_GENESIS) { 1467 /* Read and save RAM size and RAMbuffer offset */ 1468 switch(skrs) { 1469 case SK_RAMSIZE_512K_64: 1470 sc->sk_ramsize = 0x80000; 1471 sc->sk_rboff = SK_RBOFF_0; 1472 break; 1473 case SK_RAMSIZE_1024K_64: 1474 sc->sk_ramsize = 0x100000; 1475 sc->sk_rboff = SK_RBOFF_80000; 1476 break; 1477 case SK_RAMSIZE_1024K_128: 1478 sc->sk_ramsize = 0x100000; 1479 sc->sk_rboff = SK_RBOFF_0; 1480 break; 1481 case SK_RAMSIZE_2048K_128: 1482 sc->sk_ramsize = 0x200000; 1483 sc->sk_rboff = SK_RBOFF_0; 1484 break; 1485 default: 1486 printf("%s: unknown ram size: %d\n", 1487 sc->sk_dev.dv_xname, skrs); 1488 goto fail_2; 1489 break; 1490 } 1491 } else { 1492 if (skrs == 0x00) 1493 sc->sk_ramsize = 0x20000; 1494 else 1495 sc->sk_ramsize = skrs * (1<<12); 1496 sc->sk_rboff = SK_RBOFF_0; 1497 } 1498 1499 DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n", 1500 sc->sk_ramsize, sc->sk_ramsize / 1024, 1501 sc->sk_rboff)); 1502 1503 /* Read and save physical media type */ 1504 skrs = sk_win_read_1(sc, SK_PMDTYPE); 1505 if (SK_IS_YUKON2(sc)) { 1506 switch (skrs) { 1507 case 'L': 1508 sc->sk_pmd = IFM_1000_LX; 1509 break; 1510 case 'S': 1511 sc->sk_pmd = IFM_1000_SX; 1512 break; 1513 case SK_PMD_1000BASETX: 1514 case SK_PMD_1000BASETX_ALT: 1515 default: 1516 sc->sk_pmd = IFM_1000_T; 1517 break; 1518 } 1519 } else { 1520 switch (skrs) { 1521 case SK_PMD_1000BASESX: 1522 sc->sk_pmd = IFM_1000_SX; 1523 break; 1524 case SK_PMD_1000BASELX: 1525 sc->sk_pmd = IFM_1000_LX; 1526 break; 1527 case SK_PMD_1000BASECX: 1528 sc->sk_pmd = IFM_1000_CX; 1529 break; 1530 case SK_PMD_1000BASETX: 1531 case SK_PMD_1000BASETX_ALT: 1532 sc->sk_pmd = IFM_1000_T; 1533 break; 1534 default: 1535 printf("%s: unknown media type: 0x%x\n", 1536 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1537 goto fail_2; 1538 } 1539 } 1540 1541 switch (sc->sk_type) { 1542 case SK_GENESIS: 1543 sc->sk_name = "SysKonnect GEnesis"; 1544 break; 1545 case SK_YUKON: 1546 sc->sk_name = "Marvell Yukon"; 1547 break; 1548 case SK_YUKON_LITE: 1549 sc->sk_name = "Marvell Yukon Lite"; 1550 break; 1551 case SK_YUKON_LP: 1552 sc->sk_name = "Marvell Yukon LP"; 1553 break; 1554 case SK_YUKON_XL: 1555 sc->sk_name = "Marvell Yukon-2 XL"; 1556 break; 1557 case SK_YUKON_EC_U: 1558 sc->sk_name = "Marvell Yukon-2 EC Ultra"; 1559 break; 1560 case SK_YUKON_EC: 1561 sc->sk_name = "Marvell Yukon-2 EC"; 1562 break; 1563 case SK_YUKON_FE: 1564 sc->sk_name = "Marvell Yukon-2 FE"; 1565 break; 1566 default: 1567 sc->sk_name = "Marvell Yukon (Unknown)"; 1568 } 1569 1570 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1571 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1572 uint32_t flashaddr; 1573 uint8_t testbyte; 1574 1575 flashaddr = sk_win_read_4(sc, SK_EP_ADDR); 1576 1577 /* test Flash-Address Register */ 1578 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff); 1579 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1580 1581 if (testbyte != 0) { 1582 /* This is a Yukon Lite Rev A0 */ 1583 sc->sk_type = SK_YUKON_LITE; 1584 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1585 /* restore Flash-Address Register */ 1586 sk_win_write_4(sc, SK_EP_ADDR, flashaddr); 1587 } 1588 } 1589 1590 if (sc->sk_type == SK_YUKON_LITE) { 1591 switch (sc->sk_rev) { 1592 case SK_YUKON_LITE_REV_A0: 1593 revstr = "A0"; 1594 break; 1595 case SK_YUKON_LITE_REV_A1: 1596 revstr = "A1"; 1597 break; 1598 case SK_YUKON_LITE_REV_A3: 1599 revstr = "A3"; 1600 break; 1601 default: 1602 ; 1603 } 1604 } 1605 1606 /* Announce the product name. */ 1607 printf("%s: %s", sc->sk_dev.dv_xname, sc->sk_name); 1608 if (revstr != NULL) 1609 printf(" rev. %s", revstr); 1610 printf(" (0x%x)\n", sc->sk_rev); 1611 1612 skca.skc_port = SK_PORT_A; 1613 skca.skc_type = sc->sk_type; 1614 skca.skc_rev = sc->sk_rev; 1615 (void)config_found(&sc->sk_dev, &skca, skcprint); 1616 1617 if (SK_IS_YUKON2(sc)) { 1618 u_int8_t hw; 1619 1620 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1621 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1622 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1623 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) { 1624 skca.skc_port = SK_PORT_B; 1625 skca.skc_type = sc->sk_type; 1626 skca.skc_rev = sc->sk_rev; 1627 (void)config_found(&sc->sk_dev, &skca, 1628 skcprint); 1629 } 1630 } 1631 } else { 1632 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1633 skca.skc_port = SK_PORT_B; 1634 skca.skc_type = sc->sk_type; 1635 skca.skc_rev = sc->sk_rev; 1636 (void)config_found(&sc->sk_dev, &skca, skcprint); 1637 } 1638 } 1639 1640 /* Turn on the 'driver is loaded' LED. */ 1641 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1642 1643 return; 1644 1645fail_2: 1646 pci_intr_disestablish(pc, sc->sk_intrhand); 1647fail_1: 1648 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1649} 1650 1651int 1652sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1653{ 1654 struct sk_softc *sc = sc_if->sk_softc; 1655 struct sk_tx_desc *f = NULL; 1656 u_int32_t frag, cur, cnt = 0; 1657 int i; 1658 struct sk_txmap_entry *entry; 1659 bus_dmamap_t txmap; 1660 1661 DPRINTFN(2, ("sk_encap\n")); 1662 1663 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1664 if (entry == NULL) { 1665 DPRINTFN(2, ("sk_encap: no txmap available\n")); 1666 return ENOBUFS; 1667 } 1668 txmap = entry->dmamap; 1669 1670 cur = frag = *txidx; 1671 1672#ifdef SK_DEBUG 1673 if (skdebug >= 2) 1674 sk_dump_mbuf(m_head); 1675#endif 1676 1677 /* 1678 * Start packing the mbufs in this chain into 1679 * the fragment pointers. Stop when we run out 1680 * of fragments or hit the end of the mbuf chain. 1681 */ 1682 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1683 BUS_DMA_NOWAIT)) { 1684 DPRINTFN(2, ("sk_encap: dmamap failed\n")); 1685 return(ENOBUFS); 1686 } 1687 1688 DPRINTFN(2, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1689 1690 /* Sync the DMA map. */ 1691 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1692 BUS_DMASYNC_PREWRITE); 1693 1694 for (i = 0; i < txmap->dm_nsegs; i++) { 1695 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1696 DPRINTFN(2, ("sk_encap: too few descriptors free\n")); 1697 return(ENOBUFS); 1698 } 1699 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1700 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1701 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1702 if (cnt == 0) 1703 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1704 else 1705 f->sk_ctl |= SK_TXCTL_OWN; 1706 1707 cur = frag; 1708 SK_INC(frag, SK_TX_RING_CNT); 1709 cnt++; 1710 } 1711 1712 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1713 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1714 1715 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1716 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1717 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1718 1719 /* Sync descriptors before handing to chip */ 1720 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1721 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1722 1723 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1724 1725 /* Sync first descriptor to hand it off */ 1726 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1727 1728 sc_if->sk_cdata.sk_tx_cnt += cnt; 1729 1730#ifdef SK_DEBUG 1731 if (skdebug >= 2) { 1732 struct sk_tx_desc *desc; 1733 u_int32_t idx; 1734 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1735 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1736 sk_dump_txdesc(desc, idx); 1737 } 1738 } 1739#endif 1740 1741 *txidx = frag; 1742 1743 DPRINTFN(2, ("sk_encap: completed successfully\n")); 1744 1745 return(0); 1746} 1747 1748void 1749sk_start(struct ifnet *ifp) 1750{ 1751 struct sk_if_softc *sc_if = ifp->if_softc; 1752 struct sk_softc *sc = sc_if->sk_softc; 1753 struct mbuf *m_head = NULL; 1754 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1755 int pkts = 0; 1756 1757 DPRINTFN(2, ("sk_start\n")); 1758 1759 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1760 IFQ_POLL(&ifp->if_snd, m_head); 1761 if (m_head == NULL) 1762 break; 1763 1764 /* 1765 * Pack the data into the transmit ring. If we 1766 * don't have room, set the OACTIVE flag and wait 1767 * for the NIC to drain the ring. 1768 */ 1769 if (sk_encap(sc_if, m_head, &idx)) { 1770 ifp->if_flags |= IFF_OACTIVE; 1771 break; 1772 } 1773 1774 /* now we are committed to transmit the packet */ 1775 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1776 pkts++; 1777 1778 /* 1779 * If there's a BPF listener, bounce a copy of this frame 1780 * to him. 1781 */ 1782#if NBPFILTER > 0 1783 if (ifp->if_bpf) 1784 bpf_mtap(ifp->if_bpf, m_head); 1785#endif 1786 } 1787 if (pkts == 0) 1788 return; 1789 1790 /* Transmit */ 1791 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1792 sc_if->sk_cdata.sk_tx_prod = idx; 1793 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1794 1795 /* Set a timeout in case the chip goes out to lunch. */ 1796 ifp->if_timer = 5; 1797 } 1798} 1799 1800 1801void 1802sk_watchdog(struct ifnet *ifp) 1803{ 1804 struct sk_if_softc *sc_if = ifp->if_softc; 1805 1806 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1807 ifp->if_flags &= ~IFF_RUNNING; 1808 sk_init(sc_if); 1809} 1810 1811void 1812sk_shutdown(void *v) 1813{ 1814 struct sk_softc *sc = v; 1815 1816 DPRINTFN(2, ("sk_shutdown\n")); 1817 1818 /* Turn off the 'driver is loaded' LED. */ 1819 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1820 1821 /* 1822 * Reset the GEnesis controller. Doing this should also 1823 * assert the resets on the attached XMAC(s). 1824 */ 1825 sk_reset(sc); 1826} 1827 1828void 1829sk_rxeof(struct sk_if_softc *sc_if) 1830{ 1831 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1832 struct mbuf *m; 1833 struct sk_chain *cur_rx; 1834 struct sk_rx_desc *cur_desc; 1835 int i, cur, total_len = 0; 1836 u_int32_t rxstat; 1837 bus_dmamap_t dmamap; 1838 u_int16_t csum1, csum2; 1839 1840 DPRINTFN(2, ("sk_rxeof\n")); 1841 1842 i = sc_if->sk_cdata.sk_rx_prod; 1843 1844 for (;;) { 1845 cur = i; 1846 1847 /* Sync the descriptor */ 1848 SK_CDRXSYNC(sc_if, cur, 1849 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1850 1851 if (sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN) { 1852 /* Invalidate the descriptor -- it's not ready yet */ 1853 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 1854 sc_if->sk_cdata.sk_rx_prod = i; 1855 break; 1856 } 1857 1858 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1859 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1860 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1861 1862 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1863 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1864 1865 rxstat = cur_desc->sk_xmac_rxstat; 1866 m = cur_rx->sk_mbuf; 1867 cur_rx->sk_mbuf = NULL; 1868 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1869 1870 csum1 = sc_if->sk_rdata->sk_rx_ring[i].sk_csum1; 1871 csum2 = sc_if->sk_rdata->sk_rx_ring[i].sk_csum2; 1872 1873 SK_INC(i, SK_RX_RING_CNT); 1874 1875 if (rxstat & XM_RXSTAT_ERRFRAME) { 1876 ifp->if_ierrors++; 1877 sk_newbuf(sc_if, cur, m, dmamap); 1878 continue; 1879 } 1880 1881 /* 1882 * Try to allocate a new jumbo buffer. If that 1883 * fails, copy the packet to mbufs and put the 1884 * jumbo buffer back in the ring so it can be 1885 * re-used. If allocating mbufs fails, then we 1886 * have to drop the packet. 1887 */ 1888 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1889 struct mbuf *m0; 1890 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1891 total_len + ETHER_ALIGN, 0, ifp, NULL); 1892 sk_newbuf(sc_if, cur, m, dmamap); 1893 if (m0 == NULL) { 1894 ifp->if_ierrors++; 1895 continue; 1896 } 1897 m_adj(m0, ETHER_ALIGN); 1898 m = m0; 1899 } else { 1900 m->m_pkthdr.rcvif = ifp; 1901 m->m_pkthdr.len = m->m_len = total_len; 1902 } 1903 1904 ifp->if_ipackets++; 1905 1906 sk_rxcsum(ifp, m, csum1, csum2); 1907 1908#if NBPFILTER > 0 1909 if (ifp->if_bpf) 1910 bpf_mtap(ifp->if_bpf, m); 1911#endif 1912 1913 /* pass it on. */ 1914 ether_input_mbuf(ifp, m); 1915 } 1916} 1917 1918void 1919sk_rxcsum(struct ifnet *ifp, struct mbuf *m, const u_int16_t csum1, const u_int16_t csum2) 1920{ 1921 struct ether_header *eh; 1922 struct ip *ip; 1923 u_int8_t *pp; 1924 int hlen, len, plen; 1925 u_int16_t iph_csum, ipo_csum, ipd_csum, csum; 1926 1927 pp = mtod(m, u_int8_t *); 1928 plen = m->m_pkthdr.len; 1929 if (plen < sizeof(*eh)) 1930 return; 1931 eh = (struct ether_header *)pp; 1932 iph_csum = in_cksum_addword(csum1, (~csum2 & 0xffff)); 1933 1934 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1935 u_int16_t *xp = (u_int16_t *)pp; 1936 1937 xp = (u_int16_t *)pp; 1938 if (xp[1] != htons(ETHERTYPE_IP)) 1939 return; 1940 iph_csum = in_cksum_addword(iph_csum, (~xp[0] & 0xffff)); 1941 iph_csum = in_cksum_addword(iph_csum, (~xp[1] & 0xffff)); 1942 xp = (u_int16_t *)(pp + sizeof(struct ip)); 1943 iph_csum = in_cksum_addword(iph_csum, xp[0]); 1944 iph_csum = in_cksum_addword(iph_csum, xp[1]); 1945 pp += EVL_ENCAPLEN; 1946 } else if (eh->ether_type != htons(ETHERTYPE_IP)) 1947 return; 1948 1949 pp += sizeof(*eh); 1950 plen -= sizeof(*eh); 1951 1952 ip = (struct ip *)pp; 1953 1954 if (ip->ip_v != IPVERSION) 1955 return; 1956 1957 hlen = ip->ip_hl << 2; 1958 if (hlen < sizeof(struct ip)) 1959 return; 1960 if (hlen > ntohs(ip->ip_len)) 1961 return; 1962 1963 /* Don't deal with truncated or padded packets. */ 1964 if (plen != ntohs(ip->ip_len)) 1965 return; 1966 1967 len = hlen - sizeof(struct ip); 1968 if (len > 0) { 1969 u_int16_t *p; 1970 1971 p = (u_int16_t *)(ip + 1); 1972 ipo_csum = 0; 1973 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++) 1974 ipo_csum = in_cksum_addword(ipo_csum, *p); 1975 iph_csum = in_cksum_addword(iph_csum, ipo_csum); 1976 ipd_csum = in_cksum_addword(csum2, (~ipo_csum & 0xffff)); 1977 } else 1978 ipd_csum = csum2; 1979 1980 if (iph_csum != 0xffff) 1981 return; 1982 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1983 1984 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1985 return; /* ip frag, we're done for now */ 1986 1987 pp += hlen; 1988 1989 /* Only know checksum protocol for udp/tcp */ 1990 if (ip->ip_p == IPPROTO_UDP) { 1991 struct udphdr *uh = (struct udphdr *)pp; 1992 1993 if (uh->uh_sum == 0) /* udp with no checksum */ 1994 return; 1995 } else if (ip->ip_p != IPPROTO_TCP) 1996 return; 1997 1998 csum = in_cksum_phdr(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1999 htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum); 2000 if (csum == 0xffff) { 2001 m->m_pkthdr.csum_flags |= (ip->ip_p == IPPROTO_TCP) ? 2002 M_TCP_CSUM_IN_OK : M_UDP_CSUM_IN_OK; 2003 } 2004} 2005 2006void 2007sk_txeof(struct sk_if_softc *sc_if) 2008{ 2009 struct sk_softc *sc = sc_if->sk_softc; 2010 struct sk_tx_desc *cur_tx; 2011 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2012 u_int32_t idx; 2013 struct sk_txmap_entry *entry; 2014 2015 DPRINTFN(2, ("sk_txeof\n")); 2016 2017 /* 2018 * Go through our tx ring and free mbufs for those 2019 * frames that have been sent. 2020 */ 2021 idx = sc_if->sk_cdata.sk_tx_cons; 2022 while(idx != sc_if->sk_cdata.sk_tx_prod) { 2023 SK_CDTXSYNC(sc_if, idx, 1, 2024 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2025 2026 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2027#ifdef SK_DEBUG 2028 if (skdebug >= 2) 2029 sk_dump_txdesc(cur_tx, idx); 2030#endif 2031 if (cur_tx->sk_ctl & SK_TXCTL_OWN) { 2032 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2033 break; 2034 } 2035 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 2036 ifp->if_opackets++; 2037 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2038 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2039 2040 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2041 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2042 2043 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2044 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2045 2046 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2047 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2048 link); 2049 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2050 } 2051 sc_if->sk_cdata.sk_tx_cnt--; 2052 SK_INC(idx, SK_TX_RING_CNT); 2053 } 2054 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2055 ifp->if_timer = 0; 2056 else /* nudge chip to keep tx ring moving */ 2057 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2058 2059 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2060 ifp->if_flags &= ~IFF_OACTIVE; 2061 2062 sc_if->sk_cdata.sk_tx_cons = idx; 2063} 2064 2065void 2066sk_tick(void *xsc_if) 2067{ 2068 struct sk_if_softc *sc_if = xsc_if; 2069 struct mii_data *mii = &sc_if->sk_mii; 2070 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2071 int i; 2072 2073 DPRINTFN(2, ("sk_tick\n")); 2074 2075 if (!(ifp->if_flags & IFF_UP)) 2076 return; 2077 2078 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2079 sk_intr_bcom(sc_if); 2080 return; 2081 } 2082 2083 /* 2084 * According to SysKonnect, the correct way to verify that 2085 * the link has come back up is to poll bit 0 of the GPIO 2086 * register three times. This pin has the signal from the 2087 * link sync pin connected to it; if we read the same link 2088 * state 3 times in a row, we know the link is up. 2089 */ 2090 for (i = 0; i < 3; i++) { 2091 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2092 break; 2093 } 2094 2095 if (i != 3) { 2096 timeout_add(&sc_if->sk_tick_ch, hz); 2097 return; 2098 } 2099 2100 /* Turn the GP0 interrupt back on. */ 2101 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2102 SK_XM_READ_2(sc_if, XM_ISR); 2103 mii_tick(mii); 2104 timeout_del(&sc_if->sk_tick_ch); 2105} 2106 2107void 2108sk_intr_bcom(struct sk_if_softc *sc_if) 2109{ 2110 struct mii_data *mii = &sc_if->sk_mii; 2111 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2112 int status; 2113 2114 DPRINTFN(2, ("sk_intr_bcom\n")); 2115 2116 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2117 2118 /* 2119 * Read the PHY interrupt register to make sure 2120 * we clear any pending interrupts. 2121 */ 2122 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2123 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2124 2125 if (!(ifp->if_flags & IFF_RUNNING)) { 2126 sk_init_xmac(sc_if); 2127 return; 2128 } 2129 2130 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2131 int lstat; 2132 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2133 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2134 2135 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2136 mii_mediachg(mii); 2137 /* Turn off the link LED. */ 2138 SK_IF_WRITE_1(sc_if, 0, 2139 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2140 sc_if->sk_link = 0; 2141 } else if (status & BRGPHY_ISR_LNK_CHG) { 2142 sk_xmac_miibus_writereg((struct device *)sc_if, 2143 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2144 mii_tick(mii); 2145 sc_if->sk_link = 1; 2146 /* Turn on the link LED. */ 2147 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2148 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2149 SK_LINKLED_BLINK_OFF); 2150 } else { 2151 mii_tick(mii); 2152 timeout_add(&sc_if->sk_tick_ch, hz); 2153 } 2154 } 2155 2156 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2157} 2158 2159void 2160sk_intr_xmac(struct sk_if_softc *sc_if) 2161{ 2162 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2163 2164 DPRINTFN(2, ("sk_intr_xmac\n")); 2165 2166 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2167 if (status & XM_ISR_GP0_SET) { 2168 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2169 timeout_add(&sc_if->sk_tick_ch, hz); 2170 } 2171 2172 if (status & XM_ISR_AUTONEG_DONE) { 2173 timeout_add(&sc_if->sk_tick_ch, hz); 2174 } 2175 } 2176 2177 if (status & XM_IMR_TX_UNDERRUN) 2178 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2179 2180 if (status & XM_IMR_RX_OVERRUN) 2181 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2182} 2183 2184void 2185sk_intr_yukon(sc_if) 2186 struct sk_if_softc *sc_if; 2187{ 2188 int status; 2189 2190 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2191 2192 DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status)); 2193} 2194 2195int 2196sk_intr(void *xsc) 2197{ 2198 struct sk_softc *sc = xsc; 2199 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2200 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2201 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2202 u_int32_t status; 2203 int claimed = 0; 2204 2205 if (sc_if0 != NULL) 2206 ifp0 = &sc_if0->arpcom.ac_if; 2207 if (sc_if1 != NULL) 2208 ifp1 = &sc_if1->arpcom.ac_if; 2209 2210 for (;;) { 2211 status = CSR_READ_4(sc, SK_ISSR); 2212 DPRINTFN(2, ("sk_intr: status=%#x\n", status)); 2213 2214 if (!(status & sc->sk_intrmask)) 2215 break; 2216 2217 claimed = 1; 2218 2219 /* Handle receive interrupts first. */ 2220 if (status & SK_ISR_RX1_EOF) { 2221 sk_rxeof(sc_if0); 2222 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2223 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2224 } 2225 if (status & SK_ISR_RX2_EOF) { 2226 sk_rxeof(sc_if1); 2227 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2228 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2229 } 2230 2231 /* Then transmit interrupts. */ 2232 if (status & SK_ISR_TX1_S_EOF) { 2233 sk_txeof(sc_if0); 2234 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2235 SK_TXBMU_CLR_IRQ_EOF); 2236 } 2237 if (status & SK_ISR_TX2_S_EOF) { 2238 sk_txeof(sc_if1); 2239 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2240 SK_TXBMU_CLR_IRQ_EOF); 2241 } 2242 2243 /* Then MAC interrupts. */ 2244 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 2245 if (sc->sk_type == SK_GENESIS) 2246 sk_intr_xmac(sc_if0); 2247 else 2248 sk_intr_yukon(sc_if0); 2249 } 2250 2251 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 2252 if (sc->sk_type == SK_GENESIS) 2253 sk_intr_xmac(sc_if1); 2254 else 2255 sk_intr_yukon(sc_if1); 2256 2257 } 2258 2259 if (status & SK_ISR_EXTERNAL_REG) { 2260 if (ifp0 != NULL && 2261 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2262 sk_intr_bcom(sc_if0); 2263 2264 if (ifp1 != NULL && 2265 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2266 sk_intr_bcom(sc_if1); 2267 } 2268 } 2269 2270 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2271 2272 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2273 sk_start(ifp0); 2274 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2275 sk_start(ifp1); 2276 2277 return (claimed); 2278} 2279 2280void 2281sk_init_xmac(struct sk_if_softc *sc_if) 2282{ 2283 struct sk_softc *sc = sc_if->sk_softc; 2284 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2285 struct sk_bcom_hack bhack[] = { 2286 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2287 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2288 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2289 { 0, 0 } }; 2290 2291 DPRINTFN(2, ("sk_init_xmac\n")); 2292 2293 /* Unreset the XMAC. */ 2294 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2295 DELAY(1000); 2296 2297 /* Reset the XMAC's internal state. */ 2298 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2299 2300 /* Save the XMAC II revision */ 2301 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2302 2303 /* 2304 * Perform additional initialization for external PHYs, 2305 * namely for the 1000baseTX cards that use the XMAC's 2306 * GMII mode. 2307 */ 2308 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2309 int i = 0; 2310 u_int32_t val; 2311 2312 /* Take PHY out of reset. */ 2313 val = sk_win_read_4(sc, SK_GPIO); 2314 if (sc_if->sk_port == SK_PORT_A) 2315 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2316 else 2317 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2318 sk_win_write_4(sc, SK_GPIO, val); 2319 2320 /* Enable GMII mode on the XMAC. */ 2321 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2322 2323 sk_xmac_miibus_writereg((struct device *)sc_if, 2324 SK_PHYADDR_BCOM, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2325 DELAY(10000); 2326 sk_xmac_miibus_writereg((struct device *)sc_if, 2327 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2328 2329 /* 2330 * Early versions of the BCM5400 apparently have 2331 * a bug that requires them to have their reserved 2332 * registers initialized to some magic values. I don't 2333 * know what the numbers do, I'm just the messenger. 2334 */ 2335 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2336 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2337 while(bhack[i].reg) { 2338 sk_xmac_miibus_writereg((struct device *)sc_if, 2339 SK_PHYADDR_BCOM, bhack[i].reg, 2340 bhack[i].val); 2341 i++; 2342 } 2343 } 2344 } 2345 2346 /* Set station address */ 2347 SK_XM_WRITE_2(sc_if, XM_PAR0, 2348 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2349 SK_XM_WRITE_2(sc_if, XM_PAR1, 2350 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2351 SK_XM_WRITE_2(sc_if, XM_PAR2, 2352 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2353 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2354 2355 if (ifp->if_flags & IFF_PROMISC) { 2356 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2357 } else { 2358 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2359 } 2360 2361 if (ifp->if_flags & IFF_BROADCAST) { 2362 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2363 } else { 2364 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2365 } 2366 2367 /* We don't need the FCS appended to the packet. */ 2368 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2369 2370 /* We want short frames padded to 60 bytes. */ 2371 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2372 2373 /* 2374 * Enable the reception of all error frames. This is is 2375 * a necessary evil due to the design of the XMAC. The 2376 * XMAC's receive FIFO is only 8K in size, however jumbo 2377 * frames can be up to 9000 bytes in length. When bad 2378 * frame filtering is enabled, the XMAC's RX FIFO operates 2379 * in 'store and forward' mode. For this to work, the 2380 * entire frame has to fit into the FIFO, but that means 2381 * that jumbo frames larger than 8192 bytes will be 2382 * truncated. Disabling all bad frame filtering causes 2383 * the RX FIFO to operate in streaming mode, in which 2384 * case the XMAC will start transfering frames out of the 2385 * RX FIFO as soon as the FIFO threshold is reached. 2386 */ 2387 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2388 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2389 XM_MODE_RX_INRANGELEN); 2390 2391 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2392 2393 /* 2394 * Bump up the transmit threshold. This helps hold off transmit 2395 * underruns when we're blasting traffic from both ports at once. 2396 */ 2397 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2398 2399 /* Set multicast filter */ 2400 sk_setmulti(sc_if); 2401 2402 /* Clear and enable interrupts */ 2403 SK_XM_READ_2(sc_if, XM_ISR); 2404 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2405 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2406 else 2407 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2408 2409 /* Configure MAC arbiter */ 2410 switch(sc_if->sk_xmac_rev) { 2411 case XM_XMAC_REV_B2: 2412 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2413 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2414 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2415 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2416 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2417 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2418 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2419 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2420 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2421 break; 2422 case XM_XMAC_REV_C1: 2423 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2424 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2425 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2426 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2427 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2428 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2429 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2430 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2431 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2432 break; 2433 default: 2434 break; 2435 } 2436 sk_win_write_2(sc, SK_MACARB_CTL, 2437 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2438 2439 sc_if->sk_link = 1; 2440} 2441 2442void sk_init_yukon(sc_if) 2443 struct sk_if_softc *sc_if; 2444{ 2445 u_int32_t phy; 2446 u_int16_t reg; 2447 struct sk_softc *sc; 2448 int i; 2449 2450 sc = sc_if->sk_softc; 2451 2452 DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n", 2453 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2454 2455 if (sc->sk_type == SK_YUKON_LITE && 2456 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2457 /* Take PHY out of reset. */ 2458 sk_win_write_4(sc, SK_GPIO, 2459 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2460 } 2461 2462 /* GMAC and GPHY Reset */ 2463 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2464 2465 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2466 2467 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2468 DELAY(1000); 2469 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2470 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2471 DELAY(1000); 2472 2473 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2474 2475 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2476 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2477 2478 switch(sc_if->sk_softc->sk_pmd) { 2479 case IFM_1000_SX: 2480 case IFM_1000_LX: 2481 phy |= SK_GPHY_FIBER; 2482 break; 2483 2484 case IFM_1000_CX: 2485 case IFM_1000_T: 2486 phy |= SK_GPHY_COPPER; 2487 break; 2488 } 2489 2490 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2491 2492 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2493 DELAY(1000); 2494 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2495 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2496 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2497 2498 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2499 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2500 2501 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2502 2503 /* unused read of the interrupt source register */ 2504 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2505 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2506 2507 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2508 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2509 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2510 2511 /* MIB Counter Clear Mode set */ 2512 reg |= YU_PAR_MIB_CLR; 2513 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2514 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2515 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2516 2517 /* MIB Counter Clear Mode clear */ 2518 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2519 reg &= ~YU_PAR_MIB_CLR; 2520 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2521 2522 /* receive control reg */ 2523 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2524 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2525 YU_RCR_CRCR); 2526 2527 /* transmit parameter register */ 2528 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2529 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2530 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2531 2532 /* serial mode register */ 2533 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2534 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2535 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2536 YU_SMR_IPG_DATA(0x1e)); 2537 2538 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2539 /* Setup Yukon's address */ 2540 for (i = 0; i < 3; i++) { 2541 /* Write Source Address 1 (unicast filter) */ 2542 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2543 sc_if->arpcom.ac_enaddr[i * 2] | 2544 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2545 } 2546 2547 for (i = 0; i < 3; i++) { 2548 reg = sk_win_read_2(sc_if->sk_softc, 2549 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2550 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2551 } 2552 2553 /* Set multicast filter */ 2554 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2555 sk_setmulti(sc_if); 2556 2557 /* enable interrupt mask for counter overflows */ 2558 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2559 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2560 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2561 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2562 2563 /* Configure RX MAC FIFO */ 2564 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2565 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2566 2567 /* Configure TX MAC FIFO */ 2568 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2569 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2570 2571 DPRINTFN(6, ("sk_init_yukon: end\n")); 2572} 2573 2574/* 2575 * Note that to properly initialize any part of the GEnesis chip, 2576 * you first have to take it out of reset mode. 2577 */ 2578void 2579sk_init(void *xsc_if) 2580{ 2581 struct sk_if_softc *sc_if = xsc_if; 2582 struct sk_softc *sc = sc_if->sk_softc; 2583 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2584 struct mii_data *mii = &sc_if->sk_mii; 2585 int s; 2586 2587 DPRINTFN(2, ("sk_init\n")); 2588 2589 s = splnet(); 2590 2591 if (ifp->if_flags & IFF_RUNNING) { 2592 splx(s); 2593 return; 2594 } 2595 2596 /* Cancel pending I/O and free all RX/TX buffers. */ 2597 sk_stop(sc_if); 2598 2599 if (sc->sk_type == SK_GENESIS) { 2600 /* Configure LINK_SYNC LED */ 2601 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2602 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2603 SK_LINKLED_LINKSYNC_ON); 2604 2605 /* Configure RX LED */ 2606 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2607 SK_RXLEDCTL_COUNTER_START); 2608 2609 /* Configure TX LED */ 2610 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2611 SK_TXLEDCTL_COUNTER_START); 2612 } 2613 2614 /* Configure I2C registers */ 2615 2616 /* Configure XMAC(s) */ 2617 switch (sc->sk_type) { 2618 case SK_GENESIS: 2619 sk_init_xmac(sc_if); 2620 break; 2621 case SK_YUKON: 2622 case SK_YUKON_LITE: 2623 case SK_YUKON_LP: 2624 sk_init_yukon(sc_if); 2625 break; 2626 } 2627 mii_mediachg(mii); 2628 2629 if (sc->sk_type == SK_GENESIS) { 2630 /* Configure MAC FIFOs */ 2631 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2632 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2633 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2634 2635 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2636 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2637 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2638 } 2639 2640 /* Configure transmit arbiter(s) */ 2641 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2642 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2643 2644 /* Configure RAMbuffers */ 2645 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2646 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2647 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2648 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2649 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2650 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2651 2652 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2653 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2654 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2655 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2656 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2657 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2658 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2659 2660 /* Configure BMUs */ 2661 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2662 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2663 SK_RX_RING_ADDR(sc_if, 0)); 2664 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2665 2666 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2667 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2668 SK_TX_RING_ADDR(sc_if, 0)); 2669 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2670 2671 /* Init descriptors */ 2672 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2673 printf("%s: initialization failed: no " 2674 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2675 sk_stop(sc_if); 2676 splx(s); 2677 return; 2678 } 2679 2680 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2681 printf("%s: initialization failed: no " 2682 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2683 sk_stop(sc_if); 2684 splx(s); 2685 return; 2686 } 2687 2688 /* Configure interrupt handling */ 2689 CSR_READ_4(sc, SK_ISSR); 2690 if (sc_if->sk_port == SK_PORT_A) 2691 sc->sk_intrmask |= SK_INTRS1; 2692 else 2693 sc->sk_intrmask |= SK_INTRS2; 2694 2695 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2696 2697 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2698 2699 /* Start BMUs. */ 2700 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2701 2702 if (sc->sk_type == SK_GENESIS) { 2703 /* Enable XMACs TX and RX state machines */ 2704 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2705 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2706 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2707 } 2708 2709 if (SK_YUKON_FAMILY(sc->sk_type)) { 2710 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2711 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2712 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2713 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2714 } 2715 2716 2717 ifp->if_flags |= IFF_RUNNING; 2718 ifp->if_flags &= ~IFF_OACTIVE; 2719 2720 splx(s); 2721} 2722 2723void 2724sk_stop(struct sk_if_softc *sc_if) 2725{ 2726 struct sk_softc *sc = sc_if->sk_softc; 2727 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2728 struct sk_txmap_entry *dma; 2729 int i; 2730 2731 DPRINTFN(2, ("sk_stop\n")); 2732 2733 timeout_del(&sc_if->sk_tick_ch); 2734 2735 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2736 2737 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2738 u_int32_t val; 2739 2740 /* Put PHY back into reset. */ 2741 val = sk_win_read_4(sc, SK_GPIO); 2742 if (sc_if->sk_port == SK_PORT_A) { 2743 val |= SK_GPIO_DIR0; 2744 val &= ~SK_GPIO_DAT0; 2745 } else { 2746 val |= SK_GPIO_DIR2; 2747 val &= ~SK_GPIO_DAT2; 2748 } 2749 sk_win_write_4(sc, SK_GPIO, val); 2750 } 2751 2752 /* Turn off various components of this interface. */ 2753 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2754 switch (sc->sk_type) { 2755 case SK_GENESIS: 2756 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2757 SK_TXMACCTL_XMAC_RESET); 2758 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2759 break; 2760 case SK_YUKON: 2761 case SK_YUKON_LITE: 2762 case SK_YUKON_LP: 2763 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2764 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2765 break; 2766 } 2767 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2768 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2769 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2770 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2771 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2772 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2773 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2774 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2775 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2776 2777 /* Disable interrupts */ 2778 if (sc_if->sk_port == SK_PORT_A) 2779 sc->sk_intrmask &= ~SK_INTRS1; 2780 else 2781 sc->sk_intrmask &= ~SK_INTRS2; 2782 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2783 2784 SK_XM_READ_2(sc_if, XM_ISR); 2785 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2786 2787 /* Free RX and TX mbufs still in the queues. */ 2788 for (i = 0; i < SK_RX_RING_CNT; i++) { 2789 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2790 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2791 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2792 } 2793 } 2794 2795 for (i = 0; i < SK_TX_RING_CNT; i++) { 2796 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2797 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2798 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2799 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2800 sc_if->sk_cdata.sk_tx_map[i], link); 2801 sc_if->sk_cdata.sk_tx_map[i] = 0; 2802 } 2803 } 2804 2805 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2806 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2807 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2808 free(dma, M_DEVBUF); 2809 } 2810} 2811 2812struct cfattach skc_ca = { 2813 sizeof(struct sk_softc), skc_probe, skc_attach, 2814}; 2815 2816struct cfdriver skc_cd = { 2817 0, "skc", DV_DULL 2818}; 2819 2820struct cfattach sk_ca = { 2821 sizeof(struct sk_if_softc), sk_probe, sk_attach, 2822}; 2823 2824struct cfdriver sk_cd = { 2825 0, "sk", DV_IFNET 2826}; 2827 2828#ifdef SK_DEBUG 2829void 2830sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2831{ 2832#define DESC_PRINT(X) \ 2833 if (desc->X) \ 2834 printf("txdesc[%d]." #X "=%#x\n", \ 2835 idx, desc->X); 2836 2837 DESC_PRINT(sk_ctl); 2838 DESC_PRINT(sk_next); 2839 DESC_PRINT(sk_data_lo); 2840 DESC_PRINT(sk_data_hi); 2841 DESC_PRINT(sk_xmac_txstat); 2842 DESC_PRINT(sk_rsvd0); 2843 DESC_PRINT(sk_csum_startval); 2844 DESC_PRINT(sk_csum_startpos); 2845 DESC_PRINT(sk_csum_writepos); 2846 DESC_PRINT(sk_rsvd1); 2847#undef PRINT 2848} 2849 2850void 2851sk_dump_bytes(const char *data, int len) 2852{ 2853 int c, i, j; 2854 2855 for (i = 0; i < len; i += 16) { 2856 printf("%08x ", i); 2857 c = len - i; 2858 if (c > 16) c = 16; 2859 2860 for (j = 0; j < c; j++) { 2861 printf("%02x ", data[i + j] & 0xff); 2862 if ((j & 0xf) == 7 && j > 0) 2863 printf(" "); 2864 } 2865 2866 for (; j < 16; j++) 2867 printf(" "); 2868 printf(" "); 2869 2870 for (j = 0; j < c; j++) { 2871 int ch = data[i + j] & 0xff; 2872 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2873 } 2874 2875 printf("\n"); 2876 2877 if (c < 16) 2878 break; 2879 } 2880} 2881 2882void 2883sk_dump_mbuf(struct mbuf *m) 2884{ 2885 int count = m->m_pkthdr.len; 2886 2887 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2888 2889 while (count > 0 && m) { 2890 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2891 m, m->m_data, m->m_len); 2892 sk_dump_bytes(mtod(m, char *), m->m_len); 2893 2894 count -= m->m_len; 2895 m = m->m_next; 2896 } 2897} 2898#endif 2899