if_sk.c revision 1.79
1/* $OpenBSD: if_sk.c,v 1.79 2005/09/16 00:43:31 brad Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37/* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53/* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72/* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89#include "bpfilter.h" 90 91#include <sys/param.h> 92#include <sys/systm.h> 93#include <sys/sockio.h> 94#include <sys/mbuf.h> 95#include <sys/malloc.h> 96#include <sys/kernel.h> 97#include <sys/socket.h> 98#include <sys/device.h> 99#include <sys/queue.h> 100 101#include <net/if.h> 102#include <net/if_dl.h> 103#include <net/if_types.h> 104 105#ifdef INET 106#include <netinet/in.h> 107#include <netinet/in_systm.h> 108#include <netinet/in_var.h> 109#include <netinet/ip.h> 110#include <netinet/udp.h> 111#include <netinet/tcp.h> 112#include <netinet/if_ether.h> 113#endif 114 115#include <net/if_media.h> 116#include <net/if_vlan_var.h> 117 118#if NBPFILTER > 0 119#include <net/bpf.h> 120#endif 121 122#include <dev/mii/mii.h> 123#include <dev/mii/miivar.h> 124#include <dev/mii/brgphyreg.h> 125 126#include <dev/pci/pcireg.h> 127#include <dev/pci/pcivar.h> 128#include <dev/pci/pcidevs.h> 129 130#define SK_VERBOSE 131/* #define SK_USEIOSPACE */ 132 133#include <dev/pci/if_skreg.h> 134#include <dev/pci/xmaciireg.h> 135#include <dev/pci/yukonreg.h> 136 137int skc_probe(struct device *, void *, void *); 138void skc_attach(struct device *, struct device *self, void *aux); 139int sk_probe(struct device *, void *, void *); 140void sk_attach(struct device *, struct device *self, void *aux); 141int skcprint(void *, const char *); 142int sk_intr(void *); 143void sk_intr_bcom(struct sk_if_softc *); 144void sk_intr_xmac(struct sk_if_softc *); 145void sk_intr_yukon(struct sk_if_softc *); 146void sk_rxeof(struct sk_if_softc *); 147void sk_txeof(struct sk_if_softc *); 148int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 149void sk_start(struct ifnet *); 150int sk_ioctl(struct ifnet *, u_long, caddr_t); 151void sk_init(void *); 152void sk_init_xmac(struct sk_if_softc *); 153void sk_init_yukon(struct sk_if_softc *); 154void sk_stop(struct sk_if_softc *); 155void sk_watchdog(struct ifnet *); 156void sk_shutdown(void *); 157int sk_ifmedia_upd(struct ifnet *); 158void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 159void sk_reset(struct sk_softc *); 160int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 161int sk_alloc_jumbo_mem(struct sk_if_softc *); 162void *sk_jalloc(struct sk_if_softc *); 163void sk_jfree(caddr_t, u_int, void *); 164int sk_init_rx_ring(struct sk_if_softc *); 165int sk_init_tx_ring(struct sk_if_softc *); 166 167int sk_xmac_miibus_readreg(struct device *, int, int); 168void sk_xmac_miibus_writereg(struct device *, int, int, int); 169void sk_xmac_miibus_statchg(struct device *); 170 171int sk_marv_miibus_readreg(struct device *, int, int); 172void sk_marv_miibus_writereg(struct device *, int, int, int); 173void sk_marv_miibus_statchg(struct device *); 174 175u_int32_t sk_xmac_hash(caddr_t); 176u_int32_t sk_yukon_hash(caddr_t); 177void sk_setfilt(struct sk_if_softc *, caddr_t, int); 178void sk_setmulti(struct sk_if_softc *); 179void sk_tick(void *); 180void sk_rxcsum(struct ifnet *, struct mbuf *, const u_int16_t, const u_int16_t); 181 182#ifdef SK_DEBUG 183#define DPRINTF(x) if (skdebug) printf x 184#define DPRINTFN(n,x) if (skdebug >= (n)) printf x 185int skdebug = 0; 186 187void sk_dump_txdesc(struct sk_tx_desc *, int); 188void sk_dump_mbuf(struct mbuf *); 189void sk_dump_bytes(const char *, int); 190#else 191#define DPRINTF(x) 192#define DPRINTFN(n,x) 193#endif 194 195#define SK_SETBIT(sc, reg, x) \ 196 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 197 198#define SK_CLRBIT(sc, reg, x) \ 199 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 200 201#define SK_WIN_SETBIT_4(sc, reg, x) \ 202 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 203 204#define SK_WIN_CLRBIT_4(sc, reg, x) \ 205 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 206 207#define SK_WIN_SETBIT_2(sc, reg, x) \ 208 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 209 210#define SK_WIN_CLRBIT_2(sc, reg, x) \ 211 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 212 213/* supported device vendors */ 214const struct pci_matchid skc_devices[] = { 215 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940 }, 216 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_GIG }, 217 { PCI_VENDOR_CNET, PCI_PRODUCT_CNET_GIGACARD }, 218 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T }, 219 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 220 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2 }, 221 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064 }, 222 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SK_V2 }, 223 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SK_V2_BELKIN }, 224 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 }, 225 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_2 }, 226 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_3 }, 227 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_4 }, 228 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_5 }, 229 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_6 }, 230 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_7 }, 231 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8 }, 232 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 233 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 234 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 235 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 236 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 237 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_GE }, 238 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2 }, 239 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Sxx }, 240 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Exx }, 241}; 242 243#define SK_LINKSYS_EG1032_SUBID 0x00151737 244 245static inline u_int32_t 246sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 247{ 248#ifdef SK_USEIOSPACE 249 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 250 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 251#else 252 return CSR_READ_4(sc, reg); 253#endif 254} 255 256static inline u_int16_t 257sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 258{ 259#ifdef SK_USEIOSPACE 260 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 261 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 262#else 263 return CSR_READ_2(sc, reg); 264#endif 265} 266 267static inline u_int8_t 268sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 269{ 270#ifdef SK_USEIOSPACE 271 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 272 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 273#else 274 return CSR_READ_1(sc, reg); 275#endif 276} 277 278static inline void 279sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 280{ 281#ifdef SK_USEIOSPACE 282 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 283 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 284#else 285 CSR_WRITE_4(sc, reg, x); 286#endif 287} 288 289static inline void 290sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 291{ 292#ifdef SK_USEIOSPACE 293 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 294 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 295#else 296 CSR_WRITE_2(sc, reg, x); 297#endif 298} 299 300static inline void 301sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 302{ 303#ifdef SK_USEIOSPACE 304 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 305 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 306#else 307 CSR_WRITE_1(sc, reg, x); 308#endif 309} 310 311int 312sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 313{ 314 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 315 int i; 316 317 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 318 319 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 320 return(0); 321 322 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 323 SK_XM_READ_2(sc_if, XM_PHY_DATA); 324 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 325 for (i = 0; i < SK_TIMEOUT; i++) { 326 DELAY(1); 327 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 328 XM_MMUCMD_PHYDATARDY) 329 break; 330 } 331 332 if (i == SK_TIMEOUT) { 333 printf("%s: phy failed to come ready\n", 334 sc_if->sk_dev.dv_xname); 335 return(0); 336 } 337 } 338 DELAY(1); 339 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 340} 341 342void 343sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 344{ 345 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 346 int i; 347 348 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 349 350 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 351 for (i = 0; i < SK_TIMEOUT; i++) { 352 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 353 break; 354 } 355 356 if (i == SK_TIMEOUT) { 357 printf("%s: phy failed to come ready\n", 358 sc_if->sk_dev.dv_xname); 359 return; 360 } 361 362 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 363 for (i = 0; i < SK_TIMEOUT; i++) { 364 DELAY(1); 365 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 366 break; 367 } 368 369 if (i == SK_TIMEOUT) 370 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 371} 372 373void 374sk_xmac_miibus_statchg(struct device *dev) 375{ 376 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 377 struct mii_data *mii = &sc_if->sk_mii; 378 379 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 380 381 /* 382 * If this is a GMII PHY, manually set the XMAC's 383 * duplex mode accordingly. 384 */ 385 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 386 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 387 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 388 } else { 389 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 390 } 391 } 392} 393 394int 395sk_marv_miibus_readreg(dev, phy, reg) 396 struct device *dev; 397 int phy, reg; 398{ 399 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 400 u_int16_t val; 401 int i; 402 403 if (phy != 0 || 404 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 405 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 406 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 407 phy, reg)); 408 return(0); 409 } 410 411 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 412 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 413 414 for (i = 0; i < SK_TIMEOUT; i++) { 415 DELAY(1); 416 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 417 if (val & YU_SMICR_READ_VALID) 418 break; 419 } 420 421 if (i == SK_TIMEOUT) { 422 printf("%s: phy failed to come ready\n", 423 sc_if->sk_dev.dv_xname); 424 return 0; 425 } 426 427 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 428 SK_TIMEOUT)); 429 430 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 431 432 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 433 phy, reg, val)); 434 435 return val; 436} 437 438void 439sk_marv_miibus_writereg(dev, phy, reg, val) 440 struct device *dev; 441 int phy, reg, val; 442{ 443 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 444 int i; 445 446 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 447 phy, reg, val)); 448 449 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 450 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 451 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 452 453 for (i = 0; i < SK_TIMEOUT; i++) { 454 DELAY(1); 455 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 456 break; 457 } 458} 459 460void 461sk_marv_miibus_statchg(dev) 462 struct device *dev; 463{ 464 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 465 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 466} 467 468#define HASH_BITS 6 469 470u_int32_t 471sk_xmac_hash(caddr_t addr) 472{ 473 u_int32_t crc; 474 475 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 476 return (~crc & ((1 << HASH_BITS) - 1)); 477} 478 479u_int32_t 480sk_yukon_hash(caddr_t addr) 481{ 482 u_int32_t crc; 483 484 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 485 return (crc & ((1 << HASH_BITS) - 1)); 486} 487 488void 489sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 490{ 491 int base = XM_RXFILT_ENTRY(slot); 492 493 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 494 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 495 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 496} 497 498void 499sk_setmulti(struct sk_if_softc *sc_if) 500{ 501 struct sk_softc *sc = sc_if->sk_softc; 502 struct ifnet *ifp= &sc_if->arpcom.ac_if; 503 u_int32_t hashes[2] = { 0, 0 }; 504 int h, i; 505 struct arpcom *ac = &sc_if->arpcom; 506 struct ether_multi *enm; 507 struct ether_multistep step; 508 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 509 510 /* First, zot all the existing filters. */ 511 switch(sc->sk_type) { 512 case SK_GENESIS: 513 for (i = 1; i < XM_RXFILT_MAX; i++) 514 sk_setfilt(sc_if, (caddr_t)&dummy, i); 515 516 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 517 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 518 break; 519 case SK_YUKON: 520 case SK_YUKON_LITE: 521 case SK_YUKON_LP: 522 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 523 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 524 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 525 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 526 break; 527 } 528 529 /* Now program new ones. */ 530allmulti: 531 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 532 hashes[0] = 0xFFFFFFFF; 533 hashes[1] = 0xFFFFFFFF; 534 } else { 535 i = 1; 536 /* First find the tail of the list. */ 537 ETHER_FIRST_MULTI(step, ac, enm); 538 while (enm != NULL) { 539 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 540 ETHER_ADDR_LEN)) { 541 ifp->if_flags |= IFF_ALLMULTI; 542 goto allmulti; 543 } 544 /* 545 * Program the first XM_RXFILT_MAX multicast groups 546 * into the perfect filter. For all others, 547 * use the hash table. 548 */ 549 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 550 sk_setfilt(sc_if, enm->enm_addrlo, i); 551 i++; 552 } 553 else { 554 switch(sc->sk_type) { 555 case SK_GENESIS: 556 h = sk_xmac_hash(enm->enm_addrlo); 557 break; 558 559 case SK_YUKON: 560 case SK_YUKON_LITE: 561 case SK_YUKON_LP: 562 h = sk_yukon_hash(enm->enm_addrlo); 563 break; 564 } 565 if (h < 32) 566 hashes[0] |= (1 << h); 567 else 568 hashes[1] |= (1 << (h - 32)); 569 } 570 571 ETHER_NEXT_MULTI(step, enm); 572 } 573 } 574 575 switch(sc->sk_type) { 576 case SK_GENESIS: 577 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 578 XM_MODE_RX_USE_PERFECT); 579 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 580 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 581 break; 582 case SK_YUKON: 583 case SK_YUKON_LITE: 584 case SK_YUKON_LP: 585 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 586 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 587 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 588 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 589 break; 590 } 591} 592 593int 594sk_init_rx_ring(struct sk_if_softc *sc_if) 595{ 596 struct sk_chain_data *cd = &sc_if->sk_cdata; 597 struct sk_ring_data *rd = sc_if->sk_rdata; 598 int i; 599 600 bzero((char *)rd->sk_rx_ring, 601 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 602 603 for (i = 0; i < SK_RX_RING_CNT; i++) { 604 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 605 if (i == (SK_RX_RING_CNT - 1)) { 606 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 607 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 608 } else { 609 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 610 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 611 } 612 rd->sk_rx_ring[i].sk_csum1_start = ETHER_HDR_LEN; 613 rd->sk_rx_ring[i].sk_csum2_start = ETHER_HDR_LEN + 614 sizeof(struct ip); 615 } 616 617 for (i = 0; i < SK_RX_RING_CNT; i++) { 618 if (sk_newbuf(sc_if, i, NULL, 619 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 620 printf("%s: failed alloc of %dth mbuf\n", 621 sc_if->sk_dev.dv_xname, i); 622 return(ENOBUFS); 623 } 624 } 625 626 sc_if->sk_cdata.sk_rx_prod = 0; 627 sc_if->sk_cdata.sk_rx_cons = 0; 628 629 return(0); 630} 631 632int 633sk_init_tx_ring(struct sk_if_softc *sc_if) 634{ 635 struct sk_softc *sc = sc_if->sk_softc; 636 struct sk_chain_data *cd = &sc_if->sk_cdata; 637 struct sk_ring_data *rd = sc_if->sk_rdata; 638 bus_dmamap_t dmamap; 639 struct sk_txmap_entry *entry; 640 int i; 641 642 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 643 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 644 645 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 646 for (i = 0; i < SK_TX_RING_CNT; i++) { 647 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 648 if (i == (SK_TX_RING_CNT - 1)) { 649 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 650 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 651 } else { 652 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 653 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 654 } 655 656 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 657 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 658 return (ENOBUFS); 659 660 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 661 if (!entry) { 662 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 663 return (ENOBUFS); 664 } 665 entry->dmamap = dmamap; 666 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 667 } 668 669 sc_if->sk_cdata.sk_tx_prod = 0; 670 sc_if->sk_cdata.sk_tx_cons = 0; 671 sc_if->sk_cdata.sk_tx_cnt = 0; 672 673 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 674 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 675 676 return (0); 677} 678 679int 680sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 681 bus_dmamap_t dmamap) 682{ 683 struct mbuf *m_new = NULL; 684 struct sk_chain *c; 685 struct sk_rx_desc *r; 686 687 if (m == NULL) { 688 caddr_t buf = NULL; 689 690 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 691 if (m_new == NULL) 692 return(ENOBUFS); 693 694 /* Allocate the jumbo buffer */ 695 buf = sk_jalloc(sc_if); 696 if (buf == NULL) { 697 m_freem(m_new); 698 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 699 "dropped!\n", sc_if->arpcom.ac_if.if_xname)); 700 return(ENOBUFS); 701 } 702 703 /* Attach the buffer to the mbuf */ 704 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 705 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 706 } else { 707 /* 708 * We're re-using a previously allocated mbuf; 709 * be sure to re-init pointers and lengths to 710 * default values. 711 */ 712 m_new = m; 713 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 714 m_new->m_data = m_new->m_ext.ext_buf; 715 } 716 m_adj(m_new, ETHER_ALIGN); 717 718 c = &sc_if->sk_cdata.sk_rx_chain[i]; 719 r = c->sk_desc; 720 c->sk_mbuf = m_new; 721 r->sk_data_lo = dmamap->dm_segs[0].ds_addr + 722 (((vaddr_t)m_new->m_data 723 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf)); 724 r->sk_ctl = SK_JLEN | SK_RXSTAT; 725 726 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 727 728 return(0); 729} 730 731/* 732 * Memory management for jumbo frames. 733 */ 734 735int 736sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 737{ 738 struct sk_softc *sc = sc_if->sk_softc; 739 caddr_t ptr, kva; 740 bus_dma_segment_t seg; 741 int i, rseg, state, error; 742 struct sk_jpool_entry *entry; 743 744 state = error = 0; 745 746 /* Grab a big chunk o' storage. */ 747 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 748 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 749 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 750 return (ENOBUFS); 751 } 752 753 state = 1; 754 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, &kva, 755 BUS_DMA_NOWAIT)) { 756 printf("%s: can't map dma buffers (%d bytes)\n", 757 sc->sk_dev.dv_xname, SK_JMEM); 758 error = ENOBUFS; 759 goto out; 760 } 761 762 state = 2; 763 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 764 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 765 printf("%s: can't create dma map\n", sc->sk_dev.dv_xname); 766 error = ENOBUFS; 767 goto out; 768 } 769 770 state = 3; 771 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 772 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 773 printf("%s: can't load dma map\n", sc->sk_dev.dv_xname); 774 error = ENOBUFS; 775 goto out; 776 } 777 778 state = 4; 779 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 780 DPRINTFN(1,("sk_jumbo_buf = 0x%08X\n", sc_if->sk_cdata.sk_jumbo_buf)); 781 782 LIST_INIT(&sc_if->sk_jfree_listhead); 783 LIST_INIT(&sc_if->sk_jinuse_listhead); 784 785 /* 786 * Now divide it up into 9K pieces and save the addresses 787 * in an array. 788 */ 789 ptr = sc_if->sk_cdata.sk_jumbo_buf; 790 for (i = 0; i < SK_JSLOTS; i++) { 791 sc_if->sk_cdata.sk_jslots[i] = ptr; 792 ptr += SK_JLEN; 793 entry = malloc(sizeof(struct sk_jpool_entry), 794 M_DEVBUF, M_NOWAIT); 795 if (entry == NULL) { 796 printf("%s: no memory for jumbo buffer queue!\n", 797 sc->sk_dev.dv_xname); 798 error = ENOBUFS; 799 goto out; 800 } 801 entry->slot = i; 802 if (i) 803 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 804 entry, jpool_entries); 805 else 806 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 807 entry, jpool_entries); 808 } 809out: 810 if (error != 0) { 811 switch (state) { 812 case 4: 813 bus_dmamap_unload(sc->sc_dmatag, 814 sc_if->sk_cdata.sk_rx_jumbo_map); 815 case 3: 816 bus_dmamap_destroy(sc->sc_dmatag, 817 sc_if->sk_cdata.sk_rx_jumbo_map); 818 case 2: 819 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 820 case 1: 821 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 822 break; 823 default: 824 break; 825 } 826 } 827 828 return (error); 829} 830 831/* 832 * Allocate a jumbo buffer. 833 */ 834void * 835sk_jalloc(struct sk_if_softc *sc_if) 836{ 837 struct sk_jpool_entry *entry; 838 839 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 840 841 if (entry == NULL) 842 return (NULL); 843 844 LIST_REMOVE(entry, jpool_entries); 845 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 846 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 847} 848 849/* 850 * Release a jumbo buffer. 851 */ 852void 853sk_jfree(caddr_t buf, u_int size, void *arg) 854{ 855 struct sk_jpool_entry *entry; 856 struct sk_if_softc *sc; 857 int i; 858 859 /* Extract the softc struct pointer. */ 860 sc = (struct sk_if_softc *)arg; 861 862 if (sc == NULL) 863 panic("sk_jfree: can't find softc pointer!"); 864 865 /* calculate the slot this buffer belongs to */ 866 867 i = ((vaddr_t)buf 868 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 869 870 if ((i < 0) || (i >= SK_JSLOTS)) 871 panic("sk_jfree: asked to free buffer that we don't manage!"); 872 873 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 874 if (entry == NULL) 875 panic("sk_jfree: buffer not in use!"); 876 entry->slot = i; 877 LIST_REMOVE(entry, jpool_entries); 878 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 879} 880 881/* 882 * Set media options. 883 */ 884int 885sk_ifmedia_upd(struct ifnet *ifp) 886{ 887 struct sk_if_softc *sc_if = ifp->if_softc; 888 889 sk_init(sc_if); 890 mii_mediachg(&sc_if->sk_mii); 891 return(0); 892} 893 894/* 895 * Report current media status. 896 */ 897void 898sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 899{ 900 struct sk_if_softc *sc_if = ifp->if_softc; 901 902 mii_pollstat(&sc_if->sk_mii); 903 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 904 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 905} 906 907int 908sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 909{ 910 struct sk_if_softc *sc_if = ifp->if_softc; 911 struct sk_softc *sc = sc_if->sk_softc; 912 struct ifreq *ifr = (struct ifreq *) data; 913 struct ifaddr *ifa = (struct ifaddr *) data; 914 struct mii_data *mii; 915 int s, error = 0; 916 917 s = splimp(); 918 919 if ((error = ether_ioctl(ifp, &sc_if->arpcom, command, data)) > 0) { 920 splx(s); 921 return error; 922 } 923 924 switch(command) { 925 case SIOCSIFADDR: 926 ifp->if_flags |= IFF_UP; 927 switch (ifa->ifa_addr->sa_family) { 928#ifdef INET 929 case AF_INET: 930 sk_init(sc_if); 931 arp_ifinit(&sc_if->arpcom, ifa); 932 break; 933#endif /* INET */ 934 default: 935 sk_init(sc_if); 936 break; 937 } 938 break; 939 case SIOCSIFMTU: 940 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 941 error = EINVAL; 942 else if (ifp->if_mtu != ifr->ifr_mtu) 943 ifp->if_mtu = ifr->ifr_mtu; 944 break; 945 case SIOCSIFFLAGS: 946 if (ifp->if_flags & IFF_UP) { 947 if (ifp->if_flags & IFF_RUNNING && 948 ifp->if_flags & IFF_PROMISC && 949 !(sc_if->sk_if_flags & IFF_PROMISC)) { 950 switch(sc->sk_type) { 951 case SK_GENESIS: 952 SK_XM_SETBIT_4(sc_if, XM_MODE, 953 XM_MODE_RX_PROMISC); 954 break; 955 case SK_YUKON: 956 case SK_YUKON_LITE: 957 case SK_YUKON_LP: 958 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 959 YU_RCR_UFLEN | YU_RCR_MUFLEN); 960 break; 961 } 962 sk_setmulti(sc_if); 963 } else if (ifp->if_flags & IFF_RUNNING && 964 !(ifp->if_flags & IFF_PROMISC) && 965 sc_if->sk_if_flags & IFF_PROMISC) { 966 switch(sc->sk_type) { 967 case SK_GENESIS: 968 SK_XM_CLRBIT_4(sc_if, XM_MODE, 969 XM_MODE_RX_PROMISC); 970 break; 971 case SK_YUKON: 972 case SK_YUKON_LITE: 973 case SK_YUKON_LP: 974 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 975 YU_RCR_UFLEN | YU_RCR_MUFLEN); 976 break; 977 } 978 979 sk_setmulti(sc_if); 980 } else 981 sk_init(sc_if); 982 } else { 983 if (ifp->if_flags & IFF_RUNNING) 984 sk_stop(sc_if); 985 } 986 sc_if->sk_if_flags = ifp->if_flags; 987 error = 0; 988 break; 989 case SIOCADDMULTI: 990 case SIOCDELMULTI: 991 error = (command == SIOCADDMULTI) ? 992 ether_addmulti(ifr, &sc_if->arpcom) : 993 ether_delmulti(ifr, &sc_if->arpcom); 994 995 if (error == ENETRESET) { 996 /* 997 * Multicast list has changed; set the hardware 998 * filter accordingly. 999 */ 1000 if (ifp->if_flags & IFF_RUNNING) 1001 sk_setmulti(sc_if); 1002 error = 0; 1003 } 1004 break; 1005 case SIOCGIFMEDIA: 1006 case SIOCSIFMEDIA: 1007 mii = &sc_if->sk_mii; 1008 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1009 break; 1010 default: 1011 error = EINVAL; 1012 break; 1013 } 1014 1015 splx(s); 1016 1017 return(error); 1018} 1019 1020/* 1021 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1022 * IDs against our list and return a device name if we find a match. 1023 */ 1024int 1025skc_probe(struct device *parent, void *match, void *aux) 1026{ 1027 struct pci_attach_args *pa = aux; 1028 pci_chipset_tag_t pc = pa->pa_pc; 1029 pcireg_t subid; 1030 1031 subid = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1032 1033 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1034 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1035 subid == SK_LINKSYS_EG1032_SUBID) 1036 return (1); 1037 1038 return (pci_matchbyid((struct pci_attach_args *)aux, skc_devices, 1039 sizeof(skc_devices)/sizeof(skc_devices[0]))); 1040} 1041 1042/* 1043 * Force the GEnesis into reset, then bring it out of reset. 1044 */ 1045void sk_reset(struct sk_softc *sc) 1046{ 1047 DPRINTFN(2, ("sk_reset\n")); 1048 1049 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1050 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1051 if (SK_YUKON_FAMILY(sc->sk_type)) 1052 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1053 1054 DELAY(1000); 1055 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1056 DELAY(2); 1057 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1058 if (SK_YUKON_FAMILY(sc->sk_type)) 1059 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1060 1061 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1062 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1063 CSR_READ_2(sc, SK_LINK_CTRL))); 1064 1065 if (sc->sk_type == SK_GENESIS) { 1066 /* Configure packet arbiter */ 1067 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1068 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1069 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1070 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1071 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1072 } 1073 1074 /* Enable RAM interface */ 1075 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1076 1077 /* 1078 * Configure interrupt moderation. The moderation timer 1079 * defers interrupts specified in the interrupt moderation 1080 * timer mask based on the timeout specified in the interrupt 1081 * moderation timer init register. Each bit in the timer 1082 * register represents 18.825ns, so to specify a timeout in 1083 * microseconds, we have to multiply by 54. 1084 */ 1085 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(100)); 1086 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1087 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1088 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1089} 1090 1091int 1092sk_probe(struct device *parent, void *match, void *aux) 1093{ 1094 struct skc_attach_args *sa = aux; 1095 1096 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1097 return(0); 1098 1099 switch (sa->skc_type) { 1100 case SK_GENESIS: 1101 case SK_YUKON: 1102 case SK_YUKON_LITE: 1103 case SK_YUKON_LP: 1104 return (1); 1105 } 1106 1107 return (0); 1108} 1109 1110/* 1111 * Each XMAC chip is attached as a separate logical IP interface. 1112 * Single port cards will have only one logical interface of course. 1113 */ 1114void 1115sk_attach(struct device *parent, struct device *self, void *aux) 1116{ 1117 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1118 struct sk_softc *sc = (struct sk_softc *)parent; 1119 struct skc_attach_args *sa = aux; 1120 struct ifnet *ifp; 1121 caddr_t kva; 1122 bus_dma_segment_t seg; 1123 int i, rseg; 1124 1125 sc_if->sk_port = sa->skc_port; 1126 sc_if->sk_softc = sc; 1127 sc->sk_if[sa->skc_port] = sc_if; 1128 1129 if (sa->skc_port == SK_PORT_A) 1130 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1131 if (sa->skc_port == SK_PORT_B) 1132 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1133 1134 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1135 1136 /* 1137 * Get station address for this interface. Note that 1138 * dual port cards actually come with three station 1139 * addresses: one for each port, plus an extra. The 1140 * extra one is used by the SysKonnect driver software 1141 * as a 'virtual' station address for when both ports 1142 * are operating in failover mode. Currently we don't 1143 * use this extra address. 1144 */ 1145 for (i = 0; i < ETHER_ADDR_LEN; i++) 1146 sc_if->arpcom.ac_enaddr[i] = 1147 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1148 1149 1150 printf(": address %s\n", 1151 ether_sprintf(sc_if->arpcom.ac_enaddr)); 1152 1153 /* 1154 * Set up RAM buffer addresses. The NIC will have a certain 1155 * amount of SRAM on it, somewhere between 512K and 2MB. We 1156 * need to divide this up a) between the transmitter and 1157 * receiver and b) between the two XMACs, if this is a 1158 * dual port NIC. Our algorithm is to divide up the memory 1159 * evenly so that everyone gets a fair share. 1160 */ 1161 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1162 u_int32_t chunk, val; 1163 1164 chunk = sc->sk_ramsize / 2; 1165 val = sc->sk_rboff / sizeof(u_int64_t); 1166 sc_if->sk_rx_ramstart = val; 1167 val += (chunk / sizeof(u_int64_t)); 1168 sc_if->sk_rx_ramend = val - 1; 1169 sc_if->sk_tx_ramstart = val; 1170 val += (chunk / sizeof(u_int64_t)); 1171 sc_if->sk_tx_ramend = val - 1; 1172 } else { 1173 u_int32_t chunk, val; 1174 1175 chunk = sc->sk_ramsize / 4; 1176 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1177 sizeof(u_int64_t); 1178 sc_if->sk_rx_ramstart = val; 1179 val += (chunk / sizeof(u_int64_t)); 1180 sc_if->sk_rx_ramend = val - 1; 1181 sc_if->sk_tx_ramstart = val; 1182 val += (chunk / sizeof(u_int64_t)); 1183 sc_if->sk_tx_ramend = val - 1; 1184 } 1185 1186 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1187 " tx_ramstart=%#x tx_ramend=%#x\n", 1188 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1189 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1190 1191 /* Read and save PHY type and set PHY address */ 1192 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1193 switch (sc_if->sk_phytype) { 1194 case SK_PHYTYPE_XMAC: 1195 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1196 break; 1197 case SK_PHYTYPE_BCOM: 1198 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1199 break; 1200 case SK_PHYTYPE_MARV_COPPER: 1201 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1202 break; 1203 default: 1204 printf("%s: unsupported PHY type: %d\n", 1205 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1206 return; 1207 } 1208 1209 /* Allocate the descriptor queues. */ 1210 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1211 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1212 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 1213 goto fail; 1214 } 1215 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1216 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1217 printf("%s: can't map dma buffers (%d bytes)\n", 1218 sc_if->sk_dev.dv_xname, sizeof(struct sk_ring_data)); 1219 goto fail_1; 1220 } 1221 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1222 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1223 &sc_if->sk_ring_map)) { 1224 printf("%s: can't create dma map\n", sc_if->sk_dev.dv_xname); 1225 goto fail_2; 1226 } 1227 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1228 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1229 printf("%s: can't load dma map\n", sc_if->sk_dev.dv_xname); 1230 goto fail_3; 1231 } 1232 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1233 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1234 1235 /* Try to allocate memory for jumbo buffers. */ 1236 if (sk_alloc_jumbo_mem(sc_if)) { 1237 printf("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1238 goto fail_3; 1239 } 1240 1241 ifp = &sc_if->arpcom.ac_if; 1242 ifp->if_softc = sc_if; 1243 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1244 ifp->if_ioctl = sk_ioctl; 1245 ifp->if_start = sk_start; 1246 ifp->if_watchdog = sk_watchdog; 1247 ifp->if_baudrate = 1000000000; 1248 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1249 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1250 IFQ_SET_READY(&ifp->if_snd); 1251 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1252 1253 /* 1254 * Do miibus setup. 1255 */ 1256 switch (sc->sk_type) { 1257 case SK_GENESIS: 1258 sk_init_xmac(sc_if); 1259 break; 1260 case SK_YUKON: 1261 case SK_YUKON_LITE: 1262 case SK_YUKON_LP: 1263 sk_init_yukon(sc_if); 1264 break; 1265 default: 1266 printf("%s: unknown device type %d\n", sc->sk_dev.dv_xname, 1267 sc->sk_type); 1268 /* dealloc jumbo on error */ 1269 goto fail_3; 1270 } 1271 1272 DPRINTFN(2, ("sk_attach: 1\n")); 1273 1274 sc_if->sk_mii.mii_ifp = ifp; 1275 switch (sc->sk_type) { 1276 case SK_GENESIS: 1277 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1278 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1279 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1280 break; 1281 case SK_YUKON: 1282 case SK_YUKON_LITE: 1283 case SK_YUKON_LP: 1284 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1285 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1286 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1287 break; 1288 } 1289 1290 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1291 sk_ifmedia_upd, sk_ifmedia_sts); 1292 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1293 MII_OFFSET_ANY, 0); 1294 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1295 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1296 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1297 0, NULL); 1298 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1299 } 1300 else 1301 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1302 1303 timeout_set(&sc_if->sk_tick_ch, sk_tick, sc_if); 1304 timeout_add(&sc_if->sk_tick_ch, hz); 1305 1306 DPRINTFN(2, ("sk_attach: 1\n")); 1307 1308 /* 1309 * Call MI attach routines. 1310 */ 1311 if_attach(ifp); 1312 ether_ifattach(ifp); 1313 1314 DPRINTFN(2, ("sk_attach: end\n")); 1315 1316 return; 1317 1318fail_3: 1319 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1320fail_2: 1321 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct sk_ring_data)); 1322fail_1: 1323 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1324fail: 1325 sc->sk_if[sa->skc_port] = NULL; 1326} 1327 1328int 1329skcprint(void *aux, const char *pnp) 1330{ 1331 struct skc_attach_args *sa = aux; 1332 1333 if (pnp) 1334 printf("sk port %c at %s", 1335 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1336 else 1337 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1338 return (UNCONF); 1339} 1340 1341/* 1342 * Attach the interface. Allocate softc structures, do ifmedia 1343 * setup and ethernet/BPF attach. 1344 */ 1345void 1346skc_attach(struct device *parent, struct device *self, void *aux) 1347{ 1348 struct sk_softc *sc = (struct sk_softc *)self; 1349 struct pci_attach_args *pa = aux; 1350 struct skc_attach_args skca; 1351 pci_chipset_tag_t pc = pa->pa_pc; 1352 pcireg_t command, memtype; 1353 pci_intr_handle_t ih; 1354 const char *intrstr = NULL; 1355 bus_size_t size; 1356 u_int8_t skrs; 1357 char *revstr = NULL; 1358 1359 DPRINTFN(2, ("begin skc_attach\n")); 1360 1361 /* 1362 * Handle power management nonsense. 1363 */ 1364 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1365 1366 if (command == 0x01) { 1367 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1368 if (command & SK_PSTATE_MASK) { 1369 u_int32_t iobase, membase, irq; 1370 1371 /* Save important PCI config data. */ 1372 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1373 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1374 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1375 1376 /* Reset the power state. */ 1377 printf("%s chip is in D%d power mode " 1378 "-- setting to D0\n", sc->sk_dev.dv_xname, 1379 command & SK_PSTATE_MASK); 1380 command &= 0xFFFFFFFC; 1381 pci_conf_write(pc, pa->pa_tag, 1382 SK_PCI_PWRMGMTCTRL, command); 1383 1384 /* Restore PCI config data. */ 1385 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1386 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1387 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1388 } 1389 } 1390 1391 /* 1392 * Map control/status registers. 1393 */ 1394 1395#ifdef SK_USEIOSPACE 1396 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1397 &sc->sk_btag, &sc->sk_bhandle, NULL, &size, 0)) { 1398 printf(": can't map i/o space\n"); 1399 return; 1400 } 1401#else 1402 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1403 switch (memtype) { 1404 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1405 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1406 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1407 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1408 NULL, &size, 0) == 0) 1409 break; 1410 default: 1411 printf(": can't map mem space\n"); 1412 return; 1413 } 1414#endif 1415 sc->sc_dmatag = pa->pa_dmat; 1416 1417 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1418 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1419 1420 /* bail out here if chip is not recognized */ 1421 if (sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1422 printf("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1423 goto fail_1; 1424 } 1425 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1426 1427 /* Allocate interrupt */ 1428 if (pci_intr_map(pa, &ih)) { 1429 printf(": couldn't map interrupt\n"); 1430 goto fail_1; 1431 } 1432 1433 intrstr = pci_intr_string(pc, ih); 1434 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc, 1435 self->dv_xname); 1436 if (sc->sk_intrhand == NULL) { 1437 printf(": couldn't establish interrupt"); 1438 if (intrstr != NULL) 1439 printf(" at %s", intrstr); 1440 printf("\n"); 1441 goto fail_1; 1442 } 1443 printf(": %s\n", intrstr); 1444 1445 /* Reset the adapter. */ 1446 sk_reset(sc); 1447 1448 skrs = sk_win_read_1(sc, SK_EPROM0); 1449 if (sc->sk_type == SK_GENESIS) { 1450 /* Read and save RAM size and RAMbuffer offset */ 1451 switch(skrs) { 1452 case SK_RAMSIZE_512K_64: 1453 sc->sk_ramsize = 0x80000; 1454 sc->sk_rboff = SK_RBOFF_0; 1455 break; 1456 case SK_RAMSIZE_1024K_64: 1457 sc->sk_ramsize = 0x100000; 1458 sc->sk_rboff = SK_RBOFF_80000; 1459 break; 1460 case SK_RAMSIZE_1024K_128: 1461 sc->sk_ramsize = 0x100000; 1462 sc->sk_rboff = SK_RBOFF_0; 1463 break; 1464 case SK_RAMSIZE_2048K_128: 1465 sc->sk_ramsize = 0x200000; 1466 sc->sk_rboff = SK_RBOFF_0; 1467 break; 1468 default: 1469 printf("%s: unknown ram size: %d\n", 1470 sc->sk_dev.dv_xname, skrs); 1471 goto fail_2; 1472 break; 1473 } 1474 } else { 1475 if (skrs == 0x00) 1476 sc->sk_ramsize = 0x20000; 1477 else 1478 sc->sk_ramsize = skrs * (1<<12); 1479 sc->sk_rboff = SK_RBOFF_0; 1480 } 1481 1482 DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n", 1483 sc->sk_ramsize, sc->sk_ramsize / 1024, 1484 sc->sk_rboff)); 1485 1486 /* Read and save physical media type */ 1487 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1488 case SK_PMD_1000BASESX: 1489 sc->sk_pmd = IFM_1000_SX; 1490 break; 1491 case SK_PMD_1000BASELX: 1492 sc->sk_pmd = IFM_1000_LX; 1493 break; 1494 case SK_PMD_1000BASECX: 1495 sc->sk_pmd = IFM_1000_CX; 1496 break; 1497 case SK_PMD_1000BASETX: 1498 sc->sk_pmd = IFM_1000_T; 1499 break; 1500 default: 1501 printf("%s: unknown media type: 0x%x\n", 1502 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1503 goto fail_2; 1504 } 1505 1506 switch (sc->sk_type) { 1507 case SK_GENESIS: 1508 sc->sk_name = "SysKonnect GEnesis"; 1509 break; 1510 case SK_YUKON: 1511 sc->sk_name = "Marvell Yukon"; 1512 break; 1513 case SK_YUKON_LITE: 1514 sc->sk_name = "Marvell Yukon Lite"; 1515 break; 1516 case SK_YUKON_LP: 1517 sc->sk_name = "Marvell Yukon LP"; 1518 break; 1519 case SK_YUKON_XL: 1520 sc->sk_name = "Marvell Yukon-2 XL"; 1521 break; 1522 case SK_YUKON_EC: 1523 sc->sk_name = "Marvell Yukon-2 EC"; 1524 break; 1525 case SK_YUKON_FE: 1526 sc->sk_name = "Marvell Yukon-2 FE"; 1527 break; 1528 default: 1529 sc->sk_name = "Marvell Yukon (Unknown)"; 1530 } 1531 1532 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1533 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1534 uint32_t flashaddr; 1535 uint8_t testbyte; 1536 1537 flashaddr = sk_win_read_4(sc, SK_EP_ADDR); 1538 1539 /* test Flash-Address Register */ 1540 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff); 1541 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1542 1543 if (testbyte != 0) { 1544 /* This is a Yukon Lite Rev A0 */ 1545 sc->sk_type = SK_YUKON_LITE; 1546 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1547 /* restore Flash-Address Register */ 1548 sk_win_write_4(sc, SK_EP_ADDR, flashaddr); 1549 } 1550 } 1551 1552 if (sc->sk_type == SK_YUKON_LITE) { 1553 switch (sc->sk_rev) { 1554 case SK_YUKON_LITE_REV_A0: 1555 revstr = "A0"; 1556 break; 1557 case SK_YUKON_LITE_REV_A1: 1558 revstr = "A1"; 1559 break; 1560 case SK_YUKON_LITE_REV_A3: 1561 revstr = "A3"; 1562 break; 1563 default: 1564 ; 1565 } 1566 } 1567 1568 /* Announce the product name. */ 1569 printf("%s: %s", sc->sk_dev.dv_xname, sc->sk_name); 1570 if (revstr != NULL) 1571 printf(" rev. %s", revstr); 1572 printf(" (0x%x)\n", sc->sk_rev); 1573 1574 skca.skc_port = SK_PORT_A; 1575 skca.skc_type = sc->sk_type; 1576 skca.skc_rev = sc->sk_rev; 1577 (void)config_found(&sc->sk_dev, &skca, skcprint); 1578 1579 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1580 skca.skc_port = SK_PORT_B; 1581 skca.skc_type = sc->sk_type; 1582 skca.skc_rev = sc->sk_rev; 1583 (void)config_found(&sc->sk_dev, &skca, skcprint); 1584 } 1585 1586 /* Turn on the 'driver is loaded' LED. */ 1587 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1588 1589 return; 1590 1591fail_2: 1592 pci_intr_disestablish(pc, sc->sk_intrhand); 1593fail_1: 1594 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1595} 1596 1597int 1598sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1599{ 1600 struct sk_softc *sc = sc_if->sk_softc; 1601 struct sk_tx_desc *f = NULL; 1602 u_int32_t frag, cur, cnt = 0; 1603 int i; 1604 struct sk_txmap_entry *entry; 1605 bus_dmamap_t txmap; 1606 1607 DPRINTFN(2, ("sk_encap\n")); 1608 1609 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1610 if (entry == NULL) { 1611 DPRINTFN(2, ("sk_encap: no txmap available\n")); 1612 return ENOBUFS; 1613 } 1614 txmap = entry->dmamap; 1615 1616 cur = frag = *txidx; 1617 1618#ifdef SK_DEBUG 1619 if (skdebug >= 2) 1620 sk_dump_mbuf(m_head); 1621#endif 1622 1623 /* 1624 * Start packing the mbufs in this chain into 1625 * the fragment pointers. Stop when we run out 1626 * of fragments or hit the end of the mbuf chain. 1627 */ 1628 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1629 BUS_DMA_NOWAIT)) { 1630 DPRINTFN(2, ("sk_encap: dmamap failed\n")); 1631 return(ENOBUFS); 1632 } 1633 1634 DPRINTFN(2, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1635 1636 /* Sync the DMA map. */ 1637 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1638 BUS_DMASYNC_PREWRITE); 1639 1640 for (i = 0; i < txmap->dm_nsegs; i++) { 1641 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1642 DPRINTFN(2, ("sk_encap: too few descriptors free\n")); 1643 return(ENOBUFS); 1644 } 1645 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1646 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1647 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1648 if (cnt == 0) 1649 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1650 else 1651 f->sk_ctl |= SK_TXCTL_OWN; 1652 1653 cur = frag; 1654 SK_INC(frag, SK_TX_RING_CNT); 1655 cnt++; 1656 } 1657 1658 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1659 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1660 1661 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1662 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1663 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1664 1665 /* Sync descriptors before handing to chip */ 1666 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1667 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1668 1669 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1670 1671 /* Sync first descriptor to hand it off */ 1672 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1673 1674 sc_if->sk_cdata.sk_tx_cnt += cnt; 1675 1676#ifdef SK_DEBUG 1677 if (skdebug >= 2) { 1678 struct sk_tx_desc *desc; 1679 u_int32_t idx; 1680 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1681 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1682 sk_dump_txdesc(desc, idx); 1683 } 1684 } 1685#endif 1686 1687 *txidx = frag; 1688 1689 DPRINTFN(2, ("sk_encap: completed successfully\n")); 1690 1691 return(0); 1692} 1693 1694void 1695sk_start(struct ifnet *ifp) 1696{ 1697 struct sk_if_softc *sc_if = ifp->if_softc; 1698 struct sk_softc *sc = sc_if->sk_softc; 1699 struct mbuf *m_head = NULL; 1700 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1701 int pkts = 0; 1702 1703 DPRINTFN(2, ("sk_start\n")); 1704 1705 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1706 IFQ_POLL(&ifp->if_snd, m_head); 1707 if (m_head == NULL) 1708 break; 1709 1710 /* 1711 * Pack the data into the transmit ring. If we 1712 * don't have room, set the OACTIVE flag and wait 1713 * for the NIC to drain the ring. 1714 */ 1715 if (sk_encap(sc_if, m_head, &idx)) { 1716 ifp->if_flags |= IFF_OACTIVE; 1717 break; 1718 } 1719 1720 /* now we are committed to transmit the packet */ 1721 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1722 pkts++; 1723 1724 /* 1725 * If there's a BPF listener, bounce a copy of this frame 1726 * to him. 1727 */ 1728#if NBPFILTER > 0 1729 if (ifp->if_bpf) 1730 bpf_mtap(ifp->if_bpf, m_head); 1731#endif 1732 } 1733 if (pkts == 0) 1734 return; 1735 1736 /* Transmit */ 1737 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1738 sc_if->sk_cdata.sk_tx_prod = idx; 1739 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1740 1741 /* Set a timeout in case the chip goes out to lunch. */ 1742 ifp->if_timer = 5; 1743 } 1744} 1745 1746 1747void 1748sk_watchdog(struct ifnet *ifp) 1749{ 1750 struct sk_if_softc *sc_if = ifp->if_softc; 1751 1752 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1753 ifp->if_flags &= ~IFF_RUNNING; 1754 sk_init(sc_if); 1755} 1756 1757void 1758sk_shutdown(void *v) 1759{ 1760 struct sk_softc *sc = v; 1761 1762 DPRINTFN(2, ("sk_shutdown\n")); 1763 1764 /* Turn off the 'driver is loaded' LED. */ 1765 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1766 1767 /* 1768 * Reset the GEnesis controller. Doing this should also 1769 * assert the resets on the attached XMAC(s). 1770 */ 1771 sk_reset(sc); 1772} 1773 1774void 1775sk_rxeof(struct sk_if_softc *sc_if) 1776{ 1777 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1778 struct mbuf *m; 1779 struct sk_chain *cur_rx; 1780 struct sk_rx_desc *cur_desc; 1781 int i, cur, total_len = 0; 1782 u_int32_t rxstat; 1783 bus_dmamap_t dmamap; 1784 u_int16_t csum1, csum2; 1785 1786 DPRINTFN(2, ("sk_rxeof\n")); 1787 1788 i = sc_if->sk_cdata.sk_rx_prod; 1789 1790 for (;;) { 1791 cur = i; 1792 1793 /* Sync the descriptor */ 1794 SK_CDRXSYNC(sc_if, cur, 1795 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1796 1797 if (sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN) { 1798 /* Invalidate the descriptor -- it's not ready yet */ 1799 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 1800 sc_if->sk_cdata.sk_rx_prod = i; 1801 break; 1802 } 1803 1804 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1805 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1806 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1807 1808 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1809 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1810 1811 rxstat = cur_desc->sk_xmac_rxstat; 1812 m = cur_rx->sk_mbuf; 1813 cur_rx->sk_mbuf = NULL; 1814 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1815 1816 csum1 = sc_if->sk_rdata->sk_rx_ring[i].sk_csum1; 1817 csum2 = sc_if->sk_rdata->sk_rx_ring[i].sk_csum2; 1818 1819 SK_INC(i, SK_RX_RING_CNT); 1820 1821 if (rxstat & XM_RXSTAT_ERRFRAME) { 1822 ifp->if_ierrors++; 1823 sk_newbuf(sc_if, cur, m, dmamap); 1824 continue; 1825 } 1826 1827 /* 1828 * Try to allocate a new jumbo buffer. If that 1829 * fails, copy the packet to mbufs and put the 1830 * jumbo buffer back in the ring so it can be 1831 * re-used. If allocating mbufs fails, then we 1832 * have to drop the packet. 1833 */ 1834 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1835 struct mbuf *m0; 1836 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1837 total_len + ETHER_ALIGN, 0, ifp, NULL); 1838 sk_newbuf(sc_if, cur, m, dmamap); 1839 if (m0 == NULL) { 1840 ifp->if_ierrors++; 1841 continue; 1842 } 1843 m_adj(m0, ETHER_ALIGN); 1844 m = m0; 1845 } else { 1846 m->m_pkthdr.rcvif = ifp; 1847 m->m_pkthdr.len = m->m_len = total_len; 1848 } 1849 1850 ifp->if_ipackets++; 1851 1852 sk_rxcsum(ifp, m, csum1, csum2); 1853 1854#if NBPFILTER > 0 1855 if (ifp->if_bpf) 1856 bpf_mtap(ifp->if_bpf, m); 1857#endif 1858 1859 /* pass it on. */ 1860 ether_input_mbuf(ifp, m); 1861 } 1862} 1863 1864void 1865sk_rxcsum(struct ifnet *ifp, struct mbuf *m, const u_int16_t csum1, const u_int16_t csum2) 1866{ 1867 struct ether_header *eh; 1868 struct ip *ip; 1869 u_int8_t *pp; 1870 int hlen, len, plen; 1871 u_int16_t iph_csum, ipo_csum, ipd_csum, csum; 1872 1873 pp = mtod(m, u_int8_t *); 1874 plen = m->m_pkthdr.len; 1875 if (plen < sizeof(*eh)) 1876 return; 1877 eh = (struct ether_header *)pp; 1878 iph_csum = in_cksum_addword(csum1, (~csum2 & 0xffff)); 1879 1880 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1881 u_int16_t *xp = (u_int16_t *)pp; 1882 1883 xp = (u_int16_t *)pp; 1884 if (xp[1] != htons(ETHERTYPE_IP)) 1885 return; 1886 iph_csum = in_cksum_addword(iph_csum, (~xp[0] & 0xffff)); 1887 iph_csum = in_cksum_addword(iph_csum, (~xp[1] & 0xffff)); 1888 xp = (u_int16_t *)(pp + sizeof(struct ip)); 1889 iph_csum = in_cksum_addword(iph_csum, xp[0]); 1890 iph_csum = in_cksum_addword(iph_csum, xp[1]); 1891 pp += EVL_ENCAPLEN; 1892 } else if (eh->ether_type != htons(ETHERTYPE_IP)) 1893 return; 1894 1895 pp += sizeof(*eh); 1896 plen -= sizeof(*eh); 1897 1898 ip = (struct ip *)pp; 1899 1900 if (ip->ip_v != IPVERSION) 1901 return; 1902 1903 hlen = ip->ip_hl << 2; 1904 if (hlen < sizeof(struct ip)) 1905 return; 1906 if (hlen > ntohs(ip->ip_len)) 1907 return; 1908 1909 /* Don't deal with truncated or padded packets. */ 1910 if (plen != ntohs(ip->ip_len)) 1911 return; 1912 1913 len = hlen - sizeof(struct ip); 1914 if (len > 0) { 1915 u_int16_t *p; 1916 1917 p = (u_int16_t *)(ip + 1); 1918 ipo_csum = 0; 1919 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++) 1920 ipo_csum = in_cksum_addword(ipo_csum, *p); 1921 iph_csum = in_cksum_addword(iph_csum, ipo_csum); 1922 ipd_csum = in_cksum_addword(csum2, (~ipo_csum & 0xffff)); 1923 } else 1924 ipd_csum = csum2; 1925 1926 if (iph_csum != 0xffff) 1927 return; 1928 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1929 1930 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1931 return; /* ip frag, we're done for now */ 1932 1933 pp += hlen; 1934 1935 /* Only know checksum protocol for udp/tcp */ 1936 if (ip->ip_p == IPPROTO_UDP) { 1937 struct udphdr *uh = (struct udphdr *)pp; 1938 1939 if (uh->uh_sum == 0) /* udp with no checksum */ 1940 return; 1941 } else if (ip->ip_p != IPPROTO_TCP) 1942 return; 1943 1944 csum = in_cksum_phdr(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1945 htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum); 1946 if (csum == 0xffff) { 1947 m->m_pkthdr.csum_flags |= (ip->ip_p == IPPROTO_TCP) ? 1948 M_TCP_CSUM_IN_OK : M_UDP_CSUM_IN_OK; 1949 } 1950} 1951 1952void 1953sk_txeof(struct sk_if_softc *sc_if) 1954{ 1955 struct sk_softc *sc = sc_if->sk_softc; 1956 struct sk_tx_desc *cur_tx; 1957 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1958 u_int32_t idx; 1959 struct sk_txmap_entry *entry; 1960 1961 DPRINTFN(2, ("sk_txeof\n")); 1962 1963 /* 1964 * Go through our tx ring and free mbufs for those 1965 * frames that have been sent. 1966 */ 1967 idx = sc_if->sk_cdata.sk_tx_cons; 1968 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1969 SK_CDTXSYNC(sc_if, idx, 1, 1970 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1971 1972 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1973#ifdef SK_DEBUG 1974 if (skdebug >= 2) 1975 sk_dump_txdesc(cur_tx, idx); 1976#endif 1977 if (cur_tx->sk_ctl & SK_TXCTL_OWN) { 1978 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 1979 break; 1980 } 1981 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1982 ifp->if_opackets++; 1983 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1984 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1985 1986 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1987 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1988 1989 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1990 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1991 1992 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1993 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1994 link); 1995 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1996 } 1997 sc_if->sk_cdata.sk_tx_cnt--; 1998 SK_INC(idx, SK_TX_RING_CNT); 1999 } 2000 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2001 ifp->if_timer = 0; 2002 else /* nudge chip to keep tx ring moving */ 2003 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2004 2005 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2006 ifp->if_flags &= ~IFF_OACTIVE; 2007 2008 sc_if->sk_cdata.sk_tx_cons = idx; 2009} 2010 2011void 2012sk_tick(void *xsc_if) 2013{ 2014 struct sk_if_softc *sc_if = xsc_if; 2015 struct mii_data *mii = &sc_if->sk_mii; 2016 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2017 int i; 2018 2019 DPRINTFN(2, ("sk_tick\n")); 2020 2021 if (!(ifp->if_flags & IFF_UP)) 2022 return; 2023 2024 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2025 sk_intr_bcom(sc_if); 2026 return; 2027 } 2028 2029 /* 2030 * According to SysKonnect, the correct way to verify that 2031 * the link has come back up is to poll bit 0 of the GPIO 2032 * register three times. This pin has the signal from the 2033 * link sync pin connected to it; if we read the same link 2034 * state 3 times in a row, we know the link is up. 2035 */ 2036 for (i = 0; i < 3; i++) { 2037 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2038 break; 2039 } 2040 2041 if (i != 3) { 2042 timeout_add(&sc_if->sk_tick_ch, hz); 2043 return; 2044 } 2045 2046 /* Turn the GP0 interrupt back on. */ 2047 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2048 SK_XM_READ_2(sc_if, XM_ISR); 2049 mii_tick(mii); 2050 timeout_del(&sc_if->sk_tick_ch); 2051} 2052 2053void 2054sk_intr_bcom(struct sk_if_softc *sc_if) 2055{ 2056 struct mii_data *mii = &sc_if->sk_mii; 2057 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2058 int status; 2059 2060 DPRINTFN(2, ("sk_intr_bcom\n")); 2061 2062 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2063 2064 /* 2065 * Read the PHY interrupt register to make sure 2066 * we clear any pending interrupts. 2067 */ 2068 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2069 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2070 2071 if (!(ifp->if_flags & IFF_RUNNING)) { 2072 sk_init_xmac(sc_if); 2073 return; 2074 } 2075 2076 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2077 int lstat; 2078 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2079 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2080 2081 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2082 mii_mediachg(mii); 2083 /* Turn off the link LED. */ 2084 SK_IF_WRITE_1(sc_if, 0, 2085 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2086 sc_if->sk_link = 0; 2087 } else if (status & BRGPHY_ISR_LNK_CHG) { 2088 sk_xmac_miibus_writereg((struct device *)sc_if, 2089 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2090 mii_tick(mii); 2091 sc_if->sk_link = 1; 2092 /* Turn on the link LED. */ 2093 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2094 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2095 SK_LINKLED_BLINK_OFF); 2096 } else { 2097 mii_tick(mii); 2098 timeout_add(&sc_if->sk_tick_ch, hz); 2099 } 2100 } 2101 2102 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2103} 2104 2105void 2106sk_intr_xmac(struct sk_if_softc *sc_if) 2107{ 2108 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2109 2110 DPRINTFN(2, ("sk_intr_xmac\n")); 2111 2112 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2113 if (status & XM_ISR_GP0_SET) { 2114 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2115 timeout_add(&sc_if->sk_tick_ch, hz); 2116 } 2117 2118 if (status & XM_ISR_AUTONEG_DONE) { 2119 timeout_add(&sc_if->sk_tick_ch, hz); 2120 } 2121 } 2122 2123 if (status & XM_IMR_TX_UNDERRUN) 2124 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2125 2126 if (status & XM_IMR_RX_OVERRUN) 2127 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2128} 2129 2130void 2131sk_intr_yukon(sc_if) 2132 struct sk_if_softc *sc_if; 2133{ 2134 int status; 2135 2136 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2137 2138 DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status)); 2139} 2140 2141int 2142sk_intr(void *xsc) 2143{ 2144 struct sk_softc *sc = xsc; 2145 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2146 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2147 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2148 u_int32_t status; 2149 int claimed = 0; 2150 2151 if (sc_if0 != NULL) 2152 ifp0 = &sc_if0->arpcom.ac_if; 2153 if (sc_if1 != NULL) 2154 ifp1 = &sc_if1->arpcom.ac_if; 2155 2156 for (;;) { 2157 status = CSR_READ_4(sc, SK_ISSR); 2158 DPRINTFN(2, ("sk_intr: status=%#x\n", status)); 2159 2160 if (!(status & sc->sk_intrmask)) 2161 break; 2162 2163 claimed = 1; 2164 2165 /* Handle receive interrupts first. */ 2166 if (status & SK_ISR_RX1_EOF) { 2167 sk_rxeof(sc_if0); 2168 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2169 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2170 } 2171 if (status & SK_ISR_RX2_EOF) { 2172 sk_rxeof(sc_if1); 2173 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2174 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2175 } 2176 2177 /* Then transmit interrupts. */ 2178 if (status & SK_ISR_TX1_S_EOF) { 2179 sk_txeof(sc_if0); 2180 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2181 SK_TXBMU_CLR_IRQ_EOF); 2182 } 2183 if (status & SK_ISR_TX2_S_EOF) { 2184 sk_txeof(sc_if1); 2185 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2186 SK_TXBMU_CLR_IRQ_EOF); 2187 } 2188 2189 /* Then MAC interrupts. */ 2190 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 2191 if (sc->sk_type == SK_GENESIS) 2192 sk_intr_xmac(sc_if0); 2193 else 2194 sk_intr_yukon(sc_if0); 2195 } 2196 2197 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 2198 if (sc->sk_type == SK_GENESIS) 2199 sk_intr_xmac(sc_if1); 2200 else 2201 sk_intr_yukon(sc_if1); 2202 2203 } 2204 2205 if (status & SK_ISR_EXTERNAL_REG) { 2206 if (ifp0 != NULL && 2207 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2208 sk_intr_bcom(sc_if0); 2209 2210 if (ifp1 != NULL && 2211 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2212 sk_intr_bcom(sc_if1); 2213 } 2214 } 2215 2216 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2217 2218 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2219 sk_start(ifp0); 2220 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2221 sk_start(ifp1); 2222 2223 return (claimed); 2224} 2225 2226void 2227sk_init_xmac(struct sk_if_softc *sc_if) 2228{ 2229 struct sk_softc *sc = sc_if->sk_softc; 2230 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2231 struct sk_bcom_hack bhack[] = { 2232 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2233 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2234 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2235 { 0, 0 } }; 2236 2237 DPRINTFN(2, ("sk_init_xmac\n")); 2238 2239 /* Unreset the XMAC. */ 2240 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2241 DELAY(1000); 2242 2243 /* Reset the XMAC's internal state. */ 2244 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2245 2246 /* Save the XMAC II revision */ 2247 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2248 2249 /* 2250 * Perform additional initialization for external PHYs, 2251 * namely for the 1000baseTX cards that use the XMAC's 2252 * GMII mode. 2253 */ 2254 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2255 int i = 0; 2256 u_int32_t val; 2257 2258 /* Take PHY out of reset. */ 2259 val = sk_win_read_4(sc, SK_GPIO); 2260 if (sc_if->sk_port == SK_PORT_A) 2261 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2262 else 2263 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2264 sk_win_write_4(sc, SK_GPIO, val); 2265 2266 /* Enable GMII mode on the XMAC. */ 2267 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2268 2269 sk_xmac_miibus_writereg((struct device *)sc_if, 2270 SK_PHYADDR_BCOM, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2271 DELAY(10000); 2272 sk_xmac_miibus_writereg((struct device *)sc_if, 2273 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2274 2275 /* 2276 * Early versions of the BCM5400 apparently have 2277 * a bug that requires them to have their reserved 2278 * registers initialized to some magic values. I don't 2279 * know what the numbers do, I'm just the messenger. 2280 */ 2281 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2282 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2283 while(bhack[i].reg) { 2284 sk_xmac_miibus_writereg((struct device *)sc_if, 2285 SK_PHYADDR_BCOM, bhack[i].reg, 2286 bhack[i].val); 2287 i++; 2288 } 2289 } 2290 } 2291 2292 /* Set station address */ 2293 SK_XM_WRITE_2(sc_if, XM_PAR0, 2294 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2295 SK_XM_WRITE_2(sc_if, XM_PAR1, 2296 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2297 SK_XM_WRITE_2(sc_if, XM_PAR2, 2298 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2299 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2300 2301 if (ifp->if_flags & IFF_PROMISC) { 2302 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2303 } else { 2304 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2305 } 2306 2307 if (ifp->if_flags & IFF_BROADCAST) { 2308 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2309 } else { 2310 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2311 } 2312 2313 /* We don't need the FCS appended to the packet. */ 2314 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2315 2316 /* We want short frames padded to 60 bytes. */ 2317 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2318 2319 /* 2320 * Enable the reception of all error frames. This is is 2321 * a necessary evil due to the design of the XMAC. The 2322 * XMAC's receive FIFO is only 8K in size, however jumbo 2323 * frames can be up to 9000 bytes in length. When bad 2324 * frame filtering is enabled, the XMAC's RX FIFO operates 2325 * in 'store and forward' mode. For this to work, the 2326 * entire frame has to fit into the FIFO, but that means 2327 * that jumbo frames larger than 8192 bytes will be 2328 * truncated. Disabling all bad frame filtering causes 2329 * the RX FIFO to operate in streaming mode, in which 2330 * case the XMAC will start transfering frames out of the 2331 * RX FIFO as soon as the FIFO threshold is reached. 2332 */ 2333 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2334 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2335 XM_MODE_RX_INRANGELEN); 2336 2337 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2338 2339 /* 2340 * Bump up the transmit threshold. This helps hold off transmit 2341 * underruns when we're blasting traffic from both ports at once. 2342 */ 2343 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2344 2345 /* Set multicast filter */ 2346 sk_setmulti(sc_if); 2347 2348 /* Clear and enable interrupts */ 2349 SK_XM_READ_2(sc_if, XM_ISR); 2350 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2351 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2352 else 2353 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2354 2355 /* Configure MAC arbiter */ 2356 switch(sc_if->sk_xmac_rev) { 2357 case XM_XMAC_REV_B2: 2358 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2359 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2360 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2361 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2362 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2363 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2364 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2365 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2366 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2367 break; 2368 case XM_XMAC_REV_C1: 2369 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2370 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2371 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2372 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2373 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2374 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2375 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2376 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2377 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2378 break; 2379 default: 2380 break; 2381 } 2382 sk_win_write_2(sc, SK_MACARB_CTL, 2383 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2384 2385 sc_if->sk_link = 1; 2386} 2387 2388void sk_init_yukon(sc_if) 2389 struct sk_if_softc *sc_if; 2390{ 2391 u_int32_t phy; 2392 u_int16_t reg; 2393 struct sk_softc *sc; 2394 int i; 2395 2396 sc = sc_if->sk_softc; 2397 2398 DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n", 2399 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2400 2401 if (sc->sk_type == SK_YUKON_LITE && 2402 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2403 /* Take PHY out of reset. */ 2404 sk_win_write_4(sc, SK_GPIO, 2405 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2406 } 2407 2408 /* GMAC and GPHY Reset */ 2409 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2410 2411 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2412 2413 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2414 DELAY(1000); 2415 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2416 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2417 DELAY(1000); 2418 2419 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2420 2421 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2422 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2423 2424 switch(sc_if->sk_softc->sk_pmd) { 2425 case IFM_1000_SX: 2426 case IFM_1000_LX: 2427 phy |= SK_GPHY_FIBER; 2428 break; 2429 2430 case IFM_1000_CX: 2431 case IFM_1000_T: 2432 phy |= SK_GPHY_COPPER; 2433 break; 2434 } 2435 2436 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2437 2438 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2439 DELAY(1000); 2440 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2441 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2442 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2443 2444 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2445 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2446 2447 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2448 2449 /* unused read of the interrupt source register */ 2450 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2451 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2452 2453 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2454 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2455 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2456 2457 /* MIB Counter Clear Mode set */ 2458 reg |= YU_PAR_MIB_CLR; 2459 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2460 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2461 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2462 2463 /* MIB Counter Clear Mode clear */ 2464 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2465 reg &= ~YU_PAR_MIB_CLR; 2466 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2467 2468 /* receive control reg */ 2469 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2470 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2471 YU_RCR_CRCR); 2472 2473 /* transmit parameter register */ 2474 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2475 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2476 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2477 2478 /* serial mode register */ 2479 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2480 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2481 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2482 YU_SMR_IPG_DATA(0x1e)); 2483 2484 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2485 /* Setup Yukon's address */ 2486 for (i = 0; i < 3; i++) { 2487 /* Write Source Address 1 (unicast filter) */ 2488 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2489 sc_if->arpcom.ac_enaddr[i * 2] | 2490 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2491 } 2492 2493 for (i = 0; i < 3; i++) { 2494 reg = sk_win_read_2(sc_if->sk_softc, 2495 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2496 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2497 } 2498 2499 /* Set multicast filter */ 2500 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2501 sk_setmulti(sc_if); 2502 2503 /* enable interrupt mask for counter overflows */ 2504 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2505 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2506 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2507 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2508 2509 /* Configure RX MAC FIFO */ 2510 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2511 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2512 2513 /* Configure TX MAC FIFO */ 2514 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2515 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2516 2517 DPRINTFN(6, ("sk_init_yukon: end\n")); 2518} 2519 2520/* 2521 * Note that to properly initialize any part of the GEnesis chip, 2522 * you first have to take it out of reset mode. 2523 */ 2524void 2525sk_init(void *xsc_if) 2526{ 2527 struct sk_if_softc *sc_if = xsc_if; 2528 struct sk_softc *sc = sc_if->sk_softc; 2529 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2530 struct mii_data *mii = &sc_if->sk_mii; 2531 int s; 2532 2533 DPRINTFN(2, ("sk_init\n")); 2534 2535 s = splimp(); 2536 2537 if (ifp->if_flags & IFF_RUNNING) { 2538 splx(s); 2539 return; 2540 } 2541 2542 /* Cancel pending I/O and free all RX/TX buffers. */ 2543 sk_stop(sc_if); 2544 2545 if (sc->sk_type == SK_GENESIS) { 2546 /* Configure LINK_SYNC LED */ 2547 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2548 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2549 SK_LINKLED_LINKSYNC_ON); 2550 2551 /* Configure RX LED */ 2552 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2553 SK_RXLEDCTL_COUNTER_START); 2554 2555 /* Configure TX LED */ 2556 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2557 SK_TXLEDCTL_COUNTER_START); 2558 } 2559 2560 /* Configure I2C registers */ 2561 2562 /* Configure XMAC(s) */ 2563 switch (sc->sk_type) { 2564 case SK_GENESIS: 2565 sk_init_xmac(sc_if); 2566 break; 2567 case SK_YUKON: 2568 case SK_YUKON_LITE: 2569 case SK_YUKON_LP: 2570 sk_init_yukon(sc_if); 2571 break; 2572 } 2573 mii_mediachg(mii); 2574 2575 if (sc->sk_type == SK_GENESIS) { 2576 /* Configure MAC FIFOs */ 2577 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2578 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2579 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2580 2581 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2582 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2583 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2584 } 2585 2586 /* Configure transmit arbiter(s) */ 2587 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2588 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2589 2590 /* Configure RAMbuffers */ 2591 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2592 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2593 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2594 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2595 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2596 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2597 2598 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2599 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2600 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2601 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2602 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2603 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2604 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2605 2606 /* Configure BMUs */ 2607 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2608 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2609 SK_RX_RING_ADDR(sc_if, 0)); 2610 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2611 2612 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2613 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2614 SK_TX_RING_ADDR(sc_if, 0)); 2615 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2616 2617 /* Init descriptors */ 2618 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2619 printf("%s: initialization failed: no " 2620 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2621 sk_stop(sc_if); 2622 splx(s); 2623 return; 2624 } 2625 2626 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2627 printf("%s: initialization failed: no " 2628 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2629 sk_stop(sc_if); 2630 splx(s); 2631 return; 2632 } 2633 2634 /* Configure interrupt handling */ 2635 CSR_READ_4(sc, SK_ISSR); 2636 if (sc_if->sk_port == SK_PORT_A) 2637 sc->sk_intrmask |= SK_INTRS1; 2638 else 2639 sc->sk_intrmask |= SK_INTRS2; 2640 2641 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2642 2643 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2644 2645 /* Start BMUs. */ 2646 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2647 2648 if (sc->sk_type == SK_GENESIS) { 2649 /* Enable XMACs TX and RX state machines */ 2650 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2651 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2652 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2653 } 2654 2655 if (SK_YUKON_FAMILY(sc->sk_type)) { 2656 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2657 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2658 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2659 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2660 } 2661 2662 2663 ifp->if_flags |= IFF_RUNNING; 2664 ifp->if_flags &= ~IFF_OACTIVE; 2665 2666 splx(s); 2667} 2668 2669void 2670sk_stop(struct sk_if_softc *sc_if) 2671{ 2672 struct sk_softc *sc = sc_if->sk_softc; 2673 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2674 struct sk_txmap_entry *dma; 2675 int i; 2676 2677 DPRINTFN(2, ("sk_stop\n")); 2678 2679 timeout_del(&sc_if->sk_tick_ch); 2680 2681 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2682 2683 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2684 u_int32_t val; 2685 2686 /* Put PHY back into reset. */ 2687 val = sk_win_read_4(sc, SK_GPIO); 2688 if (sc_if->sk_port == SK_PORT_A) { 2689 val |= SK_GPIO_DIR0; 2690 val &= ~SK_GPIO_DAT0; 2691 } else { 2692 val |= SK_GPIO_DIR2; 2693 val &= ~SK_GPIO_DAT2; 2694 } 2695 sk_win_write_4(sc, SK_GPIO, val); 2696 } 2697 2698 /* Turn off various components of this interface. */ 2699 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2700 switch (sc->sk_type) { 2701 case SK_GENESIS: 2702 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2703 SK_TXMACCTL_XMAC_RESET); 2704 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2705 break; 2706 case SK_YUKON: 2707 case SK_YUKON_LITE: 2708 case SK_YUKON_LP: 2709 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2710 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2711 break; 2712 } 2713 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2714 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2715 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2716 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2717 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2718 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2719 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2720 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2721 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2722 2723 /* Disable interrupts */ 2724 if (sc_if->sk_port == SK_PORT_A) 2725 sc->sk_intrmask &= ~SK_INTRS1; 2726 else 2727 sc->sk_intrmask &= ~SK_INTRS2; 2728 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2729 2730 SK_XM_READ_2(sc_if, XM_ISR); 2731 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2732 2733 /* Free RX and TX mbufs still in the queues. */ 2734 for (i = 0; i < SK_RX_RING_CNT; i++) { 2735 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2736 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2737 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2738 } 2739 } 2740 2741 for (i = 0; i < SK_TX_RING_CNT; i++) { 2742 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2743 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2744 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2745 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2746 sc_if->sk_cdata.sk_tx_map[i], link); 2747 sc_if->sk_cdata.sk_tx_map[i] = 0; 2748 } 2749 } 2750 2751 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2752 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2753 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2754 free(dma, M_DEVBUF); 2755 } 2756} 2757 2758struct cfattach skc_ca = { 2759 sizeof(struct sk_softc), skc_probe, skc_attach, 2760}; 2761 2762struct cfdriver skc_cd = { 2763 0, "skc", DV_DULL 2764}; 2765 2766struct cfattach sk_ca = { 2767 sizeof(struct sk_if_softc), sk_probe, sk_attach, 2768}; 2769 2770struct cfdriver sk_cd = { 2771 0, "sk", DV_IFNET 2772}; 2773 2774#ifdef SK_DEBUG 2775void 2776sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2777{ 2778#define DESC_PRINT(X) \ 2779 if (desc->X) \ 2780 printf("txdesc[%d]." #X "=%#x\n", \ 2781 idx, desc->X); 2782 2783 DESC_PRINT(sk_ctl); 2784 DESC_PRINT(sk_next); 2785 DESC_PRINT(sk_data_lo); 2786 DESC_PRINT(sk_data_hi); 2787 DESC_PRINT(sk_xmac_txstat); 2788 DESC_PRINT(sk_rsvd0); 2789 DESC_PRINT(sk_csum_startval); 2790 DESC_PRINT(sk_csum_startpos); 2791 DESC_PRINT(sk_csum_writepos); 2792 DESC_PRINT(sk_rsvd1); 2793#undef PRINT 2794} 2795 2796void 2797sk_dump_bytes(const char *data, int len) 2798{ 2799 int c, i, j; 2800 2801 for (i = 0; i < len; i += 16) { 2802 printf("%08x ", i); 2803 c = len - i; 2804 if (c > 16) c = 16; 2805 2806 for (j = 0; j < c; j++) { 2807 printf("%02x ", data[i + j] & 0xff); 2808 if ((j & 0xf) == 7 && j > 0) 2809 printf(" "); 2810 } 2811 2812 for (; j < 16; j++) 2813 printf(" "); 2814 printf(" "); 2815 2816 for (j = 0; j < c; j++) { 2817 int ch = data[i + j] & 0xff; 2818 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2819 } 2820 2821 printf("\n"); 2822 2823 if (c < 16) 2824 break; 2825 } 2826} 2827 2828void 2829sk_dump_mbuf(struct mbuf *m) 2830{ 2831 int count = m->m_pkthdr.len; 2832 2833 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2834 2835 while (count > 0 && m) { 2836 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2837 m, m->m_data, m->m_len); 2838 sk_dump_bytes(mtod(m, char *), m->m_len); 2839 2840 count -= m->m_len; 2841 m = m->m_next; 2842 } 2843} 2844#endif 2845