if_sk.c revision 1.44
1/* $OpenBSD: if_sk.c,v 1.44 2004/08/19 16:31:42 mcbride Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37/* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53/* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72/* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89#include "bpfilter.h" 90 91#include <sys/param.h> 92#include <sys/systm.h> 93#include <sys/sockio.h> 94#include <sys/mbuf.h> 95#include <sys/malloc.h> 96#include <sys/kernel.h> 97#include <sys/socket.h> 98#include <sys/device.h> 99#include <sys/queue.h> 100 101#include <net/if.h> 102#include <net/if_dl.h> 103#include <net/if_types.h> 104 105#ifdef INET 106#include <netinet/in.h> 107#include <netinet/in_systm.h> 108#include <netinet/in_var.h> 109#include <netinet/ip.h> 110#include <netinet/udp.h> 111#include <netinet/tcp.h> 112#include <netinet/if_ether.h> 113#endif 114 115#include <net/if_media.h> 116#include <net/if_vlan_var.h> 117 118#if NBPFILTER > 0 119#include <net/bpf.h> 120#endif 121 122#include <dev/mii/mii.h> 123#include <dev/mii/miivar.h> 124#include <dev/mii/brgphyreg.h> 125 126#include <dev/pci/pcireg.h> 127#include <dev/pci/pcivar.h> 128#include <dev/pci/pcidevs.h> 129 130#define SK_VERBOSE 131/* #define SK_USEIOSPACE */ 132 133#include <dev/pci/if_skreg.h> 134#include <dev/pci/xmaciireg.h> 135#include <dev/pci/yukonreg.h> 136 137int skc_probe(struct device *, void *, void *); 138void skc_attach(struct device *, struct device *self, void *aux); 139int sk_probe(struct device *, void *, void *); 140void sk_attach(struct device *, struct device *self, void *aux); 141int skcprint(void *, const char *); 142int sk_intr(void *); 143void sk_intr_bcom(struct sk_if_softc *); 144void sk_intr_xmac(struct sk_if_softc *); 145void sk_intr_yukon(struct sk_if_softc *); 146void sk_rxeof(struct sk_if_softc *); 147void sk_txeof(struct sk_if_softc *); 148int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 149void sk_start(struct ifnet *); 150int sk_ioctl(struct ifnet *, u_long, caddr_t); 151void sk_init(void *); 152void sk_init_xmac(struct sk_if_softc *); 153void sk_init_yukon(struct sk_if_softc *); 154void sk_stop(struct sk_if_softc *); 155void sk_watchdog(struct ifnet *); 156void sk_shutdown(void *); 157int sk_ifmedia_upd(struct ifnet *); 158void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 159void sk_reset(struct sk_softc *); 160int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 161int sk_alloc_jumbo_mem(struct sk_if_softc *); 162void sk_free_jumbo_mem(struct sk_if_softc *); 163void *sk_jalloc(struct sk_if_softc *); 164void sk_jfree(caddr_t, u_int, void *); 165int sk_init_rx_ring(struct sk_if_softc *); 166int sk_init_tx_ring(struct sk_if_softc *); 167u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 168void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int); 169void sk_vpd_read(struct sk_softc *); 170 171int sk_xmac_miibus_readreg(struct device *, int, int); 172void sk_xmac_miibus_writereg(struct device *, int, int, int); 173void sk_xmac_miibus_statchg(struct device *); 174 175int sk_marv_miibus_readreg(struct device *, int, int); 176void sk_marv_miibus_writereg(struct device *, int, int, int); 177void sk_marv_miibus_statchg(struct device *); 178 179u_int32_t sk_xmac_hash(caddr_t); 180u_int32_t sk_yukon_hash(caddr_t); 181void sk_setfilt(struct sk_if_softc *, caddr_t, int); 182void sk_setmulti(struct sk_if_softc *); 183void sk_tick(void *); 184void sk_rxcsum(struct ifnet *, struct mbuf *, const u_int16_t, const u_int16_t); 185 186#ifdef SK_DEBUG 187#define DPRINTF(x) if (skdebug) printf x 188#define DPRINTFN(n,x) if (skdebug >= (n)) printf x 189int skdebug = 0; 190 191void sk_dump_txdesc(struct sk_tx_desc *, int); 192void sk_dump_mbuf(struct mbuf *); 193void sk_dump_bytes(const char *, int); 194#else 195#define DPRINTF(x) 196#define DPRINTFN(n,x) 197#endif 198 199#define SK_SETBIT(sc, reg, x) \ 200 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 201 202#define SK_CLRBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 204 205#define SK_WIN_SETBIT_4(sc, reg, x) \ 206 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 207 208#define SK_WIN_CLRBIT_4(sc, reg, x) \ 209 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 210 211#define SK_WIN_SETBIT_2(sc, reg, x) \ 212 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 213 214#define SK_WIN_CLRBIT_2(sc, reg, x) \ 215 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 216 217/* supported device vendors */ 218const struct pci_matchid skc_devices[] = { 219 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940}, 220 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T}, 221 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032}, 222 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064}, 223 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SK_V2}, 224 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_GE}, 225 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2}, 226}; 227 228static inline u_int32_t 229sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 230{ 231#ifdef SK_USEIOSPACE 232 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 233 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 234#else 235 return CSR_READ_4(sc, reg); 236#endif 237} 238 239static inline u_int16_t 240sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 241{ 242#ifdef SK_USEIOSPACE 243 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 244 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 245#else 246 return CSR_READ_2(sc, reg); 247#endif 248} 249 250static inline u_int8_t 251sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 252{ 253#ifdef SK_USEIOSPACE 254 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 255 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 256#else 257 return CSR_READ_1(sc, reg); 258#endif 259} 260 261static inline void 262sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 263{ 264#ifdef SK_USEIOSPACE 265 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 266 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 267#else 268 CSR_WRITE_4(sc, reg, x); 269#endif 270} 271 272static inline void 273sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 274{ 275#ifdef SK_USEIOSPACE 276 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 277 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 278#else 279 CSR_WRITE_2(sc, reg, x); 280#endif 281} 282 283static inline void 284sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 285{ 286#ifdef SK_USEIOSPACE 287 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 288 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 289#else 290 CSR_WRITE_1(sc, reg, x); 291#endif 292} 293 294/* 295 * The VPD EEPROM contains Vital Product Data, as suggested in 296 * the PCI 2.1 specification. The VPD data is separared into areas 297 * denoted by resource IDs. The SysKonnect VPD contains an ID string 298 * resource (the name of the adapter), a read-only area resource 299 * containing various key/data fields and a read/write area which 300 * can be used to store asset management information or log messages. 301 * We read the ID string and read-only into buffers attached to 302 * the controller softc structure for later use. At the moment, 303 * we only use the ID string during sk_attach(). 304 */ 305u_int8_t 306sk_vpd_readbyte(struct sk_softc *sc, int addr) 307{ 308 int i; 309 310 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 311 for (i = 0; i < SK_TIMEOUT; i++) { 312 DELAY(1); 313 if (sk_win_read_2(sc, 314 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 315 break; 316 } 317 318 if (i == SK_TIMEOUT) 319 return(0); 320 321 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 322} 323 324void 325sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 326{ 327 int i; 328 u_int8_t *ptr; 329 330 ptr = (u_int8_t *)res; 331 for (i = 0; i < sizeof(struct vpd_res); i++) 332 ptr[i] = sk_vpd_readbyte(sc, i + addr); 333} 334 335void 336sk_vpd_read(struct sk_softc *sc) 337{ 338 int pos = 0, i; 339 struct vpd_res res; 340 341 if (sc->sk_vpd_prodname != NULL) 342 free(sc->sk_vpd_prodname, M_DEVBUF); 343 if (sc->sk_vpd_readonly != NULL) 344 free(sc->sk_vpd_readonly, M_DEVBUF); 345 sc->sk_vpd_prodname = NULL; 346 sc->sk_vpd_readonly = NULL; 347 348 sk_vpd_read_res(sc, &res, pos); 349 350 if (res.vr_id != VPD_RES_ID) { 351 printf("%s: bad VPD resource id: expected %x got %x\n", 352 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 353 return; 354 } 355 356 pos += sizeof(res); 357 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 358 if (sc->sk_vpd_prodname == NULL) 359 panic("sk_vpd_read"); 360 for (i = 0; i < res.vr_len; i++) 361 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 362 sc->sk_vpd_prodname[i] = '\0'; 363 pos += i; 364 365 sk_vpd_read_res(sc, &res, pos); 366 367 if (res.vr_id != VPD_RES_READ) { 368 printf("%s: bad VPD resource id: expected %x got %x\n", 369 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 370 return; 371 } 372 373 pos += sizeof(res); 374 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 375 if (sc->sk_vpd_readonly == NULL) 376 panic("sk_vpd_read"); 377 for (i = 0; i < res.vr_len + 1; i++) 378 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 379} 380 381int 382sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 383{ 384 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 385 int i; 386 387 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 388 389 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 390 return(0); 391 392 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 393 SK_XM_READ_2(sc_if, XM_PHY_DATA); 394 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 395 for (i = 0; i < SK_TIMEOUT; i++) { 396 DELAY(1); 397 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 398 XM_MMUCMD_PHYDATARDY) 399 break; 400 } 401 402 if (i == SK_TIMEOUT) { 403 printf("%s: phy failed to come ready\n", 404 sc_if->sk_dev.dv_xname); 405 return(0); 406 } 407 } 408 DELAY(1); 409 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 410} 411 412void 413sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 414{ 415 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 416 int i; 417 418 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 419 420 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 421 for (i = 0; i < SK_TIMEOUT; i++) { 422 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 423 break; 424 } 425 426 if (i == SK_TIMEOUT) { 427 printf("%s: phy failed to come ready\n", 428 sc_if->sk_dev.dv_xname); 429 return; 430 } 431 432 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 433 for (i = 0; i < SK_TIMEOUT; i++) { 434 DELAY(1); 435 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 436 break; 437 } 438 439 if (i == SK_TIMEOUT) 440 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 441} 442 443void 444sk_xmac_miibus_statchg(struct device *dev) 445{ 446 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 447 struct mii_data *mii = &sc_if->sk_mii; 448 449 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 450 451 /* 452 * If this is a GMII PHY, manually set the XMAC's 453 * duplex mode accordingly. 454 */ 455 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 456 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 457 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 458 } else { 459 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 460 } 461 } 462} 463 464int 465sk_marv_miibus_readreg(dev, phy, reg) 466 struct device *dev; 467 int phy, reg; 468{ 469 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 470 u_int16_t val; 471 int i; 472 473 if (phy != 0 || 474 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 475 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 476 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 477 phy, reg)); 478 return(0); 479 } 480 481 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 482 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 483 484 for (i = 0; i < SK_TIMEOUT; i++) { 485 DELAY(1); 486 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 487 if (val & YU_SMICR_READ_VALID) 488 break; 489 } 490 491 if (i == SK_TIMEOUT) { 492 printf("%s: phy failed to come ready\n", 493 sc_if->sk_dev.dv_xname); 494 return 0; 495 } 496 497 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 498 SK_TIMEOUT)); 499 500 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 501 502 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 503 phy, reg, val)); 504 505 return val; 506} 507 508void 509sk_marv_miibus_writereg(dev, phy, reg, val) 510 struct device *dev; 511 int phy, reg, val; 512{ 513 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 514 int i; 515 516 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 517 phy, reg, val)); 518 519 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 520 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 521 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 522 523 for (i = 0; i < SK_TIMEOUT; i++) { 524 DELAY(1); 525 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 526 break; 527 } 528} 529 530void 531sk_marv_miibus_statchg(dev) 532 struct device *dev; 533{ 534 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 535 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 536} 537 538#define XMAC_POLY 0xEDB88320 539#define GMAC_POLY 0x04C11DB7L 540#define HASH_BITS 6 541 542u_int32_t 543sk_xmac_hash(caddr_t addr) 544{ 545 u_int32_t crc; 546 547 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 548 return (~crc & ((1 << HASH_BITS) - 1)); 549} 550 551u_int32_t 552sk_yukon_hash(caddr_t addr) 553{ 554 u_int32_t crc; 555 556 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 557 return (crc & ((1 << HASH_BITS) - 1)); 558} 559 560void 561sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 562{ 563 int base = XM_RXFILT_ENTRY(slot); 564 565 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 566 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 567 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 568} 569 570void 571sk_setmulti(struct sk_if_softc *sc_if) 572{ 573 struct sk_softc *sc = sc_if->sk_softc; 574 struct ifnet *ifp= &sc_if->arpcom.ac_if; 575 u_int32_t hashes[2] = { 0, 0 }; 576 int h, i; 577 struct arpcom *ac = &sc_if->arpcom; 578 struct ether_multi *enm; 579 struct ether_multistep step; 580 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 581 582 /* First, zot all the existing filters. */ 583 switch(sc->sk_type) { 584 case SK_GENESIS: 585 for (i = 1; i < XM_RXFILT_MAX; i++) 586 sk_setfilt(sc_if, (caddr_t)&dummy, i); 587 588 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 589 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 590 break; 591 case SK_YUKON: 592 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 593 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 594 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 595 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 596 break; 597 } 598 599 /* Now program new ones. */ 600allmulti: 601 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 602 hashes[0] = 0xFFFFFFFF; 603 hashes[1] = 0xFFFFFFFF; 604 } else { 605 i = 1; 606 /* First find the tail of the list. */ 607 ETHER_FIRST_MULTI(step, ac, enm); 608 while (enm != NULL) { 609 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 610 ETHER_ADDR_LEN)) { 611 ifp->if_flags |= IFF_ALLMULTI; 612 goto allmulti; 613 } 614 /* 615 * Program the first XM_RXFILT_MAX multicast groups 616 * into the perfect filter. For all others, 617 * use the hash table. 618 */ 619 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 620 sk_setfilt(sc_if, enm->enm_addrlo, i); 621 i++; 622 } 623 else { 624 switch(sc->sk_type) { 625 case SK_GENESIS: 626 h = sk_xmac_hash(enm->enm_addrlo); 627 break; 628 629 case SK_YUKON: 630 h = sk_yukon_hash(enm->enm_addrlo); 631 break; 632 } 633 if (h < 32) 634 hashes[0] |= (1 << h); 635 else 636 hashes[1] |= (1 << (h - 32)); 637 } 638 639 ETHER_NEXT_MULTI(step, enm); 640 } 641 } 642 643 switch(sc->sk_type) { 644 case SK_GENESIS: 645 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 646 XM_MODE_RX_USE_PERFECT); 647 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 648 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 649 break; 650 case SK_YUKON: 651 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 652 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 653 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 654 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 655 break; 656 } 657} 658 659int 660sk_init_rx_ring(struct sk_if_softc *sc_if) 661{ 662 struct sk_chain_data *cd = &sc_if->sk_cdata; 663 struct sk_ring_data *rd = sc_if->sk_rdata; 664 int i; 665 666 bzero((char *)rd->sk_rx_ring, 667 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 668 669 for (i = 0; i < SK_RX_RING_CNT; i++) { 670 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 671 if (i == (SK_RX_RING_CNT - 1)) { 672 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 673 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 674 } else { 675 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 676 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 677 } 678 rd->sk_rx_ring[i].sk_csum1_start = ETHER_HDR_LEN; 679 rd->sk_rx_ring[i].sk_csum2_start = ETHER_HDR_LEN + 680 sizeof(struct ip); 681 } 682 683 for (i = 0; i < SK_RX_RING_CNT; i++) { 684 if (sk_newbuf(sc_if, i, NULL, 685 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 686 printf("%s: failed alloc of %dth mbuf\n", 687 sc_if->sk_dev.dv_xname, i); 688 return(ENOBUFS); 689 } 690 } 691 692 sc_if->sk_cdata.sk_rx_prod = 0; 693 sc_if->sk_cdata.sk_rx_cons = 0; 694 695 return(0); 696} 697 698int 699sk_init_tx_ring(struct sk_if_softc *sc_if) 700{ 701 struct sk_softc *sc = sc_if->sk_softc; 702 struct sk_chain_data *cd = &sc_if->sk_cdata; 703 struct sk_ring_data *rd = sc_if->sk_rdata; 704 bus_dmamap_t dmamap; 705 struct sk_txmap_entry *entry; 706 int i; 707 708 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 709 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 710 711 SLIST_INIT(&sc_if->sk_txmap_listhead); 712 for (i = 0; i < SK_TX_RING_CNT; i++) { 713 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 714 if (i == (SK_TX_RING_CNT - 1)) { 715 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 716 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 717 } else { 718 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 719 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 720 } 721 722 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 723 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 724 return (ENOBUFS); 725 726 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 727 if (!entry) { 728 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 729 return (ENOBUFS); 730 } 731 entry->dmamap = dmamap; 732 SLIST_INSERT_HEAD(&sc_if->sk_txmap_listhead, entry, link); 733 } 734 735 sc_if->sk_cdata.sk_tx_prod = 0; 736 sc_if->sk_cdata.sk_tx_cons = 0; 737 sc_if->sk_cdata.sk_tx_cnt = 0; 738 739 return (0); 740} 741 742int 743sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 744 bus_dmamap_t dmamap) 745{ 746 struct mbuf *m_new = NULL; 747 struct sk_chain *c; 748 struct sk_rx_desc *r; 749 750 if (m == NULL) { 751 caddr_t *buf = NULL; 752 753 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 754 if (m_new == NULL) 755 return(ENOBUFS); 756 757 /* Allocate the jumbo buffer */ 758 buf = sk_jalloc(sc_if); 759 if (buf == NULL) { 760 m_freem(m_new); 761 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 762 "dropped!\n", sc_if->arpcom.ac_if.if_xname)); 763 return(ENOBUFS); 764 } 765 766 /* Attach the buffer to the mbuf */ 767 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 768 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 769 } else { 770 /* 771 * We're re-using a previously allocated mbuf; 772 * be sure to re-init pointers and lengths to 773 * default values. 774 */ 775 m_new = m; 776 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 777 m_new->m_data = m_new->m_ext.ext_buf; 778 } 779 m_adj(m_new, ETHER_ALIGN); 780 781 c = &sc_if->sk_cdata.sk_rx_chain[i]; 782 r = c->sk_desc; 783 c->sk_mbuf = m_new; 784 r->sk_data_lo = dmamap->dm_segs[0].ds_addr + 785 (((vaddr_t)m_new->m_data 786 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf)); 787 r->sk_ctl = SK_JLEN | SK_RXSTAT; 788 789 return(0); 790} 791 792/* 793 * Memory management for jumbo frames. 794 */ 795 796int 797sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 798{ 799 struct sk_softc *sc = sc_if->sk_softc; 800 caddr_t ptr, kva; 801 bus_dma_segment_t seg; 802 int i, rseg; 803 struct sk_jpool_entry *entry; 804 805 /* Grab a big chunk o' storage. */ 806 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 807 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 808 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 809 return (ENOBUFS); 810 } 811 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, &kva, 812 BUS_DMA_NOWAIT)) { 813 printf("%s: can't map dma buffers (%d bytes)\n", 814 sc->sk_dev.dv_xname, SK_JMEM); 815 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 816 return (ENOBUFS); 817 } 818 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 819 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 820 printf("%s: can't create dma map\n", sc->sk_dev.dv_xname); 821 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 822 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 823 return (ENOBUFS); 824 } 825 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 826 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 827 printf("%s: can't load dma map\n", sc->sk_dev.dv_xname); 828 bus_dmamap_destroy(sc->sc_dmatag, 829 sc_if->sk_cdata.sk_rx_jumbo_map); 830 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 831 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 832 return (ENOBUFS); 833 } 834 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 835 DPRINTFN(1,("sk_jumbo_buf = 0x%08X\n", sc_if->sk_cdata.sk_jumbo_buf)); 836 837 LIST_INIT(&sc_if->sk_jfree_listhead); 838 LIST_INIT(&sc_if->sk_jinuse_listhead); 839 840 /* 841 * Now divide it up into 9K pieces and save the addresses 842 * in an array. 843 */ 844 ptr = sc_if->sk_cdata.sk_jumbo_buf; 845 for (i = 0; i < SK_JSLOTS; i++) { 846 sc_if->sk_cdata.sk_jslots[i] = ptr; 847 ptr += SK_JLEN; 848 entry = malloc(sizeof(struct sk_jpool_entry), 849 M_DEVBUF, M_NOWAIT); 850 if (entry == NULL) { 851 bus_dmamap_unload(sc->sc_dmatag, 852 sc_if->sk_cdata.sk_rx_jumbo_map); 853 bus_dmamap_destroy(sc->sc_dmatag, 854 sc_if->sk_cdata.sk_rx_jumbo_map); 855 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 856 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 857 sc_if->sk_cdata.sk_jumbo_buf = NULL; 858 printf("%s: no memory for jumbo buffer queue!\n", 859 sc->sk_dev.dv_xname); 860 return(ENOBUFS); 861 } 862 entry->slot = i; 863 if (i) 864 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 865 entry, jpool_entries); 866 else 867 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 868 entry, jpool_entries); 869 } 870 871 return(0); 872} 873 874/* 875 * Allocate a jumbo buffer. 876 */ 877void * 878sk_jalloc(struct sk_if_softc *sc_if) 879{ 880 struct sk_jpool_entry *entry; 881 882 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 883 884 if (entry == NULL) { 885 DPRINTF(("%s: no free jumbo buffers\n", 886 sc_if->sk_dev.dv_xname)); 887 return (NULL); 888 } 889 890 LIST_REMOVE(entry, jpool_entries); 891 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 892 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 893} 894 895/* 896 * Release a jumbo buffer. 897 */ 898void 899sk_jfree(caddr_t buf, u_int size, void *arg) 900{ 901 struct sk_jpool_entry *entry; 902 struct sk_if_softc *sc; 903 int i; 904 905 /* Extract the softc struct pointer. */ 906 sc = (struct sk_if_softc *)arg; 907 908 if (sc == NULL) 909 panic("sk_jfree: can't find softc pointer!"); 910 911 /* calculate the slot this buffer belongs to */ 912 913 i = ((vaddr_t)buf 914 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 915 916 if ((i < 0) || (i >= SK_JSLOTS)) 917 panic("sk_jfree: asked to free buffer that we don't manage!"); 918 919 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 920 if (entry == NULL) 921 panic("sk_jfree: buffer not in use!"); 922 entry->slot = i; 923 LIST_REMOVE(entry, jpool_entries); 924 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 925} 926 927/* 928 * Set media options. 929 */ 930int 931sk_ifmedia_upd(struct ifnet *ifp) 932{ 933 struct sk_if_softc *sc_if = ifp->if_softc; 934 935 sk_init(sc_if); 936 mii_mediachg(&sc_if->sk_mii); 937 return(0); 938} 939 940/* 941 * Report current media status. 942 */ 943void 944sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 945{ 946 struct sk_if_softc *sc_if = ifp->if_softc; 947 948 mii_pollstat(&sc_if->sk_mii); 949 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 950 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 951} 952 953int 954sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 955{ 956 struct sk_if_softc *sc_if = ifp->if_softc; 957 struct sk_softc *sc = sc_if->sk_softc; 958 struct ifreq *ifr = (struct ifreq *) data; 959 struct ifaddr *ifa = (struct ifaddr *) data; 960 struct mii_data *mii; 961 int s, error = 0; 962 963 s = splimp(); 964 965 if ((error = ether_ioctl(ifp, &sc_if->arpcom, command, data)) > 0) { 966 splx(s); 967 return error; 968 } 969 970 switch(command) { 971 case SIOCSIFADDR: 972 ifp->if_flags |= IFF_UP; 973 switch (ifa->ifa_addr->sa_family) { 974#ifdef INET 975 case AF_INET: 976 sk_init(sc_if); 977 arp_ifinit(&sc_if->arpcom, ifa); 978 break; 979#endif /* INET */ 980 default: 981 sk_init(sc_if); 982 break; 983 } 984 break; 985 case SIOCSIFMTU: 986 if (ifr->ifr_mtu > ETHERMTU_JUMBO) 987 error = EINVAL; 988 else 989 ifp->if_mtu = ifr->ifr_mtu; 990 sk_init(sc_if); 991 break; 992 case SIOCSIFFLAGS: 993 if (ifp->if_flags & IFF_UP) { 994 if (ifp->if_flags & IFF_RUNNING && 995 ifp->if_flags & IFF_PROMISC && 996 !(sc_if->sk_if_flags & IFF_PROMISC)) { 997 switch(sc->sk_type) { 998 case SK_GENESIS: 999 SK_XM_SETBIT_4(sc_if, XM_MODE, 1000 XM_MODE_RX_PROMISC); 1001 break; 1002 case SK_YUKON: 1003 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1004 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1005 break; 1006 } 1007 sk_setmulti(sc_if); 1008 } else if (ifp->if_flags & IFF_RUNNING && 1009 !(ifp->if_flags & IFF_PROMISC) && 1010 sc_if->sk_if_flags & IFF_PROMISC) { 1011 switch(sc->sk_type) { 1012 case SK_GENESIS: 1013 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1014 XM_MODE_RX_PROMISC); 1015 break; 1016 case SK_YUKON: 1017 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1018 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1019 break; 1020 } 1021 1022 sk_setmulti(sc_if); 1023 } else 1024 sk_init(sc_if); 1025 } else { 1026 if (ifp->if_flags & IFF_RUNNING) 1027 sk_stop(sc_if); 1028 } 1029 sc_if->sk_if_flags = ifp->if_flags; 1030 error = 0; 1031 break; 1032 case SIOCADDMULTI: 1033 case SIOCDELMULTI: 1034 error = (command == SIOCADDMULTI) ? 1035 ether_addmulti(ifr, &sc_if->arpcom) : 1036 ether_delmulti(ifr, &sc_if->arpcom); 1037 1038 if (error == ENETRESET) { 1039 /* 1040 * Multicast list has changed; set the hardware 1041 * filter accordingly. 1042 */ 1043 sk_setmulti(sc_if); 1044 error = 0; 1045 } 1046 break; 1047 case SIOCGIFMEDIA: 1048 case SIOCSIFMEDIA: 1049 mii = &sc_if->sk_mii; 1050 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1051 break; 1052 default: 1053 error = EINVAL; 1054 break; 1055 } 1056 1057 splx(s); 1058 1059 return(error); 1060} 1061 1062/* 1063 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1064 * IDs against our list and return a device name if we find a match. 1065 */ 1066int 1067skc_probe(struct device *parent, void *match, void *aux) 1068{ 1069 return (pci_matchbyid((struct pci_attach_args *)aux, skc_devices, 1070 sizeof(skc_devices)/sizeof(skc_devices[0]))); 1071} 1072 1073/* 1074 * Force the GEnesis into reset, then bring it out of reset. 1075 */ 1076void sk_reset(struct sk_softc *sc) 1077{ 1078 DPRINTFN(2, ("sk_reset\n")); 1079 1080 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1081 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1082 if (sc->sk_type == SK_YUKON) 1083 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1084 1085 DELAY(1000); 1086 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1087 DELAY(2); 1088 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1089 if (sc->sk_type == SK_YUKON) 1090 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1091 1092 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1093 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1094 CSR_READ_2(sc, SK_LINK_CTRL))); 1095 1096 if (sc->sk_type == SK_GENESIS) { 1097 /* Configure packet arbiter */ 1098 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1099 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1100 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1101 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1102 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1103 } 1104 1105 /* Enable RAM interface */ 1106 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1107 1108 /* 1109 * Configure interrupt moderation. The moderation timer 1110 * defers interrupts specified in the interrupt moderation 1111 * timer mask based on the timeout specified in the interrupt 1112 * moderation timer init register. Each bit in the timer 1113 * register represents 18.825ns, so to specify a timeout in 1114 * microseconds, we have to multiply by 54. 1115 */ 1116 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1117 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1118 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1119 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1120} 1121 1122int 1123sk_probe(struct device *parent, void *match, void *aux) 1124{ 1125 struct skc_attach_args *sa = aux; 1126 1127 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1128 return(0); 1129 1130 return (1); 1131} 1132 1133/* 1134 * Each XMAC chip is attached as a separate logical IP interface. 1135 * Single port cards will have only one logical interface of course. 1136 */ 1137void 1138sk_attach(struct device *parent, struct device *self, void *aux) 1139{ 1140 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1141 struct sk_softc *sc = (struct sk_softc *)parent; 1142 struct skc_attach_args *sa = aux; 1143 struct ifnet *ifp; 1144 caddr_t kva; 1145 bus_dma_segment_t seg; 1146 int i, rseg; 1147 1148 sc_if->sk_port = sa->skc_port; 1149 sc_if->sk_softc = sc; 1150 sc->sk_if[sa->skc_port] = sc_if; 1151 1152 if (sa->skc_port == SK_PORT_A) 1153 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1154 if (sa->skc_port == SK_PORT_B) 1155 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1156 1157 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1158 1159 /* 1160 * Get station address for this interface. Note that 1161 * dual port cards actually come with three station 1162 * addresses: one for each port, plus an extra. The 1163 * extra one is used by the SysKonnect driver software 1164 * as a 'virtual' station address for when both ports 1165 * are operating in failover mode. Currently we don't 1166 * use this extra address. 1167 */ 1168 for (i = 0; i < ETHER_ADDR_LEN; i++) 1169 sc_if->arpcom.ac_enaddr[i] = 1170 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1171 1172 1173 printf(": address %s\n", 1174 ether_sprintf(sc_if->arpcom.ac_enaddr)); 1175 1176 /* 1177 * Set up RAM buffer addresses. The NIC will have a certain 1178 * amount of SRAM on it, somewhere between 512K and 2MB. We 1179 * need to divide this up a) between the transmitter and 1180 * receiver and b) between the two XMACs, if this is a 1181 * dual port NIC. Our algorithm is to divide up the memory 1182 * evenly so that everyone gets a fair share. 1183 */ 1184 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1185 u_int32_t chunk, val; 1186 1187 chunk = sc->sk_ramsize / 2; 1188 val = sc->sk_rboff / sizeof(u_int64_t); 1189 sc_if->sk_rx_ramstart = val; 1190 val += (chunk / sizeof(u_int64_t)); 1191 sc_if->sk_rx_ramend = val - 1; 1192 sc_if->sk_tx_ramstart = val; 1193 val += (chunk / sizeof(u_int64_t)); 1194 sc_if->sk_tx_ramend = val - 1; 1195 } else { 1196 u_int32_t chunk, val; 1197 1198 chunk = sc->sk_ramsize / 4; 1199 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1200 sizeof(u_int64_t); 1201 sc_if->sk_rx_ramstart = val; 1202 val += (chunk / sizeof(u_int64_t)); 1203 sc_if->sk_rx_ramend = val - 1; 1204 sc_if->sk_tx_ramstart = val; 1205 val += (chunk / sizeof(u_int64_t)); 1206 sc_if->sk_tx_ramend = val - 1; 1207 } 1208 1209 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1210 " tx_ramstart=%#x tx_ramend=%#x\n", 1211 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1212 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1213 1214 /* Read and save PHY type and set PHY address */ 1215 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1216 switch (sc_if->sk_phytype) { 1217 case SK_PHYTYPE_XMAC: 1218 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1219 break; 1220 case SK_PHYTYPE_BCOM: 1221 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1222 break; 1223 case SK_PHYTYPE_MARV_COPPER: 1224 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1225 break; 1226 default: 1227 printf("%s: unsupported PHY type: %d\n", 1228 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1229 return; 1230 } 1231 1232 /* Allocate the descriptor queues. */ 1233 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1234 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1235 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 1236 goto fail; 1237 } 1238 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1239 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1240 printf("%s: can't map dma buffers (%d bytes)\n", 1241 sc_if->sk_dev.dv_xname, sizeof(struct sk_ring_data)); 1242 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1243 goto fail; 1244 } 1245 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1246 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1247 &sc_if->sk_ring_map)) { 1248 printf("%s: can't create dma map\n", sc_if->sk_dev.dv_xname); 1249 bus_dmamem_unmap(sc->sc_dmatag, kva, 1250 sizeof(struct sk_ring_data)); 1251 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1252 goto fail; 1253 } 1254 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1255 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1256 printf("%s: can't load dma map\n", sc_if->sk_dev.dv_xname); 1257 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1258 bus_dmamem_unmap(sc->sc_dmatag, kva, 1259 sizeof(struct sk_ring_data)); 1260 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1261 goto fail; 1262 } 1263 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1264 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1265 1266 /* Try to allocate memory for jumbo buffers. */ 1267 if (sk_alloc_jumbo_mem(sc_if)) { 1268 printf("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1269 goto fail; 1270 } 1271 1272 ifp = &sc_if->arpcom.ac_if; 1273 ifp->if_softc = sc_if; 1274 ifp->if_mtu = ETHERMTU; 1275 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1276 ifp->if_ioctl = sk_ioctl; 1277 ifp->if_output = ether_output; 1278 ifp->if_start = sk_start; 1279 ifp->if_watchdog = sk_watchdog; 1280 ifp->if_baudrate = 1000000000; 1281 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1282 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1283 IFQ_SET_READY(&ifp->if_snd); 1284 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1285 1286 /* 1287 * Do miibus setup. 1288 */ 1289 switch (sc->sk_type) { 1290 case SK_GENESIS: 1291 sk_init_xmac(sc_if); 1292 break; 1293 case SK_YUKON: 1294 sk_init_yukon(sc_if); 1295 break; 1296 default: 1297 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1298 sc->sk_type); 1299 } 1300 1301 DPRINTFN(2, ("sk_attach: 1\n")); 1302 1303 sc_if->sk_mii.mii_ifp = ifp; 1304 switch (sc->sk_type) { 1305 case SK_GENESIS: 1306 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1307 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1308 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1309 break; 1310 case SK_YUKON: 1311 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1312 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1313 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1314 break; 1315 } 1316 1317 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1318 sk_ifmedia_upd, sk_ifmedia_sts); 1319 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1320 MII_OFFSET_ANY, 0); 1321 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1322 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1323 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1324 0, NULL); 1325 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1326 } 1327 else 1328 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1329 1330 timeout_set(&sc_if->sk_tick_ch, sk_tick, sc_if); 1331 timeout_add(&sc_if->sk_tick_ch, hz); 1332 1333 DPRINTFN(2, ("sk_attach: 1\n")); 1334 1335 /* 1336 * Call MI attach routines. 1337 */ 1338 if_attach(ifp); 1339 ether_ifattach(ifp); 1340 1341 DPRINTFN(2, ("sk_attach: end\n")); 1342 1343 return; 1344 1345fail: 1346 sc->sk_if[sa->skc_port] = NULL; 1347} 1348 1349int 1350skcprint(void *aux, const char *pnp) 1351{ 1352 struct skc_attach_args *sa = aux; 1353 1354 if (pnp) 1355 printf("sk port %c at %s", 1356 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1357 else 1358 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1359 return (UNCONF); 1360} 1361 1362/* 1363 * Attach the interface. Allocate softc structures, do ifmedia 1364 * setup and ethernet/BPF attach. 1365 */ 1366void 1367skc_attach(struct device *parent, struct device *self, void *aux) 1368{ 1369 struct sk_softc *sc = (struct sk_softc *)self; 1370 struct pci_attach_args *pa = aux; 1371 struct skc_attach_args skca; 1372 pci_chipset_tag_t pc = pa->pa_pc; 1373 pci_intr_handle_t ih; 1374 const char *intrstr = NULL; 1375 bus_addr_t iobase; 1376 bus_size_t iosize; 1377 int s; 1378 u_int32_t command; 1379 1380 DPRINTFN(2, ("begin skc_attach\n")); 1381 1382 s = splimp(); 1383 1384 /* 1385 * Handle power management nonsense. 1386 */ 1387 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1388 1389 if (command == 0x01) { 1390 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1391 if (command & SK_PSTATE_MASK) { 1392 u_int32_t iobase, membase, irq; 1393 1394 /* Save important PCI config data. */ 1395 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1396 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1397 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1398 1399 /* Reset the power state. */ 1400 printf("%s chip is in D%d power mode " 1401 "-- setting to D0\n", sc->sk_dev.dv_xname, 1402 command & SK_PSTATE_MASK); 1403 command &= 0xFFFFFFFC; 1404 pci_conf_write(pc, pa->pa_tag, 1405 SK_PCI_PWRMGMTCTRL, command); 1406 1407 /* Restore PCI config data. */ 1408 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1409 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1410 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1411 } 1412 } 1413 1414 /* 1415 * Map control/status registers. 1416 */ 1417 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1418 1419#define SK_MK_ID(vnd,prd) \ 1420 (((vnd) << PCI_VENDOR_SHIFT) | ((prd) << PCI_PRODUCT_SHIFT)) 1421 1422 switch (pa->pa_id) { 1423 case SK_MK_ID(PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_GE): 1424 sc->sk_type = SK_GENESIS; 1425 break; 1426 case SK_MK_ID(PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940): 1427 case SK_MK_ID(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T): 1428 case SK_MK_ID(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032): 1429 case SK_MK_ID(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064): 1430 case SK_MK_ID(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SK_V2): 1431 case SK_MK_ID(PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1432 sc->sk_type = SK_YUKON; 1433 break; 1434 default: 1435 printf(": unknown device!\n"); 1436 goto fail; 1437 } 1438#undef SK_MK_ID 1439 1440#ifdef SK_USEIOSPACE 1441 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1442 printf(": failed to enable I/O ports!\n"); 1443 goto fail; 1444 } 1445 /* 1446 * Map control/status registers. 1447 */ 1448 if (pci_io_find(pc, pa->pa_tag, SK_PCI_LOIO, &iobase, &iosize)) { 1449 printf(": can't find i/o space\n"); 1450 goto fail; 1451 } 1452 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->sk_bhandle)) { 1453 printf(": can't map i/o space\n"); 1454 goto fail; 1455 } 1456 sc->sk_btag = pa->pa_iot; 1457#else 1458 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1459 printf(": failed to enable memory mapping!\n"); 1460 goto fail; 1461 } 1462 if (pci_mem_find(pc, pa->pa_tag, SK_PCI_LOMEM, &iobase, &iosize, NULL)){ 1463 printf(": can't find mem space\n"); 1464 goto fail; 1465 } 1466 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->sk_bhandle)) { 1467 printf(": can't map mem space\n"); 1468 goto fail; 1469 } 1470 sc->sk_btag = pa->pa_memt; 1471 1472 DPRINTFN(2, ("skc_attach: iobase=%#x, iosize=%#x\n", iobase, iosize)); 1473#endif 1474 sc->sc_dmatag = pa->pa_dmat; 1475 1476 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1477 1478 /* Allocate interrupt */ 1479 if (pci_intr_map(pa, &ih)) { 1480 printf(": couldn't map interrupt\n"); 1481 goto fail; 1482 } 1483 1484 intrstr = pci_intr_string(pc, ih); 1485 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc, 1486 self->dv_xname); 1487 if (sc->sk_intrhand == NULL) { 1488 printf(": couldn't establish interrupt"); 1489 if (intrstr != NULL) 1490 printf(" at %s", intrstr); 1491 goto fail; 1492 } 1493 printf(": %s\n", intrstr); 1494 1495 /* Reset the adapter. */ 1496 sk_reset(sc); 1497 1498 /* Read and save vital product data from EEPROM. */ 1499 sk_vpd_read(sc); 1500 1501 if (sc->sk_type == SK_GENESIS) { 1502 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1503 /* Read and save RAM size and RAMbuffer offset */ 1504 switch(val) { 1505 case SK_RAMSIZE_512K_64: 1506 sc->sk_ramsize = 0x80000; 1507 sc->sk_rboff = SK_RBOFF_0; 1508 break; 1509 case SK_RAMSIZE_1024K_64: 1510 sc->sk_ramsize = 0x100000; 1511 sc->sk_rboff = SK_RBOFF_80000; 1512 break; 1513 case SK_RAMSIZE_1024K_128: 1514 sc->sk_ramsize = 0x100000; 1515 sc->sk_rboff = SK_RBOFF_0; 1516 break; 1517 case SK_RAMSIZE_2048K_128: 1518 sc->sk_ramsize = 0x200000; 1519 sc->sk_rboff = SK_RBOFF_0; 1520 break; 1521 default: 1522 printf("%s: unknown ram size: %d\n", 1523 sc->sk_dev.dv_xname, val); 1524 goto fail; 1525 break; 1526 } 1527 1528 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1529 sc->sk_ramsize, sc->sk_ramsize / 1024, 1530 sc->sk_rboff)); 1531 } else { 1532 sc->sk_ramsize = 0x20000; 1533 sc->sk_rboff = SK_RBOFF_0; 1534 1535 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1536 sc->sk_ramsize / 1024, sc->sk_ramsize, 1537 sc->sk_rboff)); 1538 } 1539 1540 /* Read and save physical media type */ 1541 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1542 case SK_PMD_1000BASESX: 1543 sc->sk_pmd = IFM_1000_SX; 1544 break; 1545 case SK_PMD_1000BASELX: 1546 sc->sk_pmd = IFM_1000_LX; 1547 break; 1548 case SK_PMD_1000BASECX: 1549 sc->sk_pmd = IFM_1000_CX; 1550 break; 1551 case SK_PMD_1000BASETX: 1552 sc->sk_pmd = IFM_1000_T; 1553 break; 1554 default: 1555 printf("%s: unknown media type: 0x%x\n", 1556 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1557 goto fail; 1558 } 1559 1560 /* Announce the product name. */ 1561 printf("%s: %s\n", sc->sk_dev.dv_xname, sc->sk_vpd_prodname); 1562 1563 skca.skc_port = SK_PORT_A; 1564 (void)config_found(&sc->sk_dev, &skca, skcprint); 1565 1566 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1567 skca.skc_port = SK_PORT_B; 1568 (void)config_found(&sc->sk_dev, &skca, skcprint); 1569 } 1570 1571 /* Turn on the 'driver is loaded' LED. */ 1572 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1573 1574fail: 1575 splx(s); 1576} 1577 1578int 1579sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1580{ 1581 struct sk_softc *sc = sc_if->sk_softc; 1582 struct sk_tx_desc *f = NULL; 1583 u_int32_t frag, cur, cnt = 0; 1584 int i; 1585 struct sk_txmap_entry *entry; 1586 bus_dmamap_t txmap; 1587 1588 DPRINTFN(2, ("sk_encap\n")); 1589 1590 entry = SLIST_FIRST(&sc_if->sk_txmap_listhead); 1591 if (entry == NULL) { 1592 DPRINTFN(2, ("sk_encap: no txmap available\n")); 1593 return ENOBUFS; 1594 } 1595 txmap = entry->dmamap; 1596 1597 cur = frag = *txidx; 1598 1599#ifdef SK_DEBUG 1600 if (skdebug >= 2) 1601 sk_dump_mbuf(m_head); 1602#endif 1603 1604 /* 1605 * Start packing the mbufs in this chain into 1606 * the fragment pointers. Stop when we run out 1607 * of fragments or hit the end of the mbuf chain. 1608 */ 1609 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1610 BUS_DMA_NOWAIT)) { 1611 DPRINTFN(2, ("sk_encap: dmamap failed\n")); 1612 return(ENOBUFS); 1613 } 1614 1615 DPRINTFN(2, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1616 1617 for (i = 0; i < txmap->dm_nsegs; i++) { 1618 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1619 DPRINTFN(2, ("sk_encap: too few descriptors free\n")); 1620 return(ENOBUFS); 1621 } 1622 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1623 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1624 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1625 if (cnt == 0) 1626 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1627 else 1628 f->sk_ctl |= SK_TXCTL_OWN; 1629 1630 cur = frag; 1631 SK_INC(frag, SK_TX_RING_CNT); 1632 cnt++; 1633 } 1634 1635 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1636 SLIST_REMOVE_HEAD(&sc_if->sk_txmap_listhead, link); 1637 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1638 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1639 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1640 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1641 sc_if->sk_cdata.sk_tx_cnt += cnt; 1642 1643#ifdef SK_DEBUG 1644 if (skdebug >= 2) { 1645 struct sk_tx_desc *desc; 1646 u_int32_t idx; 1647 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1648 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1649 sk_dump_txdesc(desc, idx); 1650 } 1651 } 1652#endif 1653 1654 *txidx = frag; 1655 1656 DPRINTFN(2, ("sk_encap: completed successfully\n")); 1657 1658 return(0); 1659} 1660 1661void 1662sk_start(struct ifnet *ifp) 1663{ 1664 struct sk_if_softc *sc_if = ifp->if_softc; 1665 struct sk_softc *sc = sc_if->sk_softc; 1666 struct mbuf *m_head = NULL; 1667 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1668 int pkts = 0; 1669 1670 DPRINTFN(2, ("sk_start\n")); 1671 1672 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1673 IFQ_POLL(&ifp->if_snd, m_head); 1674 if (m_head == NULL) 1675 break; 1676 1677 /* 1678 * Pack the data into the transmit ring. If we 1679 * don't have room, set the OACTIVE flag and wait 1680 * for the NIC to drain the ring. 1681 */ 1682 if (sk_encap(sc_if, m_head, &idx)) { 1683 ifp->if_flags |= IFF_OACTIVE; 1684 break; 1685 } 1686 1687 /* now we are committed to transmit the packet */ 1688 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1689 pkts++; 1690 1691 /* 1692 * If there's a BPF listener, bounce a copy of this frame 1693 * to him. 1694 */ 1695#if NBPFILTER > 0 1696 if (ifp->if_bpf) 1697 bpf_mtap(ifp->if_bpf, m_head); 1698#endif 1699 } 1700 if (pkts == 0) 1701 return; 1702 1703 /* Transmit */ 1704 sc_if->sk_cdata.sk_tx_prod = idx; 1705 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1706 1707 /* Set a timeout in case the chip goes out to lunch. */ 1708 ifp->if_timer = 5; 1709} 1710 1711 1712void 1713sk_watchdog(struct ifnet *ifp) 1714{ 1715 struct sk_if_softc *sc_if = ifp->if_softc; 1716 1717 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1718 sk_init(sc_if); 1719} 1720 1721void 1722sk_shutdown(void *v) 1723{ 1724 struct sk_softc *sc = v; 1725 1726 DPRINTFN(2, ("sk_shutdown\n")); 1727 1728 /* Turn off the 'driver is loaded' LED. */ 1729 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1730 1731 /* 1732 * Reset the GEnesis controller. Doing this should also 1733 * assert the resets on the attached XMAC(s). 1734 */ 1735 sk_reset(sc); 1736} 1737 1738void 1739sk_rxeof(struct sk_if_softc *sc_if) 1740{ 1741 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1742 struct mbuf *m; 1743 struct sk_chain *cur_rx; 1744 struct sk_rx_desc *cur_desc; 1745 int i, cur, total_len = 0; 1746 u_int32_t rxstat; 1747 bus_dmamap_t dmamap; 1748 u_int16_t csum1, csum2; 1749 1750 DPRINTFN(2, ("sk_rxeof\n")); 1751 1752 i = sc_if->sk_cdata.sk_rx_prod; 1753 1754 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1755 cur = i; 1756 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1757 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1758 1759 rxstat = cur_desc->sk_xmac_rxstat; 1760 m = cur_rx->sk_mbuf; 1761 cur_rx->sk_mbuf = NULL; 1762 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1763 1764 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1765 1766 csum1 = sc_if->sk_rdata->sk_rx_ring[i].sk_csum1; 1767 csum2 = sc_if->sk_rdata->sk_rx_ring[i].sk_csum2; 1768 1769 SK_INC(i, SK_RX_RING_CNT); 1770 1771 if (rxstat & XM_RXSTAT_ERRFRAME) { 1772 ifp->if_ierrors++; 1773 sk_newbuf(sc_if, cur, m, dmamap); 1774 continue; 1775 } 1776 1777 /* 1778 * Try to allocate a new jumbo buffer. If that 1779 * fails, copy the packet to mbufs and put the 1780 * jumbo buffer back in the ring so it can be 1781 * re-used. If allocating mbufs fails, then we 1782 * have to drop the packet. 1783 */ 1784 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1785 struct mbuf *m0; 1786 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1787 total_len + ETHER_ALIGN, 0, ifp, NULL); 1788 sk_newbuf(sc_if, cur, m, dmamap); 1789 if (m0 == NULL) { 1790 ifp->if_ierrors++; 1791 continue; 1792 } 1793 m_adj(m0, ETHER_ALIGN); 1794 m = m0; 1795 } else { 1796 m->m_pkthdr.rcvif = ifp; 1797 m->m_pkthdr.len = m->m_len = total_len; 1798 } 1799 1800 ifp->if_ipackets++; 1801 1802 sk_rxcsum(ifp, m, csum1, csum2); 1803 1804#if NBPFILTER > 0 1805 if (ifp->if_bpf) 1806 bpf_mtap(ifp->if_bpf, m); 1807#endif 1808 1809 /* pass it on. */ 1810 ether_input_mbuf(ifp, m); 1811 } 1812 1813 sc_if->sk_cdata.sk_rx_prod = i; 1814} 1815 1816void 1817sk_rxcsum(struct ifnet *ifp, struct mbuf *m, const u_int16_t csum1, const u_int16_t csum2) 1818{ 1819 struct ether_header *eh; 1820 struct ip *ip; 1821 u_int8_t *pp; 1822 int hlen, len, plen; 1823 u_int16_t iph_csum, ipo_csum, ipd_csum, csum; 1824 1825 pp = mtod(m, u_int8_t *); 1826 plen = m->m_pkthdr.len; 1827 if (plen < sizeof(*eh)) 1828 return; 1829 eh = (struct ether_header *)pp; 1830 iph_csum = in_cksum_addword(csum1, (~csum2 & 0xffff)); 1831 1832 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1833 u_int16_t *xp = (u_int16_t *)pp; 1834 1835 xp = (u_int16_t *)pp; 1836 if (xp[1] != htons(ETHERTYPE_IP)) 1837 return; 1838 iph_csum = in_cksum_addword(iph_csum, (~xp[0] & 0xffff)); 1839 iph_csum = in_cksum_addword(iph_csum, (~xp[1] & 0xffff)); 1840 xp = (u_int16_t *)(pp + sizeof(struct ip)); 1841 iph_csum = in_cksum_addword(iph_csum, xp[0]); 1842 iph_csum = in_cksum_addword(iph_csum, xp[1]); 1843 pp += EVL_ENCAPLEN; 1844 } else if (eh->ether_type != htons(ETHERTYPE_IP)) 1845 return; 1846 1847 pp += sizeof(*eh); 1848 plen -= sizeof(*eh); 1849 1850 ip = (struct ip *)pp; 1851 1852 if (ip->ip_v != IPVERSION) 1853 return; 1854 1855 hlen = ip->ip_hl << 2; 1856 if (hlen < sizeof(struct ip)) 1857 return; 1858 if (hlen > ntohs(ip->ip_len)) 1859 return; 1860 1861 /* Don't deal with truncated or padded packets. */ 1862 if (plen != ntohs(ip->ip_len)) 1863 return; 1864 1865 len = hlen - sizeof(struct ip); 1866 if (len > 0) { 1867 u_int16_t *p; 1868 1869 p = (u_int16_t *)(ip + 1); 1870 ipo_csum = 0; 1871 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++) 1872 ipo_csum = in_cksum_addword(ipo_csum, *p); 1873 iph_csum = in_cksum_addword(iph_csum, ipo_csum); 1874 ipd_csum = in_cksum_addword(csum2, (~ipo_csum & 0xffff)); 1875 } else 1876 ipd_csum = csum2; 1877 1878 if (iph_csum != 0xffff) { 1879 if (ifp->if_bpf) 1880 bpf_mtap(ifp->if_bpf, m); 1881 return; 1882 } 1883 m->m_pkthdr.csum |= M_IPV4_CSUM_IN_OK; 1884 1885 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1886 return; /* ip frag, we're done for now */ 1887 1888 pp += hlen; 1889 1890 /* Only know checksum protocol for udp/tcp */ 1891 if (ip->ip_p == IPPROTO_UDP) { 1892 struct udphdr *uh = (struct udphdr *)pp; 1893 1894 if (uh->uh_sum == 0) /* udp with no checksum */ 1895 return; 1896 } else if (ip->ip_p != IPPROTO_TCP) 1897 return; 1898 1899 csum = in_cksum_phdr(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1900 htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum); 1901 if (csum == 0xffff) { 1902 m->m_pkthdr.csum |= (ip->ip_p == IPPROTO_TCP) ? 1903 M_TCP_CSUM_IN_OK : M_UDP_CSUM_IN_OK; 1904 } 1905} 1906 1907void 1908sk_txeof(struct sk_if_softc *sc_if) 1909{ 1910 struct sk_softc *sc = sc_if->sk_softc; 1911 struct sk_tx_desc *cur_tx = NULL; 1912 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1913 u_int32_t idx; 1914 struct sk_txmap_entry *entry; 1915 1916 DPRINTFN(2, ("sk_txeof\n")); 1917 1918 /* 1919 * Go through our tx ring and free mbufs for those 1920 * frames that have been sent. 1921 */ 1922 idx = sc_if->sk_cdata.sk_tx_cons; 1923 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1924 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1925#ifdef SK_DEBUG 1926 if (skdebug >= 2) 1927 sk_dump_txdesc(cur_tx, idx); 1928#endif 1929 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1930 break; 1931 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1932 ifp->if_opackets++; 1933 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1934 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1935 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1936 1937 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1938 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1939 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1940 1941 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1942 SLIST_INSERT_HEAD(&sc_if->sk_txmap_listhead, entry, 1943 link); 1944 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1945 } 1946 sc_if->sk_cdata.sk_tx_cnt--; 1947 SK_INC(idx, SK_TX_RING_CNT); 1948 ifp->if_timer = 0; 1949 } 1950 1951 sc_if->sk_cdata.sk_tx_cons = idx; 1952 1953 if (cur_tx != NULL) 1954 ifp->if_flags &= ~IFF_OACTIVE; 1955} 1956 1957void 1958sk_tick(void *xsc_if) 1959{ 1960 struct sk_if_softc *sc_if = xsc_if; 1961 struct mii_data *mii = &sc_if->sk_mii; 1962 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1963 int i; 1964 1965 DPRINTFN(2, ("sk_tick\n")); 1966 1967 if (!(ifp->if_flags & IFF_UP)) 1968 return; 1969 1970 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1971 sk_intr_bcom(sc_if); 1972 return; 1973 } 1974 1975 /* 1976 * According to SysKonnect, the correct way to verify that 1977 * the link has come back up is to poll bit 0 of the GPIO 1978 * register three times. This pin has the signal from the 1979 * link sync pin connected to it; if we read the same link 1980 * state 3 times in a row, we know the link is up. 1981 */ 1982 for (i = 0; i < 3; i++) { 1983 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1984 break; 1985 } 1986 1987 if (i != 3) { 1988 timeout_add(&sc_if->sk_tick_ch, hz); 1989 return; 1990 } 1991 1992 /* Turn the GP0 interrupt back on. */ 1993 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1994 SK_XM_READ_2(sc_if, XM_ISR); 1995 mii_tick(mii); 1996 mii_pollstat(mii); 1997 timeout_del(&sc_if->sk_tick_ch); 1998} 1999 2000void 2001sk_intr_bcom(struct sk_if_softc *sc_if) 2002{ 2003 struct mii_data *mii = &sc_if->sk_mii; 2004 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2005 int status; 2006 2007 2008 DPRINTFN(2, ("sk_intr_bcom\n")); 2009 2010 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2011 2012 /* 2013 * Read the PHY interrupt register to make sure 2014 * we clear any pending interrupts. 2015 */ 2016 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2017 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2018 2019 if (!(ifp->if_flags & IFF_RUNNING)) { 2020 sk_init_xmac(sc_if); 2021 return; 2022 } 2023 2024 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2025 int lstat; 2026 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2027 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2028 2029 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2030 mii_mediachg(mii); 2031 /* Turn off the link LED. */ 2032 SK_IF_WRITE_1(sc_if, 0, 2033 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2034 sc_if->sk_link = 0; 2035 } else if (status & BRGPHY_ISR_LNK_CHG) { 2036 sk_xmac_miibus_writereg((struct device *)sc_if, 2037 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2038 mii_tick(mii); 2039 sc_if->sk_link = 1; 2040 /* Turn on the link LED. */ 2041 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2042 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2043 SK_LINKLED_BLINK_OFF); 2044 mii_pollstat(mii); 2045 } else { 2046 mii_tick(mii); 2047 timeout_add(&sc_if->sk_tick_ch, hz); 2048 } 2049 } 2050 2051 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2052} 2053 2054void 2055sk_intr_xmac(struct sk_if_softc *sc_if) 2056{ 2057 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2058 2059 DPRINTFN(2, ("sk_intr_xmac\n")); 2060 2061 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2062 if (status & XM_ISR_GP0_SET) { 2063 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2064 timeout_add(&sc_if->sk_tick_ch, hz); 2065 } 2066 2067 if (status & XM_ISR_AUTONEG_DONE) { 2068 timeout_add(&sc_if->sk_tick_ch, hz); 2069 } 2070 } 2071 2072 if (status & XM_IMR_TX_UNDERRUN) 2073 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2074 2075 if (status & XM_IMR_RX_OVERRUN) 2076 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2077} 2078 2079void 2080sk_intr_yukon(sc_if) 2081 struct sk_if_softc *sc_if; 2082{ 2083 int status; 2084 2085 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2086 2087 DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status)); 2088} 2089 2090int 2091sk_intr(void *xsc) 2092{ 2093 struct sk_softc *sc = xsc; 2094 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2095 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2096 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2097 u_int32_t status; 2098 int claimed = 0; 2099 2100 if (sc_if0 != NULL) 2101 ifp0 = &sc_if0->arpcom.ac_if; 2102 if (sc_if1 != NULL) 2103 ifp1 = &sc_if1->arpcom.ac_if; 2104 2105 for (;;) { 2106 status = CSR_READ_4(sc, SK_ISSR); 2107 DPRINTFN(2, ("sk_intr: status=%#x\n", status)); 2108 2109 if (!(status & sc->sk_intrmask)) 2110 break; 2111 2112 claimed = 1; 2113 2114 /* Handle receive interrupts first. */ 2115 if (status & SK_ISR_RX1_EOF) { 2116 sk_rxeof(sc_if0); 2117 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2118 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2119 } 2120 if (status & SK_ISR_RX2_EOF) { 2121 sk_rxeof(sc_if1); 2122 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2123 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2124 } 2125 2126 /* Then transmit interrupts. */ 2127 if (status & SK_ISR_TX1_S_EOF) { 2128 sk_txeof(sc_if0); 2129 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2130 SK_TXBMU_CLR_IRQ_EOF); 2131 } 2132 if (status & SK_ISR_TX2_S_EOF) { 2133 sk_txeof(sc_if1); 2134 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2135 SK_TXBMU_CLR_IRQ_EOF); 2136 } 2137 2138 /* Then MAC interrupts. */ 2139 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 2140 if (sc->sk_type == SK_GENESIS) 2141 sk_intr_xmac(sc_if0); 2142 else 2143 sk_intr_yukon(sc_if0); 2144 } 2145 2146 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 2147 if (sc->sk_type == SK_GENESIS) 2148 sk_intr_xmac(sc_if1); 2149 else 2150 sk_intr_yukon(sc_if1); 2151 2152 } 2153 2154 if (status & SK_ISR_EXTERNAL_REG) { 2155 if (ifp0 != NULL && 2156 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2157 sk_intr_bcom(sc_if0); 2158 2159 if (ifp1 != NULL && 2160 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2161 sk_intr_bcom(sc_if1); 2162 } 2163 } 2164 2165 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2166 2167 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2168 sk_start(ifp0); 2169 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2170 sk_start(ifp1); 2171 2172 return (claimed); 2173} 2174 2175void 2176sk_init_xmac(struct sk_if_softc *sc_if) 2177{ 2178 struct sk_softc *sc = sc_if->sk_softc; 2179 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2180 struct sk_bcom_hack bhack[] = { 2181 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2182 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2183 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2184 { 0, 0 } }; 2185 2186 DPRINTFN(2, ("sk_init_xmac\n")); 2187 2188 /* Unreset the XMAC. */ 2189 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2190 DELAY(1000); 2191 2192 /* Reset the XMAC's internal state. */ 2193 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2194 2195 /* Save the XMAC II revision */ 2196 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2197 2198 /* 2199 * Perform additional initialization for external PHYs, 2200 * namely for the 1000baseTX cards that use the XMAC's 2201 * GMII mode. 2202 */ 2203 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2204 int i = 0; 2205 u_int32_t val; 2206 2207 /* Take PHY out of reset. */ 2208 val = sk_win_read_4(sc, SK_GPIO); 2209 if (sc_if->sk_port == SK_PORT_A) 2210 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2211 else 2212 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2213 sk_win_write_4(sc, SK_GPIO, val); 2214 2215 /* Enable GMII mode on the XMAC. */ 2216 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2217 2218 sk_xmac_miibus_writereg((struct device *)sc_if, 2219 SK_PHYADDR_BCOM, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2220 DELAY(10000); 2221 sk_xmac_miibus_writereg((struct device *)sc_if, 2222 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2223 2224 /* 2225 * Early versions of the BCM5400 apparently have 2226 * a bug that requires them to have their reserved 2227 * registers initialized to some magic values. I don't 2228 * know what the numbers do, I'm just the messenger. 2229 */ 2230 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2231 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2232 while(bhack[i].reg) { 2233 sk_xmac_miibus_writereg((struct device *)sc_if, 2234 SK_PHYADDR_BCOM, bhack[i].reg, 2235 bhack[i].val); 2236 i++; 2237 } 2238 } 2239 } 2240 2241 /* Set station address */ 2242 SK_XM_WRITE_2(sc_if, XM_PAR0, 2243 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2244 SK_XM_WRITE_2(sc_if, XM_PAR1, 2245 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2246 SK_XM_WRITE_2(sc_if, XM_PAR2, 2247 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2248 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2249 2250 if (ifp->if_flags & IFF_PROMISC) { 2251 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2252 } else { 2253 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2254 } 2255 2256 if (ifp->if_flags & IFF_BROADCAST) { 2257 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2258 } else { 2259 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2260 } 2261 2262 /* We don't need the FCS appended to the packet. */ 2263 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2264 2265 /* We want short frames padded to 60 bytes. */ 2266 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2267 2268 /* 2269 * Enable the reception of all error frames. This is is 2270 * a necessary evil due to the design of the XMAC. The 2271 * XMAC's receive FIFO is only 8K in size, however jumbo 2272 * frames can be up to 9000 bytes in length. When bad 2273 * frame filtering is enabled, the XMAC's RX FIFO operates 2274 * in 'store and forward' mode. For this to work, the 2275 * entire frame has to fit into the FIFO, but that means 2276 * that jumbo frames larger than 8192 bytes will be 2277 * truncated. Disabling all bad frame filtering causes 2278 * the RX FIFO to operate in streaming mode, in which 2279 * case the XMAC will start transfering frames out of the 2280 * RX FIFO as soon as the FIFO threshold is reached. 2281 */ 2282 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2283 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2284 XM_MODE_RX_INRANGELEN); 2285 2286 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2287 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2288 else 2289 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2290 2291 /* 2292 * Bump up the transmit threshold. This helps hold off transmit 2293 * underruns when we're blasting traffic from both ports at once. 2294 */ 2295 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2296 2297 /* Set multicast filter */ 2298 sk_setmulti(sc_if); 2299 2300 /* Clear and enable interrupts */ 2301 SK_XM_READ_2(sc_if, XM_ISR); 2302 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2303 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2304 else 2305 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2306 2307 /* Configure MAC arbiter */ 2308 switch(sc_if->sk_xmac_rev) { 2309 case XM_XMAC_REV_B2: 2310 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2311 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2312 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2313 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2314 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2315 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2316 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2317 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2318 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2319 break; 2320 case XM_XMAC_REV_C1: 2321 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2322 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2323 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2324 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2325 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2326 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2327 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2328 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2329 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2330 break; 2331 default: 2332 break; 2333 } 2334 sk_win_write_2(sc, SK_MACARB_CTL, 2335 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2336 2337 sc_if->sk_link = 1; 2338} 2339 2340void sk_init_yukon(sc_if) 2341 struct sk_if_softc *sc_if; 2342{ 2343 u_int32_t /*mac, */phy; 2344 u_int16_t reg; 2345 int i; 2346 2347 DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n", 2348 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2349 2350 /* GMAC and GPHY Reset */ 2351 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2352 2353 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2354 2355 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2356 DELAY(1000); 2357 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2358 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2359 DELAY(1000); 2360 2361 2362 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2363 2364 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2365 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2366 2367 switch(sc_if->sk_softc->sk_pmd) { 2368 case IFM_1000_SX: 2369 case IFM_1000_LX: 2370 phy |= SK_GPHY_FIBER; 2371 break; 2372 2373 case IFM_1000_CX: 2374 case IFM_1000_T: 2375 phy |= SK_GPHY_COPPER; 2376 break; 2377 } 2378 2379 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2380 2381 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2382 DELAY(1000); 2383 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2384 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2385 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2386 2387 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2388 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2389 2390 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2391 2392 /* unused read of the interrupt source register */ 2393 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2394 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2395 2396 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2397 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2398 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2399 2400 /* MIB Counter Clear Mode set */ 2401 reg |= YU_PAR_MIB_CLR; 2402 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2403 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2404 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2405 2406 /* MIB Counter Clear Mode clear */ 2407 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2408 reg &= ~YU_PAR_MIB_CLR; 2409 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2410 2411 /* receive control reg */ 2412 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2413 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2414 YU_RCR_CRCR); 2415 2416 /* transmit parameter register */ 2417 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2418 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2419 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2420 2421 /* serial mode register */ 2422 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2423 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2424 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2425 2426 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2427 /* Setup Yukon's address */ 2428 for (i = 0; i < 3; i++) { 2429 /* Write Source Address 1 (unicast filter) */ 2430 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2431 sc_if->arpcom.ac_enaddr[i * 2] | 2432 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2433 } 2434 2435 for (i = 0; i < 3; i++) { 2436 reg = sk_win_read_2(sc_if->sk_softc, 2437 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2438 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2439 } 2440 2441 /* Set multicast filter */ 2442 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2443 sk_setmulti(sc_if); 2444 2445 /* enable interrupt mask for counter overflows */ 2446 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2447 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2448 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2449 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2450 2451 /* Configure RX MAC FIFO */ 2452 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2453 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2454 2455 /* Configure TX MAC FIFO */ 2456 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2457 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2458 2459 DPRINTFN(6, ("sk_init_yukon: end\n")); 2460} 2461 2462/* 2463 * Note that to properly initialize any part of the GEnesis chip, 2464 * you first have to take it out of reset mode. 2465 */ 2466void 2467sk_init(void *xsc_if) 2468{ 2469 struct sk_if_softc *sc_if = xsc_if; 2470 struct sk_softc *sc = sc_if->sk_softc; 2471 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2472 struct mii_data *mii = &sc_if->sk_mii; 2473 int s; 2474 2475 DPRINTFN(2, ("sk_init\n")); 2476 2477 s = splimp(); 2478 2479 /* Cancel pending I/O and free all RX/TX buffers. */ 2480 sk_stop(sc_if); 2481 2482 if (sc->sk_type == SK_GENESIS) { 2483 /* Configure LINK_SYNC LED */ 2484 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2485 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2486 SK_LINKLED_LINKSYNC_ON); 2487 2488 /* Configure RX LED */ 2489 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2490 SK_RXLEDCTL_COUNTER_START); 2491 2492 /* Configure TX LED */ 2493 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2494 SK_TXLEDCTL_COUNTER_START); 2495 } 2496 2497 /* Configure I2C registers */ 2498 2499 /* Configure XMAC(s) */ 2500 switch (sc->sk_type) { 2501 case SK_GENESIS: 2502 sk_init_xmac(sc_if); 2503 break; 2504 case SK_YUKON: 2505 sk_init_yukon(sc_if); 2506 break; 2507 } 2508 mii_mediachg(mii); 2509 2510 if (sc->sk_type == SK_GENESIS) { 2511 /* Configure MAC FIFOs */ 2512 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2513 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2514 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2515 2516 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2517 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2518 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2519 } 2520 2521 /* Configure transmit arbiter(s) */ 2522 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2523 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2524 2525 /* Configure RAMbuffers */ 2526 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2527 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2528 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2529 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2530 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2531 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2532 2533 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2534 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2535 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2536 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2537 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2538 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2539 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2540 2541 /* Configure BMUs */ 2542 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2543 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2544 SK_RX_RING_ADDR(sc_if, 0)); 2545 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2546 2547 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2548 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2549 SK_TX_RING_ADDR(sc_if, 0)); 2550 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2551 2552 /* Init descriptors */ 2553 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2554 printf("%s: initialization failed: no " 2555 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2556 sk_stop(sc_if); 2557 splx(s); 2558 return; 2559 } 2560 2561 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2562 printf("%s: initialization failed: no " 2563 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2564 sk_stop(sc_if); 2565 splx(s); 2566 return; 2567 } 2568 2569 /* Configure interrupt handling */ 2570 CSR_READ_4(sc, SK_ISSR); 2571 if (sc_if->sk_port == SK_PORT_A) 2572 sc->sk_intrmask |= SK_INTRS1; 2573 else 2574 sc->sk_intrmask |= SK_INTRS2; 2575 2576 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2577 2578 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2579 2580 /* Start BMUs. */ 2581 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2582 2583 if (sc->sk_type == SK_GENESIS) { 2584 /* Enable XMACs TX and RX state machines */ 2585 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2586 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2587 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2588 } 2589 2590 if (sc->sk_type == SK_YUKON) { 2591 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2592 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2593 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2594 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2595 } 2596 2597 2598 ifp->if_flags |= IFF_RUNNING; 2599 ifp->if_flags &= ~IFF_OACTIVE; 2600 2601 splx(s); 2602} 2603 2604void 2605sk_stop(struct sk_if_softc *sc_if) 2606{ 2607 struct sk_softc *sc = sc_if->sk_softc; 2608 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2609 int i; 2610 2611 DPRINTFN(2, ("sk_stop\n")); 2612 2613 timeout_del(&sc_if->sk_tick_ch); 2614 2615 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2616 u_int32_t val; 2617 2618 /* Put PHY back into reset. */ 2619 val = sk_win_read_4(sc, SK_GPIO); 2620 if (sc_if->sk_port == SK_PORT_A) { 2621 val |= SK_GPIO_DIR0; 2622 val &= ~SK_GPIO_DAT0; 2623 } else { 2624 val |= SK_GPIO_DIR2; 2625 val &= ~SK_GPIO_DAT2; 2626 } 2627 sk_win_write_4(sc, SK_GPIO, val); 2628 } 2629 2630 /* Turn off various components of this interface. */ 2631 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2632 switch (sc->sk_type) { 2633 case SK_GENESIS: 2634 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2635 SK_TXMACCTL_XMAC_RESET); 2636 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2637 break; 2638 case SK_YUKON: 2639 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2640 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2641 break; 2642 } 2643 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2644 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2645 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2646 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2647 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2648 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2649 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2650 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2651 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2652 2653 /* Disable interrupts */ 2654 if (sc_if->sk_port == SK_PORT_A) 2655 sc->sk_intrmask &= ~SK_INTRS1; 2656 else 2657 sc->sk_intrmask &= ~SK_INTRS2; 2658 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2659 2660 SK_XM_READ_2(sc_if, XM_ISR); 2661 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2662 2663 /* Free RX and TX mbufs still in the queues. */ 2664 for (i = 0; i < SK_RX_RING_CNT; i++) { 2665 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2666 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2667 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2668 } 2669 } 2670 2671 for (i = 0; i < SK_TX_RING_CNT; i++) { 2672 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2673 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2674 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2675 } 2676 } 2677 2678 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2679} 2680 2681struct cfattach skc_ca = { 2682 sizeof(struct sk_softc), skc_probe, skc_attach, 2683}; 2684 2685struct cfdriver skc_cd = { 2686 0, "skc", DV_DULL 2687}; 2688 2689struct cfattach sk_ca = { 2690 sizeof(struct sk_if_softc), sk_probe, sk_attach, 2691}; 2692 2693struct cfdriver sk_cd = { 2694 0, "sk", DV_IFNET 2695}; 2696 2697#ifdef SK_DEBUG 2698void 2699sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2700{ 2701#define DESC_PRINT(X) \ 2702 if (desc->X) \ 2703 printf("txdesc[%d]." #X "=%#x\n", \ 2704 idx, desc->X); 2705 2706 DESC_PRINT(sk_ctl); 2707 DESC_PRINT(sk_next); 2708 DESC_PRINT(sk_data_lo); 2709 DESC_PRINT(sk_data_hi); 2710 DESC_PRINT(sk_xmac_txstat); 2711 DESC_PRINT(sk_rsvd0); 2712 DESC_PRINT(sk_csum_startval); 2713 DESC_PRINT(sk_csum_startpos); 2714 DESC_PRINT(sk_csum_writepos); 2715 DESC_PRINT(sk_rsvd1); 2716#undef PRINT 2717} 2718 2719void 2720sk_dump_bytes(const char *data, int len) 2721{ 2722 int c, i, j; 2723 2724 for (i = 0; i < len; i += 16) { 2725 printf("%08x ", i); 2726 c = len - i; 2727 if (c > 16) c = 16; 2728 2729 for (j = 0; j < c; j++) { 2730 printf("%02x ", data[i + j] & 0xff); 2731 if ((j & 0xf) == 7 && j > 0) 2732 printf(" "); 2733 } 2734 2735 for (; j < 16; j++) 2736 printf(" "); 2737 printf(" "); 2738 2739 for (j = 0; j < c; j++) { 2740 int ch = data[i + j] & 0xff; 2741 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2742 } 2743 2744 printf("\n"); 2745 2746 if (c < 16) 2747 break; 2748 } 2749} 2750 2751void 2752sk_dump_mbuf(struct mbuf *m) 2753{ 2754 int count = m->m_pkthdr.len; 2755 2756 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2757 2758 while (count > 0 && m) { 2759 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2760 m, m->m_data, m->m_len); 2761 sk_dump_bytes(mtod(m, char *), m->m_len); 2762 2763 count -= m->m_len; 2764 m = m->m_next; 2765 } 2766} 2767#endif 2768