if_sk.c revision 1.42
1/* $OpenBSD: if_sk.c,v 1.42 2004/08/04 19:37:26 mcbride Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37/* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53/* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72/* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89#include "bpfilter.h" 90 91#include <sys/param.h> 92#include <sys/systm.h> 93#include <sys/sockio.h> 94#include <sys/mbuf.h> 95#include <sys/malloc.h> 96#include <sys/kernel.h> 97#include <sys/socket.h> 98#include <sys/device.h> 99#include <sys/queue.h> 100 101#include <net/if.h> 102#include <net/if_dl.h> 103#include <net/if_types.h> 104 105#ifdef INET 106#include <netinet/in.h> 107#include <netinet/in_systm.h> 108#include <netinet/in_var.h> 109#include <netinet/ip.h> 110#include <netinet/udp.h> 111#include <netinet/tcp.h> 112#include <netinet/if_ether.h> 113#endif 114 115#include <net/if_media.h> 116#include <net/if_vlan_var.h> 117 118#if NBPFILTER > 0 119#include <net/bpf.h> 120#endif 121 122#include <dev/mii/mii.h> 123#include <dev/mii/miivar.h> 124#include <dev/mii/brgphyreg.h> 125 126#include <dev/pci/pcireg.h> 127#include <dev/pci/pcivar.h> 128#include <dev/pci/pcidevs.h> 129 130#define SK_VERBOSE 131/* #define SK_USEIOSPACE */ 132 133#include <dev/pci/if_skreg.h> 134#include <dev/pci/xmaciireg.h> 135#include <dev/pci/yukonreg.h> 136 137int skc_probe(struct device *, void *, void *); 138void skc_attach(struct device *, struct device *self, void *aux); 139int sk_probe(struct device *, void *, void *); 140void sk_attach(struct device *, struct device *self, void *aux); 141int skcprint(void *, const char *); 142int sk_intr(void *); 143void sk_intr_bcom(struct sk_if_softc *); 144void sk_intr_xmac(struct sk_if_softc *); 145void sk_intr_yukon(struct sk_if_softc *); 146void sk_rxeof(struct sk_if_softc *); 147void sk_txeof(struct sk_if_softc *); 148int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 149void sk_start(struct ifnet *); 150int sk_ioctl(struct ifnet *, u_long, caddr_t); 151void sk_init(void *); 152void sk_init_xmac(struct sk_if_softc *); 153void sk_init_yukon(struct sk_if_softc *); 154void sk_stop(struct sk_if_softc *); 155void sk_watchdog(struct ifnet *); 156void sk_shutdown(void *); 157int sk_ifmedia_upd(struct ifnet *); 158void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 159void sk_reset(struct sk_softc *); 160int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 161int sk_alloc_jumbo_mem(struct sk_if_softc *); 162void sk_free_jumbo_mem(struct sk_if_softc *); 163void *sk_jalloc(struct sk_if_softc *); 164void sk_jfree(caddr_t, u_int, void *); 165int sk_init_rx_ring(struct sk_if_softc *); 166int sk_init_tx_ring(struct sk_if_softc *); 167u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 168void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int); 169void sk_vpd_read(struct sk_softc *); 170 171int sk_xmac_miibus_readreg(struct device *, int, int); 172void sk_xmac_miibus_writereg(struct device *, int, int, int); 173void sk_xmac_miibus_statchg(struct device *); 174 175int sk_marv_miibus_readreg(struct device *, int, int); 176void sk_marv_miibus_writereg(struct device *, int, int, int); 177void sk_marv_miibus_statchg(struct device *); 178 179u_int32_t sk_xmac_hash(caddr_t); 180u_int32_t sk_yukon_hash(caddr_t); 181void sk_setfilt(struct sk_if_softc *, caddr_t, int); 182void sk_setmulti(struct sk_if_softc *); 183void sk_tick(void *); 184void sk_rxcsum(struct ifnet *, struct mbuf *, const u_int16_t, const u_int16_t); 185 186#ifdef SK_DEBUG 187#define DPRINTF(x) if (skdebug) printf x 188#define DPRINTFN(n,x) if (skdebug >= (n)) printf x 189int skdebug = 0; 190 191void sk_dump_txdesc(struct sk_tx_desc *, int); 192void sk_dump_mbuf(struct mbuf *); 193void sk_dump_bytes(const char *, int); 194#else 195#define DPRINTF(x) 196#define DPRINTFN(n,x) 197#endif 198 199#define SK_SETBIT(sc, reg, x) \ 200 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 201 202#define SK_CLRBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 204 205#define SK_WIN_SETBIT_4(sc, reg, x) \ 206 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 207 208#define SK_WIN_CLRBIT_4(sc, reg, x) \ 209 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 210 211#define SK_WIN_SETBIT_2(sc, reg, x) \ 212 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 213 214#define SK_WIN_CLRBIT_2(sc, reg, x) \ 215 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 216 217/* supported device vendors */ 218const struct pci_matchid skc_devices[] = { 219 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940}, 220 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T}, 221 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032}, 222 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064}, 223 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SK_V2}, 224 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_GE}, 225 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2}, 226}; 227 228static inline u_int32_t 229sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 230{ 231#ifdef SK_USEIOSPACE 232 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 233 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 234#else 235 return CSR_READ_4(sc, reg); 236#endif 237} 238 239static inline u_int16_t 240sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 241{ 242#ifdef SK_USEIOSPACE 243 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 244 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 245#else 246 return CSR_READ_2(sc, reg); 247#endif 248} 249 250static inline u_int8_t 251sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 252{ 253#ifdef SK_USEIOSPACE 254 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 255 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 256#else 257 return CSR_READ_1(sc, reg); 258#endif 259} 260 261static inline void 262sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 263{ 264#ifdef SK_USEIOSPACE 265 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 266 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 267#else 268 CSR_WRITE_4(sc, reg, x); 269#endif 270} 271 272static inline void 273sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 274{ 275#ifdef SK_USEIOSPACE 276 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 277 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 278#else 279 CSR_WRITE_2(sc, reg, x); 280#endif 281} 282 283static inline void 284sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 285{ 286#ifdef SK_USEIOSPACE 287 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 288 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 289#else 290 CSR_WRITE_1(sc, reg, x); 291#endif 292} 293 294/* 295 * The VPD EEPROM contains Vital Product Data, as suggested in 296 * the PCI 2.1 specification. The VPD data is separared into areas 297 * denoted by resource IDs. The SysKonnect VPD contains an ID string 298 * resource (the name of the adapter), a read-only area resource 299 * containing various key/data fields and a read/write area which 300 * can be used to store asset management information or log messages. 301 * We read the ID string and read-only into buffers attached to 302 * the controller softc structure for later use. At the moment, 303 * we only use the ID string during sk_attach(). 304 */ 305u_int8_t 306sk_vpd_readbyte(struct sk_softc *sc, int addr) 307{ 308 int i; 309 310 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 311 for (i = 0; i < SK_TIMEOUT; i++) { 312 DELAY(1); 313 if (sk_win_read_2(sc, 314 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 315 break; 316 } 317 318 if (i == SK_TIMEOUT) 319 return(0); 320 321 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 322} 323 324void 325sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 326{ 327 int i; 328 u_int8_t *ptr; 329 330 ptr = (u_int8_t *)res; 331 for (i = 0; i < sizeof(struct vpd_res); i++) 332 ptr[i] = sk_vpd_readbyte(sc, i + addr); 333} 334 335void 336sk_vpd_read(struct sk_softc *sc) 337{ 338 int pos = 0, i; 339 struct vpd_res res; 340 341 if (sc->sk_vpd_prodname != NULL) 342 free(sc->sk_vpd_prodname, M_DEVBUF); 343 if (sc->sk_vpd_readonly != NULL) 344 free(sc->sk_vpd_readonly, M_DEVBUF); 345 sc->sk_vpd_prodname = NULL; 346 sc->sk_vpd_readonly = NULL; 347 348 sk_vpd_read_res(sc, &res, pos); 349 350 if (res.vr_id != VPD_RES_ID) { 351 printf("%s: bad VPD resource id: expected %x got %x\n", 352 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 353 return; 354 } 355 356 pos += sizeof(res); 357 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 358 if (sc->sk_vpd_prodname == NULL) 359 panic("sk_vpd_read"); 360 for (i = 0; i < res.vr_len; i++) 361 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 362 sc->sk_vpd_prodname[i] = '\0'; 363 pos += i; 364 365 sk_vpd_read_res(sc, &res, pos); 366 367 if (res.vr_id != VPD_RES_READ) { 368 printf("%s: bad VPD resource id: expected %x got %x\n", 369 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 370 return; 371 } 372 373 pos += sizeof(res); 374 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 375 if (sc->sk_vpd_readonly == NULL) 376 panic("sk_vpd_read"); 377 for (i = 0; i < res.vr_len + 1; i++) 378 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 379} 380 381int 382sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 383{ 384 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 385 int i; 386 387 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 388 389 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 390 return(0); 391 392 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 393 SK_XM_READ_2(sc_if, XM_PHY_DATA); 394 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 395 for (i = 0; i < SK_TIMEOUT; i++) { 396 DELAY(1); 397 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 398 XM_MMUCMD_PHYDATARDY) 399 break; 400 } 401 402 if (i == SK_TIMEOUT) { 403 printf("%s: phy failed to come ready\n", 404 sc_if->sk_dev.dv_xname); 405 return(0); 406 } 407 } 408 DELAY(1); 409 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 410} 411 412void 413sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 414{ 415 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 416 int i; 417 418 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 419 420 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 421 for (i = 0; i < SK_TIMEOUT; i++) { 422 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 423 break; 424 } 425 426 if (i == SK_TIMEOUT) { 427 printf("%s: phy failed to come ready\n", 428 sc_if->sk_dev.dv_xname); 429 return; 430 } 431 432 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 433 for (i = 0; i < SK_TIMEOUT; i++) { 434 DELAY(1); 435 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 436 break; 437 } 438 439 if (i == SK_TIMEOUT) 440 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 441} 442 443void 444sk_xmac_miibus_statchg(struct device *dev) 445{ 446 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 447 struct mii_data *mii = &sc_if->sk_mii; 448 449 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 450 451 /* 452 * If this is a GMII PHY, manually set the XMAC's 453 * duplex mode accordingly. 454 */ 455 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 456 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 457 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 458 } else { 459 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 460 } 461 } 462} 463 464int 465sk_marv_miibus_readreg(dev, phy, reg) 466 struct device *dev; 467 int phy, reg; 468{ 469 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 470 u_int16_t val; 471 int i; 472 473 if (phy != 0 || 474 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 475 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 476 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 477 phy, reg)); 478 return(0); 479 } 480 481 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 482 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 483 484 for (i = 0; i < SK_TIMEOUT; i++) { 485 DELAY(1); 486 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 487 if (val & YU_SMICR_READ_VALID) 488 break; 489 } 490 491 if (i == SK_TIMEOUT) { 492 printf("%s: phy failed to come ready\n", 493 sc_if->sk_dev.dv_xname); 494 return 0; 495 } 496 497 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 498 SK_TIMEOUT)); 499 500 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 501 502 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 503 phy, reg, val)); 504 505 return val; 506} 507 508void 509sk_marv_miibus_writereg(dev, phy, reg, val) 510 struct device *dev; 511 int phy, reg, val; 512{ 513 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 514 int i; 515 516 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 517 phy, reg, val)); 518 519 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 520 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 521 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 522 523 for (i = 0; i < SK_TIMEOUT; i++) { 524 DELAY(1); 525 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 526 break; 527 } 528} 529 530void 531sk_marv_miibus_statchg(dev) 532 struct device *dev; 533{ 534 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 535 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 536} 537 538#define XMAC_POLY 0xEDB88320 539#define GMAC_POLY 0x04C11DB7L 540#define HASH_BITS 6 541 542u_int32_t 543sk_xmac_hash(caddr_t addr) 544{ 545 u_int32_t crc; 546 547 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 548 return (~crc & ((1 << HASH_BITS) - 1)); 549} 550 551u_int32_t 552sk_yukon_hash(caddr_t addr) 553{ 554 u_int32_t crc; 555 556 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 557 return (crc & ((1 << HASH_BITS) - 1)); 558} 559 560void 561sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 562{ 563 int base = XM_RXFILT_ENTRY(slot); 564 565 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 566 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 567 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 568} 569 570void 571sk_setmulti(struct sk_if_softc *sc_if) 572{ 573 struct sk_softc *sc = sc_if->sk_softc; 574 struct ifnet *ifp= &sc_if->arpcom.ac_if; 575 u_int32_t hashes[2] = { 0, 0 }; 576 int h, i; 577 struct arpcom *ac = &sc_if->arpcom; 578 struct ether_multi *enm; 579 struct ether_multistep step; 580 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 581 582 /* First, zot all the existing filters. */ 583 switch(sc->sk_type) { 584 case SK_GENESIS: 585 for (i = 1; i < XM_RXFILT_MAX; i++) 586 sk_setfilt(sc_if, (caddr_t)&dummy, i); 587 588 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 589 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 590 break; 591 case SK_YUKON: 592 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 593 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 594 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 595 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 596 break; 597 } 598 599 /* Now program new ones. */ 600allmulti: 601 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 602 hashes[0] = 0xFFFFFFFF; 603 hashes[1] = 0xFFFFFFFF; 604 } else { 605 i = 1; 606 /* First find the tail of the list. */ 607 ETHER_FIRST_MULTI(step, ac, enm); 608 while (enm != NULL) { 609 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 610 ETHER_ADDR_LEN)) { 611 ifp->if_flags |= IFF_ALLMULTI; 612 goto allmulti; 613 } 614 /* 615 * Program the first XM_RXFILT_MAX multicast groups 616 * into the perfect filter. For all others, 617 * use the hash table. 618 */ 619 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 620 sk_setfilt(sc_if, enm->enm_addrlo, i); 621 i++; 622 } 623 else { 624 switch(sc->sk_type) { 625 case SK_GENESIS: 626 h = sk_xmac_hash(enm->enm_addrlo); 627 break; 628 629 case SK_YUKON: 630 h = sk_yukon_hash(enm->enm_addrlo); 631 break; 632 } 633 if (h < 32) 634 hashes[0] |= (1 << h); 635 else 636 hashes[1] |= (1 << (h - 32)); 637 } 638 639 ETHER_NEXT_MULTI(step, enm); 640 } 641 } 642 643 switch(sc->sk_type) { 644 case SK_GENESIS: 645 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 646 XM_MODE_RX_USE_PERFECT); 647 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 648 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 649 break; 650 case SK_YUKON: 651 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 652 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 653 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 654 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 655 break; 656 } 657} 658 659int 660sk_init_rx_ring(struct sk_if_softc *sc_if) 661{ 662 struct sk_chain_data *cd = &sc_if->sk_cdata; 663 struct sk_ring_data *rd = sc_if->sk_rdata; 664 int i; 665 666 bzero((char *)rd->sk_rx_ring, 667 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 668 669 for (i = 0; i < SK_RX_RING_CNT; i++) { 670 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 671 if (i == (SK_RX_RING_CNT - 1)) { 672 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 673 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 674 } else { 675 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 676 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 677 } 678 rd->sk_rx_ring[i].sk_csum1_start = ETHER_HDR_LEN; 679 rd->sk_rx_ring[i].sk_csum2_start = ETHER_HDR_LEN + 680 sizeof(struct ip); 681 } 682 683 for (i = 0; i < SK_RX_RING_CNT; i++) { 684 if (sk_newbuf(sc_if, i, NULL, 685 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 686 printf("%s: failed alloc of %dth mbuf\n", 687 sc_if->sk_dev.dv_xname, i); 688 return(ENOBUFS); 689 } 690 } 691 692 sc_if->sk_cdata.sk_rx_prod = 0; 693 sc_if->sk_cdata.sk_rx_cons = 0; 694 695 return(0); 696} 697 698int 699sk_init_tx_ring(struct sk_if_softc *sc_if) 700{ 701 struct sk_softc *sc = sc_if->sk_softc; 702 struct sk_chain_data *cd = &sc_if->sk_cdata; 703 struct sk_ring_data *rd = sc_if->sk_rdata; 704 bus_dmamap_t dmamap; 705 struct sk_txmap_entry *entry; 706 int i; 707 708 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 709 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 710 711 SLIST_INIT(&sc_if->sk_txmap_listhead); 712 for (i = 0; i < SK_TX_RING_CNT; i++) { 713 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 714 if (i == (SK_TX_RING_CNT - 1)) { 715 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 716 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 717 } else { 718 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 719 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 720 } 721 722 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 723 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 724 return (ENOBUFS); 725 726 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 727 if (!entry) { 728 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 729 return (ENOBUFS); 730 } 731 entry->dmamap = dmamap; 732 SLIST_INSERT_HEAD(&sc_if->sk_txmap_listhead, entry, link); 733 } 734 735 sc_if->sk_cdata.sk_tx_prod = 0; 736 sc_if->sk_cdata.sk_tx_cons = 0; 737 sc_if->sk_cdata.sk_tx_cnt = 0; 738 739 return (0); 740} 741 742int 743sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 744 bus_dmamap_t dmamap) 745{ 746 struct mbuf *m_new = NULL; 747 struct sk_chain *c; 748 struct sk_rx_desc *r; 749 750 if (m == NULL) { 751 caddr_t *buf = NULL; 752 753 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 754 if (m_new == NULL) 755 return(ENOBUFS); 756 757 /* Allocate the jumbo buffer */ 758 buf = sk_jalloc(sc_if); 759 if (buf == NULL) { 760 m_freem(m_new); 761 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 762 "dropped!\n", sc_if->arpcom.ac_if.if_xname)); 763 return(ENOBUFS); 764 } 765 766 /* Attach the buffer to the mbuf */ 767 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 768 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 769 } else { 770 /* 771 * We're re-using a previously allocated mbuf; 772 * be sure to re-init pointers and lengths to 773 * default values. 774 */ 775 m_new = m; 776 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 777 m_new->m_data = m_new->m_ext.ext_buf; 778 } 779 m_adj(m_new, ETHER_ALIGN); 780 781 c = &sc_if->sk_cdata.sk_rx_chain[i]; 782 r = c->sk_desc; 783 c->sk_mbuf = m_new; 784 r->sk_data_lo = dmamap->dm_segs[0].ds_addr + 785 (((vaddr_t)m_new->m_data 786 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf)); 787 r->sk_ctl = SK_JLEN | SK_RXSTAT; 788 789 return(0); 790} 791 792/* 793 * Memory management for jumbo frames. 794 */ 795 796int 797sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 798{ 799 struct sk_softc *sc = sc_if->sk_softc; 800 caddr_t ptr, kva; 801 bus_dma_segment_t seg; 802 int i, rseg; 803 struct sk_jpool_entry *entry; 804 805 /* Grab a big chunk o' storage. */ 806 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 807 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 808 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 809 return (ENOBUFS); 810 } 811 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, &kva, 812 BUS_DMA_NOWAIT)) { 813 printf("%s: can't map dma buffers (%d bytes)\n", 814 sc->sk_dev.dv_xname, SK_JMEM); 815 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 816 return (ENOBUFS); 817 } 818 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 819 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 820 printf("%s: can't create dma map\n", sc->sk_dev.dv_xname); 821 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 822 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 823 return (ENOBUFS); 824 } 825 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 826 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 827 printf("%s: can't load dma map\n", sc->sk_dev.dv_xname); 828 bus_dmamap_destroy(sc->sc_dmatag, 829 sc_if->sk_cdata.sk_rx_jumbo_map); 830 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 831 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 832 return (ENOBUFS); 833 } 834 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 835 DPRINTFN(1,("sk_jumbo_buf = 0x%08X\n", sc_if->sk_cdata.sk_jumbo_buf)); 836 837 LIST_INIT(&sc_if->sk_jfree_listhead); 838 LIST_INIT(&sc_if->sk_jinuse_listhead); 839 840 /* 841 * Now divide it up into 9K pieces and save the addresses 842 * in an array. 843 */ 844 ptr = sc_if->sk_cdata.sk_jumbo_buf; 845 for (i = 0; i < SK_JSLOTS; i++) { 846 sc_if->sk_cdata.sk_jslots[i] = ptr; 847 ptr += SK_JLEN; 848 entry = malloc(sizeof(struct sk_jpool_entry), 849 M_DEVBUF, M_NOWAIT); 850 if (entry == NULL) { 851 bus_dmamap_unload(sc->sc_dmatag, 852 sc_if->sk_cdata.sk_rx_jumbo_map); 853 bus_dmamap_destroy(sc->sc_dmatag, 854 sc_if->sk_cdata.sk_rx_jumbo_map); 855 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 856 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 857 sc_if->sk_cdata.sk_jumbo_buf = NULL; 858 printf("%s: no memory for jumbo buffer queue!\n", 859 sc->sk_dev.dv_xname); 860 return(ENOBUFS); 861 } 862 entry->slot = i; 863 if (i) 864 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 865 entry, jpool_entries); 866 else 867 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 868 entry, jpool_entries); 869 } 870 871 return(0); 872} 873 874/* 875 * Allocate a jumbo buffer. 876 */ 877void * 878sk_jalloc(struct sk_if_softc *sc_if) 879{ 880 struct sk_jpool_entry *entry; 881 882 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 883 884 if (entry == NULL) { 885 printf("%s: no free jumbo buffers\n", sc_if->sk_dev.dv_xname); 886 return (NULL); 887 } 888 889 LIST_REMOVE(entry, jpool_entries); 890 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 891 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 892} 893 894/* 895 * Release a jumbo buffer. 896 */ 897void 898sk_jfree(caddr_t buf, u_int size, void *arg) 899{ 900 struct sk_jpool_entry *entry; 901 struct sk_if_softc *sc; 902 int i; 903 904 /* Extract the softc struct pointer. */ 905 sc = (struct sk_if_softc *)arg; 906 907 if (sc == NULL) 908 panic("sk_jfree: can't find softc pointer!"); 909 910 /* calculate the slot this buffer belongs to */ 911 912 i = ((vaddr_t)buf 913 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 914 915 if ((i < 0) || (i >= SK_JSLOTS)) 916 panic("sk_jfree: asked to free buffer that we don't manage!"); 917 918 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 919 if (entry == NULL) 920 panic("sk_jfree: buffer not in use!"); 921 entry->slot = i; 922 LIST_REMOVE(entry, jpool_entries); 923 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 924} 925 926/* 927 * Set media options. 928 */ 929int 930sk_ifmedia_upd(struct ifnet *ifp) 931{ 932 struct sk_if_softc *sc_if = ifp->if_softc; 933 934 sk_init(sc_if); 935 mii_mediachg(&sc_if->sk_mii); 936 return(0); 937} 938 939/* 940 * Report current media status. 941 */ 942void 943sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 944{ 945 struct sk_if_softc *sc_if = ifp->if_softc; 946 947 mii_pollstat(&sc_if->sk_mii); 948 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 949 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 950} 951 952int 953sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 954{ 955 struct sk_if_softc *sc_if = ifp->if_softc; 956 struct sk_softc *sc = sc_if->sk_softc; 957 struct ifreq *ifr = (struct ifreq *) data; 958 struct ifaddr *ifa = (struct ifaddr *) data; 959 struct mii_data *mii; 960 int s, error = 0; 961 962 s = splimp(); 963 964 if ((error = ether_ioctl(ifp, &sc_if->arpcom, command, data)) > 0) { 965 splx(s); 966 return error; 967 } 968 969 switch(command) { 970 case SIOCSIFADDR: 971 ifp->if_flags |= IFF_UP; 972 switch (ifa->ifa_addr->sa_family) { 973#ifdef INET 974 case AF_INET: 975 sk_init(sc_if); 976 arp_ifinit(&sc_if->arpcom, ifa); 977 break; 978#endif /* INET */ 979 default: 980 sk_init(sc_if); 981 break; 982 } 983 break; 984 case SIOCSIFMTU: 985 if (ifr->ifr_mtu > SK_JUMBO_MTU) 986 error = EINVAL; 987 else 988 ifp->if_mtu = ifr->ifr_mtu; 989 sk_init(sc_if); 990 break; 991 case SIOCSIFFLAGS: 992 if (ifp->if_flags & IFF_UP) { 993 if (ifp->if_flags & IFF_RUNNING && 994 ifp->if_flags & IFF_PROMISC && 995 !(sc_if->sk_if_flags & IFF_PROMISC)) { 996 switch(sc->sk_type) { 997 case SK_GENESIS: 998 SK_XM_SETBIT_4(sc_if, XM_MODE, 999 XM_MODE_RX_PROMISC); 1000 break; 1001 case SK_YUKON: 1002 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1003 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1004 break; 1005 } 1006 sk_setmulti(sc_if); 1007 } else if (ifp->if_flags & IFF_RUNNING && 1008 !(ifp->if_flags & IFF_PROMISC) && 1009 sc_if->sk_if_flags & IFF_PROMISC) { 1010 switch(sc->sk_type) { 1011 case SK_GENESIS: 1012 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1013 XM_MODE_RX_PROMISC); 1014 break; 1015 case SK_YUKON: 1016 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1017 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1018 break; 1019 } 1020 1021 sk_setmulti(sc_if); 1022 } else 1023 sk_init(sc_if); 1024 } else { 1025 if (ifp->if_flags & IFF_RUNNING) 1026 sk_stop(sc_if); 1027 } 1028 sc_if->sk_if_flags = ifp->if_flags; 1029 error = 0; 1030 break; 1031 case SIOCADDMULTI: 1032 case SIOCDELMULTI: 1033 error = (command == SIOCADDMULTI) ? 1034 ether_addmulti(ifr, &sc_if->arpcom) : 1035 ether_delmulti(ifr, &sc_if->arpcom); 1036 1037 if (error == ENETRESET) { 1038 /* 1039 * Multicast list has changed; set the hardware 1040 * filter accordingly. 1041 */ 1042 sk_setmulti(sc_if); 1043 error = 0; 1044 } 1045 break; 1046 case SIOCGIFMEDIA: 1047 case SIOCSIFMEDIA: 1048 mii = &sc_if->sk_mii; 1049 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1050 break; 1051 default: 1052 error = EINVAL; 1053 break; 1054 } 1055 1056 splx(s); 1057 1058 return(error); 1059} 1060 1061/* 1062 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1063 * IDs against our list and return a device name if we find a match. 1064 */ 1065int 1066skc_probe(struct device *parent, void *match, void *aux) 1067{ 1068 return (pci_matchbyid((struct pci_attach_args *)aux, skc_devices, 1069 sizeof(skc_devices)/sizeof(skc_devices[0]))); 1070} 1071 1072/* 1073 * Force the GEnesis into reset, then bring it out of reset. 1074 */ 1075void sk_reset(struct sk_softc *sc) 1076{ 1077 DPRINTFN(2, ("sk_reset\n")); 1078 1079 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1080 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1081 if (sc->sk_type == SK_YUKON) 1082 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1083 1084 DELAY(1000); 1085 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1086 DELAY(2); 1087 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1088 if (sc->sk_type == SK_YUKON) 1089 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1090 1091 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1092 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1093 CSR_READ_2(sc, SK_LINK_CTRL))); 1094 1095 if (sc->sk_type == SK_GENESIS) { 1096 /* Configure packet arbiter */ 1097 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1098 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1099 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1100 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1101 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1102 } 1103 1104 /* Enable RAM interface */ 1105 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1106 1107 /* 1108 * Configure interrupt moderation. The moderation timer 1109 * defers interrupts specified in the interrupt moderation 1110 * timer mask based on the timeout specified in the interrupt 1111 * moderation timer init register. Each bit in the timer 1112 * register represents 18.825ns, so to specify a timeout in 1113 * microseconds, we have to multiply by 54. 1114 */ 1115 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1116 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1117 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1118 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1119} 1120 1121int 1122sk_probe(struct device *parent, void *match, void *aux) 1123{ 1124 struct skc_attach_args *sa = aux; 1125 1126 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1127 return(0); 1128 1129 return (1); 1130} 1131 1132/* 1133 * Each XMAC chip is attached as a separate logical IP interface. 1134 * Single port cards will have only one logical interface of course. 1135 */ 1136void 1137sk_attach(struct device *parent, struct device *self, void *aux) 1138{ 1139 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1140 struct sk_softc *sc = (struct sk_softc *)parent; 1141 struct skc_attach_args *sa = aux; 1142 struct ifnet *ifp; 1143 caddr_t kva; 1144 bus_dma_segment_t seg; 1145 int i, rseg; 1146 1147 sc_if->sk_port = sa->skc_port; 1148 sc_if->sk_softc = sc; 1149 sc->sk_if[sa->skc_port] = sc_if; 1150 1151 if (sa->skc_port == SK_PORT_A) 1152 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1153 if (sa->skc_port == SK_PORT_B) 1154 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1155 1156 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1157 1158 /* 1159 * Get station address for this interface. Note that 1160 * dual port cards actually come with three station 1161 * addresses: one for each port, plus an extra. The 1162 * extra one is used by the SysKonnect driver software 1163 * as a 'virtual' station address for when both ports 1164 * are operating in failover mode. Currently we don't 1165 * use this extra address. 1166 */ 1167 for (i = 0; i < ETHER_ADDR_LEN; i++) 1168 sc_if->arpcom.ac_enaddr[i] = 1169 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1170 1171 1172 printf(": address %s\n", 1173 ether_sprintf(sc_if->arpcom.ac_enaddr)); 1174 1175 /* 1176 * Set up RAM buffer addresses. The NIC will have a certain 1177 * amount of SRAM on it, somewhere between 512K and 2MB. We 1178 * need to divide this up a) between the transmitter and 1179 * receiver and b) between the two XMACs, if this is a 1180 * dual port NIC. Our algorithm is to divide up the memory 1181 * evenly so that everyone gets a fair share. 1182 */ 1183 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1184 u_int32_t chunk, val; 1185 1186 chunk = sc->sk_ramsize / 2; 1187 val = sc->sk_rboff / sizeof(u_int64_t); 1188 sc_if->sk_rx_ramstart = val; 1189 val += (chunk / sizeof(u_int64_t)); 1190 sc_if->sk_rx_ramend = val - 1; 1191 sc_if->sk_tx_ramstart = val; 1192 val += (chunk / sizeof(u_int64_t)); 1193 sc_if->sk_tx_ramend = val - 1; 1194 } else { 1195 u_int32_t chunk, val; 1196 1197 chunk = sc->sk_ramsize / 4; 1198 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1199 sizeof(u_int64_t); 1200 sc_if->sk_rx_ramstart = val; 1201 val += (chunk / sizeof(u_int64_t)); 1202 sc_if->sk_rx_ramend = val - 1; 1203 sc_if->sk_tx_ramstart = val; 1204 val += (chunk / sizeof(u_int64_t)); 1205 sc_if->sk_tx_ramend = val - 1; 1206 } 1207 1208 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1209 " tx_ramstart=%#x tx_ramend=%#x\n", 1210 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1211 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1212 1213 /* Read and save PHY type and set PHY address */ 1214 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1215 switch (sc_if->sk_phytype) { 1216 case SK_PHYTYPE_XMAC: 1217 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1218 break; 1219 case SK_PHYTYPE_BCOM: 1220 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1221 break; 1222 case SK_PHYTYPE_MARV_COPPER: 1223 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1224 break; 1225 default: 1226 printf("%s: unsupported PHY type: %d\n", 1227 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1228 return; 1229 } 1230 1231 /* Allocate the descriptor queues. */ 1232 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1233 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1234 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 1235 goto fail; 1236 } 1237 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1238 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1239 printf("%s: can't map dma buffers (%d bytes)\n", 1240 sc_if->sk_dev.dv_xname, sizeof(struct sk_ring_data)); 1241 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1242 goto fail; 1243 } 1244 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1245 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1246 &sc_if->sk_ring_map)) { 1247 printf("%s: can't create dma map\n", sc_if->sk_dev.dv_xname); 1248 bus_dmamem_unmap(sc->sc_dmatag, kva, 1249 sizeof(struct sk_ring_data)); 1250 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1251 goto fail; 1252 } 1253 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1254 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1255 printf("%s: can't load dma map\n", sc_if->sk_dev.dv_xname); 1256 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1257 bus_dmamem_unmap(sc->sc_dmatag, kva, 1258 sizeof(struct sk_ring_data)); 1259 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1260 goto fail; 1261 } 1262 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1263 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1264 1265 /* Try to allocate memory for jumbo buffers. */ 1266 if (sk_alloc_jumbo_mem(sc_if)) { 1267 printf("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1268 goto fail; 1269 } 1270 1271 ifp = &sc_if->arpcom.ac_if; 1272 ifp->if_softc = sc_if; 1273 ifp->if_mtu = ETHERMTU; 1274 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1275 ifp->if_ioctl = sk_ioctl; 1276 ifp->if_output = ether_output; 1277 ifp->if_start = sk_start; 1278 ifp->if_watchdog = sk_watchdog; 1279 ifp->if_baudrate = 1000000000; 1280 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1281 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1282 IFQ_SET_READY(&ifp->if_snd); 1283 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1284 1285 /* 1286 * Do miibus setup. 1287 */ 1288 switch (sc->sk_type) { 1289 case SK_GENESIS: 1290 sk_init_xmac(sc_if); 1291 break; 1292 case SK_YUKON: 1293 sk_init_yukon(sc_if); 1294 break; 1295 default: 1296 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1297 sc->sk_type); 1298 } 1299 1300 DPRINTFN(2, ("sk_attach: 1\n")); 1301 1302 sc_if->sk_mii.mii_ifp = ifp; 1303 switch (sc->sk_type) { 1304 case SK_GENESIS: 1305 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1306 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1307 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1308 break; 1309 case SK_YUKON: 1310 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1311 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1312 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1313 break; 1314 } 1315 1316 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1317 sk_ifmedia_upd, sk_ifmedia_sts); 1318 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1319 MII_OFFSET_ANY, 0); 1320 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1321 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1322 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1323 0, NULL); 1324 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1325 } 1326 else 1327 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1328 1329 timeout_set(&sc_if->sk_tick_ch, sk_tick, sc_if); 1330 timeout_add(&sc_if->sk_tick_ch, hz); 1331 1332 DPRINTFN(2, ("sk_attach: 1\n")); 1333 1334 /* 1335 * Call MI attach routines. 1336 */ 1337 if_attach(ifp); 1338 ether_ifattach(ifp); 1339 1340 DPRINTFN(2, ("sk_attach: end\n")); 1341 1342 return; 1343 1344fail: 1345 sc->sk_if[sa->skc_port] = NULL; 1346} 1347 1348int 1349skcprint(void *aux, const char *pnp) 1350{ 1351 struct skc_attach_args *sa = aux; 1352 1353 if (pnp) 1354 printf("sk port %c at %s", 1355 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1356 else 1357 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1358 return (UNCONF); 1359} 1360 1361/* 1362 * Attach the interface. Allocate softc structures, do ifmedia 1363 * setup and ethernet/BPF attach. 1364 */ 1365void 1366skc_attach(struct device *parent, struct device *self, void *aux) 1367{ 1368 struct sk_softc *sc = (struct sk_softc *)self; 1369 struct pci_attach_args *pa = aux; 1370 struct skc_attach_args skca; 1371 pci_chipset_tag_t pc = pa->pa_pc; 1372 pci_intr_handle_t ih; 1373 const char *intrstr = NULL; 1374 bus_addr_t iobase; 1375 bus_size_t iosize; 1376 int s; 1377 u_int32_t command; 1378 1379 DPRINTFN(2, ("begin skc_attach\n")); 1380 1381 s = splimp(); 1382 1383 /* 1384 * Handle power management nonsense. 1385 */ 1386 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1387 1388 if (command == 0x01) { 1389 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1390 if (command & SK_PSTATE_MASK) { 1391 u_int32_t iobase, membase, irq; 1392 1393 /* Save important PCI config data. */ 1394 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1395 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1396 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1397 1398 /* Reset the power state. */ 1399 printf("%s chip is in D%d power mode " 1400 "-- setting to D0\n", sc->sk_dev.dv_xname, 1401 command & SK_PSTATE_MASK); 1402 command &= 0xFFFFFFFC; 1403 pci_conf_write(pc, pa->pa_tag, 1404 SK_PCI_PWRMGMTCTRL, command); 1405 1406 /* Restore PCI config data. */ 1407 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1408 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1409 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1410 } 1411 } 1412 1413 /* 1414 * Map control/status registers. 1415 */ 1416 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1417 1418#define SK_MK_ID(vnd,prd) \ 1419 (((vnd) << PCI_VENDOR_SHIFT) | ((prd) << PCI_PRODUCT_SHIFT)) 1420 1421 switch (pa->pa_id) { 1422 case SK_MK_ID(PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_GE): 1423 sc->sk_type = SK_GENESIS; 1424 break; 1425 case SK_MK_ID(PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940): 1426 case SK_MK_ID(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T): 1427 case SK_MK_ID(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032): 1428 case SK_MK_ID(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064): 1429 case SK_MK_ID(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SK_V2): 1430 case SK_MK_ID(PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1431 sc->sk_type = SK_YUKON; 1432 break; 1433 default: 1434 printf(": unknown device!\n"); 1435 goto fail; 1436 } 1437#undef SK_MK_ID 1438 1439#ifdef SK_USEIOSPACE 1440 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1441 printf(": failed to enable I/O ports!\n"); 1442 goto fail; 1443 } 1444 /* 1445 * Map control/status registers. 1446 */ 1447 if (pci_io_find(pc, pa->pa_tag, SK_PCI_LOIO, &iobase, &iosize)) { 1448 printf(": can't find i/o space\n"); 1449 goto fail; 1450 } 1451 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->sk_bhandle)) { 1452 printf(": can't map i/o space\n"); 1453 goto fail; 1454 } 1455 sc->sk_btag = pa->pa_iot; 1456#else 1457 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1458 printf(": failed to enable memory mapping!\n"); 1459 goto fail; 1460 } 1461 if (pci_mem_find(pc, pa->pa_tag, SK_PCI_LOMEM, &iobase, &iosize, NULL)){ 1462 printf(": can't find mem space\n"); 1463 goto fail; 1464 } 1465 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->sk_bhandle)) { 1466 printf(": can't map mem space\n"); 1467 goto fail; 1468 } 1469 sc->sk_btag = pa->pa_memt; 1470 1471 DPRINTFN(2, ("skc_attach: iobase=%#x, iosize=%#x\n", iobase, iosize)); 1472#endif 1473 sc->sc_dmatag = pa->pa_dmat; 1474 1475 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1476 1477 /* Allocate interrupt */ 1478 if (pci_intr_map(pa, &ih)) { 1479 printf(": couldn't map interrupt\n"); 1480 goto fail; 1481 } 1482 1483 intrstr = pci_intr_string(pc, ih); 1484 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc, 1485 self->dv_xname); 1486 if (sc->sk_intrhand == NULL) { 1487 printf(": couldn't establish interrupt"); 1488 if (intrstr != NULL) 1489 printf(" at %s", intrstr); 1490 goto fail; 1491 } 1492 printf(": %s\n", intrstr); 1493 1494 /* Reset the adapter. */ 1495 sk_reset(sc); 1496 1497 /* Read and save vital product data from EEPROM. */ 1498 sk_vpd_read(sc); 1499 1500 if (sc->sk_type == SK_GENESIS) { 1501 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1502 /* Read and save RAM size and RAMbuffer offset */ 1503 switch(val) { 1504 case SK_RAMSIZE_512K_64: 1505 sc->sk_ramsize = 0x80000; 1506 sc->sk_rboff = SK_RBOFF_0; 1507 break; 1508 case SK_RAMSIZE_1024K_64: 1509 sc->sk_ramsize = 0x100000; 1510 sc->sk_rboff = SK_RBOFF_80000; 1511 break; 1512 case SK_RAMSIZE_1024K_128: 1513 sc->sk_ramsize = 0x100000; 1514 sc->sk_rboff = SK_RBOFF_0; 1515 break; 1516 case SK_RAMSIZE_2048K_128: 1517 sc->sk_ramsize = 0x200000; 1518 sc->sk_rboff = SK_RBOFF_0; 1519 break; 1520 default: 1521 printf("%s: unknown ram size: %d\n", 1522 sc->sk_dev.dv_xname, val); 1523 goto fail; 1524 break; 1525 } 1526 1527 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1528 sc->sk_ramsize, sc->sk_ramsize / 1024, 1529 sc->sk_rboff)); 1530 } else { 1531 sc->sk_ramsize = 0x20000; 1532 sc->sk_rboff = SK_RBOFF_0; 1533 1534 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1535 sc->sk_ramsize / 1024, sc->sk_ramsize, 1536 sc->sk_rboff)); 1537 } 1538 1539 /* Read and save physical media type */ 1540 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1541 case SK_PMD_1000BASESX: 1542 sc->sk_pmd = IFM_1000_SX; 1543 break; 1544 case SK_PMD_1000BASELX: 1545 sc->sk_pmd = IFM_1000_LX; 1546 break; 1547 case SK_PMD_1000BASECX: 1548 sc->sk_pmd = IFM_1000_CX; 1549 break; 1550 case SK_PMD_1000BASETX: 1551 sc->sk_pmd = IFM_1000_T; 1552 break; 1553 default: 1554 printf("%s: unknown media type: 0x%x\n", 1555 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1556 goto fail; 1557 } 1558 1559 /* Announce the product name. */ 1560 printf("%s: %s\n", sc->sk_dev.dv_xname, sc->sk_vpd_prodname); 1561 1562 skca.skc_port = SK_PORT_A; 1563 (void)config_found(&sc->sk_dev, &skca, skcprint); 1564 1565 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1566 skca.skc_port = SK_PORT_B; 1567 (void)config_found(&sc->sk_dev, &skca, skcprint); 1568 } 1569 1570 /* Turn on the 'driver is loaded' LED. */ 1571 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1572 1573fail: 1574 splx(s); 1575} 1576 1577int 1578sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1579{ 1580 struct sk_softc *sc = sc_if->sk_softc; 1581 struct sk_tx_desc *f = NULL; 1582 u_int32_t frag, cur, cnt = 0; 1583 int i; 1584 struct sk_txmap_entry *entry; 1585 bus_dmamap_t txmap; 1586 1587 DPRINTFN(2, ("sk_encap\n")); 1588 1589 entry = SLIST_FIRST(&sc_if->sk_txmap_listhead); 1590 if (entry == NULL) { 1591 DPRINTFN(2, ("sk_encap: no txmap available\n")); 1592 return ENOBUFS; 1593 } 1594 txmap = entry->dmamap; 1595 1596 cur = frag = *txidx; 1597 1598#ifdef SK_DEBUG 1599 if (skdebug >= 2) 1600 sk_dump_mbuf(m_head); 1601#endif 1602 1603 /* 1604 * Start packing the mbufs in this chain into 1605 * the fragment pointers. Stop when we run out 1606 * of fragments or hit the end of the mbuf chain. 1607 */ 1608 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1609 BUS_DMA_NOWAIT)) { 1610 DPRINTFN(2, ("sk_encap: dmamap failed\n")); 1611 return(ENOBUFS); 1612 } 1613 1614 DPRINTFN(2, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1615 1616 for (i = 0; i < txmap->dm_nsegs; i++) { 1617 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1618 DPRINTFN(2, ("sk_encap: too few descriptors free\n")); 1619 return(ENOBUFS); 1620 } 1621 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1622 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1623 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1624 if (cnt == 0) 1625 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1626 else 1627 f->sk_ctl |= SK_TXCTL_OWN; 1628 1629 cur = frag; 1630 SK_INC(frag, SK_TX_RING_CNT); 1631 cnt++; 1632 } 1633 1634 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1635 SLIST_REMOVE_HEAD(&sc_if->sk_txmap_listhead, link); 1636 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1637 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1638 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1639 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1640 sc_if->sk_cdata.sk_tx_cnt += cnt; 1641 1642#ifdef SK_DEBUG 1643 if (skdebug >= 2) { 1644 struct sk_tx_desc *desc; 1645 u_int32_t idx; 1646 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1647 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1648 sk_dump_txdesc(desc, idx); 1649 } 1650 } 1651#endif 1652 1653 *txidx = frag; 1654 1655 DPRINTFN(2, ("sk_encap: completed successfully\n")); 1656 1657 return(0); 1658} 1659 1660void 1661sk_start(struct ifnet *ifp) 1662{ 1663 struct sk_if_softc *sc_if = ifp->if_softc; 1664 struct sk_softc *sc = sc_if->sk_softc; 1665 struct mbuf *m_head = NULL; 1666 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1667 int pkts = 0; 1668 1669 DPRINTFN(2, ("sk_start\n")); 1670 1671 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1672 IFQ_POLL(&ifp->if_snd, m_head); 1673 if (m_head == NULL) 1674 break; 1675 1676 /* 1677 * Pack the data into the transmit ring. If we 1678 * don't have room, set the OACTIVE flag and wait 1679 * for the NIC to drain the ring. 1680 */ 1681 if (sk_encap(sc_if, m_head, &idx)) { 1682 ifp->if_flags |= IFF_OACTIVE; 1683 break; 1684 } 1685 1686 /* now we are committed to transmit the packet */ 1687 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1688 pkts++; 1689 1690 /* 1691 * If there's a BPF listener, bounce a copy of this frame 1692 * to him. 1693 */ 1694#if NBPFILTER > 0 1695 if (ifp->if_bpf) 1696 bpf_mtap(ifp->if_bpf, m_head); 1697#endif 1698 } 1699 if (pkts == 0) 1700 return; 1701 1702 /* Transmit */ 1703 sc_if->sk_cdata.sk_tx_prod = idx; 1704 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1705 1706 /* Set a timeout in case the chip goes out to lunch. */ 1707 ifp->if_timer = 5; 1708} 1709 1710 1711void 1712sk_watchdog(struct ifnet *ifp) 1713{ 1714 struct sk_if_softc *sc_if = ifp->if_softc; 1715 1716 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1717 sk_init(sc_if); 1718} 1719 1720void 1721sk_shutdown(void *v) 1722{ 1723 struct sk_softc *sc = v; 1724 1725 DPRINTFN(2, ("sk_shutdown\n")); 1726 1727 /* Turn off the 'driver is loaded' LED. */ 1728 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1729 1730 /* 1731 * Reset the GEnesis controller. Doing this should also 1732 * assert the resets on the attached XMAC(s). 1733 */ 1734 sk_reset(sc); 1735} 1736 1737void 1738sk_rxeof(struct sk_if_softc *sc_if) 1739{ 1740 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1741 struct mbuf *m; 1742 struct sk_chain *cur_rx; 1743 struct sk_rx_desc *cur_desc; 1744 int i, cur, total_len = 0; 1745 u_int32_t rxstat; 1746 bus_dmamap_t dmamap; 1747 u_int16_t csum1, csum2; 1748 1749 DPRINTFN(2, ("sk_rxeof\n")); 1750 1751 i = sc_if->sk_cdata.sk_rx_prod; 1752 1753 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1754 cur = i; 1755 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1756 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1757 1758 rxstat = cur_desc->sk_xmac_rxstat; 1759 m = cur_rx->sk_mbuf; 1760 cur_rx->sk_mbuf = NULL; 1761 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1762 1763 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1764 1765 csum1 = sc_if->sk_rdata->sk_rx_ring[i].sk_csum1; 1766 csum2 = sc_if->sk_rdata->sk_rx_ring[i].sk_csum2; 1767 1768 SK_INC(i, SK_RX_RING_CNT); 1769 1770 if (rxstat & XM_RXSTAT_ERRFRAME) { 1771 ifp->if_ierrors++; 1772 sk_newbuf(sc_if, cur, m, dmamap); 1773 continue; 1774 } 1775 1776 /* 1777 * Try to allocate a new jumbo buffer. If that 1778 * fails, copy the packet to mbufs and put the 1779 * jumbo buffer back in the ring so it can be 1780 * re-used. If allocating mbufs fails, then we 1781 * have to drop the packet. 1782 */ 1783 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1784 struct mbuf *m0; 1785 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1786 total_len + ETHER_ALIGN, 0, ifp, NULL); 1787 sk_newbuf(sc_if, cur, m, dmamap); 1788 if (m0 == NULL) { 1789 ifp->if_ierrors++; 1790 continue; 1791 } 1792 m_adj(m0, ETHER_ALIGN); 1793 m = m0; 1794 } else { 1795 m->m_pkthdr.rcvif = ifp; 1796 m->m_pkthdr.len = m->m_len = total_len; 1797 } 1798 1799 ifp->if_ipackets++; 1800 1801 sk_rxcsum(ifp, m, csum1, csum2); 1802 1803#if NBPFILTER > 0 1804 if (ifp->if_bpf) 1805 bpf_mtap(ifp->if_bpf, m); 1806#endif 1807 1808 /* pass it on. */ 1809 ether_input_mbuf(ifp, m); 1810 } 1811 1812 sc_if->sk_cdata.sk_rx_prod = i; 1813} 1814 1815void 1816sk_rxcsum(struct ifnet *ifp, struct mbuf *m, const u_int16_t csum1, const u_int16_t csum2) 1817{ 1818 struct ether_header *eh; 1819 struct ip *ip; 1820 u_int8_t *pp; 1821 int hlen, len, plen; 1822 u_int16_t iph_csum, ipo_csum, ipd_csum, csum; 1823 1824 pp = mtod(m, u_int8_t *); 1825 plen = m->m_pkthdr.len; 1826 if (plen < sizeof(*eh)) 1827 return; 1828 eh = (struct ether_header *)pp; 1829 iph_csum = in_cksum_addword(csum1, (~csum2 & 0xffff)); 1830 1831 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1832 u_int16_t *xp = (u_int16_t *)pp; 1833 1834 xp = (u_int16_t *)pp; 1835 if (xp[1] != htons(ETHERTYPE_IP)) 1836 return; 1837 iph_csum = in_cksum_addword(iph_csum, (~xp[0] & 0xffff)); 1838 iph_csum = in_cksum_addword(iph_csum, (~xp[1] & 0xffff)); 1839 xp = (u_int16_t *)(pp + sizeof(struct ip)); 1840 iph_csum = in_cksum_addword(iph_csum, xp[0]); 1841 iph_csum = in_cksum_addword(iph_csum, xp[1]); 1842 pp += EVL_ENCAPLEN; 1843 } else if (eh->ether_type != htons(ETHERTYPE_IP)) 1844 return; 1845 1846 pp += sizeof(*eh); 1847 plen -= sizeof(*eh); 1848 1849 ip = (struct ip *)pp; 1850 1851 if (ip->ip_v != IPVERSION) 1852 return; 1853 1854 hlen = ip->ip_hl << 2; 1855 if (hlen < sizeof(struct ip)) 1856 return; 1857 if (hlen > ntohs(ip->ip_len)) 1858 return; 1859 1860 /* Don't deal with truncated or padded packets. */ 1861 if (plen != ntohs(ip->ip_len)) 1862 return; 1863 1864 len = hlen - sizeof(struct ip); 1865 if (len > 0) { 1866 u_int16_t *p; 1867 1868 p = (u_int16_t *)(ip + 1); 1869 ipo_csum = 0; 1870 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++) 1871 ipo_csum = in_cksum_addword(ipo_csum, *p); 1872 iph_csum = in_cksum_addword(iph_csum, ipo_csum); 1873 ipd_csum = in_cksum_addword(csum2, (~ipo_csum & 0xffff)); 1874 } else 1875 ipd_csum = csum2; 1876 1877 if (iph_csum != 0xffff) { 1878 if (ifp->if_bpf) 1879 bpf_mtap(ifp->if_bpf, m); 1880 return; 1881 } 1882 m->m_pkthdr.csum |= M_IPV4_CSUM_IN_OK; 1883 1884 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1885 return; /* ip frag, we're done for now */ 1886 1887 pp += hlen; 1888 1889 /* Only know checksum protocol for udp/tcp */ 1890 if (ip->ip_p == IPPROTO_UDP) { 1891 struct udphdr *uh = (struct udphdr *)pp; 1892 1893 if (uh->uh_sum == 0) /* udp with no checksum */ 1894 return; 1895 } else if (ip->ip_p != IPPROTO_TCP) 1896 return; 1897 1898 csum = in_cksum_phdr(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1899 htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum); 1900 if (csum == 0xffff) { 1901 m->m_pkthdr.csum |= (ip->ip_p == IPPROTO_TCP) ? 1902 M_TCP_CSUM_IN_OK : M_UDP_CSUM_IN_OK; 1903 } 1904} 1905 1906void 1907sk_txeof(struct sk_if_softc *sc_if) 1908{ 1909 struct sk_softc *sc = sc_if->sk_softc; 1910 struct sk_tx_desc *cur_tx = NULL; 1911 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1912 u_int32_t idx; 1913 struct sk_txmap_entry *entry; 1914 1915 DPRINTFN(2, ("sk_txeof\n")); 1916 1917 /* 1918 * Go through our tx ring and free mbufs for those 1919 * frames that have been sent. 1920 */ 1921 idx = sc_if->sk_cdata.sk_tx_cons; 1922 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1923 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1924#ifdef SK_DEBUG 1925 if (skdebug >= 2) 1926 sk_dump_txdesc(cur_tx, idx); 1927#endif 1928 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1929 break; 1930 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1931 ifp->if_opackets++; 1932 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1933 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1934 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1935 1936 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1937 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1938 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1939 1940 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1941 SLIST_INSERT_HEAD(&sc_if->sk_txmap_listhead, entry, 1942 link); 1943 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1944 } 1945 sc_if->sk_cdata.sk_tx_cnt--; 1946 SK_INC(idx, SK_TX_RING_CNT); 1947 ifp->if_timer = 0; 1948 } 1949 1950 sc_if->sk_cdata.sk_tx_cons = idx; 1951 1952 if (cur_tx != NULL) 1953 ifp->if_flags &= ~IFF_OACTIVE; 1954} 1955 1956void 1957sk_tick(void *xsc_if) 1958{ 1959 struct sk_if_softc *sc_if = xsc_if; 1960 struct mii_data *mii = &sc_if->sk_mii; 1961 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1962 int i; 1963 1964 DPRINTFN(2, ("sk_tick\n")); 1965 1966 if (!(ifp->if_flags & IFF_UP)) 1967 return; 1968 1969 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1970 sk_intr_bcom(sc_if); 1971 return; 1972 } 1973 1974 /* 1975 * According to SysKonnect, the correct way to verify that 1976 * the link has come back up is to poll bit 0 of the GPIO 1977 * register three times. This pin has the signal from the 1978 * link sync pin connected to it; if we read the same link 1979 * state 3 times in a row, we know the link is up. 1980 */ 1981 for (i = 0; i < 3; i++) { 1982 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1983 break; 1984 } 1985 1986 if (i != 3) { 1987 timeout_add(&sc_if->sk_tick_ch, hz); 1988 return; 1989 } 1990 1991 /* Turn the GP0 interrupt back on. */ 1992 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1993 SK_XM_READ_2(sc_if, XM_ISR); 1994 mii_tick(mii); 1995 mii_pollstat(mii); 1996 timeout_del(&sc_if->sk_tick_ch); 1997} 1998 1999void 2000sk_intr_bcom(struct sk_if_softc *sc_if) 2001{ 2002 struct mii_data *mii = &sc_if->sk_mii; 2003 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2004 int status; 2005 2006 2007 DPRINTFN(2, ("sk_intr_bcom\n")); 2008 2009 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2010 2011 /* 2012 * Read the PHY interrupt register to make sure 2013 * we clear any pending interrupts. 2014 */ 2015 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2016 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2017 2018 if (!(ifp->if_flags & IFF_RUNNING)) { 2019 sk_init_xmac(sc_if); 2020 return; 2021 } 2022 2023 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2024 int lstat; 2025 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2026 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2027 2028 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2029 mii_mediachg(mii); 2030 /* Turn off the link LED. */ 2031 SK_IF_WRITE_1(sc_if, 0, 2032 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2033 sc_if->sk_link = 0; 2034 } else if (status & BRGPHY_ISR_LNK_CHG) { 2035 sk_xmac_miibus_writereg((struct device *)sc_if, 2036 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2037 mii_tick(mii); 2038 sc_if->sk_link = 1; 2039 /* Turn on the link LED. */ 2040 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2041 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2042 SK_LINKLED_BLINK_OFF); 2043 mii_pollstat(mii); 2044 } else { 2045 mii_tick(mii); 2046 timeout_add(&sc_if->sk_tick_ch, hz); 2047 } 2048 } 2049 2050 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2051} 2052 2053void 2054sk_intr_xmac(struct sk_if_softc *sc_if) 2055{ 2056 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2057 2058 DPRINTFN(2, ("sk_intr_xmac\n")); 2059 2060 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2061 if (status & XM_ISR_GP0_SET) { 2062 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2063 timeout_add(&sc_if->sk_tick_ch, hz); 2064 } 2065 2066 if (status & XM_ISR_AUTONEG_DONE) { 2067 timeout_add(&sc_if->sk_tick_ch, hz); 2068 } 2069 } 2070 2071 if (status & XM_IMR_TX_UNDERRUN) 2072 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2073 2074 if (status & XM_IMR_RX_OVERRUN) 2075 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2076} 2077 2078void 2079sk_intr_yukon(sc_if) 2080 struct sk_if_softc *sc_if; 2081{ 2082 int status; 2083 2084 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2085 2086 DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status)); 2087} 2088 2089int 2090sk_intr(void *xsc) 2091{ 2092 struct sk_softc *sc = xsc; 2093 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2094 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2095 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2096 u_int32_t status; 2097 int claimed = 0; 2098 2099 if (sc_if0 != NULL) 2100 ifp0 = &sc_if0->arpcom.ac_if; 2101 if (sc_if1 != NULL) 2102 ifp1 = &sc_if1->arpcom.ac_if; 2103 2104 for (;;) { 2105 status = CSR_READ_4(sc, SK_ISSR); 2106 DPRINTFN(2, ("sk_intr: status=%#x\n", status)); 2107 2108 if (!(status & sc->sk_intrmask)) 2109 break; 2110 2111 claimed = 1; 2112 2113 /* Handle receive interrupts first. */ 2114 if (status & SK_ISR_RX1_EOF) { 2115 sk_rxeof(sc_if0); 2116 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2117 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2118 } 2119 if (status & SK_ISR_RX2_EOF) { 2120 sk_rxeof(sc_if1); 2121 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2122 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2123 } 2124 2125 /* Then transmit interrupts. */ 2126 if (status & SK_ISR_TX1_S_EOF) { 2127 sk_txeof(sc_if0); 2128 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2129 SK_TXBMU_CLR_IRQ_EOF); 2130 } 2131 if (status & SK_ISR_TX2_S_EOF) { 2132 sk_txeof(sc_if1); 2133 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2134 SK_TXBMU_CLR_IRQ_EOF); 2135 } 2136 2137 /* Then MAC interrupts. */ 2138 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 2139 if (sc->sk_type == SK_GENESIS) 2140 sk_intr_xmac(sc_if0); 2141 else 2142 sk_intr_yukon(sc_if0); 2143 } 2144 2145 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 2146 if (sc->sk_type == SK_GENESIS) 2147 sk_intr_xmac(sc_if1); 2148 else 2149 sk_intr_yukon(sc_if1); 2150 2151 } 2152 2153 if (status & SK_ISR_EXTERNAL_REG) { 2154 if (ifp0 != NULL && 2155 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2156 sk_intr_bcom(sc_if0); 2157 2158 if (ifp1 != NULL && 2159 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2160 sk_intr_bcom(sc_if1); 2161 } 2162 } 2163 2164 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2165 2166 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2167 sk_start(ifp0); 2168 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2169 sk_start(ifp1); 2170 2171 return (claimed); 2172} 2173 2174void 2175sk_init_xmac(struct sk_if_softc *sc_if) 2176{ 2177 struct sk_softc *sc = sc_if->sk_softc; 2178 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2179 struct sk_bcom_hack bhack[] = { 2180 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2181 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2182 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2183 { 0, 0 } }; 2184 2185 DPRINTFN(2, ("sk_init_xmac\n")); 2186 2187 /* Unreset the XMAC. */ 2188 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2189 DELAY(1000); 2190 2191 /* Reset the XMAC's internal state. */ 2192 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2193 2194 /* Save the XMAC II revision */ 2195 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2196 2197 /* 2198 * Perform additional initialization for external PHYs, 2199 * namely for the 1000baseTX cards that use the XMAC's 2200 * GMII mode. 2201 */ 2202 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2203 int i = 0; 2204 u_int32_t val; 2205 2206 /* Take PHY out of reset. */ 2207 val = sk_win_read_4(sc, SK_GPIO); 2208 if (sc_if->sk_port == SK_PORT_A) 2209 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2210 else 2211 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2212 sk_win_write_4(sc, SK_GPIO, val); 2213 2214 /* Enable GMII mode on the XMAC. */ 2215 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2216 2217 sk_xmac_miibus_writereg((struct device *)sc_if, 2218 SK_PHYADDR_BCOM, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2219 DELAY(10000); 2220 sk_xmac_miibus_writereg((struct device *)sc_if, 2221 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2222 2223 /* 2224 * Early versions of the BCM5400 apparently have 2225 * a bug that requires them to have their reserved 2226 * registers initialized to some magic values. I don't 2227 * know what the numbers do, I'm just the messenger. 2228 */ 2229 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2230 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2231 while(bhack[i].reg) { 2232 sk_xmac_miibus_writereg((struct device *)sc_if, 2233 SK_PHYADDR_BCOM, bhack[i].reg, 2234 bhack[i].val); 2235 i++; 2236 } 2237 } 2238 } 2239 2240 /* Set station address */ 2241 SK_XM_WRITE_2(sc_if, XM_PAR0, 2242 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2243 SK_XM_WRITE_2(sc_if, XM_PAR1, 2244 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2245 SK_XM_WRITE_2(sc_if, XM_PAR2, 2246 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2247 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2248 2249 if (ifp->if_flags & IFF_PROMISC) { 2250 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2251 } else { 2252 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2253 } 2254 2255 if (ifp->if_flags & IFF_BROADCAST) { 2256 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2257 } else { 2258 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2259 } 2260 2261 /* We don't need the FCS appended to the packet. */ 2262 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2263 2264 /* We want short frames padded to 60 bytes. */ 2265 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2266 2267 /* 2268 * Enable the reception of all error frames. This is is 2269 * a necessary evil due to the design of the XMAC. The 2270 * XMAC's receive FIFO is only 8K in size, however jumbo 2271 * frames can be up to 9000 bytes in length. When bad 2272 * frame filtering is enabled, the XMAC's RX FIFO operates 2273 * in 'store and forward' mode. For this to work, the 2274 * entire frame has to fit into the FIFO, but that means 2275 * that jumbo frames larger than 8192 bytes will be 2276 * truncated. Disabling all bad frame filtering causes 2277 * the RX FIFO to operate in streaming mode, in which 2278 * case the XMAC will start transfering frames out of the 2279 * RX FIFO as soon as the FIFO threshold is reached. 2280 */ 2281 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2282 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2283 XM_MODE_RX_INRANGELEN); 2284 2285 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2286 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2287 else 2288 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2289 2290 /* 2291 * Bump up the transmit threshold. This helps hold off transmit 2292 * underruns when we're blasting traffic from both ports at once. 2293 */ 2294 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2295 2296 /* Set multicast filter */ 2297 sk_setmulti(sc_if); 2298 2299 /* Clear and enable interrupts */ 2300 SK_XM_READ_2(sc_if, XM_ISR); 2301 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2302 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2303 else 2304 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2305 2306 /* Configure MAC arbiter */ 2307 switch(sc_if->sk_xmac_rev) { 2308 case XM_XMAC_REV_B2: 2309 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2310 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2311 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2312 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2313 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2314 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2315 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2316 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2317 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2318 break; 2319 case XM_XMAC_REV_C1: 2320 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2321 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2322 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2323 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2324 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2325 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2326 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2327 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2328 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2329 break; 2330 default: 2331 break; 2332 } 2333 sk_win_write_2(sc, SK_MACARB_CTL, 2334 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2335 2336 sc_if->sk_link = 1; 2337} 2338 2339void sk_init_yukon(sc_if) 2340 struct sk_if_softc *sc_if; 2341{ 2342 u_int32_t /*mac, */phy; 2343 u_int16_t reg; 2344 int i; 2345 2346 DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n", 2347 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2348 2349 /* GMAC and GPHY Reset */ 2350 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2351 2352 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2353 2354 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2355 DELAY(1000); 2356 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2357 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2358 DELAY(1000); 2359 2360 2361 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2362 2363 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2364 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2365 2366 switch(sc_if->sk_softc->sk_pmd) { 2367 case IFM_1000_SX: 2368 case IFM_1000_LX: 2369 phy |= SK_GPHY_FIBER; 2370 break; 2371 2372 case IFM_1000_CX: 2373 case IFM_1000_T: 2374 phy |= SK_GPHY_COPPER; 2375 break; 2376 } 2377 2378 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2379 2380 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2381 DELAY(1000); 2382 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2383 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2384 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2385 2386 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2387 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2388 2389 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2390 2391 /* unused read of the interrupt source register */ 2392 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2393 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2394 2395 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2396 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2397 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2398 2399 /* MIB Counter Clear Mode set */ 2400 reg |= YU_PAR_MIB_CLR; 2401 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2402 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2403 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2404 2405 /* MIB Counter Clear Mode clear */ 2406 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2407 reg &= ~YU_PAR_MIB_CLR; 2408 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2409 2410 /* receive control reg */ 2411 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2412 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2413 YU_RCR_CRCR); 2414 2415 /* transmit parameter register */ 2416 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2417 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2418 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2419 2420 /* serial mode register */ 2421 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2422 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2423 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2424 2425 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2426 /* Setup Yukon's address */ 2427 for (i = 0; i < 3; i++) { 2428 /* Write Source Address 1 (unicast filter) */ 2429 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2430 sc_if->arpcom.ac_enaddr[i * 2] | 2431 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2432 } 2433 2434 for (i = 0; i < 3; i++) { 2435 reg = sk_win_read_2(sc_if->sk_softc, 2436 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2437 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2438 } 2439 2440 /* Set multicast filter */ 2441 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2442 sk_setmulti(sc_if); 2443 2444 /* enable interrupt mask for counter overflows */ 2445 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2446 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2447 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2448 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2449 2450 /* Configure RX MAC FIFO */ 2451 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2452 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2453 2454 /* Configure TX MAC FIFO */ 2455 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2456 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2457 2458 DPRINTFN(6, ("sk_init_yukon: end\n")); 2459} 2460 2461/* 2462 * Note that to properly initialize any part of the GEnesis chip, 2463 * you first have to take it out of reset mode. 2464 */ 2465void 2466sk_init(void *xsc_if) 2467{ 2468 struct sk_if_softc *sc_if = xsc_if; 2469 struct sk_softc *sc = sc_if->sk_softc; 2470 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2471 struct mii_data *mii = &sc_if->sk_mii; 2472 int s; 2473 2474 DPRINTFN(2, ("sk_init\n")); 2475 2476 s = splimp(); 2477 2478 /* Cancel pending I/O and free all RX/TX buffers. */ 2479 sk_stop(sc_if); 2480 2481 if (sc->sk_type == SK_GENESIS) { 2482 /* Configure LINK_SYNC LED */ 2483 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2484 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2485 SK_LINKLED_LINKSYNC_ON); 2486 2487 /* Configure RX LED */ 2488 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2489 SK_RXLEDCTL_COUNTER_START); 2490 2491 /* Configure TX LED */ 2492 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2493 SK_TXLEDCTL_COUNTER_START); 2494 } 2495 2496 /* Configure I2C registers */ 2497 2498 /* Configure XMAC(s) */ 2499 switch (sc->sk_type) { 2500 case SK_GENESIS: 2501 sk_init_xmac(sc_if); 2502 break; 2503 case SK_YUKON: 2504 sk_init_yukon(sc_if); 2505 break; 2506 } 2507 mii_mediachg(mii); 2508 2509 if (sc->sk_type == SK_GENESIS) { 2510 /* Configure MAC FIFOs */ 2511 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2512 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2513 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2514 2515 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2516 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2517 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2518 } 2519 2520 /* Configure transmit arbiter(s) */ 2521 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2522 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2523 2524 /* Configure RAMbuffers */ 2525 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2526 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2527 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2528 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2529 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2530 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2531 2532 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2533 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2534 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2535 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2536 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2537 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2538 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2539 2540 /* Configure BMUs */ 2541 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2542 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2543 SK_RX_RING_ADDR(sc_if, 0)); 2544 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2545 2546 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2547 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2548 SK_TX_RING_ADDR(sc_if, 0)); 2549 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2550 2551 /* Init descriptors */ 2552 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2553 printf("%s: initialization failed: no " 2554 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2555 sk_stop(sc_if); 2556 splx(s); 2557 return; 2558 } 2559 2560 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2561 printf("%s: initialization failed: no " 2562 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2563 sk_stop(sc_if); 2564 splx(s); 2565 return; 2566 } 2567 2568 /* Configure interrupt handling */ 2569 CSR_READ_4(sc, SK_ISSR); 2570 if (sc_if->sk_port == SK_PORT_A) 2571 sc->sk_intrmask |= SK_INTRS1; 2572 else 2573 sc->sk_intrmask |= SK_INTRS2; 2574 2575 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2576 2577 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2578 2579 /* Start BMUs. */ 2580 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2581 2582 if (sc->sk_type == SK_GENESIS) { 2583 /* Enable XMACs TX and RX state machines */ 2584 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2585 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2586 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2587 } 2588 2589 if (sc->sk_type == SK_YUKON) { 2590 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2591 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2592 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2593 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2594 } 2595 2596 2597 ifp->if_flags |= IFF_RUNNING; 2598 ifp->if_flags &= ~IFF_OACTIVE; 2599 2600 splx(s); 2601} 2602 2603void 2604sk_stop(struct sk_if_softc *sc_if) 2605{ 2606 struct sk_softc *sc = sc_if->sk_softc; 2607 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2608 int i; 2609 2610 DPRINTFN(2, ("sk_stop\n")); 2611 2612 timeout_del(&sc_if->sk_tick_ch); 2613 2614 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2615 u_int32_t val; 2616 2617 /* Put PHY back into reset. */ 2618 val = sk_win_read_4(sc, SK_GPIO); 2619 if (sc_if->sk_port == SK_PORT_A) { 2620 val |= SK_GPIO_DIR0; 2621 val &= ~SK_GPIO_DAT0; 2622 } else { 2623 val |= SK_GPIO_DIR2; 2624 val &= ~SK_GPIO_DAT2; 2625 } 2626 sk_win_write_4(sc, SK_GPIO, val); 2627 } 2628 2629 /* Turn off various components of this interface. */ 2630 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2631 switch (sc->sk_type) { 2632 case SK_GENESIS: 2633 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2634 SK_TXMACCTL_XMAC_RESET); 2635 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2636 break; 2637 case SK_YUKON: 2638 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2639 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2640 break; 2641 } 2642 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2643 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2644 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2645 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2646 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2647 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2648 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2649 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2650 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2651 2652 /* Disable interrupts */ 2653 if (sc_if->sk_port == SK_PORT_A) 2654 sc->sk_intrmask &= ~SK_INTRS1; 2655 else 2656 sc->sk_intrmask &= ~SK_INTRS2; 2657 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2658 2659 SK_XM_READ_2(sc_if, XM_ISR); 2660 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2661 2662 /* Free RX and TX mbufs still in the queues. */ 2663 for (i = 0; i < SK_RX_RING_CNT; i++) { 2664 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2665 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2666 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2667 } 2668 } 2669 2670 for (i = 0; i < SK_TX_RING_CNT; i++) { 2671 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2672 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2673 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2674 } 2675 } 2676 2677 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2678} 2679 2680struct cfattach skc_ca = { 2681 sizeof(struct sk_softc), skc_probe, skc_attach, 2682}; 2683 2684struct cfdriver skc_cd = { 2685 0, "skc", DV_DULL 2686}; 2687 2688struct cfattach sk_ca = { 2689 sizeof(struct sk_if_softc), sk_probe, sk_attach, 2690}; 2691 2692struct cfdriver sk_cd = { 2693 0, "sk", DV_IFNET 2694}; 2695 2696#ifdef SK_DEBUG 2697void 2698sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2699{ 2700#define DESC_PRINT(X) \ 2701 if (desc->X) \ 2702 printf("txdesc[%d]." #X "=%#x\n", \ 2703 idx, desc->X); 2704 2705 DESC_PRINT(sk_ctl); 2706 DESC_PRINT(sk_next); 2707 DESC_PRINT(sk_data_lo); 2708 DESC_PRINT(sk_data_hi); 2709 DESC_PRINT(sk_xmac_txstat); 2710 DESC_PRINT(sk_rsvd0); 2711 DESC_PRINT(sk_csum_startval); 2712 DESC_PRINT(sk_csum_startpos); 2713 DESC_PRINT(sk_csum_writepos); 2714 DESC_PRINT(sk_rsvd1); 2715#undef PRINT 2716} 2717 2718void 2719sk_dump_bytes(const char *data, int len) 2720{ 2721 int c, i, j; 2722 2723 for (i = 0; i < len; i += 16) { 2724 printf("%08x ", i); 2725 c = len - i; 2726 if (c > 16) c = 16; 2727 2728 for (j = 0; j < c; j++) { 2729 printf("%02x ", data[i + j] & 0xff); 2730 if ((j & 0xf) == 7 && j > 0) 2731 printf(" "); 2732 } 2733 2734 for (; j < 16; j++) 2735 printf(" "); 2736 printf(" "); 2737 2738 for (j = 0; j < c; j++) { 2739 int ch = data[i + j] & 0xff; 2740 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2741 } 2742 2743 printf("\n"); 2744 2745 if (c < 16) 2746 break; 2747 } 2748} 2749 2750void 2751sk_dump_mbuf(struct mbuf *m) 2752{ 2753 int count = m->m_pkthdr.len; 2754 2755 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2756 2757 while (count > 0 && m) { 2758 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2759 m, m->m_data, m->m_len); 2760 sk_dump_bytes(mtod(m, char *), m->m_len); 2761 2762 count -= m->m_len; 2763 m = m->m_next; 2764 } 2765} 2766#endif 2767