1/* $OpenBSD: if_sk.c,v 1.197 2024/06/26 01:40:49 jsg Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37/* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53/* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72/* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89#include "bpfilter.h" 90 91#include <sys/param.h> 92#include <sys/systm.h> 93#include <sys/sockio.h> 94#include <sys/mbuf.h> 95#include <sys/malloc.h> 96#include <sys/timeout.h> 97#include <sys/device.h> 98#include <sys/queue.h> 99 100#include <net/if.h> 101 102#include <netinet/in.h> 103#include <netinet/if_ether.h> 104 105#include <net/if_media.h> 106 107#if NBPFILTER > 0 108#include <net/bpf.h> 109#endif 110 111#include <dev/mii/mii.h> 112#include <dev/mii/miivar.h> 113#include <dev/mii/brgphyreg.h> 114 115#include <dev/pci/pcireg.h> 116#include <dev/pci/pcivar.h> 117#include <dev/pci/pcidevs.h> 118 119#include <dev/pci/if_skreg.h> 120#include <dev/pci/if_skvar.h> 121 122int skc_probe(struct device *, void *, void *); 123void skc_attach(struct device *, struct device *self, void *aux); 124int skc_detach(struct device *, int); 125int skc_activate(struct device *, int); 126int sk_probe(struct device *, void *, void *); 127void sk_attach(struct device *, struct device *self, void *aux); 128int sk_detach(struct device *, int); 129int sk_activate(struct device *, int); 130int skcprint(void *, const char *); 131int sk_intr(void *); 132void sk_intr_bcom(struct sk_if_softc *); 133void sk_intr_xmac(struct sk_if_softc *); 134void sk_intr_yukon(struct sk_if_softc *); 135static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 136void sk_rxeof(struct sk_if_softc *); 137void sk_txeof(struct sk_if_softc *); 138int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 139void sk_start(struct ifnet *); 140int sk_ioctl(struct ifnet *, u_long, caddr_t); 141void sk_init(void *); 142void sk_init_xmac(struct sk_if_softc *); 143void sk_init_yukon(struct sk_if_softc *); 144void sk_stop(struct sk_if_softc *, int softonly); 145void sk_watchdog(struct ifnet *); 146int sk_ifmedia_upd(struct ifnet *); 147void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 148void skc_reset(struct sk_softc *); 149int sk_newbuf(struct sk_if_softc *); 150int sk_reset(struct sk_if_softc *); 151int sk_init_rx_ring(struct sk_if_softc *); 152void sk_fill_rx_ring(struct sk_if_softc *); 153int sk_init_tx_ring(struct sk_if_softc *); 154 155int sk_xmac_miibus_readreg(struct device *, int, int); 156void sk_xmac_miibus_writereg(struct device *, int, int, int); 157void sk_xmac_miibus_statchg(struct device *); 158 159int sk_marv_miibus_readreg(struct device *, int, int); 160void sk_marv_miibus_writereg(struct device *, int, int, int); 161void sk_marv_miibus_statchg(struct device *); 162 163void sk_setfilt(struct sk_if_softc *, caddr_t, int); 164void sk_iff(struct sk_if_softc *); 165void sk_iff_xmac(struct sk_if_softc *); 166void sk_iff_yukon(struct sk_if_softc *); 167 168void sk_tick(void *); 169void sk_yukon_tick(void *); 170 171#ifdef SK_DEBUG 172#define DPRINTF(x) if (skdebug) printf x 173#define DPRINTFN(n,x) if (skdebug >= (n)) printf x 174int skdebug = 0; 175 176void sk_dump_txdesc(struct sk_tx_desc *, int); 177void sk_dump_mbuf(struct mbuf *); 178void sk_dump_bytes(const char *, int); 179#else 180#define DPRINTF(x) 181#define DPRINTFN(n,x) 182#endif 183 184/* supported device vendors */ 185const struct pci_matchid skc_devices[] = { 186 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940 }, 187 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940B }, 188 { PCI_VENDOR_CNET, PCI_PRODUCT_CNET_GIGACARD }, 189 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_A1 }, 190 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_B1 }, 191 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_BELKIN }, 194 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK98XX }, 195 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK98XX2 }, 196 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821 }, 197 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9843 } 198}; 199 200#define SK_LINKSYS_EG1032_SUBID 0x00151737 201 202static inline u_int32_t 203sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 204{ 205 return CSR_READ_4(sc, reg); 206} 207 208static inline u_int16_t 209sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 210{ 211 return CSR_READ_2(sc, reg); 212} 213 214static inline u_int8_t 215sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 216{ 217 return CSR_READ_1(sc, reg); 218} 219 220static inline void 221sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 222{ 223 CSR_WRITE_4(sc, reg, x); 224} 225 226static inline void 227sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 228{ 229 CSR_WRITE_2(sc, reg, x); 230} 231 232static inline void 233sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 234{ 235 CSR_WRITE_1(sc, reg, x); 236} 237 238int 239sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 240{ 241 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 242 int i; 243 244 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 245 246 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 247 return (0); 248 249 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 250 SK_XM_READ_2(sc_if, XM_PHY_DATA); 251 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 252 for (i = 0; i < SK_TIMEOUT; i++) { 253 DELAY(1); 254 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 255 XM_MMUCMD_PHYDATARDY) 256 break; 257 } 258 259 if (i == SK_TIMEOUT) { 260 printf("%s: phy failed to come ready\n", 261 sc_if->sk_dev.dv_xname); 262 return (0); 263 } 264 } 265 DELAY(1); 266 return (SK_XM_READ_2(sc_if, XM_PHY_DATA)); 267} 268 269void 270sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 271{ 272 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 273 int i; 274 275 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 276 277 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 278 for (i = 0; i < SK_TIMEOUT; i++) { 279 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 280 break; 281 } 282 283 if (i == SK_TIMEOUT) { 284 printf("%s: phy failed to come ready\n", 285 sc_if->sk_dev.dv_xname); 286 return; 287 } 288 289 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 290 for (i = 0; i < SK_TIMEOUT; i++) { 291 DELAY(1); 292 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 293 break; 294 } 295 296 if (i == SK_TIMEOUT) 297 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 298} 299 300void 301sk_xmac_miibus_statchg(struct device *dev) 302{ 303 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 304 struct mii_data *mii = &sc_if->sk_mii; 305 306 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 307 308 /* 309 * If this is a GMII PHY, manually set the XMAC's 310 * duplex mode accordingly. 311 */ 312 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 313 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 314 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 315 else 316 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 317 } 318} 319 320int 321sk_marv_miibus_readreg(struct device *dev, int phy, int reg) 322{ 323 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 324 u_int16_t val; 325 int i; 326 327 if (phy != 0 || 328 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 329 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 330 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 331 phy, reg)); 332 return (0); 333 } 334 335 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 336 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 337 338 for (i = 0; i < SK_TIMEOUT; i++) { 339 DELAY(1); 340 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 341 if (val & YU_SMICR_READ_VALID) 342 break; 343 } 344 345 if (i == SK_TIMEOUT) { 346 printf("%s: phy failed to come ready\n", 347 sc_if->sk_dev.dv_xname); 348 return (0); 349 } 350 351 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 352 SK_TIMEOUT)); 353 354 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 355 356 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 357 phy, reg, val)); 358 359 return (val); 360} 361 362void 363sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 364{ 365 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 366 int i; 367 368 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 369 phy, reg, val)); 370 371 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 372 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 373 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 374 375 for (i = 0; i < SK_TIMEOUT; i++) { 376 DELAY(1); 377 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 378 break; 379 } 380 381 if (i == SK_TIMEOUT) 382 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 383} 384 385void 386sk_marv_miibus_statchg(struct device *dev) 387{ 388 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 389 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 390} 391 392void 393sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 394{ 395 int base = XM_RXFILT_ENTRY(slot); 396 397 SK_XM_WRITE_2(sc_if, base, letoh16(*(u_int16_t *)(&addr[0]))); 398 SK_XM_WRITE_2(sc_if, base + 2, letoh16(*(u_int16_t *)(&addr[2]))); 399 SK_XM_WRITE_2(sc_if, base + 4, letoh16(*(u_int16_t *)(&addr[4]))); 400} 401 402void 403sk_iff(struct sk_if_softc *sc_if) 404{ 405 struct sk_softc *sc = sc_if->sk_softc; 406 407 if (SK_IS_GENESIS(sc)) 408 sk_iff_xmac(sc_if); 409 else 410 sk_iff_yukon(sc_if); 411} 412 413void 414sk_iff_xmac(struct sk_if_softc *sc_if) 415{ 416 struct ifnet *ifp = &sc_if->arpcom.ac_if; 417 struct arpcom *ac = &sc_if->arpcom; 418 struct ether_multi *enm; 419 struct ether_multistep step; 420 u_int32_t reg, hashes[2]; 421 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 422 int h, i; 423 424 reg = SK_XM_READ_4(sc_if, XM_MODE); 425 reg &= ~(XM_MODE_RX_NOBROAD | XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH | 426 XM_MODE_RX_USE_PERFECT | XM_MODE_RX_USE_STATION); 427 ifp->if_flags &= ~IFF_ALLMULTI; 428 429 /* 430 * Always accept frames destined to our station address. 431 */ 432 reg |= XM_MODE_RX_USE_STATION; 433 434 /* don't use perfect filter. */ 435 for (i = 1; i < XM_RXFILT_MAX; i++) 436 sk_setfilt(sc_if, (caddr_t)&dummy, i); 437 438 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 439 ifp->if_flags |= IFF_ALLMULTI; 440 if (ifp->if_flags & IFF_PROMISC) 441 reg |= XM_MODE_RX_PROMISC; 442 else 443 reg |= XM_MODE_RX_USE_HASH; 444 hashes[0] = hashes[1] = 0xFFFFFFFF; 445 } else { 446 reg |= XM_MODE_RX_USE_HASH; 447 /* Program new filter. */ 448 bzero(hashes, sizeof(hashes)); 449 450 ETHER_FIRST_MULTI(step, ac, enm); 451 while (enm != NULL) { 452 h = ether_crc32_le(enm->enm_addrlo, 453 ETHER_ADDR_LEN) & ((1 << SK_HASH_BITS) - 1); 454 455 if (h < 32) 456 hashes[0] |= (1 << h); 457 else 458 hashes[1] |= (1 << (h - 32)); 459 460 ETHER_NEXT_MULTI(step, enm); 461 } 462 } 463 464 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 465 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 466 SK_XM_WRITE_4(sc_if, XM_MODE, reg); 467} 468 469void 470sk_iff_yukon(struct sk_if_softc *sc_if) 471{ 472 struct ifnet *ifp = &sc_if->arpcom.ac_if; 473 struct arpcom *ac = &sc_if->arpcom; 474 struct ether_multi *enm; 475 struct ether_multistep step; 476 u_int32_t hashes[2]; 477 u_int16_t rcr; 478 int h; 479 480 rcr = SK_YU_READ_2(sc_if, YUKON_RCR); 481 rcr &= ~(YU_RCR_MUFLEN | YU_RCR_UFLEN); 482 ifp->if_flags &= ~IFF_ALLMULTI; 483 484 /* 485 * Always accept frames destined to our station address. 486 */ 487 rcr |= YU_RCR_UFLEN; 488 489 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 490 ifp->if_flags |= IFF_ALLMULTI; 491 if (ifp->if_flags & IFF_PROMISC) 492 rcr &= ~YU_RCR_UFLEN; 493 else 494 rcr |= YU_RCR_MUFLEN; 495 hashes[0] = hashes[1] = 0xFFFFFFFF; 496 } else { 497 rcr |= YU_RCR_MUFLEN; 498 /* Program new filter. */ 499 bzero(hashes, sizeof(hashes)); 500 501 ETHER_FIRST_MULTI(step, ac, enm); 502 while (enm != NULL) { 503 h = ether_crc32_be(enm->enm_addrlo, 504 ETHER_ADDR_LEN) & ((1 << SK_HASH_BITS) - 1); 505 506 if (h < 32) 507 hashes[0] |= (1 << h); 508 else 509 hashes[1] |= (1 << (h - 32)); 510 511 ETHER_NEXT_MULTI(step, enm); 512 } 513 } 514 515 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 516 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 517 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 518 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 519 SK_YU_WRITE_2(sc_if, YUKON_RCR, rcr); 520} 521 522int 523sk_init_rx_ring(struct sk_if_softc *sc_if) 524{ 525 struct sk_chain_data *cd = &sc_if->sk_cdata; 526 struct sk_ring_data *rd = sc_if->sk_rdata; 527 int i, nexti; 528 529 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 530 531 for (i = 0; i < SK_RX_RING_CNT; i++) { 532 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 533 if (i == (SK_RX_RING_CNT - 1)) 534 nexti = 0; 535 else 536 nexti = i + 1; 537 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 538 htolem32(&rd->sk_rx_ring[i].sk_next, 539 SK_RX_RING_ADDR(sc_if, nexti)); 540 } 541 542 sc_if->sk_cdata.sk_rx_prod = 0; 543 sc_if->sk_cdata.sk_rx_cons = 0; 544 545 if_rxr_init(&sc_if->sk_cdata.sk_rx_ring, 2, SK_RX_RING_CNT); 546 547 sk_fill_rx_ring(sc_if); 548 549 return (0); 550} 551 552void 553sk_fill_rx_ring(struct sk_if_softc *sc_if) 554{ 555 struct if_rxring *rxr = &sc_if->sk_cdata.sk_rx_ring; 556 u_int slots; 557 558 for (slots = if_rxr_get(rxr, SK_RX_RING_CNT); slots > 0; slots--) { 559 if (sk_newbuf(sc_if) == ENOBUFS) 560 break; 561 } 562 if_rxr_put(rxr, slots); 563} 564 565int 566sk_init_tx_ring(struct sk_if_softc *sc_if) 567{ 568 struct sk_softc *sc = sc_if->sk_softc; 569 struct sk_chain_data *cd = &sc_if->sk_cdata; 570 struct sk_ring_data *rd = sc_if->sk_rdata; 571 bus_dmamap_t dmamap; 572 struct sk_txmap_entry *entry; 573 int i, nexti; 574 575 bzero(sc_if->sk_rdata->sk_tx_ring, 576 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 577 578 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 579 for (i = 0; i < SK_TX_RING_CNT; i++) { 580 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 581 if (i == (SK_TX_RING_CNT - 1)) 582 nexti = 0; 583 else 584 nexti = i + 1; 585 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 586 htolem32(&rd->sk_tx_ring[i].sk_next, 587 SK_TX_RING_ADDR(sc_if, nexti)); 588 589 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 590 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 591 return (ENOBUFS); 592 593 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 594 if (!entry) { 595 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 596 return (ENOBUFS); 597 } 598 entry->dmamap = dmamap; 599 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 600 } 601 602 sc_if->sk_cdata.sk_tx_prod = 0; 603 sc_if->sk_cdata.sk_tx_cons = 0; 604 sc_if->sk_cdata.sk_tx_cnt = 0; 605 606 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 607 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 608 609 return (0); 610} 611 612int 613sk_newbuf(struct sk_if_softc *sc_if) 614{ 615 struct mbuf *m; 616 struct sk_chain *c; 617 struct sk_rx_desc *r; 618 bus_dmamap_t dmamap; 619 u_int prod; 620 int error; 621 uint64_t dva; 622 623 m = MCLGETL(NULL, M_DONTWAIT, SK_JLEN); 624 if (m == NULL) 625 return (ENOBUFS); 626 627 m->m_len = m->m_pkthdr.len = SK_JLEN; 628 m_adj(m, ETHER_ALIGN); 629 630 prod = sc_if->sk_cdata.sk_rx_prod; 631 dmamap = sc_if->sk_cdata.sk_rx_map[prod]; 632 633 error = bus_dmamap_load_mbuf(sc_if->sk_softc->sc_dmatag, dmamap, m, 634 BUS_DMA_READ|BUS_DMA_NOWAIT); 635 if (error) { 636 m_freem(m); 637 return (ENOBUFS); 638 } 639 640 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 641 dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 642 643 c = &sc_if->sk_cdata.sk_rx_chain[prod]; 644 c->sk_mbuf = m; 645 646 r = c->sk_desc; 647 dva = dmamap->dm_segs[0].ds_addr; 648 htolem32(&r->sk_data_lo, dva); 649 htolem32(&r->sk_data_hi, dva >> 32); 650 htolem32(&r->sk_ctl, dmamap->dm_segs[0].ds_len | SK_RXSTAT); 651 652 SK_CDRXSYNC(sc_if, prod, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 653 654 SK_INC(prod, SK_RX_RING_CNT); 655 sc_if->sk_cdata.sk_rx_prod = prod; 656 657 return (0); 658} 659 660/* 661 * Set media options. 662 */ 663int 664sk_ifmedia_upd(struct ifnet *ifp) 665{ 666 struct sk_if_softc *sc_if = ifp->if_softc; 667 668 mii_mediachg(&sc_if->sk_mii); 669 return (0); 670} 671 672/* 673 * Report current media status. 674 */ 675void 676sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 677{ 678 struct sk_if_softc *sc_if = ifp->if_softc; 679 680 mii_pollstat(&sc_if->sk_mii); 681 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 682 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 683} 684 685int 686sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 687{ 688 struct sk_if_softc *sc_if = ifp->if_softc; 689 struct ifreq *ifr = (struct ifreq *) data; 690 struct mii_data *mii; 691 int s, error = 0; 692 693 s = splnet(); 694 695 switch(command) { 696 case SIOCSIFADDR: 697 ifp->if_flags |= IFF_UP; 698 if (!(ifp->if_flags & IFF_RUNNING)) 699 sk_init(sc_if); 700 break; 701 702 case SIOCSIFFLAGS: 703 if (ifp->if_flags & IFF_UP) { 704 if (ifp->if_flags & IFF_RUNNING) 705 error = ENETRESET; 706 else 707 sk_init(sc_if); 708 } else { 709 if (ifp->if_flags & IFF_RUNNING) 710 sk_stop(sc_if, 0); 711 } 712 break; 713 714 case SIOCGIFMEDIA: 715 case SIOCSIFMEDIA: 716 mii = &sc_if->sk_mii; 717 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 718 break; 719 720 case SIOCGIFRXR: 721 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 722 NULL, SK_JLEN, &sc_if->sk_cdata.sk_rx_ring); 723 724 break; 725 726 default: 727 error = ether_ioctl(ifp, &sc_if->arpcom, command, data); 728 } 729 730 if (error == ENETRESET) { 731 if (ifp->if_flags & IFF_RUNNING) 732 sk_iff(sc_if); 733 error = 0; 734 } 735 736 splx(s); 737 return (error); 738} 739 740/* 741 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 742 * IDs against our list and return a device name if we find a match. 743 */ 744int 745skc_probe(struct device *parent, void *match, void *aux) 746{ 747 struct pci_attach_args *pa = aux; 748 pci_chipset_tag_t pc = pa->pa_pc; 749 pcireg_t subid; 750 751 subid = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 752 753 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 754 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 755 subid == SK_LINKSYS_EG1032_SUBID) 756 return (1); 757 758 return (pci_matchbyid((struct pci_attach_args *)aux, skc_devices, 759 nitems(skc_devices))); 760} 761 762/* 763 * Force the GEnesis into reset, then bring it out of reset. 764 */ 765void 766skc_reset(struct sk_softc *sc) 767{ 768 u_int32_t imtimer_ticks; 769 770 DPRINTFN(2, ("skc_reset\n")); 771 772 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 773 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 774 if (SK_IS_YUKON(sc)) 775 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 776 777 DELAY(1000); 778 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 779 DELAY(2); 780 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 781 if (SK_IS_YUKON(sc)) 782 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 783 784 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 785 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 786 CSR_READ_2(sc, SK_LINK_CTRL))); 787 788 if (SK_IS_GENESIS(sc)) { 789 /* Configure packet arbiter */ 790 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 791 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 792 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 793 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 794 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 795 } 796 797 /* Enable RAM interface */ 798 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 799 800 /* 801 * Configure interrupt moderation. The moderation timer 802 * defers interrupts specified in the interrupt moderation 803 * timer mask based on the timeout specified in the interrupt 804 * moderation timer init register. Each bit in the timer 805 * register represents one tick, so to specify a timeout in 806 * microseconds, we have to multiply by the correct number of 807 * ticks-per-microsecond. 808 */ 809 switch (sc->sk_type) { 810 case SK_GENESIS: 811 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 812 break; 813 default: 814 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 815 break; 816 } 817 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(100)); 818 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 819 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 820 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 821} 822 823int 824sk_probe(struct device *parent, void *match, void *aux) 825{ 826 struct skc_attach_args *sa = aux; 827 828 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 829 return (0); 830 831 switch (sa->skc_type) { 832 case SK_GENESIS: 833 case SK_YUKON: 834 case SK_YUKON_LITE: 835 case SK_YUKON_LP: 836 return (1); 837 } 838 839 return (0); 840} 841 842/* 843 * Each XMAC chip is attached as a separate logical IP interface. 844 * Single port cards will have only one logical interface of course. 845 */ 846void 847sk_attach(struct device *parent, struct device *self, void *aux) 848{ 849 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 850 struct sk_softc *sc = (struct sk_softc *)parent; 851 struct skc_attach_args *sa = aux; 852 struct ifnet *ifp; 853 caddr_t kva; 854 int i, error; 855 856 sc_if->sk_port = sa->skc_port; 857 sc_if->sk_softc = sc; 858 sc->sk_if[sa->skc_port] = sc_if; 859 860 if (sa->skc_port == SK_PORT_A) 861 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 862 if (sa->skc_port == SK_PORT_B) 863 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 864 865 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 866 867 /* 868 * Get station address for this interface. Note that 869 * dual port cards actually come with three station 870 * addresses: one for each port, plus an extra. The 871 * extra one is used by the SysKonnect driver software 872 * as a 'virtual' station address for when both ports 873 * are operating in failover mode. Currently we don't 874 * use this extra address. 875 */ 876 for (i = 0; i < ETHER_ADDR_LEN; i++) 877 sc_if->arpcom.ac_enaddr[i] = 878 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 879 880 printf(": address %s\n", 881 ether_sprintf(sc_if->arpcom.ac_enaddr)); 882 883 /* 884 * Set up RAM buffer addresses. The NIC will have a certain 885 * amount of SRAM on it, somewhere between 512K and 2MB. We 886 * need to divide this up a) between the transmitter and 887 * receiver and b) between the two XMACs, if this is a 888 * dual port NIC. Our algorithm is to divide up the memory 889 * evenly so that everyone gets a fair share. 890 */ 891 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 892 u_int32_t chunk, val; 893 894 chunk = sc->sk_ramsize / 2; 895 val = sc->sk_rboff / sizeof(u_int64_t); 896 sc_if->sk_rx_ramstart = val; 897 val += (chunk / sizeof(u_int64_t)); 898 sc_if->sk_rx_ramend = val - 1; 899 sc_if->sk_tx_ramstart = val; 900 val += (chunk / sizeof(u_int64_t)); 901 sc_if->sk_tx_ramend = val - 1; 902 } else { 903 u_int32_t chunk, val; 904 905 chunk = sc->sk_ramsize / 4; 906 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 907 sizeof(u_int64_t); 908 sc_if->sk_rx_ramstart = val; 909 val += (chunk / sizeof(u_int64_t)); 910 sc_if->sk_rx_ramend = val - 1; 911 sc_if->sk_tx_ramstart = val; 912 val += (chunk / sizeof(u_int64_t)); 913 sc_if->sk_tx_ramend = val - 1; 914 } 915 916 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 917 " tx_ramstart=%#x tx_ramend=%#x\n", 918 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 919 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 920 921 /* Read and save PHY type */ 922 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 923 924 /* Set PHY address */ 925 if (SK_IS_GENESIS(sc)) { 926 switch (sc_if->sk_phytype) { 927 case SK_PHYTYPE_XMAC: 928 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 929 break; 930 case SK_PHYTYPE_BCOM: 931 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 932 break; 933 default: 934 printf("%s: unsupported PHY type: %d\n", 935 sc->sk_dev.dv_xname, sc_if->sk_phytype); 936 return; 937 } 938 } 939 940 if (SK_IS_YUKON(sc)) { 941 if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 942 sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) { 943 /* not initialized, punt */ 944 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 945 946 sc->sk_coppertype = 1; 947 } 948 949 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 950 951 if (!(sc->sk_coppertype)) 952 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 953 } 954 955 /* Allocate the descriptor queues. */ 956 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 957 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 958 BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 959 printf(": can't alloc rx buffers\n"); 960 goto fail; 961 } 962 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 963 sc_if->sk_ring_nseg, sizeof(struct sk_ring_data), 964 &kva, BUS_DMA_NOWAIT)) { 965 printf(": can't map dma buffers (%lu bytes)\n", 966 (ulong)sizeof(struct sk_ring_data)); 967 goto fail_1; 968 } 969 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 970 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 971 &sc_if->sk_ring_map)) { 972 printf(": can't create dma map\n"); 973 goto fail_2; 974 } 975 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 976 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 977 printf(": can't load dma map\n"); 978 goto fail_3; 979 } 980 sc_if->sk_rdata = (struct sk_ring_data *)kva; 981 982 for (i = 0; i < SK_RX_RING_CNT; i++) { 983 error = bus_dmamap_create(sc->sc_dmatag, SK_JLEN, 1, 984 SK_JLEN, 0, 0, &sc_if->sk_cdata.sk_rx_map[i]); 985 if (error != 0) { 986 printf(": unable to create rx DMA map %d, " 987 "error = %d\n", i, error); 988 goto fail_4; 989 } 990 } 991 992 ifp = &sc_if->arpcom.ac_if; 993 ifp->if_softc = sc_if; 994 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 995 ifp->if_ioctl = sk_ioctl; 996 ifp->if_start = sk_start; 997 ifp->if_watchdog = sk_watchdog; 998 ifp->if_hardmtu = SK_JUMBO_MTU; 999 ifq_init_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1); 1000 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1001 1002 ifp->if_capabilities = IFCAP_VLAN_MTU; 1003 1004 if (sk_reset(sc_if) == -1) { 1005 printf(": unknown device type %d\n", sc_if->sk_softc->sk_type); 1006 /* dealloc jumbo on error */ 1007 goto fail_3; 1008 } 1009 1010 DPRINTFN(2, ("sk_attach: 1\n")); 1011 1012 sc_if->sk_mii.mii_ifp = ifp; 1013 if (SK_IS_GENESIS(sc)) { 1014 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1015 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1016 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1017 } else { 1018 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1019 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1020 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1021 } 1022 1023 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1024 sk_ifmedia_upd, sk_ifmedia_sts); 1025 if (SK_IS_GENESIS(sc)) { 1026 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1027 MII_OFFSET_ANY, 0); 1028 } else { 1029 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1030 MII_OFFSET_ANY, MIIF_DOPAUSE); 1031 } 1032 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1033 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1034 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1035 0, NULL); 1036 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1037 } else 1038 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1039 1040 if (SK_IS_GENESIS(sc)) { 1041 timeout_set(&sc_if->sk_tick_ch, sk_tick, sc_if); 1042 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1043 } else 1044 timeout_set(&sc_if->sk_tick_ch, sk_yukon_tick, sc_if); 1045 1046 /* 1047 * Call MI attach routines. 1048 */ 1049 if_attach(ifp); 1050 ether_ifattach(ifp); 1051 1052 DPRINTFN(2, ("sk_attach: end\n")); 1053 return; 1054fail_4: 1055 for (i = 0; i < SK_RX_RING_CNT; i++) { 1056 if (sc_if->sk_cdata.sk_rx_map[i] == NULL) 1057 continue; 1058 1059 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_map[i]); 1060 } 1061fail_3: 1062 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct sk_ring_data)); 1063fail_2: 1064 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1065fail_1: 1066 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1067fail: 1068 sc->sk_if[sa->skc_port] = NULL; 1069} 1070 1071int 1072sk_reset(struct sk_if_softc *sc_if) 1073{ 1074 /* 1075 * Do miibus setup. 1076 */ 1077 switch (sc_if->sk_softc->sk_type) { 1078 case SK_GENESIS: 1079 sk_init_xmac(sc_if); 1080 break; 1081 case SK_YUKON: 1082 case SK_YUKON_LITE: 1083 case SK_YUKON_LP: 1084 sk_init_yukon(sc_if); 1085 break; 1086 default: 1087 return (-1); 1088 } 1089 return (0); 1090} 1091 1092int 1093sk_detach(struct device *self, int flags) 1094{ 1095 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 1096 struct sk_softc *sc = sc_if->sk_softc; 1097 struct ifnet *ifp= &sc_if->arpcom.ac_if; 1098 1099 if (sc->sk_if[sc_if->sk_port] == NULL) 1100 return (0); 1101 1102 sk_stop(sc_if, 1); 1103 1104 /* Detach any PHYs we might have. */ 1105 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1106 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1107 1108 /* Delete any remaining media. */ 1109 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1110 1111 ether_ifdetach(ifp); 1112 if_detach(ifp); 1113 1114 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc_if->sk_rdata, 1115 sizeof(struct sk_ring_data)); 1116 bus_dmamem_free(sc->sc_dmatag, 1117 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1118 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1119 sc->sk_if[sc_if->sk_port] = NULL; 1120 1121 return (0); 1122} 1123 1124int 1125sk_activate(struct device *self, int act) 1126{ 1127 struct sk_if_softc *sc_if = (void *)self; 1128 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1129 int rv = 0; 1130 1131 switch (act) { 1132 case DVACT_RESUME: 1133 sk_reset(sc_if); 1134 if (ifp->if_flags & IFF_RUNNING) 1135 sk_init(sc_if); 1136 break; 1137 default: 1138 rv = config_activate_children(self, act); 1139 break; 1140 } 1141 return (rv); 1142} 1143 1144int 1145skcprint(void *aux, const char *pnp) 1146{ 1147 struct skc_attach_args *sa = aux; 1148 1149 if (pnp) 1150 printf("sk port %c at %s", 1151 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1152 else 1153 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1154 return (UNCONF); 1155} 1156 1157/* 1158 * Attach the interface. Allocate softc structures, do ifmedia 1159 * setup and ethernet/BPF attach. 1160 */ 1161void 1162skc_attach(struct device *parent, struct device *self, void *aux) 1163{ 1164 struct sk_softc *sc = (struct sk_softc *)self; 1165 struct pci_attach_args *pa = aux; 1166 struct skc_attach_args skca; 1167 pci_chipset_tag_t pc = pa->pa_pc; 1168 pcireg_t memtype; 1169 pci_intr_handle_t ih; 1170 const char *intrstr = NULL; 1171 u_int8_t skrs; 1172 char *revstr = NULL; 1173 1174 DPRINTFN(2, ("begin skc_attach\n")); 1175 1176 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 1177 1178 /* 1179 * Map control/status registers. 1180 */ 1181 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1182 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1183 &sc->sk_bhandle, NULL, &sc->sk_bsize, 0)) { 1184 printf(": can't map mem space\n"); 1185 return; 1186 } 1187 1188 sc->sc_dmatag = pa->pa_dmat; 1189 1190 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1191 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1192 sc->sk_pc = pc; 1193 1194 /* bail out here if chip is not recognized */ 1195 if (! SK_IS_GENESIS(sc) && ! SK_IS_YUKON(sc)) { 1196 printf(": unknown chip type: %d\n", sc->sk_type); 1197 goto fail_1; 1198 } 1199 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1200 1201 /* Allocate interrupt */ 1202 if (pci_intr_map(pa, &ih)) { 1203 printf(": couldn't map interrupt\n"); 1204 goto fail_1; 1205 } 1206 1207 intrstr = pci_intr_string(pc, ih); 1208 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc, 1209 self->dv_xname); 1210 if (sc->sk_intrhand == NULL) { 1211 printf(": couldn't establish interrupt"); 1212 if (intrstr != NULL) 1213 printf(" at %s", intrstr); 1214 printf("\n"); 1215 goto fail_1; 1216 } 1217 1218 /* Reset the adapter. */ 1219 skc_reset(sc); 1220 1221 skrs = sk_win_read_1(sc, SK_EPROM0); 1222 if (SK_IS_GENESIS(sc)) { 1223 /* Read and save RAM size and RAMbuffer offset */ 1224 switch(skrs) { 1225 case SK_RAMSIZE_512K_64: 1226 sc->sk_ramsize = 0x80000; 1227 sc->sk_rboff = SK_RBOFF_0; 1228 break; 1229 case SK_RAMSIZE_1024K_64: 1230 sc->sk_ramsize = 0x100000; 1231 sc->sk_rboff = SK_RBOFF_80000; 1232 break; 1233 case SK_RAMSIZE_1024K_128: 1234 sc->sk_ramsize = 0x100000; 1235 sc->sk_rboff = SK_RBOFF_0; 1236 break; 1237 case SK_RAMSIZE_2048K_128: 1238 sc->sk_ramsize = 0x200000; 1239 sc->sk_rboff = SK_RBOFF_0; 1240 break; 1241 default: 1242 printf(": unknown ram size: %d\n", skrs); 1243 goto fail_2; 1244 break; 1245 } 1246 } else { 1247 if (skrs == 0x00) 1248 sc->sk_ramsize = 0x20000; 1249 else 1250 sc->sk_ramsize = skrs * (1<<12); 1251 sc->sk_rboff = SK_RBOFF_0; 1252 } 1253 1254 DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n", 1255 sc->sk_ramsize, sc->sk_ramsize / 1024, sc->sk_rboff)); 1256 1257 /* Read and save physical media type */ 1258 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1259 1260 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1') 1261 sc->sk_coppertype = 1; 1262 else 1263 sc->sk_coppertype = 0; 1264 1265 switch (sc->sk_type) { 1266 case SK_GENESIS: 1267 sc->sk_name = "GEnesis"; 1268 break; 1269 case SK_YUKON: 1270 sc->sk_name = "Yukon"; 1271 break; 1272 case SK_YUKON_LITE: 1273 sc->sk_name = "Yukon Lite"; 1274 break; 1275 case SK_YUKON_LP: 1276 sc->sk_name = "Yukon LP"; 1277 break; 1278 default: 1279 sc->sk_name = "Yukon (Unknown)"; 1280 } 1281 1282 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1283 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1284 u_int32_t flashaddr; 1285 u_int8_t testbyte; 1286 1287 flashaddr = sk_win_read_4(sc, SK_EP_ADDR); 1288 1289 /* test Flash-Address Register */ 1290 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff); 1291 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1292 1293 if (testbyte != 0) { 1294 /* This is a Yukon Lite Rev A0 */ 1295 sc->sk_type = SK_YUKON_LITE; 1296 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1297 /* restore Flash-Address Register */ 1298 sk_win_write_4(sc, SK_EP_ADDR, flashaddr); 1299 } 1300 } 1301 1302 if (sc->sk_type == SK_YUKON_LITE) { 1303 switch (sc->sk_rev) { 1304 case SK_YUKON_LITE_REV_A0: 1305 revstr = "A0"; 1306 break; 1307 case SK_YUKON_LITE_REV_A1: 1308 revstr = "A1"; 1309 break; 1310 case SK_YUKON_LITE_REV_A3: 1311 revstr = "A3"; 1312 break; 1313 default: 1314 ; 1315 } 1316 } 1317 1318 /* Announce the product name. */ 1319 printf(", %s", sc->sk_name); 1320 if (revstr != NULL) 1321 printf(" rev. %s", revstr); 1322 printf(" (0x%x): %s\n", sc->sk_rev, intrstr); 1323 1324 sc->sk_macs = 1; 1325 1326 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) 1327 sc->sk_macs++; 1328 1329 skca.skc_port = SK_PORT_A; 1330 skca.skc_type = sc->sk_type; 1331 skca.skc_rev = sc->sk_rev; 1332 (void)config_found(&sc->sk_dev, &skca, skcprint); 1333 1334 if (sc->sk_macs > 1) { 1335 skca.skc_port = SK_PORT_B; 1336 skca.skc_type = sc->sk_type; 1337 skca.skc_rev = sc->sk_rev; 1338 (void)config_found(&sc->sk_dev, &skca, skcprint); 1339 } 1340 1341 /* Turn on the 'driver is loaded' LED. */ 1342 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1343 1344 return; 1345 1346fail_2: 1347 pci_intr_disestablish(pc, sc->sk_intrhand); 1348fail_1: 1349 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1350} 1351 1352int 1353skc_detach(struct device *self, int flags) 1354{ 1355 struct sk_softc *sc = (struct sk_softc *)self; 1356 int rv; 1357 1358 if (sc->sk_intrhand) 1359 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1360 1361 rv = config_detach_children(self, flags); 1362 if (rv != 0) 1363 return (rv); 1364 1365 if (sc->sk_bsize > 0) 1366 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1367 1368 return(0); 1369} 1370 1371int 1372skc_activate(struct device *self, int act) 1373{ 1374 struct sk_softc *sc = (void *)self; 1375 int rv = 0; 1376 1377 switch (act) { 1378 case DVACT_RESUME: 1379 skc_reset(sc); 1380 rv = config_activate_children(self, act); 1381 break; 1382 default: 1383 rv = config_activate_children(self, act); 1384 break; 1385 } 1386 return (rv); 1387} 1388 1389int 1390sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1391{ 1392 struct sk_softc *sc = sc_if->sk_softc; 1393 struct sk_tx_desc *f = NULL; 1394 u_int32_t frag, cur, sk_ctl; 1395 int i; 1396 struct sk_txmap_entry *entry; 1397 bus_dmamap_t txmap; 1398 uint64_t dva; 1399 1400 DPRINTFN(2, ("sk_encap\n")); 1401 1402 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1403 if (entry == NULL) { 1404 DPRINTFN(2, ("sk_encap: no txmap available\n")); 1405 return (ENOBUFS); 1406 } 1407 txmap = entry->dmamap; 1408 1409 cur = frag = *txidx; 1410 1411 switch (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1412 BUS_DMA_STREAMING | BUS_DMA_NOWAIT)) { 1413 case 0: 1414 break; 1415 1416 case EFBIG: /* mbuf chain is too fragmented */ 1417 if (m_defrag(m_head, M_DONTWAIT) == 0 && 1418 bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1419 BUS_DMA_STREAMING | BUS_DMA_NOWAIT) == 0) 1420 break; 1421 default: 1422 return (1); 1423 } 1424 1425 /* Sync the DMA map. */ 1426 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1427 BUS_DMASYNC_PREWRITE); 1428 1429 for (i = 0; i < txmap->dm_nsegs; i++) { 1430 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1431 dva = txmap->dm_segs[i].ds_addr; 1432 htolem32(&f->sk_data_lo, dva); 1433 htolem32(&f->sk_data_hi, dva >> 32); 1434 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1435 if (i == 0) 1436 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1437 else 1438 sk_ctl |= SK_TXCTL_OWN; 1439 htolem32(&f->sk_ctl, sk_ctl); 1440 cur = frag; 1441 SK_INC(frag, SK_TX_RING_CNT); 1442 } 1443 1444 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1445 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1446 1447 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1448 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1449 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1450 1451 /* Sync descriptors before handing to chip */ 1452 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1453 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1454 1455 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1456 htole32(SK_TXCTL_OWN); 1457 1458 /* Sync first descriptor to hand it off */ 1459 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1460 1461 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1462 1463#ifdef SK_DEBUG 1464 if (skdebug >= 2) { 1465 struct sk_tx_desc *desc; 1466 u_int32_t idx; 1467 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1468 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1469 sk_dump_txdesc(desc, idx); 1470 } 1471 } 1472#endif 1473 1474 *txidx = frag; 1475 1476 DPRINTFN(2, ("sk_encap: completed successfully\n")); 1477 1478 return (0); 1479} 1480 1481void 1482sk_start(struct ifnet *ifp) 1483{ 1484 struct sk_if_softc *sc_if = ifp->if_softc; 1485 struct sk_softc *sc = sc_if->sk_softc; 1486 struct mbuf *m_head = NULL; 1487 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1488 int post = 0; 1489 1490 DPRINTFN(2, ("sk_start\n")); 1491 1492 for (;;) { 1493 if (sc_if->sk_cdata.sk_tx_cnt + SK_NTXSEG + 1 > 1494 SK_TX_RING_CNT) { 1495 ifq_set_oactive(&ifp->if_snd); 1496 break; 1497 } 1498 1499 m_head = ifq_dequeue(&ifp->if_snd); 1500 if (m_head == NULL) 1501 break; 1502 1503 /* 1504 * Pack the data into the transmit ring. If we 1505 * don't have room, set the OACTIVE flag and wait 1506 * for the NIC to drain the ring. 1507 */ 1508 if (sk_encap(sc_if, m_head, &idx)) { 1509 m_freem(m_head); 1510 continue; 1511 } 1512 1513 /* now we are committed to transmit the packet */ 1514 1515 /* 1516 * If there's a BPF listener, bounce a copy of this frame 1517 * to him. 1518 */ 1519#if NBPFILTER > 0 1520 if (ifp->if_bpf) 1521 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1522#endif 1523 1524 post = 1; 1525 } 1526 if (post == 0) 1527 return; 1528 1529 /* Transmit */ 1530 sc_if->sk_cdata.sk_tx_prod = idx; 1531 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1532 1533 /* Set a timeout in case the chip goes out to lunch. */ 1534 ifp->if_timer = SK_TX_TIMEOUT; 1535} 1536 1537 1538void 1539sk_watchdog(struct ifnet *ifp) 1540{ 1541 struct sk_if_softc *sc_if = ifp->if_softc; 1542 1543 /* 1544 * Reclaim first as there is a possibility of losing Tx completion 1545 * interrupts. 1546 */ 1547 sk_txeof(sc_if); 1548 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1549 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1550 1551 ifp->if_oerrors++; 1552 1553 sk_init(sc_if); 1554 } 1555} 1556 1557static __inline int 1558sk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1559{ 1560 if (sc->sk_type == SK_GENESIS) { 1561 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME || 1562 XM_RXSTAT_BYTES(stat) != len) 1563 return (0); 1564 } else { 1565 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1566 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1567 YU_RXSTAT_JABBER)) != 0 || 1568 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1569 YU_RXSTAT_BYTES(stat) != len) 1570 return (0); 1571 } 1572 1573 return (1); 1574} 1575 1576void 1577sk_rxeof(struct sk_if_softc *sc_if) 1578{ 1579 struct sk_softc *sc = sc_if->sk_softc; 1580 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1581 struct if_rxring *rxr = &sc_if->sk_cdata.sk_rx_ring; 1582 struct mbuf *m; 1583 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1584 struct sk_chain *cur_rx; 1585 struct sk_rx_desc *cur_desc; 1586 int cur, total_len = 0; 1587 u_int32_t rxstat, sk_ctl; 1588 bus_dmamap_t dmamap; 1589 1590 DPRINTFN(2, ("sk_rxeof\n")); 1591 1592 cur = sc_if->sk_cdata.sk_rx_cons; 1593 while (if_rxr_inuse(rxr) > 0) { 1594 /* Sync the descriptor */ 1595 SK_CDRXSYNC(sc_if, cur, 1596 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1597 1598 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1599 if (cur_rx->sk_mbuf == NULL) 1600 break; 1601 1602 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1603 sk_ctl = lemtoh32(&cur_desc->sk_ctl); 1604 if ((sk_ctl & SK_RXCTL_OWN) != 0) 1605 break; 1606 1607 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1608 1609 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1610 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1611 bus_dmamap_unload(sc_if->sk_softc->sc_dmatag, dmamap); 1612 1613 m = cur_rx->sk_mbuf; 1614 cur_rx->sk_mbuf = NULL; 1615 if_rxr_put(rxr, 1); 1616 SK_INC(cur, SK_RX_RING_CNT); 1617 1618 total_len = SK_RXBYTES(sk_ctl); 1619 rxstat = lemtoh32(&cur_desc->sk_xmac_rxstat); 1620 1621 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 1622 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 1623 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 1624 total_len < SK_MIN_FRAMELEN || 1625 total_len > SK_JUMBO_FRAMELEN || 1626 sk_rxvalid(sc, rxstat, total_len) == 0) { 1627 ifp->if_ierrors++; 1628 m_freem(m); 1629 continue; 1630 } 1631 1632 m->m_pkthdr.len = m->m_len = total_len; 1633 1634 ml_enqueue(&ml, m); 1635 } 1636 sc_if->sk_cdata.sk_rx_cons = cur; 1637 1638 if (ifiq_input(&ifp->if_rcv, &ml)) 1639 if_rxr_livelocked(rxr); 1640 1641 sk_fill_rx_ring(sc_if); 1642 1643} 1644 1645void 1646sk_txeof(struct sk_if_softc *sc_if) 1647{ 1648 struct sk_softc *sc = sc_if->sk_softc; 1649 struct sk_tx_desc *cur_tx; 1650 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1651 u_int32_t idx, sk_ctl; 1652 struct sk_txmap_entry *entry; 1653 1654 DPRINTFN(2, ("sk_txeof\n")); 1655 1656 /* 1657 * Go through our tx ring and free mbufs for those 1658 * frames that have been sent. 1659 */ 1660 idx = sc_if->sk_cdata.sk_tx_cons; 1661 while (idx != sc_if->sk_cdata.sk_tx_prod) { 1662 SK_CDTXSYNC(sc_if, idx, 1, 1663 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1664 1665 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1666 sk_ctl = lemtoh32(&cur_tx->sk_ctl); 1667#ifdef SK_DEBUG 1668 if (skdebug >= 2) 1669 sk_dump_txdesc(cur_tx, idx); 1670#endif 1671 if (sk_ctl & SK_TXCTL_OWN) { 1672 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 1673 break; 1674 } 1675 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1676 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1677 1678 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1679 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1680 1681 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1682 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1683 1684 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1685 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1686 link); 1687 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1688 } 1689 sc_if->sk_cdata.sk_tx_cnt--; 1690 SK_INC(idx, SK_TX_RING_CNT); 1691 } 1692 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? SK_TX_TIMEOUT : 0; 1693 1694 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 1695 ifq_clr_oactive(&ifp->if_snd); 1696 1697 sc_if->sk_cdata.sk_tx_cons = idx; 1698} 1699 1700void 1701sk_tick(void *xsc_if) 1702{ 1703 struct sk_if_softc *sc_if = xsc_if; 1704 struct mii_data *mii = &sc_if->sk_mii; 1705 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1706 int i; 1707 1708 DPRINTFN(2, ("sk_tick\n")); 1709 1710 if (!(ifp->if_flags & IFF_UP)) 1711 return; 1712 1713 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1714 sk_intr_bcom(sc_if); 1715 return; 1716 } 1717 1718 /* 1719 * According to SysKonnect, the correct way to verify that 1720 * the link has come back up is to poll bit 0 of the GPIO 1721 * register three times. This pin has the signal from the 1722 * link sync pin connected to it; if we read the same link 1723 * state 3 times in a row, we know the link is up. 1724 */ 1725 for (i = 0; i < 3; i++) { 1726 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1727 break; 1728 } 1729 1730 if (i != 3) { 1731 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1732 return; 1733 } 1734 1735 /* Turn the GP0 interrupt back on. */ 1736 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1737 SK_XM_READ_2(sc_if, XM_ISR); 1738 mii_tick(mii); 1739 timeout_del(&sc_if->sk_tick_ch); 1740} 1741 1742void 1743sk_yukon_tick(void *xsc_if) 1744{ 1745 struct sk_if_softc *sc_if = xsc_if; 1746 struct mii_data *mii = &sc_if->sk_mii; 1747 int s; 1748 1749 s = splnet(); 1750 mii_tick(mii); 1751 splx(s); 1752 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1753} 1754 1755void 1756sk_intr_bcom(struct sk_if_softc *sc_if) 1757{ 1758 struct mii_data *mii = &sc_if->sk_mii; 1759 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1760 int status; 1761 1762 DPRINTFN(2, ("sk_intr_bcom\n")); 1763 1764 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1765 1766 /* 1767 * Read the PHY interrupt register to make sure 1768 * we clear any pending interrupts. 1769 */ 1770 status = sk_xmac_miibus_readreg((struct device *)sc_if, 1771 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1772 1773 if (!(ifp->if_flags & IFF_RUNNING)) { 1774 sk_init_xmac(sc_if); 1775 return; 1776 } 1777 1778 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1779 int lstat; 1780 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 1781 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 1782 1783 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1784 mii_mediachg(mii); 1785 /* Turn off the link LED. */ 1786 SK_IF_WRITE_1(sc_if, 0, 1787 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1788 sc_if->sk_link = 0; 1789 } else if (status & BRGPHY_ISR_LNK_CHG) { 1790 sk_xmac_miibus_writereg((struct device *)sc_if, 1791 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 1792 mii_tick(mii); 1793 sc_if->sk_link = 1; 1794 /* Turn on the link LED. */ 1795 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1796 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1797 SK_LINKLED_BLINK_OFF); 1798 } else { 1799 mii_tick(mii); 1800 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1801 } 1802 } 1803 1804 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1805} 1806 1807void 1808sk_intr_xmac(struct sk_if_softc *sc_if) 1809{ 1810 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 1811 1812 DPRINTFN(2, ("sk_intr_xmac\n")); 1813 1814 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1815 if (status & XM_ISR_GP0_SET) { 1816 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1817 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1818 } 1819 1820 if (status & XM_ISR_AUTONEG_DONE) { 1821 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1822 } 1823 } 1824 1825 if (status & XM_IMR_TX_UNDERRUN) 1826 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1827 1828 if (status & XM_IMR_RX_OVERRUN) 1829 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1830} 1831 1832void 1833sk_intr_yukon(struct sk_if_softc *sc_if) 1834{ 1835 u_int8_t status; 1836 1837 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1838 /* RX overrun */ 1839 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1840 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1841 SK_RFCTL_RX_FIFO_OVER); 1842 } 1843 /* TX underrun */ 1844 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1845 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1846 SK_TFCTL_TX_FIFO_UNDER); 1847 } 1848 1849 DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status)); 1850} 1851 1852int 1853sk_intr(void *xsc) 1854{ 1855 struct sk_softc *sc = xsc; 1856 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1857 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1858 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1859 u_int32_t status; 1860 int claimed = 0; 1861 1862 status = CSR_READ_4(sc, SK_ISSR); 1863 if (status == 0 || status == 0xffffffff) 1864 return (0); 1865 1866 if (sc_if0 != NULL) 1867 ifp0 = &sc_if0->arpcom.ac_if; 1868 if (sc_if1 != NULL) 1869 ifp1 = &sc_if1->arpcom.ac_if; 1870 1871 for (; (status &= sc->sk_intrmask) != 0;) { 1872 claimed = 1; 1873 1874 /* Handle receive interrupts first. */ 1875 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 1876 sk_rxeof(sc_if0); 1877 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1878 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1879 } 1880 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 1881 sk_rxeof(sc_if1); 1882 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1883 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1884 } 1885 1886 /* Then transmit interrupts. */ 1887 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 1888 sk_txeof(sc_if0); 1889 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1890 SK_TXBMU_CLR_IRQ_EOF); 1891 } 1892 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 1893 sk_txeof(sc_if1); 1894 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1895 SK_TXBMU_CLR_IRQ_EOF); 1896 } 1897 1898 /* Then MAC interrupts. */ 1899 if (sc_if0 && (status & SK_ISR_MAC1) && 1900 (ifp0->if_flags & IFF_RUNNING)) { 1901 if (SK_IS_GENESIS(sc)) 1902 sk_intr_xmac(sc_if0); 1903 else 1904 sk_intr_yukon(sc_if0); 1905 } 1906 1907 if (sc_if1 && (status & SK_ISR_MAC2) && 1908 (ifp1->if_flags & IFF_RUNNING)) { 1909 if (SK_IS_GENESIS(sc)) 1910 sk_intr_xmac(sc_if1); 1911 else 1912 sk_intr_yukon(sc_if1); 1913 1914 } 1915 1916 if (status & SK_ISR_EXTERNAL_REG) { 1917 if (sc_if0 != NULL && 1918 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 1919 sk_intr_bcom(sc_if0); 1920 1921 if (sc_if1 != NULL && 1922 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 1923 sk_intr_bcom(sc_if1); 1924 } 1925 status = CSR_READ_4(sc, SK_ISSR); 1926 } 1927 1928 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1929 1930 if (ifp0 != NULL && !ifq_empty(&ifp0->if_snd)) 1931 sk_start(ifp0); 1932 if (ifp1 != NULL && !ifq_empty(&ifp1->if_snd)) 1933 sk_start(ifp1); 1934 1935 return (claimed); 1936} 1937 1938void 1939sk_init_xmac(struct sk_if_softc *sc_if) 1940{ 1941 struct sk_softc *sc = sc_if->sk_softc; 1942 struct sk_bcom_hack bhack[] = { 1943 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 1944 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 1945 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 1946 { 0, 0 } }; 1947 1948 DPRINTFN(2, ("sk_init_xmac\n")); 1949 1950 /* Unreset the XMAC. */ 1951 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 1952 DELAY(1000); 1953 1954 /* Reset the XMAC's internal state. */ 1955 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 1956 1957 /* Save the XMAC II revision */ 1958 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 1959 1960 /* 1961 * Perform additional initialization for external PHYs, 1962 * namely for the 1000baseTX cards that use the XMAC's 1963 * GMII mode. 1964 */ 1965 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1966 int i = 0; 1967 u_int32_t val; 1968 1969 /* Take PHY out of reset. */ 1970 val = sk_win_read_4(sc, SK_GPIO); 1971 if (sc_if->sk_port == SK_PORT_A) 1972 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 1973 else 1974 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 1975 sk_win_write_4(sc, SK_GPIO, val); 1976 1977 /* Enable GMII mode on the XMAC. */ 1978 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 1979 1980 sk_xmac_miibus_writereg((struct device *)sc_if, 1981 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 1982 DELAY(10000); 1983 sk_xmac_miibus_writereg((struct device *)sc_if, 1984 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 1985 1986 /* 1987 * Early versions of the BCM5400 apparently have 1988 * a bug that requires them to have their reserved 1989 * registers initialized to some magic values. I don't 1990 * know what the numbers do, I'm just the messenger. 1991 */ 1992 if (sk_xmac_miibus_readreg((struct device *)sc_if, 1993 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 1994 while(bhack[i].reg) { 1995 sk_xmac_miibus_writereg((struct device *)sc_if, 1996 SK_PHYADDR_BCOM, bhack[i].reg, 1997 bhack[i].val); 1998 i++; 1999 } 2000 } 2001 } 2002 2003 /* Set station address */ 2004 SK_XM_WRITE_2(sc_if, XM_PAR0, 2005 letoh16(*(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0]))); 2006 SK_XM_WRITE_2(sc_if, XM_PAR1, 2007 letoh16(*(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2]))); 2008 SK_XM_WRITE_2(sc_if, XM_PAR2, 2009 letoh16(*(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4]))); 2010 2011 /* We don't need the FCS appended to the packet. */ 2012 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2013 2014 /* We want short frames padded to 60 bytes. */ 2015 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2016 2017 /* 2018 * Enable the reception of all error frames. This is 2019 * a necessary evil due to the design of the XMAC. The 2020 * XMAC's receive FIFO is only 8K in size, however jumbo 2021 * frames can be up to 9000 bytes in length. When bad 2022 * frame filtering is enabled, the XMAC's RX FIFO operates 2023 * in 'store and forward' mode. For this to work, the 2024 * entire frame has to fit into the FIFO, but that means 2025 * that jumbo frames larger than 8192 bytes will be 2026 * truncated. Disabling all bad frame filtering causes 2027 * the RX FIFO to operate in streaming mode, in which 2028 * case the XMAC will start transferring frames out of the 2029 * RX FIFO as soon as the FIFO threshold is reached. 2030 */ 2031 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2032 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2033 XM_MODE_RX_INRANGELEN); 2034 2035 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2036 2037 /* 2038 * Bump up the transmit threshold. This helps hold off transmit 2039 * underruns when we're blasting traffic from both ports at once. 2040 */ 2041 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2042 2043 /* Program promiscuous mode and multicast filters. */ 2044 sk_iff(sc_if); 2045 2046 /* Clear and enable interrupts */ 2047 SK_XM_READ_2(sc_if, XM_ISR); 2048 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2049 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2050 else 2051 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2052 2053 /* Configure MAC arbiter */ 2054 switch(sc_if->sk_xmac_rev) { 2055 case XM_XMAC_REV_B2: 2056 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2057 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2058 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2059 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2060 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2061 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2062 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2063 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2064 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2065 break; 2066 case XM_XMAC_REV_C1: 2067 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2068 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2069 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2070 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2071 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2072 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2073 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2074 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2075 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2076 break; 2077 default: 2078 break; 2079 } 2080 sk_win_write_2(sc, SK_MACARB_CTL, 2081 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2082 2083 sc_if->sk_link = 1; 2084} 2085 2086void 2087sk_init_yukon(struct sk_if_softc *sc_if) 2088{ 2089 u_int32_t phy, v; 2090 u_int16_t reg; 2091 struct sk_softc *sc; 2092 int i; 2093 2094 sc = sc_if->sk_softc; 2095 2096 DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n", 2097 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2098 2099 if (sc->sk_type == SK_YUKON_LITE && 2100 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2101 /* 2102 * Workaround code for COMA mode, set PHY reset. 2103 * Otherwise it will not correctly take chip out of 2104 * powerdown (coma) 2105 */ 2106 v = sk_win_read_4(sc, SK_GPIO); 2107 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9; 2108 sk_win_write_4(sc, SK_GPIO, v); 2109 } 2110 2111 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2112 2113 /* GMAC and GPHY Reset */ 2114 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2115 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2116 DELAY(1000); 2117 2118 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2119 2120 if (sc->sk_type == SK_YUKON_LITE && 2121 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2122 /* 2123 * Workaround code for COMA mode, clear PHY reset 2124 */ 2125 v = sk_win_read_4(sc, SK_GPIO); 2126 v |= SK_GPIO_DIR9; 2127 v &= ~SK_GPIO_DAT9; 2128 sk_win_write_4(sc, SK_GPIO, v); 2129 } 2130 2131 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2132 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2133 2134 if (sc->sk_coppertype) 2135 phy |= SK_GPHY_COPPER; 2136 else 2137 phy |= SK_GPHY_FIBER; 2138 2139 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2140 2141 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2142 DELAY(1000); 2143 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2144 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2145 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2146 2147 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2148 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2149 2150 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2151 2152 /* unused read of the interrupt source register */ 2153 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2154 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2155 2156 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2157 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2158 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2159 2160 /* MIB Counter Clear Mode set */ 2161 reg |= YU_PAR_MIB_CLR; 2162 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2163 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2164 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2165 2166 /* MIB Counter Clear Mode clear */ 2167 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2168 reg &= ~YU_PAR_MIB_CLR; 2169 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2170 2171 /* receive control reg */ 2172 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2173 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2174 2175 /* transmit parameter register */ 2176 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2177 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2178 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2179 2180 /* serial mode register */ 2181 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2182 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2183 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | YU_SMR_IPG_DATA(0x1e)); 2184 2185 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2186 /* Setup Yukon's address */ 2187 for (i = 0; i < 3; i++) { 2188 /* Write Source Address 1 (unicast filter) */ 2189 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2190 sc_if->arpcom.ac_enaddr[i * 2] | 2191 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2192 } 2193 2194 for (i = 0; i < 3; i++) { 2195 reg = sk_win_read_2(sc_if->sk_softc, 2196 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2197 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2198 } 2199 2200 /* Program promiscuous mode and multicast filters. */ 2201 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2202 sk_iff(sc_if); 2203 2204 /* enable interrupt mask for counter overflows */ 2205 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2206 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2207 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2208 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2209 2210 /* Configure RX MAC FIFO Flush Mask */ 2211 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2212 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2213 YU_RXSTAT_JABBER; 2214 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2215 2216 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 2217 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 2218 v = SK_TFCTL_OPERATION_ON; 2219 else 2220 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 2221 /* Configure RX MAC FIFO */ 2222 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2223 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 2224 2225 /* Increase flush threshold to 64 bytes */ 2226 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2227 SK_RFCTL_FIFO_THRESHOLD + 1); 2228 2229 /* Configure TX MAC FIFO */ 2230 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2231 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2232 2233 DPRINTFN(6, ("sk_init_yukon: end\n")); 2234} 2235 2236/* 2237 * Note that to properly initialize any part of the GEnesis chip, 2238 * you first have to take it out of reset mode. 2239 */ 2240void 2241sk_init(void *xsc_if) 2242{ 2243 struct sk_if_softc *sc_if = xsc_if; 2244 struct sk_softc *sc = sc_if->sk_softc; 2245 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2246 struct mii_data *mii = &sc_if->sk_mii; 2247 int s; 2248 2249 DPRINTFN(2, ("sk_init\n")); 2250 2251 s = splnet(); 2252 2253 /* Cancel pending I/O and free all RX/TX buffers. */ 2254 sk_stop(sc_if, 0); 2255 2256 if (SK_IS_GENESIS(sc)) { 2257 /* Configure LINK_SYNC LED */ 2258 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2259 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2260 SK_LINKLED_LINKSYNC_ON); 2261 2262 /* Configure RX LED */ 2263 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2264 SK_RXLEDCTL_COUNTER_START); 2265 2266 /* Configure TX LED */ 2267 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2268 SK_TXLEDCTL_COUNTER_START); 2269 } 2270 2271 /* 2272 * Configure descriptor poll timer 2273 * 2274 * SK-NET GENESIS data sheet says that possibility of losing Start 2275 * transmit command due to CPU/cache related interim storage problems 2276 * under certain conditions. The document recommends a polling 2277 * mechanism to send a Start transmit command to initiate transfer 2278 * of ready descriptors regulary. To cope with this issue sk(4) now 2279 * enables descriptor poll timer to initiate descriptor processing 2280 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still 2281 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx 2282 * command instead of waiting for next descriptor polling time. 2283 * The same rule may apply to Rx side too but it seems that is not 2284 * needed at the moment. 2285 * Since sk(4) uses descriptor polling as a last resort there is no 2286 * need to set smaller polling time than maximum allowable one. 2287 */ 2288 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX); 2289 2290 /* Configure I2C registers */ 2291 2292 /* Configure XMAC(s) */ 2293 switch (sc->sk_type) { 2294 case SK_GENESIS: 2295 sk_init_xmac(sc_if); 2296 break; 2297 case SK_YUKON: 2298 case SK_YUKON_LITE: 2299 case SK_YUKON_LP: 2300 sk_init_yukon(sc_if); 2301 break; 2302 } 2303 mii_mediachg(mii); 2304 2305 if (SK_IS_GENESIS(sc)) { 2306 /* Configure MAC FIFOs */ 2307 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2308 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2309 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2310 2311 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2312 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2313 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2314 } 2315 2316 /* Configure transmit arbiter(s) */ 2317 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2318 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2319 2320 /* Configure RAMbuffers */ 2321 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2322 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2323 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2324 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2325 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2326 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2327 2328 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2329 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2330 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2331 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2332 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2333 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2334 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2335 2336 /* Configure BMUs */ 2337 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2338 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2339 SK_RX_RING_ADDR(sc_if, 0)); 2340 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2341 2342 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2343 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2344 SK_TX_RING_ADDR(sc_if, 0)); 2345 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2346 2347 /* Init descriptors */ 2348 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2349 printf("%s: initialization failed: no " 2350 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2351 sk_stop(sc_if, 0); 2352 splx(s); 2353 return; 2354 } 2355 2356 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2357 printf("%s: initialization failed: no " 2358 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2359 sk_stop(sc_if, 0); 2360 splx(s); 2361 return; 2362 } 2363 2364 /* Configure interrupt handling */ 2365 CSR_READ_4(sc, SK_ISSR); 2366 if (sc_if->sk_port == SK_PORT_A) 2367 sc->sk_intrmask |= SK_INTRS1; 2368 else 2369 sc->sk_intrmask |= SK_INTRS2; 2370 2371 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2372 2373 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2374 2375 /* Start BMUs. */ 2376 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2377 2378 if (SK_IS_GENESIS(sc)) { 2379 /* Enable XMACs TX and RX state machines */ 2380 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2381 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2382 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2383 } 2384 2385 if (SK_IS_YUKON(sc)) { 2386 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2387 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2388 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2389 } 2390 2391 /* Activate descriptor polling timer */ 2392 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START); 2393 /* start transfer of Tx descriptors */ 2394 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2395 2396 ifp->if_flags |= IFF_RUNNING; 2397 ifq_clr_oactive(&ifp->if_snd); 2398 2399 if (SK_IS_YUKON(sc)) 2400 timeout_add_sec(&sc_if->sk_tick_ch, 1); 2401 2402 splx(s); 2403} 2404 2405void 2406sk_stop(struct sk_if_softc *sc_if, int softonly) 2407{ 2408 struct sk_softc *sc = sc_if->sk_softc; 2409 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2410 bus_dmamap_t dmamap; 2411 struct sk_txmap_entry *dma; 2412 int i; 2413 u_int32_t val; 2414 2415 DPRINTFN(2, ("sk_stop\n")); 2416 2417 timeout_del(&sc_if->sk_tick_ch); 2418 2419 ifp->if_flags &= ~IFF_RUNNING; 2420 ifq_clr_oactive(&ifp->if_snd); 2421 2422 if (!softonly) { 2423 /* stop Tx descriptor polling timer */ 2424 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 2425 /* stop transfer of Tx descriptors */ 2426 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); 2427 for (i = 0; i < SK_TIMEOUT; i++) { 2428 val = CSR_READ_4(sc, sc_if->sk_tx_bmu); 2429 if (!(val & SK_TXBMU_TX_STOP)) 2430 break; 2431 DELAY(1); 2432 } 2433 if (i == SK_TIMEOUT) { 2434 printf("%s: cannot stop transfer of Tx descriptors\n", 2435 sc_if->sk_dev.dv_xname); 2436 } 2437 /* stop transfer of Rx descriptors */ 2438 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP); 2439 for (i = 0; i < SK_TIMEOUT; i++) { 2440 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR); 2441 if (!(val & SK_RXBMU_RX_STOP)) 2442 break; 2443 DELAY(1); 2444 } 2445 if (i == SK_TIMEOUT) { 2446 printf("%s: cannot stop transfer of Rx descriptors\n", 2447 sc_if->sk_dev.dv_xname); 2448 } 2449 2450 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2451 u_int32_t val; 2452 2453 /* Put PHY back into reset. */ 2454 val = sk_win_read_4(sc, SK_GPIO); 2455 if (sc_if->sk_port == SK_PORT_A) { 2456 val |= SK_GPIO_DIR0; 2457 val &= ~SK_GPIO_DAT0; 2458 } else { 2459 val |= SK_GPIO_DIR2; 2460 val &= ~SK_GPIO_DAT2; 2461 } 2462 sk_win_write_4(sc, SK_GPIO, val); 2463 } 2464 2465 /* Turn off various components of this interface. */ 2466 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2467 switch (sc->sk_type) { 2468 case SK_GENESIS: 2469 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2470 SK_TXMACCTL_XMAC_RESET); 2471 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2472 break; 2473 case SK_YUKON: 2474 case SK_YUKON_LITE: 2475 case SK_YUKON_LP: 2476 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2477 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2478 break; 2479 } 2480 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2481 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2482 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2483 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2484 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2485 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2486 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2487 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2488 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2489 2490 /* Disable interrupts */ 2491 if (sc_if->sk_port == SK_PORT_A) 2492 sc->sk_intrmask &= ~SK_INTRS1; 2493 else 2494 sc->sk_intrmask &= ~SK_INTRS2; 2495 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2496 2497 SK_XM_READ_2(sc_if, XM_ISR); 2498 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2499 } 2500 2501 /* Free RX and TX mbufs still in the queues. */ 2502 for (i = 0; i < SK_RX_RING_CNT; i++) { 2503 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2504 dmamap = sc_if->sk_cdata.sk_rx_map[i]; 2505 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2506 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2507 bus_dmamap_unload(sc_if->sk_softc->sc_dmatag, dmamap); 2508 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2509 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2510 } 2511 } 2512 2513 for (i = 0; i < SK_TX_RING_CNT; i++) { 2514 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2515 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2516 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2517 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2518 sc_if->sk_cdata.sk_tx_map[i], link); 2519 sc_if->sk_cdata.sk_tx_map[i] = 0; 2520 } 2521 } 2522 2523 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2524 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2525 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2526 free(dma, M_DEVBUF, 0); 2527 } 2528} 2529 2530const struct cfattach skc_ca = { 2531 sizeof(struct sk_softc), skc_probe, skc_attach, skc_detach, 2532 skc_activate 2533}; 2534 2535struct cfdriver skc_cd = { 2536 0, "skc", DV_DULL 2537}; 2538 2539const struct cfattach sk_ca = { 2540 sizeof(struct sk_if_softc), sk_probe, sk_attach, sk_detach, 2541 sk_activate 2542}; 2543 2544struct cfdriver sk_cd = { 2545 NULL, "sk", DV_IFNET 2546}; 2547 2548#ifdef SK_DEBUG 2549void 2550sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2551{ 2552#define DESC_PRINT(X) \ 2553 if (X) \ 2554 printf("txdesc[%d]." #X "=%#x\n", idx, X); 2555 2556 DESC_PRINT(letoh32(desc->sk_ctl)); 2557 DESC_PRINT(letoh32(desc->sk_next)); 2558 DESC_PRINT(letoh32(desc->sk_data_lo)); 2559 DESC_PRINT(letoh32(desc->sk_data_hi)); 2560 DESC_PRINT(letoh32(desc->sk_xmac_txstat)); 2561 DESC_PRINT(letoh16(desc->sk_rsvd0)); 2562 DESC_PRINT(letoh16(desc->sk_rsvd1)); 2563#undef PRINT 2564} 2565 2566void 2567sk_dump_bytes(const char *data, int len) 2568{ 2569 int c, i, j; 2570 2571 for (i = 0; i < len; i += 16) { 2572 printf("%08x ", i); 2573 c = len - i; 2574 if (c > 16) c = 16; 2575 2576 for (j = 0; j < c; j++) { 2577 printf("%02x ", data[i + j] & 0xff); 2578 if ((j & 0xf) == 7 && j > 0) 2579 printf(" "); 2580 } 2581 2582 for (; j < 16; j++) 2583 printf(" "); 2584 printf(" "); 2585 2586 for (j = 0; j < c; j++) { 2587 int ch = data[i + j] & 0xff; 2588 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2589 } 2590 2591 printf("\n"); 2592 2593 if (c < 16) 2594 break; 2595 } 2596} 2597 2598void 2599sk_dump_mbuf(struct mbuf *m) 2600{ 2601 int count = m->m_pkthdr.len; 2602 2603 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2604 2605 while (count > 0 && m) { 2606 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2607 m, m->m_data, m->m_len); 2608 sk_dump_bytes(mtod(m, char *), m->m_len); 2609 2610 count -= m->m_len; 2611 m = m->m_next; 2612 } 2613} 2614#endif 2615