if_rtw_pci.c revision 1.17 
1/*	$OpenBSD: if_rtw_pci.c,v 1.17 2012/12/05 23:20:20 deraadt Exp $	*/
2/*	$NetBSD: if_rtw_pci.c,v 1.1 2004/09/26 02:33:36 dyoung Exp $	*/
3
4/*-
5 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10 * NASA Ames Research Center; Charles M. Hannum; and David Young.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 *    notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 *    notice, this list of conditions and the following disclaimer in the
19 *    documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34/*
35 * PCI bus front-end for the Realtek RTL8180L 802.11 MAC/BBP chip.
36 *
37 * Derived from the ADMtek ADM8211 PCI bus front-end.
38 *
39 * Derived from the ``Tulip'' PCI bus front-end.
40 */
41
42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/mbuf.h>
45#include <sys/malloc.h>
46#include <sys/kernel.h>
47#include <sys/socket.h>
48#include <sys/ioctl.h>
49#include <sys/errno.h>
50#include <sys/device.h>
51
52#include <machine/endian.h>
53
54#include <net/if.h>
55#include <net/if_dl.h>
56#include <net/if_media.h>
57#ifdef INET
58#include <netinet/in.h>
59#include <netinet/if_ether.h>
60#endif
61
62#include <net80211/ieee80211_radiotap.h>
63#include <net80211/ieee80211_var.h>
64
65#include <machine/bus.h>
66#include <machine/intr.h>
67
68#include <dev/ic/rtwreg.h>
69#include <dev/ic/sa2400reg.h>
70#include <dev/ic/rtwvar.h>
71
72#include <dev/pci/pcivar.h>
73#include <dev/pci/pcireg.h>
74#include <dev/pci/pcidevs.h>
75
76int rtw_pci_enable(struct rtw_softc *);
77void rtw_pci_disable(struct rtw_softc *);
78int rtw_pci_detach(struct device *, int);
79
80/*
81 * PCI configuration space registers used by the RTL8180L.
82 */
83#define	RTW_PCI_IOBA		0x10	/* i/o mapped base */
84#define	RTW_PCI_MMBA		0x14	/* memory mapped base */
85
86struct rtw_pci_softc {
87	struct rtw_softc	psc_rtw;	/* real RTL8180L softc */
88
89	pci_intr_handle_t	psc_ih;		/* interrupt handle */
90	void			*psc_intrcookie;
91
92	pci_chipset_tag_t	psc_pc;		/* our PCI chipset */
93	pcitag_t		psc_pcitag;	/* our PCI tag */
94	bus_size_t		psc_mapsize;
95};
96
97int	rtw_pci_match(struct device *, void *, void *);
98void	rtw_pci_attach(struct device *, struct device *, void *);
99
100struct cfattach rtw_pci_ca = {
101	sizeof (struct rtw_pci_softc), rtw_pci_match, rtw_pci_attach,
102	    rtw_pci_detach, rtw_activate
103};
104
105const struct pci_matchid rtw_pci_products[] = {
106	{ PCI_VENDOR_REALTEK,	PCI_PRODUCT_REALTEK_RT8180 },
107#ifdef RTW_DEBUG
108	{ PCI_VENDOR_REALTEK,	PCI_PRODUCT_REALTEK_RT8185 },
109	{ PCI_VENDOR_BELKIN2,	PCI_PRODUCT_BELKIN2_F5D7010 },
110#endif
111	{ PCI_VENDOR_BELKIN2,	PCI_PRODUCT_BELKIN2_F5D6001 },
112	{ PCI_VENDOR_BELKIN2,	PCI_PRODUCT_BELKIN2_F5D6020V3 },
113	{ PCI_VENDOR_DLINK,	PCI_PRODUCT_DLINK_DWL610 },
114};
115
116int
117rtw_pci_match(struct device *parent, void *match, void *aux)
118{
119	return (pci_matchbyid((struct pci_attach_args *)aux, rtw_pci_products,
120	    nitems(rtw_pci_products)));
121}
122
123int
124rtw_pci_enable(struct rtw_softc *sc)
125{
126	struct rtw_pci_softc *psc = (void *)sc;
127
128	/* Establish the interrupt. */
129	psc->psc_intrcookie = pci_intr_establish(psc->psc_pc, psc->psc_ih,
130	    IPL_NET, rtw_intr, sc, sc->sc_dev.dv_xname);
131	if (psc->psc_intrcookie == NULL) {
132		printf("%s: unable to establish interrupt\n",
133		    sc->sc_dev.dv_xname);
134		return (1);
135	}
136
137	return (0);
138}
139
140void
141rtw_pci_disable(struct rtw_softc *sc)
142{
143	struct rtw_pci_softc *psc = (void *)sc;
144
145	/* Unhook the interrupt handler. */
146	pci_intr_disestablish(psc->psc_pc, psc->psc_intrcookie);
147	psc->psc_intrcookie = NULL;
148}
149
150void
151rtw_pci_attach(struct device *parent, struct device *self, void *aux)
152{
153	struct rtw_pci_softc *psc = (void *) self;
154	struct rtw_softc *sc = &psc->psc_rtw;
155	struct rtw_regs *regs = &sc->sc_regs;
156	struct pci_attach_args *pa = aux;
157	pci_chipset_tag_t pc = pa->pa_pc;
158	const char *intrstr = NULL;
159	bus_space_tag_t iot, memt;
160	bus_space_handle_t ioh, memh;
161	bus_size_t iosize, memsize;
162	int ioh_valid, memh_valid;
163
164	psc->psc_pc = pa->pa_pc;
165	psc->psc_pcitag = pa->pa_tag;
166
167	/*
168	 * No power management hooks.
169	 * XXX Maybe we should add some!
170	 */
171	sc->sc_flags |= RTW_F_ENABLED;
172
173	/*
174	 * Get revision info, and set some chip-specific variables.
175	 */
176	sc->sc_rev = PCI_REVISION(pa->pa_class);
177
178	pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
179
180	/*
181	 * Map the device.
182	 */
183	ioh_valid = (pci_mapreg_map(pa, RTW_PCI_IOBA,
184	    PCI_MAPREG_TYPE_IO, 0,
185	    &iot, &ioh, NULL, &iosize, 0) == 0);
186	memh_valid = (pci_mapreg_map(pa, RTW_PCI_MMBA,
187	    PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
188	    &memt, &memh, NULL, &memsize, 0) == 0);
189
190	if (memh_valid) {
191		regs->r_bt = memt;
192		regs->r_bh = memh;
193		psc->psc_mapsize = memsize;
194	} else if (ioh_valid) {
195		regs->r_bt = iot;
196		regs->r_bh = ioh;
197		psc->psc_mapsize = iosize;
198	} else {
199		printf(": unable to map device registers\n");
200		return;
201	}
202
203	sc->sc_dmat = pa->pa_dmat;
204
205	/*
206	 * Map and establish our interrupt.
207	 */
208	if (pci_intr_map(pa, &psc->psc_ih)) {
209		printf(": unable to map interrupt\n");
210		return;
211	}
212	intrstr = pci_intr_string(pc, psc->psc_ih);
213	psc->psc_intrcookie = pci_intr_establish(pc, psc->psc_ih, IPL_NET,
214	    rtw_intr, sc, sc->sc_dev.dv_xname);
215	if (psc->psc_intrcookie == NULL) {
216		printf(": unable to establish interrupt");
217		if (intrstr != NULL)
218			printf(" at %s", intrstr);
219		printf("\n");
220		return;
221	}
222
223	printf(": %s\n", intrstr);
224
225	sc->sc_enable = rtw_pci_enable;
226	sc->sc_disable = rtw_pci_disable;
227
228	/*
229	 * Finish off the attach.
230	 */
231	rtw_attach(sc);
232}
233
234int
235rtw_pci_detach(struct device *self, int flags)
236{
237	struct rtw_pci_softc *psc = (void *)self;
238	struct rtw_softc *sc = &psc->psc_rtw;
239	struct rtw_regs *regs = &sc->sc_regs;
240	int rv;
241
242	rv = rtw_detach(sc);
243	if (rv)
244		return (rv);
245	if (psc->psc_intrcookie != NULL)
246		pci_intr_disestablish(psc->psc_pc, psc->psc_intrcookie);
247	bus_space_unmap(regs->r_bt, regs->r_bh, psc->psc_mapsize);
248
249	return (0);
250}
251