if_nfe.c revision 1.48
1/* $OpenBSD: if_nfe.c,v 1.48 2006/02/24 04:58:25 brad Exp $ */ 2 3/*- 4 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 21 22#include "bpfilter.h" 23#include "vlan.h" 24 25#include <sys/param.h> 26#include <sys/endian.h> 27#include <sys/systm.h> 28#include <sys/types.h> 29#include <sys/sockio.h> 30#include <sys/mbuf.h> 31#include <sys/queue.h> 32#include <sys/malloc.h> 33#include <sys/kernel.h> 34#include <sys/device.h> 35#include <sys/socket.h> 36 37#include <machine/bus.h> 38 39#include <net/if.h> 40#include <net/if_dl.h> 41#include <net/if_media.h> 42 43#ifdef INET 44#include <netinet/in.h> 45#include <netinet/in_systm.h> 46#include <netinet/in_var.h> 47#include <netinet/ip.h> 48#include <netinet/if_ether.h> 49#endif 50 51#if NVLAN > 0 52#include <net/if_types.h> 53#include <net/if_vlan_var.h> 54#endif 55 56#if NBPFILTER > 0 57#include <net/bpf.h> 58#endif 59 60#include <dev/mii/mii.h> 61#include <dev/mii/miivar.h> 62 63#include <dev/pci/pcireg.h> 64#include <dev/pci/pcivar.h> 65#include <dev/pci/pcidevs.h> 66 67#include <dev/pci/if_nfereg.h> 68#include <dev/pci/if_nfevar.h> 69 70int nfe_match(struct device *, void *, void *); 71void nfe_attach(struct device *, struct device *, void *); 72void nfe_power(int, void *); 73void nfe_miibus_statchg(struct device *); 74int nfe_miibus_readreg(struct device *, int, int); 75void nfe_miibus_writereg(struct device *, int, int, int); 76int nfe_intr(void *); 77int nfe_ioctl(struct ifnet *, u_long, caddr_t); 78void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 79void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 80void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 81void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 82void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 83void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 84void nfe_rxeof(struct nfe_softc *); 85void nfe_txeof(struct nfe_softc *); 86int nfe_encap(struct nfe_softc *, struct mbuf *); 87void nfe_start(struct ifnet *); 88void nfe_watchdog(struct ifnet *); 89int nfe_init(struct ifnet *); 90void nfe_stop(struct ifnet *, int); 91struct nfe_jbuf *nfe_jalloc(struct nfe_softc *); 92void nfe_jfree(caddr_t, u_int, void *); 93int nfe_jpool_alloc(struct nfe_softc *); 94void nfe_jpool_free(struct nfe_softc *); 95int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 96void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 97void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 98int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 99void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 100void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 101int nfe_ifmedia_upd(struct ifnet *); 102void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 103void nfe_setmulti(struct nfe_softc *); 104void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 105void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 106void nfe_tick(void *); 107 108struct cfattach nfe_ca = { 109 sizeof (struct nfe_softc), nfe_match, nfe_attach 110}; 111 112struct cfdriver nfe_cd = { 113 NULL, "nfe", DV_IFNET 114}; 115 116#define NFE_DEBUG 117/*#define NFE_NO_JUMBO*/ 118 119#ifdef NFE_DEBUG 120int nfedebug = 1; 121#define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 122#define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 123#else 124#define DPRINTF(x) 125#define DPRINTFN(n,x) 126#endif 127 128const struct pci_matchid nfe_devices[] = { 129 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 130 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 131 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 132 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 133 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 134 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 135 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 136 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 137 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 138 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 139 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 140 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 141 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 142 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 143 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 } 144}; 145 146int 147nfe_match(struct device *dev, void *match, void *aux) 148{ 149 return pci_matchbyid((struct pci_attach_args *)aux, nfe_devices, 150 sizeof (nfe_devices) / sizeof (nfe_devices[0])); 151} 152 153void 154nfe_attach(struct device *parent, struct device *self, void *aux) 155{ 156 struct nfe_softc *sc = (struct nfe_softc *)self; 157 struct pci_attach_args *pa = aux; 158 pci_chipset_tag_t pc = pa->pa_pc; 159 pci_intr_handle_t ih; 160 const char *intrstr; 161 struct ifnet *ifp; 162 bus_size_t memsize; 163 pcireg_t memtype; 164 165 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 166 switch (memtype) { 167 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 168 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 169 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 170 &sc->sc_memh, NULL, &memsize, 0) == 0) 171 break; 172 /* FALLTHROUGH */ 173 default: 174 printf(": could not map mem space\n"); 175 return; 176 } 177 178 if (pci_intr_map(pa, &ih) != 0) { 179 printf(": could not map interrupt\n"); 180 return; 181 } 182 183 intrstr = pci_intr_string(pc, ih); 184 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc, 185 sc->sc_dev.dv_xname); 186 if (sc->sc_ih == NULL) { 187 printf(": could not establish interrupt"); 188 if (intrstr != NULL) 189 printf(" at %s", intrstr); 190 printf("\n"); 191 return; 192 } 193 printf(": %s", intrstr); 194 195 sc->sc_dmat = pa->pa_dmat; 196 197 nfe_get_macaddr(sc, sc->sc_arpcom.ac_enaddr); 198 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 199 200 sc->sc_flags = 0; 201 202 switch (PCI_PRODUCT(pa->pa_id)) { 203 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 204 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 205 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 206 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 207 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 208 break; 209 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 210 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 211 sc->sc_flags |= NFE_40BIT_ADDR; 212 break; 213 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 214 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 215 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 216 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 217 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 218 break; 219 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 220 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 221 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 222 NFE_HW_VLAN; 223 break; 224 } 225 226#ifndef NFE_NO_JUMBO 227 /* enable jumbo frames for adapters that support it */ 228 if (sc->sc_flags & NFE_JUMBO_SUP) 229 sc->sc_flags |= NFE_USE_JUMBO; 230#endif 231 232 /* 233 * Allocate Tx and Rx rings. 234 */ 235 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 236 printf("%s: could not allocate Tx ring\n", 237 sc->sc_dev.dv_xname); 238 return; 239 } 240 241 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 242 printf("%s: could not allocate Rx ring\n", 243 sc->sc_dev.dv_xname); 244 nfe_free_tx_ring(sc, &sc->txq); 245 return; 246 } 247 248 ifp = &sc->sc_arpcom.ac_if; 249 ifp->if_softc = sc; 250 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 251 ifp->if_ioctl = nfe_ioctl; 252 ifp->if_start = nfe_start; 253 ifp->if_watchdog = nfe_watchdog; 254 ifp->if_init = nfe_init; 255 ifp->if_baudrate = IF_Gbps(1); 256 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 257 IFQ_SET_READY(&ifp->if_snd); 258 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 259 260 ifp->if_capabilities = IFCAP_VLAN_MTU; 261#if NVLAN > 0 262 if (sc->sc_flags & NFE_HW_VLAN) 263 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 264#endif 265#ifdef NFE_CSUM 266 if (sc->sc_flags & NFE_HW_CSUM) { 267 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 268 IFCAP_CSUM_UDPv4; 269 } 270#endif 271 272 sc->sc_mii.mii_ifp = ifp; 273 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 274 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 275 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 276 277 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 278 nfe_ifmedia_sts); 279 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 280 MII_OFFSET_ANY, 0); 281 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 282 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 283 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 284 0, NULL); 285 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 286 } else 287 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 288 289 if_attach(ifp); 290 ether_ifattach(ifp); 291 292 timeout_set(&sc->sc_tick_ch, nfe_tick, sc); 293 294 sc->sc_powerhook = powerhook_establish(nfe_power, sc); 295} 296 297void 298nfe_power(int why, void *arg) 299{ 300 struct nfe_softc *sc = arg; 301 struct ifnet *ifp; 302 303 if (why == PWR_RESUME) { 304 ifp = &sc->sc_arpcom.ac_if; 305 if (ifp->if_flags & IFF_UP) { 306 ifp->if_flags &= ~IFF_RUNNING; 307 nfe_init(ifp); 308 if (ifp->if_flags & IFF_RUNNING) 309 nfe_start(ifp); 310 } 311 } 312} 313 314void 315nfe_miibus_statchg(struct device *dev) 316{ 317 struct nfe_softc *sc = (struct nfe_softc *)dev; 318 struct mii_data *mii = &sc->sc_mii; 319 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 320 321 phy = NFE_READ(sc, NFE_PHY_IFACE); 322 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 323 324 seed = NFE_READ(sc, NFE_RNDSEED); 325 seed &= ~NFE_SEED_MASK; 326 327 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 328 phy |= NFE_PHY_HDX; /* half-duplex */ 329 misc |= NFE_MISC1_HDX; 330 } 331 332 switch (IFM_SUBTYPE(mii->mii_media_active)) { 333 case IFM_1000_T: /* full-duplex only */ 334 link |= NFE_MEDIA_1000T; 335 seed |= NFE_SEED_1000T; 336 phy |= NFE_PHY_1000T; 337 break; 338 case IFM_100_TX: 339 link |= NFE_MEDIA_100TX; 340 seed |= NFE_SEED_100TX; 341 phy |= NFE_PHY_100TX; 342 break; 343 case IFM_10_T: 344 link |= NFE_MEDIA_10T; 345 seed |= NFE_SEED_10T; 346 break; 347 } 348 349 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 350 351 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 352 NFE_WRITE(sc, NFE_MISC1, misc); 353 NFE_WRITE(sc, NFE_LINKSPEED, link); 354} 355 356int 357nfe_miibus_readreg(struct device *dev, int phy, int reg) 358{ 359 struct nfe_softc *sc = (struct nfe_softc *)dev; 360 uint32_t val; 361 int ntries; 362 363 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 364 365 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 366 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 367 DELAY(100); 368 } 369 370 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 371 372 for (ntries = 0; ntries < 1000; ntries++) { 373 DELAY(100); 374 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 375 break; 376 } 377 if (ntries == 1000) { 378 DPRINTFN(2, ("timeout waiting for PHY\n")); 379 return 0; 380 } 381 382 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 383 DPRINTFN(2, ("could not read PHY\n")); 384 return 0; 385 } 386 387 val = NFE_READ(sc, NFE_PHY_DATA); 388 if (val != 0xffffffff && val != 0) 389 sc->mii_phyaddr = phy; 390 391 DPRINTFN(2, ("mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val)); 392 393 return val; 394} 395 396void 397nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 398{ 399 struct nfe_softc *sc = (struct nfe_softc *)dev; 400 uint32_t ctl; 401 int ntries; 402 403 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 404 405 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 406 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 407 DELAY(100); 408 } 409 410 NFE_WRITE(sc, NFE_PHY_DATA, val); 411 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 412 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 413 414 for (ntries = 0; ntries < 1000; ntries++) { 415 DELAY(100); 416 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 417 break; 418 } 419#ifdef NFE_DEBUG 420 if (nfedebug >= 2 && ntries == 1000) 421 printf("could not write to PHY\n"); 422#endif 423} 424 425int 426nfe_intr(void *arg) 427{ 428 struct nfe_softc *sc = arg; 429 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 430 uint32_t r; 431 432 if ((r = NFE_READ(sc, NFE_IRQ_STATUS)) == 0) 433 return 0; /* not for us */ 434 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 435 436 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 437 438 if (r & NFE_IRQ_LINK) { 439 NFE_READ(sc, NFE_PHY_STATUS); 440 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 441 DPRINTF(("link state changed\n")); 442 } 443 444 if (ifp->if_flags & IFF_RUNNING) { 445 /* check Rx ring */ 446 nfe_rxeof(sc); 447 448 /* check Tx ring */ 449 nfe_txeof(sc); 450 } 451 452 return 1; 453} 454 455int 456nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 457{ 458 struct nfe_softc *sc = ifp->if_softc; 459 struct ifreq *ifr = (struct ifreq *)data; 460 struct ifaddr *ifa = (struct ifaddr *)data; 461 int s, error = 0; 462 463 s = splnet(); 464 465 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) { 466 splx(s); 467 return error; 468 } 469 470 switch (cmd) { 471 case SIOCSIFADDR: 472 ifp->if_flags |= IFF_UP; 473 nfe_init(ifp); 474 switch (ifa->ifa_addr->sa_family) { 475#ifdef INET 476 case AF_INET: 477 arp_ifinit(&sc->sc_arpcom, ifa); 478 break; 479#endif 480 default: 481 break; 482 } 483 break; 484 case SIOCSIFMTU: 485 if (ifr->ifr_mtu < ETHERMIN || 486 ((sc->sc_flags & NFE_USE_JUMBO) && 487 ifr->ifr_mtu > ETHERMTU_JUMBO) || 488 (!(sc->sc_flags & NFE_USE_JUMBO) && 489 ifr->ifr_mtu > ETHERMTU)) 490 error = EINVAL; 491 else if (ifp->if_mtu != ifr->ifr_mtu) 492 ifp->if_mtu = ifr->ifr_mtu; 493 break; 494 case SIOCSIFFLAGS: 495 if (ifp->if_flags & IFF_UP) { 496 /* 497 * If only the PROMISC or ALLMULTI flag changes, then 498 * don't do a full re-init of the chip, just update 499 * the Rx filter. 500 */ 501 if ((ifp->if_flags & IFF_RUNNING) && 502 ((ifp->if_flags ^ sc->sc_if_flags) & 503 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 504 nfe_setmulti(sc); 505 else 506 nfe_init(ifp); 507 } else { 508 if (ifp->if_flags & IFF_RUNNING) 509 nfe_stop(ifp, 1); 510 } 511 sc->sc_if_flags = ifp->if_flags; 512 break; 513 case SIOCADDMULTI: 514 case SIOCDELMULTI: 515 error = (cmd == SIOCADDMULTI) ? 516 ether_addmulti(ifr, &sc->sc_arpcom) : 517 ether_delmulti(ifr, &sc->sc_arpcom); 518 519 if (error == ENETRESET) { 520 if (ifp->if_flags & IFF_RUNNING) 521 nfe_setmulti(sc); 522 error = 0; 523 } 524 break; 525 case SIOCSIFMEDIA: 526 case SIOCGIFMEDIA: 527 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 528 break; 529 default: 530 error = EINVAL; 531 } 532 533 splx(s); 534 535 return error; 536} 537 538void 539nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 540{ 541 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 542 (caddr_t)desc32 - (caddr_t)sc->txq.desc32, 543 sizeof (struct nfe_desc32), ops); 544} 545 546void 547nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 548{ 549 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 550 (caddr_t)desc64 - (caddr_t)sc->txq.desc64, 551 sizeof (struct nfe_desc64), ops); 552} 553 554void 555nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 556{ 557 if (end > start) { 558 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 559 (caddr_t)&sc->txq.desc32[start] - (caddr_t)sc->txq.desc32, 560 (caddr_t)&sc->txq.desc32[end] - 561 (caddr_t)&sc->txq.desc32[start], ops); 562 return; 563 } 564 /* sync from 'start' to end of ring */ 565 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 566 (caddr_t)&sc->txq.desc32[start] - (caddr_t)sc->txq.desc32, 567 (caddr_t)&sc->txq.desc32[NFE_TX_RING_COUNT] - 568 (caddr_t)&sc->txq.desc32[start], ops); 569 570 /* sync from start of ring to 'end' */ 571 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 572 (caddr_t)&sc->txq.desc32[end] - (caddr_t)sc->txq.desc32, ops); 573} 574 575void 576nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 577{ 578 if (end > start) { 579 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 580 (caddr_t)&sc->txq.desc64[start] - (caddr_t)sc->txq.desc64, 581 (caddr_t)&sc->txq.desc64[end] - 582 (caddr_t)&sc->txq.desc64[start], ops); 583 return; 584 } 585 /* sync from 'start' to end of ring */ 586 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 587 (caddr_t)&sc->txq.desc64[start] - (caddr_t)sc->txq.desc64, 588 (caddr_t)&sc->txq.desc64[NFE_TX_RING_COUNT] - 589 (caddr_t)&sc->txq.desc64[start], ops); 590 591 /* sync from start of ring to 'end' */ 592 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 593 (caddr_t)&sc->txq.desc64[end] - (caddr_t)sc->txq.desc64, ops); 594} 595 596void 597nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 598{ 599 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 600 (caddr_t)desc32 - (caddr_t)sc->rxq.desc32, 601 sizeof (struct nfe_desc32), ops); 602} 603 604void 605nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 606{ 607 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 608 (caddr_t)desc64 - (caddr_t)sc->rxq.desc64, 609 sizeof (struct nfe_desc64), ops); 610} 611 612void 613nfe_rxeof(struct nfe_softc *sc) 614{ 615 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 616 struct nfe_desc32 *desc32; 617 struct nfe_desc64 *desc64; 618 struct nfe_rx_data *data; 619 struct nfe_jbuf *jbuf; 620 struct mbuf *m, *mnew; 621 bus_addr_t physaddr; 622 uint16_t flags; 623 int error, len; 624 625 for (;;) { 626 data = &sc->rxq.data[sc->rxq.cur]; 627 628 if (sc->sc_flags & NFE_40BIT_ADDR) { 629 desc64 = &sc->rxq.desc64[sc->rxq.cur]; 630 nfe_rxdesc64_sync(sc, desc64, BUS_DMASYNC_POSTREAD); 631 632 flags = letoh16(desc64->flags); 633 len = letoh16(desc64->length) & 0x3fff; 634 } else { 635 desc32 = &sc->rxq.desc32[sc->rxq.cur]; 636 nfe_rxdesc32_sync(sc, desc32, BUS_DMASYNC_POSTREAD); 637 638 flags = letoh16(desc32->flags); 639 len = letoh16(desc32->length) & 0x3fff; 640 } 641 642 if (flags & NFE_RX_READY) 643 break; 644 645 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 646 if (!(flags & NFE_RX_VALID_V1)) 647 goto skip; 648 649 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 650 flags &= ~NFE_RX_ERROR; 651 len--; /* fix buffer length */ 652 } 653 } else { 654 if (!(flags & NFE_RX_VALID_V2)) 655 goto skip; 656 657 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 658 flags &= ~NFE_RX_ERROR; 659 len--; /* fix buffer length */ 660 } 661 } 662 663 if (flags & NFE_RX_ERROR) { 664 ifp->if_ierrors++; 665 goto skip; 666 } 667 668 /* 669 * Try to allocate a new mbuf for this ring element and load 670 * it before processing the current mbuf. If the ring element 671 * cannot be loaded, drop the received packet and reuse the 672 * old mbuf. In the unlikely case that the old mbuf can't be 673 * reloaded either, explicitly panic. 674 */ 675 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 676 if (mnew == NULL) { 677 ifp->if_ierrors++; 678 goto skip; 679 } 680 681 if (sc->sc_flags & NFE_USE_JUMBO) { 682 if ((jbuf = nfe_jalloc(sc)) == NULL) { 683 m_freem(mnew); 684 ifp->if_ierrors++; 685 goto skip; 686 } 687 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 688 689 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 690 mtod(data->m, caddr_t) - sc->rxq.jpool, NFE_JBYTES, 691 BUS_DMASYNC_POSTREAD); 692 693 physaddr = jbuf->physaddr; 694 } else { 695 MCLGET(mnew, M_DONTWAIT); 696 if (!(mnew->m_flags & M_EXT)) { 697 m_freem(mnew); 698 ifp->if_ierrors++; 699 goto skip; 700 } 701 702 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 703 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 704 bus_dmamap_unload(sc->sc_dmat, data->map); 705 706 error = bus_dmamap_load(sc->sc_dmat, data->map, 707 mtod(mnew, void *), MCLBYTES, NULL, 708 BUS_DMA_READ | BUS_DMA_NOWAIT); 709 if (error != 0) { 710 m_freem(mnew); 711 712 /* try to reload the old mbuf */ 713 error = bus_dmamap_load(sc->sc_dmat, data->map, 714 mtod(data->m, void *), MCLBYTES, NULL, 715 BUS_DMA_READ | BUS_DMA_NOWAIT); 716 if (error != 0) { 717 /* very unlikely that it will fail.. */ 718 panic("%s: could not load old rx mbuf", 719 sc->sc_dev.dv_xname); 720 } 721 ifp->if_ierrors++; 722 goto skip; 723 } 724 physaddr = data->map->dm_segs[0].ds_addr; 725 } 726 727 /* 728 * New mbuf successfully loaded, update Rx ring and continue 729 * processing. 730 */ 731 m = data->m; 732 data->m = mnew; 733 734 /* finalize mbuf */ 735 m->m_pkthdr.len = m->m_len = len; 736 m->m_pkthdr.rcvif = ifp; 737 738#ifdef notyet 739 if (sc->sc_flags & NFE_HW_CSUM) { 740 if (flags & NFE_RX_IP_CSUMOK) 741 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 742 if (flags & NFE_RX_UDP_CSUMOK) 743 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 744 if (flags & NFE_RX_TCP_CSUMOK) 745 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 746 } 747#elif defined(NFE_CSUM) 748 if ((sc->sc_flags & NFE_HW_CSUM) && (flags & NFE_RX_CSUMOK)) 749 m->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 750#endif 751 752#if NBPFILTER > 0 753 if (ifp->if_bpf) 754 bpf_mtap(ifp->if_bpf, m); 755#endif 756 ifp->if_ipackets++; 757 ether_input_mbuf(ifp, m); 758 759 /* update mapping address in h/w descriptor */ 760 if (sc->sc_flags & NFE_40BIT_ADDR) { 761#if defined(__LP64__) 762 desc64->physaddr[0] = htole32(physaddr >> 32); 763#endif 764 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 765 } else { 766 desc32->physaddr = htole32(physaddr); 767 } 768 769skip: if (sc->sc_flags & NFE_40BIT_ADDR) { 770 desc64->length = htole16(sc->rxq.bufsz); 771 desc64->flags = htole16(NFE_RX_READY); 772 773 nfe_rxdesc64_sync(sc, desc64, BUS_DMASYNC_PREWRITE); 774 } else { 775 desc32->length = htole16(sc->rxq.bufsz); 776 desc32->flags = htole16(NFE_RX_READY); 777 778 nfe_rxdesc32_sync(sc, desc32, BUS_DMASYNC_PREWRITE); 779 } 780 781 sc->rxq.cur = (sc->rxq.cur + 1) % NFE_RX_RING_COUNT; 782 } 783} 784 785void 786nfe_txeof(struct nfe_softc *sc) 787{ 788 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 789 struct nfe_desc32 *desc32; 790 struct nfe_desc64 *desc64; 791 struct nfe_tx_data *data = NULL; 792 uint16_t flags; 793 794 while (sc->txq.next != sc->txq.cur) { 795 if (sc->sc_flags & NFE_40BIT_ADDR) { 796 desc64 = &sc->txq.desc64[sc->txq.next]; 797 nfe_txdesc64_sync(sc, desc64, BUS_DMASYNC_POSTREAD); 798 799 flags = letoh16(desc64->flags); 800 } else { 801 desc32 = &sc->txq.desc32[sc->txq.next]; 802 nfe_txdesc32_sync(sc, desc32, BUS_DMASYNC_POSTREAD); 803 804 flags = letoh16(desc32->flags); 805 } 806 807 if (flags & NFE_TX_VALID) 808 break; 809 810 data = &sc->txq.data[sc->txq.next]; 811 812 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 813 if (!(flags & NFE_TX_LASTFRAG_V1)) 814 goto skip; 815 816 if ((flags & NFE_TX_ERROR_V1) != 0) { 817 DPRINTF(("tx error 0x%04x\n", flags)); 818 ifp->if_oerrors++; 819 } else 820 ifp->if_opackets++; 821 } else { 822 if (!(flags & NFE_TX_LASTFRAG_V2)) 823 goto skip; 824 825 if ((flags & NFE_TX_ERROR_V2) != 0) { 826 DPRINTF(("tx error 0x%04x\n", flags)); 827 ifp->if_oerrors++; 828 } else 829 ifp->if_opackets++; 830 } 831 832 if (data->m == NULL) { /* should not get there */ 833 DPRINTF(("last fragment bit w/o associated mbuf!\n")); 834 goto skip; 835 } 836 837 /* last fragment of the mbuf chain transmitted */ 838 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 839 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 840 bus_dmamap_unload(sc->sc_dmat, data->active); 841 m_freem(data->m); 842 data->m = NULL; 843 844 ifp->if_timer = 0; 845 846skip: sc->txq.queued--; 847 sc->txq.next = (sc->txq.next + 1) % NFE_TX_RING_COUNT; 848 } 849 850 if (data != NULL) { /* at least one slot freed */ 851 ifp->if_flags &= ~IFF_OACTIVE; 852 nfe_start(ifp); 853 } 854} 855 856int 857nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 858{ 859 struct nfe_desc32 *desc32; 860 struct nfe_desc64 *desc64; 861 struct nfe_tx_data *data; 862 bus_dmamap_t map; 863 uint16_t flags = NFE_TX_VALID; 864#if NVLAN > 0 865 uint32_t vtag = 0; 866#endif 867 int error, i; 868 869 map = sc->txq.data[sc->txq.cur].map; 870 871 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 872 if (error != 0) { 873 printf("%s: could not map mbuf (error %d)\n", 874 sc->sc_dev.dv_xname, error); 875 return error; 876 } 877 878 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 879 bus_dmamap_unload(sc->sc_dmat, map); 880 return ENOBUFS; 881 } 882 883#if NVLAN > 0 884 /* setup h/w VLAN tagging */ 885 if ((m0->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 886 m0->m_pkthdr.rcvif != NULL) { 887 struct ifvlan *ifv = m0->m_pkthdr.rcvif->if_softc; 888 vtag = NFE_TX_VTAG | htons(ifv->ifv_tag); 889 } 890#endif 891#ifdef NFE_CSUM 892 if (m0->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 893 flags |= NFE_TX_IP_CSUM; 894 if (m0->m_pkthdr.csum_flags & (M_TCPV4_CSUM_OUT | M_UDPV4_CSUM_OUT)) 895 flags |= NFE_TX_TCP_CSUM; 896#endif 897 898 for (i = 0; i < map->dm_nsegs; i++) { 899 data = &sc->txq.data[sc->txq.cur]; 900 901 if (sc->sc_flags & NFE_40BIT_ADDR) { 902 desc64 = &sc->txq.desc64[sc->txq.cur]; 903#if defined(__LP64__) 904 desc64->physaddr[0] = 905 htole32(map->dm_segs[i].ds_addr >> 32); 906#endif 907 desc64->physaddr[1] = 908 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 909 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 910 desc64->flags = htole16(flags); 911#if NVLAN > 0 912 desc64->vtag = htole32(vtag); 913#endif 914 } else { 915 desc32 = &sc->txq.desc32[sc->txq.cur]; 916 917 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 918 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 919 desc32->flags = htole16(flags); 920 } 921 922 /* csum flags and vtag belong to the first fragment only */ 923 if (map->dm_nsegs > 1) { 924 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM); 925#if NVLAN > 0 926 vtag = 0; 927#endif 928 } 929 930 sc->txq.queued++; 931 sc->txq.cur = (sc->txq.cur + 1) % NFE_TX_RING_COUNT; 932 } 933 934 /* the whole mbuf chain has been DMA mapped, fix last descriptor */ 935 if (sc->sc_flags & NFE_40BIT_ADDR) { 936 flags |= NFE_TX_LASTFRAG_V2; 937 desc64->flags = htole16(flags); 938 } else { 939 if (sc->sc_flags & NFE_JUMBO_SUP) 940 flags |= NFE_TX_LASTFRAG_V2; 941 else 942 flags |= NFE_TX_LASTFRAG_V1; 943 desc32->flags = htole16(flags); 944 } 945 946 data->m = m0; 947 data->active = map; 948 949 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 950 BUS_DMASYNC_PREWRITE); 951 952 return 0; 953} 954 955void 956nfe_start(struct ifnet *ifp) 957{ 958 struct nfe_softc *sc = ifp->if_softc; 959 int old = sc->txq.cur; 960 struct mbuf *m0; 961 962 for (;;) { 963 IFQ_POLL(&ifp->if_snd, m0); 964 if (m0 == NULL) 965 break; 966 967 if (nfe_encap(sc, m0) != 0) { 968 ifp->if_flags |= IFF_OACTIVE; 969 break; 970 } 971 972 /* packet put in h/w queue, remove from s/w queue */ 973 IFQ_DEQUEUE(&ifp->if_snd, m0); 974 975#if NBPFILTER > 0 976 if (ifp->if_bpf != NULL) 977 bpf_mtap(ifp->if_bpf, m0); 978#endif 979 } 980 if (sc->txq.cur == old) /* nothing sent */ 981 return; 982 983 if (sc->sc_flags & NFE_40BIT_ADDR) 984 nfe_txdesc64_rsync(sc, old, sc->txq.cur, BUS_DMASYNC_PREWRITE); 985 else 986 nfe_txdesc32_rsync(sc, old, sc->txq.cur, BUS_DMASYNC_PREWRITE); 987 988 /* kick Tx */ 989 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 990 991 /* 992 * Set a timeout in case the chip goes out to lunch. 993 */ 994 ifp->if_timer = 5; 995} 996 997void 998nfe_watchdog(struct ifnet *ifp) 999{ 1000 struct nfe_softc *sc = ifp->if_softc; 1001 1002 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1003 1004 ifp->if_flags &= ~IFF_RUNNING; 1005 nfe_init(ifp); 1006 1007 ifp->if_oerrors++; 1008} 1009 1010int 1011nfe_init(struct ifnet *ifp) 1012{ 1013 struct nfe_softc *sc = ifp->if_softc; 1014 uint32_t tmp; 1015 1016 if (ifp->if_flags & IFF_RUNNING) 1017 return 0; 1018 1019 nfe_stop(ifp, 0); 1020 1021 NFE_WRITE(sc, NFE_TX_UNK, 0); 1022 NFE_WRITE(sc, NFE_STATUS, 0); 1023 1024 sc->rxtxctl = NFE_RXTX_BIT2; 1025 if (sc->sc_flags & NFE_40BIT_ADDR) 1026 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1027 else if (sc->sc_flags & NFE_JUMBO_SUP) 1028 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1029#ifdef NFE_CSUM 1030 if (sc->sc_flags & NFE_HW_CSUM) 1031 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1032#endif 1033#if NVLAN > 0 1034 /* 1035 * Although the adapter is capable of stripping VLAN tags from received 1036 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on 1037 * purpose. This will be done in software by our network stack. 1038 */ 1039 if (sc->sc_flags & NFE_HW_VLAN) 1040 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT; 1041#endif 1042 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1043 DELAY(10); 1044 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1045 1046#if NVLAN 1047 if (sc->sc_flags & NFE_HW_VLAN) 1048 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1049#endif 1050 1051 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1052 1053 /* set MAC address */ 1054 nfe_set_macaddr(sc, sc->sc_arpcom.ac_enaddr); 1055 1056 /* tell MAC where rings are in memory */ 1057#ifdef __LP64__ 1058 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1059#endif 1060 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1061#ifdef __LP64__ 1062 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1063#endif 1064 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1065 1066 NFE_WRITE(sc, NFE_RING_SIZE, 1067 (NFE_RX_RING_COUNT - 1) << 16 | 1068 (NFE_TX_RING_COUNT - 1)); 1069 1070 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1071 1072 /* force MAC to wakeup */ 1073 tmp = NFE_READ(sc, NFE_PWR_STATE); 1074 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1075 DELAY(10); 1076 tmp = NFE_READ(sc, NFE_PWR_STATE); 1077 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1078 1079#if 1 1080 /* configure interrupts coalescing/mitigation */ 1081 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1082#else 1083 /* no interrupt mitigation: one interrupt per packet */ 1084 NFE_WRITE(sc, NFE_IMTIMER, 970); 1085#endif 1086 1087 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1088 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1089 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1090 1091 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1092 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1093 1094 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1095 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1096 1097 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1098 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1099 DELAY(10); 1100 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1101 1102 /* set Rx filter */ 1103 nfe_setmulti(sc); 1104 1105 /* enable Rx */ 1106 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1107 1108 /* enable Tx */ 1109 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1110 1111 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1112 1113 /* enable interrupts */ 1114 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1115 1116 nfe_ifmedia_upd(ifp); 1117 1118 timeout_add(&sc->sc_tick_ch, hz); 1119 1120 ifp->if_flags |= IFF_RUNNING; 1121 ifp->if_flags &= ~IFF_OACTIVE; 1122 1123 return 0; 1124} 1125 1126void 1127nfe_stop(struct ifnet *ifp, int disable) 1128{ 1129 struct nfe_softc *sc = ifp->if_softc; 1130 1131 timeout_del(&sc->sc_tick_ch); 1132 1133 ifp->if_timer = 0; 1134 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1135 1136 mii_down(&sc->sc_mii); 1137 1138 /* abort Tx */ 1139 NFE_WRITE(sc, NFE_TX_CTL, 0); 1140 1141 /* disable Rx */ 1142 NFE_WRITE(sc, NFE_RX_CTL, 0); 1143 1144 /* disable interrupts */ 1145 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1146 1147 /* reset Tx and Rx rings */ 1148 nfe_reset_tx_ring(sc, &sc->txq); 1149 nfe_reset_rx_ring(sc, &sc->rxq); 1150} 1151 1152int 1153nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1154{ 1155 struct nfe_desc32 *desc32; 1156 struct nfe_desc64 *desc64; 1157 struct nfe_rx_data *data; 1158 struct nfe_jbuf *jbuf; 1159 void **desc; 1160 bus_addr_t physaddr; 1161 int i, nsegs, error, descsize; 1162 1163 if (sc->sc_flags & NFE_40BIT_ADDR) { 1164 desc = (void **)&ring->desc64; 1165 descsize = sizeof (struct nfe_desc64); 1166 } else { 1167 desc = (void **)&ring->desc32; 1168 descsize = sizeof (struct nfe_desc32); 1169 } 1170 1171 ring->cur = ring->next = 0; 1172 ring->bufsz = MCLBYTES; 1173 1174 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1175 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1176 if (error != 0) { 1177 printf("%s: could not create desc DMA map\n", 1178 sc->sc_dev.dv_xname); 1179 goto fail; 1180 } 1181 1182 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1183 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1184 if (error != 0) { 1185 printf("%s: could not allocate DMA memory\n", 1186 sc->sc_dev.dv_xname); 1187 goto fail; 1188 } 1189 1190 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1191 NFE_RX_RING_COUNT * descsize, (caddr_t *)desc, BUS_DMA_NOWAIT); 1192 if (error != 0) { 1193 printf("%s: could not map desc DMA memory\n", 1194 sc->sc_dev.dv_xname); 1195 goto fail; 1196 } 1197 1198 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1199 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1200 if (error != 0) { 1201 printf("%s: could not load desc DMA map\n", 1202 sc->sc_dev.dv_xname); 1203 goto fail; 1204 } 1205 1206 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1207 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1208 1209 if (sc->sc_flags & NFE_USE_JUMBO) { 1210 ring->bufsz = NFE_JBYTES; 1211 if ((error = nfe_jpool_alloc(sc)) != 0) { 1212 printf("%s: could not allocate jumbo frames\n", 1213 sc->sc_dev.dv_xname); 1214 goto fail; 1215 } 1216 } 1217 1218 /* 1219 * Pre-allocate Rx buffers and populate Rx ring. 1220 */ 1221 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1222 data = &sc->rxq.data[i]; 1223 1224 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1225 if (data->m == NULL) { 1226 printf("%s: could not allocate rx mbuf\n", 1227 sc->sc_dev.dv_xname); 1228 error = ENOMEM; 1229 goto fail; 1230 } 1231 1232 if (sc->sc_flags & NFE_USE_JUMBO) { 1233 if ((jbuf = nfe_jalloc(sc)) == NULL) { 1234 printf("%s: could not allocate jumbo buffer\n", 1235 sc->sc_dev.dv_xname); 1236 goto fail; 1237 } 1238 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1239 sc); 1240 1241 physaddr = jbuf->physaddr; 1242 } else { 1243 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1244 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1245 if (error != 0) { 1246 printf("%s: could not create DMA map\n", 1247 sc->sc_dev.dv_xname); 1248 goto fail; 1249 } 1250 MCLGET(data->m, M_DONTWAIT); 1251 if (!(data->m->m_flags & M_EXT)) { 1252 printf("%s: could not allocate mbuf cluster\n", 1253 sc->sc_dev.dv_xname); 1254 error = ENOMEM; 1255 goto fail; 1256 } 1257 1258 error = bus_dmamap_load(sc->sc_dmat, data->map, 1259 mtod(data->m, void *), MCLBYTES, NULL, 1260 BUS_DMA_READ | BUS_DMA_NOWAIT); 1261 if (error != 0) { 1262 printf("%s: could not load rx buf DMA map", 1263 sc->sc_dev.dv_xname); 1264 goto fail; 1265 } 1266 physaddr = data->map->dm_segs[0].ds_addr; 1267 } 1268 1269 if (sc->sc_flags & NFE_40BIT_ADDR) { 1270 desc64 = &sc->rxq.desc64[i]; 1271#if defined(__LP64__) 1272 desc64->physaddr[0] = htole32(physaddr >> 32); 1273#endif 1274 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1275 desc64->length = htole16(sc->rxq.bufsz); 1276 desc64->flags = htole16(NFE_RX_READY); 1277 } else { 1278 desc32 = &sc->rxq.desc32[i]; 1279 desc32->physaddr = htole32(physaddr); 1280 desc32->length = htole16(sc->rxq.bufsz); 1281 desc32->flags = htole16(NFE_RX_READY); 1282 } 1283 } 1284 1285 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1286 BUS_DMASYNC_PREWRITE); 1287 1288 return 0; 1289 1290fail: nfe_free_rx_ring(sc, ring); 1291 return error; 1292} 1293 1294void 1295nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1296{ 1297 int i; 1298 1299 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1300 if (sc->sc_flags & NFE_40BIT_ADDR) { 1301 ring->desc64[i].length = htole16(ring->bufsz); 1302 ring->desc64[i].flags = htole16(NFE_RX_READY); 1303 } else { 1304 ring->desc32[i].length = htole16(ring->bufsz); 1305 ring->desc32[i].flags = htole16(NFE_RX_READY); 1306 } 1307 } 1308 1309 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1310 BUS_DMASYNC_PREWRITE); 1311 1312 ring->cur = ring->next = 0; 1313} 1314 1315void 1316nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1317{ 1318 struct nfe_rx_data *data; 1319 void *desc; 1320 int i, descsize; 1321 1322 if (sc->sc_flags & NFE_40BIT_ADDR) { 1323 desc = ring->desc64; 1324 descsize = sizeof (struct nfe_desc64); 1325 } else { 1326 desc = ring->desc32; 1327 descsize = sizeof (struct nfe_desc32); 1328 } 1329 1330 if (desc != NULL) { 1331 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1332 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1333 bus_dmamap_unload(sc->sc_dmat, ring->map); 1334 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)desc, 1335 NFE_RX_RING_COUNT * descsize); 1336 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1337 } 1338 1339 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1340 data = &ring->data[i]; 1341 1342 if (data->map != NULL) { 1343 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1344 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1345 bus_dmamap_unload(sc->sc_dmat, data->map); 1346 bus_dmamap_destroy(sc->sc_dmat, data->map); 1347 } 1348 if (data->m != NULL) 1349 m_freem(data->m); 1350 } 1351} 1352 1353struct nfe_jbuf * 1354nfe_jalloc(struct nfe_softc *sc) 1355{ 1356 struct nfe_jbuf *jbuf; 1357 1358 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1359 if (jbuf == NULL) 1360 return NULL; 1361 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1362 return jbuf; 1363} 1364 1365/* 1366 * This is called automatically by the network stack when the mbuf is freed. 1367 * Caution must be taken that the NIC might be reset by the time the mbuf is 1368 * freed. 1369 */ 1370void 1371nfe_jfree(caddr_t buf, u_int size, void *arg) 1372{ 1373 struct nfe_softc *sc = arg; 1374 struct nfe_jbuf *jbuf; 1375 int i; 1376 1377 /* find the jbuf from the base pointer */ 1378 i = (buf - sc->rxq.jpool) / NFE_JBYTES; 1379 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1380 printf("%s: request to free a buffer (%p) not managed by us\n", 1381 sc->sc_dev.dv_xname, buf); 1382 return; 1383 } 1384 jbuf = &sc->rxq.jbuf[i]; 1385 1386 /* ..and put it back in the free list */ 1387 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1388} 1389 1390int 1391nfe_jpool_alloc(struct nfe_softc *sc) 1392{ 1393 struct nfe_rx_ring *ring = &sc->rxq; 1394 struct nfe_jbuf *jbuf; 1395 bus_addr_t physaddr; 1396 caddr_t buf; 1397 int i, nsegs, error; 1398 1399 /* 1400 * Allocate a big chunk of DMA'able memory. 1401 */ 1402 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1403 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1404 if (error != 0) { 1405 printf("%s: could not create jumbo DMA map\n", 1406 sc->sc_dev.dv_xname); 1407 goto fail; 1408 } 1409 1410 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1411 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1412 if (error != 0) { 1413 printf("%s could not allocate jumbo DMA memory\n", 1414 sc->sc_dev.dv_xname); 1415 goto fail; 1416 } 1417 1418 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1419 &ring->jpool, BUS_DMA_NOWAIT); 1420 if (error != 0) { 1421 printf("%s: could not map jumbo DMA memory\n", 1422 sc->sc_dev.dv_xname); 1423 goto fail; 1424 } 1425 1426 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1427 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1428 if (error != 0) { 1429 printf("%s: could not load jumbo DMA map\n", 1430 sc->sc_dev.dv_xname); 1431 goto fail; 1432 } 1433 1434 /* ..and split it into 9KB chunks */ 1435 SLIST_INIT(&ring->jfreelist); 1436 1437 buf = ring->jpool; 1438 physaddr = ring->jmap->dm_segs[0].ds_addr; 1439 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1440 jbuf = &ring->jbuf[i]; 1441 1442 jbuf->buf = buf; 1443 jbuf->physaddr = physaddr; 1444 1445 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1446 1447 buf += NFE_JBYTES; 1448 physaddr += NFE_JBYTES; 1449 } 1450 1451 return 0; 1452 1453fail: nfe_jpool_free(sc); 1454 return error; 1455} 1456 1457void 1458nfe_jpool_free(struct nfe_softc *sc) 1459{ 1460 struct nfe_rx_ring *ring = &sc->rxq; 1461 1462 if (ring->jmap != NULL) { 1463 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1464 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1465 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1466 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1467 } 1468 if (ring->jpool != NULL) { 1469 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1470 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1471 } 1472} 1473 1474int 1475nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1476{ 1477 int i, nsegs, error; 1478 void **desc; 1479 int descsize; 1480 1481 if (sc->sc_flags & NFE_40BIT_ADDR) { 1482 desc = (void **)&ring->desc64; 1483 descsize = sizeof (struct nfe_desc64); 1484 } else { 1485 desc = (void **)&ring->desc32; 1486 descsize = sizeof (struct nfe_desc32); 1487 } 1488 1489 ring->queued = 0; 1490 ring->cur = ring->next = 0; 1491 1492 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1493 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1494 1495 if (error != 0) { 1496 printf("%s: could not create desc DMA map\n", 1497 sc->sc_dev.dv_xname); 1498 goto fail; 1499 } 1500 1501 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1502 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1503 if (error != 0) { 1504 printf("%s: could not allocate DMA memory\n", 1505 sc->sc_dev.dv_xname); 1506 goto fail; 1507 } 1508 1509 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1510 NFE_TX_RING_COUNT * descsize, (caddr_t *)desc, BUS_DMA_NOWAIT); 1511 if (error != 0) { 1512 printf("%s: could not map desc DMA memory\n", 1513 sc->sc_dev.dv_xname); 1514 goto fail; 1515 } 1516 1517 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1518 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1519 if (error != 0) { 1520 printf("%s: could not load desc DMA map\n", 1521 sc->sc_dev.dv_xname); 1522 goto fail; 1523 } 1524 1525 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1526 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1527 1528 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1529 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1530 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1531 &ring->data[i].map); 1532 if (error != 0) { 1533 printf("%s: could not create DMA map\n", 1534 sc->sc_dev.dv_xname); 1535 goto fail; 1536 } 1537 } 1538 1539 return 0; 1540 1541fail: nfe_free_tx_ring(sc, ring); 1542 return error; 1543} 1544 1545void 1546nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1547{ 1548 struct nfe_tx_data *data; 1549 int i; 1550 1551 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1552 if (sc->sc_flags & NFE_40BIT_ADDR) 1553 ring->desc64[i].flags = 0; 1554 else 1555 ring->desc32[i].flags = 0; 1556 1557 data = &ring->data[i]; 1558 1559 if (data->m != NULL) { 1560 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1561 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1562 bus_dmamap_unload(sc->sc_dmat, data->active); 1563 m_freem(data->m); 1564 data->m = NULL; 1565 } 1566 } 1567 1568 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1569 BUS_DMASYNC_PREWRITE); 1570 1571 ring->queued = 0; 1572 ring->cur = ring->next = 0; 1573} 1574 1575void 1576nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1577{ 1578 struct nfe_tx_data *data; 1579 void *desc; 1580 int i, descsize; 1581 1582 if (sc->sc_flags & NFE_40BIT_ADDR) { 1583 desc = ring->desc64; 1584 descsize = sizeof (struct nfe_desc64); 1585 } else { 1586 desc = ring->desc32; 1587 descsize = sizeof (struct nfe_desc32); 1588 } 1589 1590 if (desc != NULL) { 1591 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1592 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1593 bus_dmamap_unload(sc->sc_dmat, ring->map); 1594 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)desc, 1595 NFE_TX_RING_COUNT * descsize); 1596 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1597 } 1598 1599 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1600 data = &ring->data[i]; 1601 1602 if (data->m != NULL) { 1603 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1604 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1605 bus_dmamap_unload(sc->sc_dmat, data->active); 1606 m_freem(data->m); 1607 } 1608 } 1609 1610 /* ..and now actually destroy the DMA mappings */ 1611 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1612 data = &ring->data[i]; 1613 if (data->map == NULL) 1614 continue; 1615 bus_dmamap_destroy(sc->sc_dmat, data->map); 1616 } 1617} 1618 1619int 1620nfe_ifmedia_upd(struct ifnet *ifp) 1621{ 1622 struct nfe_softc *sc = ifp->if_softc; 1623 struct mii_data *mii = &sc->sc_mii; 1624 struct mii_softc *miisc; 1625 1626 if (mii->mii_instance != 0) { 1627 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1628 mii_phy_reset(miisc); 1629 } 1630 return mii_mediachg(mii); 1631} 1632 1633void 1634nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1635{ 1636 struct nfe_softc *sc = ifp->if_softc; 1637 struct mii_data *mii = &sc->sc_mii; 1638 1639 mii_pollstat(mii); 1640 ifmr->ifm_status = mii->mii_media_status; 1641 ifmr->ifm_active = mii->mii_media_active; 1642} 1643 1644void 1645nfe_setmulti(struct nfe_softc *sc) 1646{ 1647 struct arpcom *ac = &sc->sc_arpcom; 1648 struct ifnet *ifp = &ac->ac_if; 1649 struct ether_multi *enm; 1650 struct ether_multistep step; 1651 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1652 uint32_t filter = NFE_RXFILTER_MAGIC; 1653 int i; 1654 1655 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1656 bzero(addr, ETHER_ADDR_LEN); 1657 bzero(mask, ETHER_ADDR_LEN); 1658 goto done; 1659 } 1660 1661 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1662 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1663 1664 ETHER_FIRST_MULTI(step, ac, enm); 1665 while (enm != NULL) { 1666 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1667 ifp->if_flags |= IFF_ALLMULTI; 1668 bzero(addr, ETHER_ADDR_LEN); 1669 bzero(mask, ETHER_ADDR_LEN); 1670 goto done; 1671 } 1672 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1673 addr[i] &= enm->enm_addrlo[i]; 1674 mask[i] &= ~enm->enm_addrlo[i]; 1675 } 1676 ETHER_NEXT_MULTI(step, enm); 1677 } 1678 for (i = 0; i < ETHER_ADDR_LEN; i++) 1679 mask[i] |= addr[i]; 1680 1681done: 1682 addr[0] |= 0x01; /* make sure multicast bit is set */ 1683 1684 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1685 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1686 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1687 addr[5] << 8 | addr[4]); 1688 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1689 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1690 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1691 mask[5] << 8 | mask[4]); 1692 1693 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1694 NFE_WRITE(sc, NFE_RXFILTER, filter); 1695} 1696 1697void 1698nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1699{ 1700 uint32_t tmp; 1701 1702 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1703 addr[0] = (tmp >> 8) & 0xff; 1704 addr[1] = (tmp & 0xff); 1705 1706 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1707 addr[2] = (tmp >> 24) & 0xff; 1708 addr[3] = (tmp >> 16) & 0xff; 1709 addr[4] = (tmp >> 8) & 0xff; 1710 addr[5] = (tmp & 0xff); 1711} 1712 1713void 1714nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1715{ 1716 NFE_WRITE(sc, NFE_MACADDR_LO, 1717 addr[5] << 8 | addr[4]); 1718 NFE_WRITE(sc, NFE_MACADDR_HI, 1719 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1720} 1721 1722void 1723nfe_tick(void *arg) 1724{ 1725 struct nfe_softc *sc = arg; 1726 int s; 1727 1728 s = splnet(); 1729 mii_tick(&sc->sc_mii); 1730 splx(s); 1731 1732 timeout_add(&sc->sc_tick_ch, hz); 1733} 1734