if_nfe.c revision 1.33
1228753Smm/* $OpenBSD: if_nfe.c,v 1.33 2006/02/12 13:28:30 damien Exp $ */ 2228753Smm 3228753Smm/*- 4228753Smm * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr> 5228753Smm * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org> 6228753Smm * 7228753Smm * Permission to use, copy, modify, and distribute this software for any 8228753Smm * purpose with or without fee is hereby granted, provided that the above 9228753Smm * copyright notice and this permission notice appear in all copies. 10228753Smm * 11228753Smm * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12228753Smm * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13228753Smm * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14228753Smm * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15228753Smm * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16228753Smm * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17228753Smm * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18228753Smm */ 19228753Smm 20228753Smm/* Driver for nvidia nForce Ethernet */ 21228753Smm 22228753Smm#include "bpfilter.h" 23228753Smm#include "vlan.h" 24228753Smm 25228753Smm#include <sys/param.h> 26228753Smm#include <sys/endian.h> 27228753Smm#include <sys/systm.h> 28228753Smm#include <sys/types.h> 29228753Smm#include <sys/sockio.h> 30228753Smm#include <sys/mbuf.h> 31228753Smm#include <sys/queue.h> 32228753Smm#include <sys/malloc.h> 33228753Smm#include <sys/kernel.h> 34228753Smm#include <sys/device.h> 35228753Smm#include <sys/socket.h> 36228753Smm 37228753Smm#include <machine/bus.h> 38228753Smm 39228753Smm#include <net/if.h> 40228753Smm#include <net/if_dl.h> 41228753Smm#include <net/if_media.h> 42228753Smm 43228753Smm#ifdef INET 44228753Smm#include <netinet/in.h> 45228753Smm#include <netinet/in_systm.h> 46228753Smm#include <netinet/in_var.h> 47228753Smm#include <netinet/ip.h> 48228753Smm#include <netinet/if_ether.h> 49228753Smm#endif 50228753Smm 51228753Smm#if NVLAN > 0 52228753Smm#include <net/if_types.h> 53228753Smm#include <net/if_vlan_var.h> 54228753Smm#endif 55228753Smm 56228753Smm#if NBPFILTER > 0 57228753Smm#include <net/bpf.h> 58228753Smm#endif 59228753Smm 60228753Smm#include <dev/mii/mii.h> 61228753Smm#include <dev/mii/miivar.h> 62228753Smm 63228753Smm#include <dev/pci/pcireg.h> 64228753Smm#include <dev/pci/pcivar.h> 65228753Smm#include <dev/pci/pcidevs.h> 66228753Smm 67228753Smm#include <dev/pci/if_nfereg.h> 68228753Smm#include <dev/pci/if_nfevar.h> 69228753Smm 70228753Smmint nfe_match(struct device *, void *, void *); 71228753Smmvoid nfe_attach(struct device *, struct device *, void *); 72228753Smmvoid nfe_power(int, void *); 73228753Smmvoid nfe_miibus_statchg(struct device *); 74228753Smmint nfe_miibus_readreg(struct device *, int, int); 75228753Smmvoid nfe_miibus_writereg(struct device *, int, int, int); 76228753Smmint nfe_intr(void *); 77228753Smmint nfe_ioctl(struct ifnet *, u_long, caddr_t); 78228753Smmvoid nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 79228753Smmvoid nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 80228753Smmvoid nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 81228753Smmvoid nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 82228753Smmvoid nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 83228753Smmvoid nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 84228753Smmvoid nfe_rxeof(struct nfe_softc *); 85228753Smmvoid nfe_txeof(struct nfe_softc *); 86228753Smmint nfe_encap(struct nfe_softc *, struct mbuf *); 87228753Smmvoid nfe_start(struct ifnet *); 88228753Smmvoid nfe_watchdog(struct ifnet *); 89228753Smmint nfe_init(struct ifnet *); 90228753Smmvoid nfe_stop(struct ifnet *, int); 91228753Smmstruct nfe_jbuf *nfe_jalloc(struct nfe_softc *); 92228753Smmvoid nfe_jfree(caddr_t, u_int, void *); 93228753Smmint nfe_jpool_alloc(struct nfe_softc *); 94228753Smmvoid nfe_jpool_free(struct nfe_softc *); 95228753Smmint nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 96228753Smmvoid nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 97228753Smmvoid nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 98228753Smmint nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 99228753Smmvoid nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 100228753Smmvoid nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 101228753Smmint nfe_ifmedia_upd(struct ifnet *); 102228753Smmvoid nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 103228753Smmvoid nfe_setmulti(struct nfe_softc *); 104228753Smmvoid nfe_get_macaddr(struct nfe_softc *, uint8_t *); 105228753Smmvoid nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 106228753Smmvoid nfe_tick(void *); 107228753Smm 108228753Smmstruct cfattach nfe_ca = { 109228753Smm sizeof (struct nfe_softc), nfe_match, nfe_attach 110}; 111 112struct cfdriver nfe_cd = { 113 NULL, "nfe", DV_IFNET 114}; 115 116#define NFE_DEBUG 117#define NFE_NO_JUMBO 118 119#ifdef NFE_DEBUG 120int nfedebug = 1; 121#define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 122#define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 123#else 124#define DPRINTF(x) 125#define DPRINTFN(n,x) 126#endif 127 128const struct pci_matchid nfe_devices[] = { 129 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 130 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 131 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 132 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 133 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 134 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 135 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 136 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 137 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 138 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 139 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 140 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 141 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 142 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 143 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 } 144}; 145 146int 147nfe_match(struct device *dev, void *match, void *aux) 148{ 149 return pci_matchbyid((struct pci_attach_args *)aux, nfe_devices, 150 sizeof (nfe_devices) / sizeof (nfe_devices[0])); 151} 152 153void 154nfe_attach(struct device *parent, struct device *self, void *aux) 155{ 156 struct nfe_softc *sc = (struct nfe_softc *)self; 157 struct pci_attach_args *pa = aux; 158 pci_chipset_tag_t pc = pa->pa_pc; 159 pci_intr_handle_t ih; 160 const char *intrstr; 161 struct ifnet *ifp; 162 bus_size_t memsize; 163 164 if (pci_mapreg_map(pa, NFE_PCI_BA, PCI_MAPREG_TYPE_MEM, 0, 165 &sc->sc_memt, &sc->sc_memh, NULL, &memsize, 0) != 0) { 166 printf(": can't map mem space\n"); 167 return; 168 } 169 170 if (pci_intr_map(pa, &ih) != 0) { 171 printf(": couldn't map interrupt\n"); 172 return; 173 } 174 175 intrstr = pci_intr_string(pc, ih); 176 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc, 177 sc->sc_dev.dv_xname); 178 if (sc->sc_ih == NULL) { 179 printf(": couldn't establish interrupt"); 180 if (intrstr != NULL) 181 printf(" at %s", intrstr); 182 printf("\n"); 183 return; 184 } 185 printf(": %s", intrstr); 186 187 sc->sc_dmat = pa->pa_dmat; 188 189 nfe_get_macaddr(sc, sc->sc_arpcom.ac_enaddr); 190 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 191 192 sc->sc_flags = 0; 193 194 switch (PCI_PRODUCT(pa->pa_id)) { 195 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 196 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 197 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 198 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 199 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 200 break; 201 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 202 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 203 sc->sc_flags |= NFE_40BIT_ADDR; 204 break; 205 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 206 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 207 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 208 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 209 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 210 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 211 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 212 break; 213 } 214 215#ifndef NFE_NO_JUMBO 216 /* enable jumbo frames for adapters that support it */ 217 if (sc->sc_flags & NFE_JUMBO_SUP) 218 sc->sc_flags |= NFE_USE_JUMBO; 219#endif 220 221 /* 222 * Allocate Tx and Rx rings. 223 */ 224 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 225 printf("%s: could not allocate Tx ring\n", 226 sc->sc_dev.dv_xname); 227 return; 228 } 229 230 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 231 printf("%s: could not allocate Rx ring\n", 232 sc->sc_dev.dv_xname); 233 nfe_free_tx_ring(sc, &sc->txq); 234 return; 235 } 236 237 ifp = &sc->sc_arpcom.ac_if; 238 ifp->if_softc = sc; 239 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 240 ifp->if_ioctl = nfe_ioctl; 241 ifp->if_start = nfe_start; 242 ifp->if_watchdog = nfe_watchdog; 243 ifp->if_init = nfe_init; 244 ifp->if_baudrate = IF_Gbps(1); 245 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 246 IFQ_SET_READY(&ifp->if_snd); 247 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 248 249 ifp->if_capabilities = IFCAP_VLAN_MTU; 250#ifdef NFE_CSUM 251 if (sc->sc_flags & NFE_HW_CSUM) { 252 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 253 IFCAP_CSUM_UDPv4; 254 } 255#endif 256 257 sc->sc_mii.mii_ifp = ifp; 258 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 259 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 260 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 261 262 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 263 nfe_ifmedia_sts); 264 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 265 MII_OFFSET_ANY, 0); 266 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 267 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 268 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 269 0, NULL); 270 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 271 } else 272 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 273 274 if_attach(ifp); 275 ether_ifattach(ifp); 276 277 timeout_set(&sc->sc_tick_ch, nfe_tick, sc); 278 279 sc->sc_powerhook = powerhook_establish(nfe_power, sc); 280} 281 282void 283nfe_power(int why, void *arg) 284{ 285 struct nfe_softc *sc = arg; 286 struct ifnet *ifp; 287 288 if (why == PWR_RESUME) { 289 ifp = &sc->sc_arpcom.ac_if; 290 if (ifp->if_flags & IFF_UP) { 291 ifp->if_flags &= ~IFF_RUNNING; 292 nfe_init(ifp); 293 if (ifp->if_flags & IFF_RUNNING) 294 nfe_start(ifp); 295 } 296 } 297} 298 299void 300nfe_miibus_statchg(struct device *dev) 301{ 302 struct nfe_softc *sc = (struct nfe_softc *)dev; 303 struct mii_data *mii = &sc->sc_mii; 304 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 305 306 phy = NFE_READ(sc, NFE_PHY_IFACE); 307 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 308 309 seed = NFE_READ(sc, NFE_RNDSEED); 310 seed &= ~NFE_SEED_MASK; 311 312 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 313 phy |= NFE_PHY_HDX; /* half-duplex */ 314 misc |= NFE_MISC1_HDX; 315 } 316 317 switch (IFM_SUBTYPE(mii->mii_media_active)) { 318 case IFM_1000_T: /* full-duplex only */ 319 link |= NFE_MEDIA_1000T; 320 seed |= NFE_SEED_1000T; 321 phy |= NFE_PHY_1000T; 322 break; 323 case IFM_100_TX: 324 link |= NFE_MEDIA_100TX; 325 seed |= NFE_SEED_100TX; 326 phy |= NFE_PHY_100TX; 327 break; 328 case IFM_10_T: 329 link |= NFE_MEDIA_10T; 330 seed |= NFE_SEED_10T; 331 break; 332 } 333 334 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 335 336 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 337 NFE_WRITE(sc, NFE_MISC1, misc); 338 NFE_WRITE(sc, NFE_LINKSPEED, link); 339} 340 341int 342nfe_miibus_readreg(struct device *dev, int phy, int reg) 343{ 344 struct nfe_softc *sc = (struct nfe_softc *)dev; 345 uint32_t val; 346 int ntries; 347 348 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 349 350 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 351 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 352 DELAY(100); 353 } 354 355 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 356 357 for (ntries = 0; ntries < 1000; ntries++) { 358 DELAY(100); 359 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 360 break; 361 } 362 if (ntries == 1000) { 363 DPRINTFN(2, ("timeout waiting for PHY\n")); 364 return 0; 365 } 366 367 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 368 DPRINTFN(2, ("could not read PHY\n")); 369 return 0; 370 } 371 372 val = NFE_READ(sc, NFE_PHY_DATA); 373 if (val != 0xffffffff && val != 0) 374 sc->phyaddr = phy; 375 376 DPRINTFN(2, ("mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val)); 377 378 return val; 379} 380 381void 382nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 383{ 384 struct nfe_softc *sc = (struct nfe_softc *)dev; 385 uint32_t ctl; 386 int ntries; 387 388 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 389 390 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 391 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 392 DELAY(100); 393 } 394 395 NFE_WRITE(sc, NFE_PHY_DATA, val); 396 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 397 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 398 399 for (ntries = 0; ntries < 1000; ntries++) { 400 DELAY(100); 401 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 402 break; 403 } 404#ifdef NFE_DEBUG 405 if (nfedebug >= 2 && ntries == 1000) 406 printf("could not write to PHY\n"); 407#endif 408} 409 410int 411nfe_intr(void *arg) 412{ 413 struct nfe_softc *sc = arg; 414 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 415 uint32_t r; 416 417 /* disable interrupts */ 418 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 419 420 r = NFE_READ(sc, NFE_IRQ_STATUS); 421 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 422 423 if (r == 0) { 424 /* re-enable interrupts */ 425 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 426 return 0; 427 } 428 429 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 430 431 if (r & NFE_IRQ_LINK) { 432 NFE_READ(sc, NFE_PHY_STATUS); 433 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 434 DPRINTF(("link state changed\n")); 435 } 436 437 if (ifp->if_flags & IFF_RUNNING) { 438 /* check Rx ring */ 439 nfe_rxeof(sc); 440 441 /* check Tx ring */ 442 nfe_txeof(sc); 443 } 444 445 /* re-enable interrupts */ 446 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 447 448 return 1; 449} 450 451int 452nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 453{ 454 struct nfe_softc *sc = ifp->if_softc; 455 struct ifreq *ifr = (struct ifreq *)data; 456 struct ifaddr *ifa = (struct ifaddr *)data; 457 int s, error = 0; 458 459 s = splnet(); 460 461 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) { 462 splx(s); 463 return error; 464 } 465 466 switch (cmd) { 467 case SIOCSIFADDR: 468 ifp->if_flags |= IFF_UP; 469 nfe_init(ifp); 470 switch (ifa->ifa_addr->sa_family) { 471#ifdef INET 472 case AF_INET: 473 arp_ifinit(&sc->sc_arpcom, ifa); 474 break; 475#endif 476 default: 477 break; 478 } 479 break; 480 case SIOCSIFMTU: 481 if (ifr->ifr_mtu < ETHERMIN || 482 ((sc->sc_flags & NFE_USE_JUMBO) && 483 ifr->ifr_mtu > ETHERMTU_JUMBO) || 484 (!(sc->sc_flags & NFE_USE_JUMBO) && 485 ifr->ifr_mtu > ETHERMTU)) 486 error = EINVAL; 487 else if (ifp->if_mtu != ifr->ifr_mtu) 488 ifp->if_mtu = ifr->ifr_mtu; 489 break; 490 case SIOCSIFFLAGS: 491 if (ifp->if_flags & IFF_UP) { 492 /* 493 * If only the PROMISC or ALLMULTI flag changes, then 494 * don't do a full re-init of the chip, just update 495 * the Rx filter. 496 */ 497 if ((ifp->if_flags & IFF_RUNNING) && 498 ((ifp->if_flags ^ sc->sc_if_flags) & 499 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 500 nfe_setmulti(sc); 501 else 502 nfe_init(ifp); 503 } else { 504 if (ifp->if_flags & IFF_RUNNING) 505 nfe_stop(ifp, 1); 506 } 507 sc->sc_if_flags = ifp->if_flags; 508 break; 509 case SIOCADDMULTI: 510 case SIOCDELMULTI: 511 error = (cmd == SIOCADDMULTI) ? 512 ether_addmulti(ifr, &sc->sc_arpcom) : 513 ether_delmulti(ifr, &sc->sc_arpcom); 514 515 if (error == ENETRESET) { 516 if (ifp->if_flags & IFF_RUNNING) 517 nfe_setmulti(sc); 518 error = 0; 519 } 520 break; 521 case SIOCSIFMEDIA: 522 case SIOCGIFMEDIA: 523 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 524 break; 525 default: 526 error = EINVAL; 527 } 528 529 splx(s); 530 531 return error; 532} 533 534void 535nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 536{ 537 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 538 (caddr_t)desc32 - (caddr_t)sc->txq.desc32, 539 sizeof (struct nfe_desc32), ops); 540} 541 542void 543nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 544{ 545 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 546 (caddr_t)desc64 - (caddr_t)sc->txq.desc64, 547 sizeof (struct nfe_desc64), ops); 548} 549 550void 551nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 552{ 553 if (end >= start) { 554 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 555 (caddr_t)&sc->txq.desc32[start] - (caddr_t)sc->txq.desc32, 556 (caddr_t)&sc->txq.desc32[end] - 557 (caddr_t)&sc->txq.desc32[start], ops); 558 return; 559 } 560 /* sync from 'start' to end of ring */ 561 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 562 (caddr_t)&sc->txq.desc32[start] - (caddr_t)sc->txq.desc32, 563 (caddr_t)&sc->txq.desc32[NFE_TX_RING_COUNT] - 564 (caddr_t)&sc->txq.desc32[start], ops); 565 566 /* sync from start of ring to 'end' */ 567 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 568 (caddr_t)&sc->txq.desc32[end] - (caddr_t)sc->txq.desc32, ops); 569} 570 571void 572nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 573{ 574 if (end >= start) { 575 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 576 (caddr_t)&sc->txq.desc64[start] - (caddr_t)sc->txq.desc64, 577 (caddr_t)&sc->txq.desc64[end] - 578 (caddr_t)&sc->txq.desc64[start], ops); 579 return; 580 } 581 /* sync from 'start' to end of ring */ 582 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 583 (caddr_t)&sc->txq.desc64[start] - (caddr_t)sc->txq.desc64, 584 (caddr_t)&sc->txq.desc64[NFE_TX_RING_COUNT] - 585 (caddr_t)&sc->txq.desc64[start], ops); 586 587 /* sync from start of ring to 'end' */ 588 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 589 (caddr_t)&sc->txq.desc64[end] - (caddr_t)sc->txq.desc64, ops); 590} 591 592void 593nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 594{ 595 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 596 (caddr_t)desc32 - (caddr_t)sc->rxq.desc32, 597 sizeof (struct nfe_desc32), ops); 598} 599 600void 601nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 602{ 603 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 604 (caddr_t)desc64 - (caddr_t)sc->rxq.desc64, 605 sizeof (struct nfe_desc64), ops); 606} 607 608void 609nfe_rxeof(struct nfe_softc *sc) 610{ 611 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 612 struct nfe_desc32 *desc32; 613 struct nfe_desc64 *desc64; 614 struct nfe_rx_data *data; 615 struct nfe_jbuf *jbuf; 616 struct mbuf *m, *mnew; 617 bus_addr_t physaddr; 618 uint16_t flags; 619 int error, len; 620 621 for (;;) { 622 data = &sc->rxq.data[sc->rxq.cur]; 623 624 if (sc->sc_flags & NFE_40BIT_ADDR) { 625 desc64 = &sc->rxq.desc64[sc->rxq.cur]; 626 nfe_rxdesc64_sync(sc, desc64, BUS_DMASYNC_POSTREAD); 627 628 flags = letoh16(desc64->flags); 629 len = letoh16(desc64->length) & 0x3fff; 630 } else { 631 desc32 = &sc->rxq.desc32[sc->rxq.cur]; 632 nfe_rxdesc32_sync(sc, desc32, BUS_DMASYNC_POSTREAD); 633 634 flags = letoh16(desc32->flags); 635 len = letoh16(desc32->length) & 0x3fff; 636 } 637 638 if (flags & NFE_RX_READY) 639 break; 640 641 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 642 if (!(flags & NFE_RX_VALID_V1)) 643 goto skip; 644 645 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 646 flags &= ~NFE_RX_ERROR; 647 len--; /* fix buffer length */ 648 } 649 } else { 650 if (!(flags & NFE_RX_VALID_V2)) 651 goto skip; 652 653 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 654 flags &= ~NFE_RX_ERROR; 655 len--; /* fix buffer length */ 656 } 657 } 658 659 if (flags & NFE_RX_ERROR) { 660 ifp->if_ierrors++; 661 goto skip; 662 } 663 664 /* 665 * Try to allocate a new mbuf for this ring element and load 666 * it before processing the current mbuf. If the ring element 667 * cannot be loaded, drop the received packet and reuse the 668 * old mbuf. In the unlikely case that the old mbuf can't be 669 * reloaded either, explicitly panic. 670 */ 671 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 672 if (mnew == NULL) { 673 ifp->if_ierrors++; 674 goto skip; 675 } 676 677 if (sc->sc_flags & NFE_USE_JUMBO) { 678 if ((jbuf = nfe_jalloc(sc)) == NULL) { 679 m_freem(mnew); 680 ifp->if_ierrors++; 681 goto skip; 682 } 683 MEXTADD(mnew, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, sc); 684 685 bus_dmamap_sync(sc->sc_dmat, sc->rxq.jmap, 686 mtod(data->m, caddr_t) - sc->rxq.jpool, NFE_JBYTES, 687 BUS_DMASYNC_POSTREAD); 688 689 physaddr = jbuf->physaddr; 690 } else { 691 MCLGET(mnew, M_DONTWAIT); 692 if (!(mnew->m_flags & M_EXT)) { 693 m_freem(mnew); 694 ifp->if_ierrors++; 695 goto skip; 696 } 697 698 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 699 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 700 bus_dmamap_unload(sc->sc_dmat, data->map); 701 702 error = bus_dmamap_load(sc->sc_dmat, data->map, 703 mtod(mnew, void *), MCLBYTES, NULL, 704 BUS_DMA_READ | BUS_DMA_NOWAIT); 705 if (error != 0) { 706 m_freem(mnew); 707 708 /* try to reload the old mbuf */ 709 error = bus_dmamap_load(sc->sc_dmat, data->map, 710 mtod(data->m, void *), MCLBYTES, NULL, 711 BUS_DMA_READ | BUS_DMA_NOWAIT); 712 if (error != 0) { 713 /* very unlikely that it will fail.. */ 714 panic("%s: could not load old rx mbuf", 715 sc->sc_dev.dv_xname); 716 } 717 ifp->if_ierrors++; 718 goto skip; 719 } 720 physaddr = data->map->dm_segs[0].ds_addr; 721 } 722 723 /* 724 * New mbuf successfully loaded, update Rx ring and continue 725 * processing. 726 */ 727 m = data->m; 728 data->m = mnew; 729 730 /* finalize mbuf */ 731 m->m_pkthdr.len = m->m_len = len; 732 m->m_pkthdr.rcvif = ifp; 733 734#ifdef notyet 735 if (sc->sc_flags & NFE_HW_CSUM) { 736 if (flags & NFE_RX_IP_CSUMOK) 737 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 738 if (flags & NFE_RX_UDP_CSUMOK) 739 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 740 if (flags & NFE_RX_TCP_CSUMOK) 741 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 742 } 743#elif defined(NFE_CSUM) 744 if ((sc->sc_flags & NFE_HW_CSUM) && (flags & NFE_RX_CSUMOK)) 745 m->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 746#endif 747 748#if NBPFILTER > 0 749 if (ifp->if_bpf) 750 bpf_mtap(ifp->if_bpf, m); 751#endif 752 ifp->if_ipackets++; 753 ether_input_mbuf(ifp, m); 754 755 /* update mapping address in h/w descriptor */ 756 if (sc->sc_flags & NFE_40BIT_ADDR) { 757#if defined(__LP64__) 758 desc64->physaddr[0] = htole32(physaddr >> 32); 759#endif 760 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 761 } else { 762 desc32->physaddr = htole32(physaddr); 763 } 764 765skip: if (sc->sc_flags & NFE_40BIT_ADDR) { 766 desc64->length = htole16(sc->rxq.bufsz); 767 desc64->flags = htole16(NFE_RX_READY); 768 769 nfe_rxdesc64_sync(sc, desc64, BUS_DMASYNC_PREWRITE); 770 } else { 771 desc32->length = htole16(sc->rxq.bufsz); 772 desc32->flags = htole16(NFE_RX_READY); 773 774 nfe_rxdesc32_sync(sc, desc32, BUS_DMASYNC_PREWRITE); 775 } 776 777 sc->rxq.cur = (sc->rxq.cur + 1) % NFE_RX_RING_COUNT; 778 } 779} 780 781void 782nfe_txeof(struct nfe_softc *sc) 783{ 784 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 785 struct nfe_desc32 *desc32; 786 struct nfe_desc64 *desc64; 787 struct nfe_tx_data *data; 788 uint16_t flags; 789 790 while (sc->txq.next != sc->txq.cur) { 791 data = &sc->txq.data[sc->txq.next]; 792 793 if (sc->sc_flags & NFE_40BIT_ADDR) { 794 desc64 = &sc->txq.desc64[sc->txq.next]; 795 nfe_txdesc64_sync(sc, desc64, BUS_DMASYNC_POSTREAD); 796 797 flags = letoh16(desc64->flags); 798 } else { 799 desc32 = &sc->txq.desc32[sc->txq.next]; 800 nfe_txdesc32_sync(sc, desc32, BUS_DMASYNC_POSTREAD); 801 802 flags = letoh16(desc32->flags); 803 } 804 805 if (flags & NFE_TX_VALID) 806 break; 807 808 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 809 if (!(flags & NFE_TX_LASTFRAG_V1)) 810 goto skip; 811 812 if ((flags & NFE_TX_ERROR_V1) != 0) { 813 DPRINTF(("tx error 0x%04x\n", flags)); 814 ifp->if_oerrors++; 815 } else 816 ifp->if_opackets++; 817 } else { 818 if (!(flags & NFE_TX_LASTFRAG_V2)) 819 goto skip; 820 821 if ((flags & NFE_TX_ERROR_V2) != 0) { 822 DPRINTF(("tx error 0x%04x\n", flags)); 823 ifp->if_oerrors++; 824 } else 825 ifp->if_opackets++; 826 } 827 828 if (data->m == NULL) { /* should not get there */ 829 DPRINTF(("last fragment bit w/o associated mbuf!\n")); 830 goto skip; 831 } 832 833 /* last fragment of the mbuf chain transmitted */ 834 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 835 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 836 bus_dmamap_unload(sc->sc_dmat, data->active); 837 m_freem(data->m); 838 data->m = NULL; 839 840skip: sc->txq.queued--; 841 sc->txq.next = (sc->txq.next + 1) % NFE_TX_RING_COUNT; 842 } 843 844 ifp->if_timer = 0; 845 ifp->if_flags &= ~IFF_OACTIVE; 846 nfe_start(ifp); 847} 848 849int 850nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 851{ 852 struct nfe_desc32 *desc32; 853 struct nfe_desc64 *desc64; 854 struct nfe_tx_data *data; 855 struct mbuf *mnew; 856 bus_dmamap_t map; 857 uint16_t flags = NFE_TX_VALID; 858 int error, i; 859 860 map = sc->txq.data[sc->txq.cur].map; 861 862 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 863 if (error != 0 && error != EFBIG) { 864 printf("%s: could not map mbuf (error %d)\n", 865 sc->sc_dev.dv_xname, error); 866 return error; 867 } 868 if (error != 0) { 869 /* too many fragments, linearize */ 870 871 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 872 if (mnew == NULL) 873 return ENOBUFS; 874 875 M_DUP_PKTHDR(mnew, m0); 876 if (m0->m_pkthdr.len > MHLEN) { 877 MCLGET(mnew, M_DONTWAIT); 878 if (!(mnew->m_flags & M_EXT)) { 879 m_freem(mnew); 880 return ENOBUFS; 881 } 882 } 883 884 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, caddr_t)); 885 m_freem(m0); 886 mnew->m_len = mnew->m_pkthdr.len; 887 m0 = mnew; 888 889 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, 890 BUS_DMA_NOWAIT); 891 if (error != 0) { 892 printf("%s: could not map mbuf (error %d)\n", 893 sc->sc_dev.dv_xname, error); 894 m_freem(m0); 895 return error; 896 } 897 } 898 899 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 900 bus_dmamap_unload(sc->sc_dmat, map); 901 return ENOBUFS; 902 } 903 904#ifdef NFE_CSUM 905 if (m0->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 906 flags |= NFE_TX_IP_CSUM; 907 if (m0->m_pkthdr.csum_flags & (M_TCPV4_CSUM_OUT | M_UDPV4_CSUM_OUT)) 908 flags |= NFE_TX_TCP_CSUM; 909#endif 910 911 for (i = 0; i < map->dm_nsegs; i++) { 912 data = &sc->txq.data[sc->txq.cur]; 913 914 if (sc->sc_flags & NFE_40BIT_ADDR) { 915 desc64 = &sc->txq.desc64[sc->txq.cur]; 916#if defined(__LP64__) 917 desc64->physaddr[0] = 918 htole32(map->dm_segs[i].ds_addr >> 32); 919#endif 920 desc64->physaddr[1] = 921 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 922 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 923 desc64->flags = htole16(flags); 924 } else { 925 desc32 = &sc->txq.desc32[sc->txq.cur]; 926 927 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 928 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 929 desc32->flags = htole16(flags); 930 } 931 932 /* csum flags belong to the first fragment only */ 933 if (map->dm_nsegs > 1) 934 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM); 935 936 sc->txq.queued++; 937 sc->txq.cur = (sc->txq.cur + 1) % NFE_TX_RING_COUNT; 938 } 939 940 /* the whole mbuf chain has been DMA mapped, fix last descriptor */ 941 if (sc->sc_flags & NFE_40BIT_ADDR) { 942 flags |= NFE_TX_LASTFRAG_V2; 943 desc64->flags = htole16(flags); 944 } else { 945 if (sc->sc_flags & NFE_JUMBO_SUP) 946 flags |= NFE_TX_LASTFRAG_V2; 947 else 948 flags |= NFE_TX_LASTFRAG_V1; 949 desc32->flags = htole16(flags); 950 } 951 952 data->m = m0; 953 data->active = map; 954 955 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 956 BUS_DMASYNC_PREWRITE); 957 958 return 0; 959} 960 961void 962nfe_start(struct ifnet *ifp) 963{ 964 struct nfe_softc *sc = ifp->if_softc; 965 int old = sc->txq.cur; 966 struct mbuf *m0; 967 uint32_t txctl; 968 969 for (;;) { 970 IFQ_POLL(&ifp->if_snd, m0); 971 if (m0 == NULL) 972 break; 973 974 if (nfe_encap(sc, m0) != 0) { 975 ifp->if_flags |= IFF_OACTIVE; 976 break; 977 } 978 979 /* packet put in h/w queue, remove from s/w queue */ 980 IFQ_DEQUEUE(&ifp->if_snd, m0); 981 982#if NBPFILTER > 0 983 if (ifp->if_bpf != NULL) 984 bpf_mtap(ifp->if_bpf, m0); 985#endif 986 } 987 if (sc->txq.cur == old) /* nothing sent */ 988 return; 989 990 if (sc->sc_flags & NFE_40BIT_ADDR) 991 nfe_txdesc64_rsync(sc, old, sc->txq.cur, BUS_DMASYNC_PREWRITE); 992 else 993 nfe_txdesc32_rsync(sc, old, sc->txq.cur, BUS_DMASYNC_PREWRITE); 994 995 txctl = NFE_RXTX_KICKTX; 996 if (sc->sc_flags & NFE_40BIT_ADDR) 997 txctl |= NFE_RXTX_V3MAGIC; 998 else if (sc->sc_flags & NFE_JUMBO_SUP) 999 txctl |= NFE_RXTX_V2MAGIC; 1000#ifdef NFE_CSUM 1001 if (sc->sc_flags & NFE_HW_CSUM) 1002 txctl |= NFE_RXTX_RXCHECK; 1003#endif 1004 1005 /* kick Tx */ 1006 NFE_WRITE(sc, NFE_RXTX_CTL, txctl); 1007 1008 /* 1009 * Set a timeout in case the chip goes out to lunch. 1010 */ 1011 ifp->if_timer = 5; 1012} 1013 1014void 1015nfe_watchdog(struct ifnet *ifp) 1016{ 1017 struct nfe_softc *sc = ifp->if_softc; 1018 1019 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1020 1021 ifp->if_flags &= ~IFF_RUNNING; 1022 nfe_init(ifp); 1023 1024 ifp->if_oerrors++; 1025} 1026 1027int 1028nfe_init(struct ifnet *ifp) 1029{ 1030 struct nfe_softc *sc = ifp->if_softc; 1031 uint32_t tmp, rxtxctl; 1032 1033 if (ifp->if_flags & IFF_RUNNING) 1034 return 0; 1035 1036 nfe_stop(ifp, 0); 1037 1038 nfe_ifmedia_upd(ifp); 1039 1040 NFE_WRITE(sc, NFE_TX_UNK, 0); 1041 1042 rxtxctl = NFE_RXTX_BIT2; 1043 if (sc->sc_flags & NFE_40BIT_ADDR) 1044 rxtxctl |= NFE_RXTX_V3MAGIC; 1045 else if (sc->sc_flags & NFE_JUMBO_SUP) 1046 rxtxctl |= NFE_RXTX_V2MAGIC; 1047#ifdef NFE_CSUM 1048 if (sc->sc_flags & NFE_HW_CSUM) 1049 rxtxctl |= NFE_RXTX_RXCHECK; 1050#endif 1051 1052 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl); 1053 DELAY(10); 1054 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl); 1055 1056 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1057 1058 /* set MAC address */ 1059 nfe_set_macaddr(sc, sc->sc_arpcom.ac_enaddr); 1060 1061 /* tell MAC where rings are in memory */ 1062 NFE_WRITE(sc, NFE_RX_RING_ADDR, sc->rxq.physaddr); 1063 NFE_WRITE(sc, NFE_TX_RING_ADDR, sc->txq.physaddr); 1064 1065 NFE_WRITE(sc, NFE_RING_SIZE, 1066 (NFE_RX_RING_COUNT - 1) << 16 | 1067 (NFE_TX_RING_COUNT - 1)); 1068 1069 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1070 1071 /* force MAC to wakeup */ 1072 tmp = NFE_READ(sc, NFE_PWR_STATE); 1073 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1074 DELAY(10); 1075 tmp = NFE_READ(sc, NFE_PWR_STATE); 1076 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1077 1078 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1079 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1080 NFE_WRITE(sc, NFE_TIMER_INT, 970); /* XXX Magic */ 1081 1082 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1083 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 1084 1085 rxtxctl &= ~NFE_RXTX_BIT2; 1086 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl); 1087 DELAY(10); 1088 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | rxtxctl); 1089 1090 /* set Rx filter */ 1091 nfe_setmulti(sc); 1092 1093 /* enable Rx */ 1094 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1095 1096 /* enable Tx */ 1097 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1098 1099 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1100 1101 /* enable interrupts */ 1102 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1103 1104 timeout_add(&sc->sc_tick_ch, hz); 1105 1106 ifp->if_flags |= IFF_RUNNING; 1107 ifp->if_flags &= ~IFF_OACTIVE; 1108 1109 return 0; 1110} 1111 1112void 1113nfe_stop(struct ifnet *ifp, int disable) 1114{ 1115 struct nfe_softc *sc = ifp->if_softc; 1116 1117 timeout_del(&sc->sc_tick_ch); 1118 1119 ifp->if_timer = 0; 1120 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1121 1122 mii_down(&sc->sc_mii); 1123 1124 /* abort Tx */ 1125 NFE_WRITE(sc, NFE_TX_CTL, 0); 1126 1127 /* disable Rx */ 1128 NFE_WRITE(sc, NFE_RX_CTL, 0); 1129 1130 /* disable interrupts */ 1131 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1132 1133 /* reset Tx and Rx rings */ 1134 nfe_reset_tx_ring(sc, &sc->txq); 1135 nfe_reset_rx_ring(sc, &sc->rxq); 1136} 1137 1138int 1139nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1140{ 1141 struct nfe_desc32 *desc32; 1142 struct nfe_desc64 *desc64; 1143 struct nfe_rx_data *data; 1144 struct nfe_jbuf *jbuf; 1145 void **desc; 1146 bus_addr_t physaddr; 1147 int i, nsegs, error, descsize; 1148 1149 if (sc->sc_flags & NFE_40BIT_ADDR) { 1150 desc = (void **)&ring->desc64; 1151 descsize = sizeof (struct nfe_desc64); 1152 } else { 1153 desc = (void **)&ring->desc32; 1154 descsize = sizeof (struct nfe_desc32); 1155 } 1156 1157 ring->cur = ring->next = 0; 1158 ring->bufsz = MCLBYTES; 1159 1160 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1161 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1162 if (error != 0) { 1163 printf("%s: could not create desc DMA map\n", 1164 sc->sc_dev.dv_xname); 1165 goto fail; 1166 } 1167 1168 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1169 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1170 if (error != 0) { 1171 printf("%s: could not allocate DMA memory\n", 1172 sc->sc_dev.dv_xname); 1173 goto fail; 1174 } 1175 1176 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1177 NFE_RX_RING_COUNT * descsize, (caddr_t *)desc, BUS_DMA_NOWAIT); 1178 if (error != 0) { 1179 printf("%s: could not map desc DMA memory\n", 1180 sc->sc_dev.dv_xname); 1181 goto fail; 1182 } 1183 1184 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1185 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1186 if (error != 0) { 1187 printf("%s: could not load desc DMA map\n", 1188 sc->sc_dev.dv_xname); 1189 goto fail; 1190 } 1191 1192 bzero(*desc, NFE_RX_RING_COUNT * descsize); 1193 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1194 1195 if (sc->sc_flags & NFE_USE_JUMBO) { 1196 ring->bufsz = NFE_JBYTES; 1197 if ((error = nfe_jpool_alloc(sc)) != 0) { 1198 printf("%s: could not allocate jumbo frames\n", 1199 sc->sc_dev.dv_xname); 1200 goto fail; 1201 } 1202 } 1203 1204 /* 1205 * Pre-allocate Rx buffers and populate Rx ring. 1206 */ 1207 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1208 data = &sc->rxq.data[i]; 1209 1210 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1211 if (data->m == NULL) { 1212 printf("%s: could not allocate rx mbuf\n", 1213 sc->sc_dev.dv_xname); 1214 error = ENOMEM; 1215 goto fail; 1216 } 1217 1218 if (sc->sc_flags & NFE_USE_JUMBO) { 1219 if ((jbuf = nfe_jalloc(sc)) == NULL) { 1220 printf("%s: could not allocate jumbo buffer\n", 1221 sc->sc_dev.dv_xname); 1222 goto fail; 1223 } 1224 MEXTADD(data->m, jbuf->buf, NFE_JBYTES, 0, nfe_jfree, 1225 sc); 1226 1227 physaddr = jbuf->physaddr; 1228 } else { 1229 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1230 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1231 if (error != 0) { 1232 printf("%s: could not create DMA map\n", 1233 sc->sc_dev.dv_xname); 1234 goto fail; 1235 } 1236 MCLGET(data->m, M_DONTWAIT); 1237 if (!(data->m->m_flags & M_EXT)) { 1238 printf("%s: could not allocate mbuf cluster\n", 1239 sc->sc_dev.dv_xname); 1240 error = ENOMEM; 1241 goto fail; 1242 } 1243 1244 error = bus_dmamap_load(sc->sc_dmat, data->map, 1245 mtod(data->m, void *), MCLBYTES, NULL, 1246 BUS_DMA_READ | BUS_DMA_NOWAIT); 1247 if (error != 0) { 1248 printf("%s: could not load rx buf DMA map", 1249 sc->sc_dev.dv_xname); 1250 goto fail; 1251 } 1252 physaddr = data->map->dm_segs[0].ds_addr; 1253 } 1254 1255 if (sc->sc_flags & NFE_40BIT_ADDR) { 1256 desc64 = &sc->rxq.desc64[i]; 1257#if defined(__LP64__) 1258 desc64->physaddr[0] = htole32(physaddr >> 32); 1259#endif 1260 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1261 desc64->length = htole16(sc->rxq.bufsz); 1262 desc64->flags = htole16(NFE_RX_READY); 1263 } else { 1264 desc32 = &sc->rxq.desc32[i]; 1265 desc32->physaddr = htole32(physaddr); 1266 desc32->length = htole16(sc->rxq.bufsz); 1267 desc32->flags = htole16(NFE_RX_READY); 1268 } 1269 } 1270 1271 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1272 BUS_DMASYNC_PREWRITE); 1273 1274 return 0; 1275 1276fail: nfe_free_rx_ring(sc, ring); 1277 return error; 1278} 1279 1280void 1281nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1282{ 1283 int i; 1284 1285 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1286 if (sc->sc_flags & NFE_40BIT_ADDR) { 1287 ring->desc64[i].length = htole16(ring->bufsz); 1288 ring->desc64[i].flags = htole16(NFE_RX_READY); 1289 } else { 1290 ring->desc32[i].length = htole16(ring->bufsz); 1291 ring->desc32[i].flags = htole16(NFE_RX_READY); 1292 } 1293 } 1294 1295 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1296 BUS_DMASYNC_PREWRITE); 1297 1298 ring->cur = ring->next = 0; 1299} 1300 1301void 1302nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1303{ 1304 struct nfe_rx_data *data; 1305 void *desc; 1306 int i, descsize; 1307 1308 if (sc->sc_flags & NFE_40BIT_ADDR) { 1309 desc = ring->desc64; 1310 descsize = sizeof (struct nfe_desc64); 1311 } else { 1312 desc = ring->desc32; 1313 descsize = sizeof (struct nfe_desc32); 1314 } 1315 1316 if (desc != NULL) { 1317 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1318 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1319 bus_dmamap_unload(sc->sc_dmat, ring->map); 1320 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)desc, 1321 NFE_RX_RING_COUNT * descsize); 1322 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1323 } 1324 1325 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1326 data = &ring->data[i]; 1327 1328 if (data->m != NULL) { 1329 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1330 data->map->dm_mapsize, 1331 BUS_DMASYNC_POSTREAD); 1332 bus_dmamap_unload(sc->sc_dmat, data->map); 1333 m_freem(data->m); 1334 } 1335 1336 if (data->map != NULL) 1337 bus_dmamap_destroy(sc->sc_dmat, data->map); 1338 } 1339} 1340 1341struct nfe_jbuf * 1342nfe_jalloc(struct nfe_softc *sc) 1343{ 1344 struct nfe_jbuf *jbuf; 1345 1346 jbuf = SLIST_FIRST(&sc->rxq.jfreelist); 1347 if (jbuf == NULL) 1348 return NULL; 1349 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext); 1350 return jbuf; 1351} 1352 1353/* 1354 * This is called automatically by the network stack when the mbuf is freed. 1355 * Caution must be taken that the NIC might be reset by the time the mbuf is 1356 * freed. 1357 */ 1358void 1359nfe_jfree(caddr_t buf, u_int size, void *arg) 1360{ 1361 struct nfe_softc *sc = arg; 1362 struct nfe_jbuf *jbuf; 1363 int i; 1364 1365 /* find the jbuf from the base pointer */ 1366 i = (buf - sc->rxq.jpool) / NFE_JBYTES; 1367 if (i < 0 || i >= NFE_JPOOL_COUNT) { 1368 printf("%s: request to free a buffer (%p) not managed by us\n", 1369 buf, sc->sc_dev.dv_xname); 1370 return; 1371 } 1372 jbuf = &sc->rxq.jbuf[i]; 1373 1374 /* ..and put it back in the free list */ 1375 SLIST_INSERT_HEAD(&sc->rxq.jfreelist, jbuf, jnext); 1376} 1377 1378int 1379nfe_jpool_alloc(struct nfe_softc *sc) 1380{ 1381 struct nfe_rx_ring *ring = &sc->rxq; 1382 struct nfe_jbuf *jbuf; 1383 bus_addr_t physaddr; 1384 caddr_t buf; 1385 int i, nsegs, error; 1386 1387 /* 1388 * Allocate a big chunk of DMA'able memory. 1389 */ 1390 error = bus_dmamap_create(sc->sc_dmat, NFE_JPOOL_SIZE, 1, 1391 NFE_JPOOL_SIZE, 0, BUS_DMA_NOWAIT, &ring->jmap); 1392 if (error != 0) { 1393 printf("%s: could not create jumbo DMA map\n", 1394 sc->sc_dev.dv_xname); 1395 goto fail; 1396 } 1397 1398 error = bus_dmamem_alloc(sc->sc_dmat, NFE_JPOOL_SIZE, PAGE_SIZE, 0, 1399 &ring->jseg, 1, &nsegs, BUS_DMA_NOWAIT); 1400 if (error != 0) { 1401 printf("%s could not allocate jumbo DMA memory\n", 1402 sc->sc_dev.dv_xname); 1403 goto fail; 1404 } 1405 1406 error = bus_dmamem_map(sc->sc_dmat, &ring->jseg, nsegs, NFE_JPOOL_SIZE, 1407 &ring->jpool, BUS_DMA_NOWAIT); 1408 if (error != 0) { 1409 printf("%s: could not map jumbo DMA memory\n", 1410 sc->sc_dev.dv_xname); 1411 goto fail; 1412 } 1413 1414 error = bus_dmamap_load(sc->sc_dmat, ring->jmap, ring->jpool, 1415 NFE_JPOOL_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1416 if (error != 0) { 1417 printf("%s: could not load jumbo DMA map\n", 1418 sc->sc_dev.dv_xname); 1419 goto fail; 1420 } 1421 1422 /* ..and split it into 9KB chunks */ 1423 SLIST_INIT(&ring->jfreelist); 1424 1425 buf = ring->jpool; 1426 physaddr = ring->jmap->dm_segs[0].ds_addr; 1427 for (i = 0; i < NFE_JPOOL_COUNT; i++) { 1428 jbuf = &ring->jbuf[i]; 1429 1430 jbuf->buf = buf; 1431 jbuf->physaddr = physaddr; 1432 1433 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext); 1434 1435 buf += NFE_JBYTES; 1436 physaddr += NFE_JBYTES; 1437 } 1438 1439 return 0; 1440 1441fail: nfe_jpool_free(sc); 1442 return error; 1443} 1444 1445void 1446nfe_jpool_free(struct nfe_softc *sc) 1447{ 1448 struct nfe_rx_ring *ring = &sc->rxq; 1449 1450 if (ring->jmap != NULL) { 1451 bus_dmamap_sync(sc->sc_dmat, ring->jmap, 0, 1452 ring->jmap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1453 bus_dmamap_unload(sc->sc_dmat, ring->jmap); 1454 bus_dmamap_destroy(sc->sc_dmat, ring->jmap); 1455 } 1456 if (ring->jpool != NULL) { 1457 bus_dmamem_unmap(sc->sc_dmat, ring->jpool, NFE_JPOOL_SIZE); 1458 bus_dmamem_free(sc->sc_dmat, &ring->jseg, 1); 1459 } 1460} 1461 1462int 1463nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1464{ 1465 int i, nsegs, error; 1466 void **desc; 1467 int descsize; 1468 1469 if (sc->sc_flags & NFE_40BIT_ADDR) { 1470 desc = (void **)&ring->desc64; 1471 descsize = sizeof (struct nfe_desc64); 1472 } else { 1473 desc = (void **)&ring->desc32; 1474 descsize = sizeof (struct nfe_desc32); 1475 } 1476 1477 ring->queued = 0; 1478 ring->cur = ring->next = 0; 1479 1480 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1481 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1482 1483 if (error != 0) { 1484 printf("%s: could not create desc DMA map\n", 1485 sc->sc_dev.dv_xname); 1486 goto fail; 1487 } 1488 1489 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1490 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 1491 if (error != 0) { 1492 printf("%s: could not allocate DMA memory\n", 1493 sc->sc_dev.dv_xname); 1494 goto fail; 1495 } 1496 1497 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1498 NFE_TX_RING_COUNT * descsize, (caddr_t *)desc, BUS_DMA_NOWAIT); 1499 if (error != 0) { 1500 printf("%s: could not map desc DMA memory\n", 1501 sc->sc_dev.dv_xname); 1502 goto fail; 1503 } 1504 1505 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1506 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1507 if (error != 0) { 1508 printf("%s: could not load desc DMA map\n", 1509 sc->sc_dev.dv_xname); 1510 goto fail; 1511 } 1512 1513 bzero(*desc, NFE_TX_RING_COUNT * descsize); 1514 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1515 1516 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1517 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1518 NFE_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 1519 &ring->data[i].map); 1520 if (error != 0) { 1521 printf("%s: could not create DMA map\n", 1522 sc->sc_dev.dv_xname); 1523 goto fail; 1524 } 1525 } 1526 1527 return 0; 1528 1529fail: nfe_free_tx_ring(sc, ring); 1530 return error; 1531} 1532 1533void 1534nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1535{ 1536 struct nfe_tx_data *data; 1537 int i; 1538 1539 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1540 if (sc->sc_flags & NFE_40BIT_ADDR) 1541 ring->desc64[i].flags = 0; 1542 else 1543 ring->desc32[i].flags = 0; 1544 1545 data = &ring->data[i]; 1546 1547 if (data->m != NULL) { 1548 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1549 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1550 bus_dmamap_unload(sc->sc_dmat, data->active); 1551 m_freem(data->m); 1552 data->m = NULL; 1553 } 1554 } 1555 1556 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1557 BUS_DMASYNC_PREWRITE); 1558 1559 ring->queued = 0; 1560 ring->cur = ring->next = 0; 1561} 1562 1563void 1564nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1565{ 1566 struct nfe_tx_data *data; 1567 void *desc; 1568 int i, descsize; 1569 1570 if (sc->sc_flags & NFE_40BIT_ADDR) { 1571 desc = ring->desc64; 1572 descsize = sizeof (struct nfe_desc64); 1573 } else { 1574 desc = ring->desc32; 1575 descsize = sizeof (struct nfe_desc32); 1576 } 1577 1578 if (desc != NULL) { 1579 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1580 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1581 bus_dmamap_unload(sc->sc_dmat, ring->map); 1582 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)desc, 1583 NFE_TX_RING_COUNT * descsize); 1584 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1585 } 1586 1587 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1588 data = &ring->data[i]; 1589 1590 if (data->m != NULL) { 1591 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1592 data->active->dm_mapsize, 1593 BUS_DMASYNC_POSTWRITE); 1594 bus_dmamap_unload(sc->sc_dmat, data->active); 1595 m_freem(data->m); 1596 } 1597 } 1598 1599 /* ..and now actually destroy the DMA mappings */ 1600 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1601 data = &ring->data[i]; 1602 if (data->map == NULL) 1603 continue; 1604 bus_dmamap_destroy(sc->sc_dmat, data->map); 1605 } 1606} 1607 1608int 1609nfe_ifmedia_upd(struct ifnet *ifp) 1610{ 1611 struct nfe_softc *sc = ifp->if_softc; 1612 struct mii_data *mii = &sc->sc_mii; 1613 struct mii_softc *miisc; 1614 1615 if (mii->mii_instance != 0) { 1616 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1617 mii_phy_reset(miisc); 1618 } 1619 return mii_mediachg(mii); 1620} 1621 1622void 1623nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1624{ 1625 struct nfe_softc *sc = ifp->if_softc; 1626 struct mii_data *mii = &sc->sc_mii; 1627 1628 mii_pollstat(mii); 1629 ifmr->ifm_status = mii->mii_media_status; 1630 ifmr->ifm_active = mii->mii_media_active; 1631} 1632 1633void 1634nfe_setmulti(struct nfe_softc *sc) 1635{ 1636 struct arpcom *ac = &sc->sc_arpcom; 1637 struct ifnet *ifp = &ac->ac_if; 1638 struct ether_multi *enm; 1639 struct ether_multistep step; 1640 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1641 uint32_t filter = NFE_RXFILTER_MAGIC; 1642 int i; 1643 1644 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1645 bzero(addr, ETHER_ADDR_LEN); 1646 bzero(mask, ETHER_ADDR_LEN); 1647 goto done; 1648 } 1649 1650 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1651 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1652 1653 ETHER_FIRST_MULTI(step, ac, enm); 1654 while (enm != NULL) { 1655 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1656 ifp->if_flags |= IFF_ALLMULTI; 1657 bzero(addr, ETHER_ADDR_LEN); 1658 bzero(mask, ETHER_ADDR_LEN); 1659 goto done; 1660 } 1661 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1662 addr[i] &= enm->enm_addrlo[i]; 1663 mask[i] &= ~enm->enm_addrlo[i]; 1664 } 1665 ETHER_NEXT_MULTI(step, enm); 1666 } 1667 for (i = 0; i < ETHER_ADDR_LEN; i++) 1668 mask[i] |= addr[i]; 1669 1670done: 1671 addr[0] |= 0x01; /* make sure multicast bit is set */ 1672 1673 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1674 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1675 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1676 addr[5] << 8 | addr[4]); 1677 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1678 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1679 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1680 mask[5] << 8 | mask[4]); 1681 1682 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M; 1683 NFE_WRITE(sc, NFE_RXFILTER, filter); 1684} 1685 1686void 1687nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1688{ 1689 uint32_t tmp; 1690 1691 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1692 addr[0] = (tmp >> 8) & 0xff; 1693 addr[1] = (tmp & 0xff); 1694 1695 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1696 addr[2] = (tmp >> 24) & 0xff; 1697 addr[3] = (tmp >> 16) & 0xff; 1698 addr[4] = (tmp >> 8) & 0xff; 1699 addr[5] = (tmp & 0xff); 1700} 1701 1702void 1703nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1704{ 1705 NFE_WRITE(sc, NFE_MACADDR_LO, 1706 addr[5] << 8 | addr[4]); 1707 NFE_WRITE(sc, NFE_MACADDR_HI, 1708 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1709} 1710 1711void 1712nfe_tick(void *arg) 1713{ 1714 struct nfe_softc *sc = arg; 1715 int s; 1716 1717 s = splnet(); 1718 mii_tick(&sc->sc_mii); 1719 splx(s); 1720 1721 timeout_add(&sc->sc_tick_ch, hz); 1722} 1723