if_nfe.c revision 1.115
1/* $OpenBSD: if_nfe.c,v 1.115 2015/11/24 17:11:39 mpi Exp $ */ 2 3/*- 4 * Copyright (c) 2006, 2007 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 21 22#include "bpfilter.h" 23#include "vlan.h" 24 25#include <sys/param.h> 26#include <sys/endian.h> 27#include <sys/systm.h> 28#include <sys/types.h> 29#include <sys/sockio.h> 30#include <sys/mbuf.h> 31#include <sys/queue.h> 32#include <sys/kernel.h> 33#include <sys/device.h> 34#include <sys/timeout.h> 35#include <sys/socket.h> 36 37#include <machine/bus.h> 38 39#include <net/if.h> 40#include <net/if_media.h> 41 42#include <netinet/in.h> 43#include <netinet/if_ether.h> 44 45#if NBPFILTER > 0 46#include <net/bpf.h> 47#endif 48 49#include <dev/mii/miivar.h> 50 51#include <dev/pci/pcireg.h> 52#include <dev/pci/pcivar.h> 53#include <dev/pci/pcidevs.h> 54 55#include <dev/pci/if_nfereg.h> 56#include <dev/pci/if_nfevar.h> 57 58int nfe_match(struct device *, void *, void *); 59void nfe_attach(struct device *, struct device *, void *); 60int nfe_activate(struct device *, int); 61void nfe_miibus_statchg(struct device *); 62int nfe_miibus_readreg(struct device *, int, int); 63void nfe_miibus_writereg(struct device *, int, int, int); 64int nfe_intr(void *); 65int nfe_ioctl(struct ifnet *, u_long, caddr_t); 66void nfe_txdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 67void nfe_txdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 68void nfe_txdesc32_rsync(struct nfe_softc *, int, int, int); 69void nfe_txdesc64_rsync(struct nfe_softc *, int, int, int); 70void nfe_rxdesc32_sync(struct nfe_softc *, struct nfe_desc32 *, int); 71void nfe_rxdesc64_sync(struct nfe_softc *, struct nfe_desc64 *, int); 72void nfe_rxeof(struct nfe_softc *); 73void nfe_txeof(struct nfe_softc *); 74int nfe_encap(struct nfe_softc *, struct mbuf *); 75void nfe_start(struct ifnet *); 76void nfe_watchdog(struct ifnet *); 77int nfe_init(struct ifnet *); 78void nfe_stop(struct ifnet *, int); 79int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 80void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 81void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 82int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 83void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 84void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 85int nfe_ifmedia_upd(struct ifnet *); 86void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 87void nfe_iff(struct nfe_softc *); 88void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 89void nfe_set_macaddr(struct nfe_softc *, const uint8_t *); 90void nfe_tick(void *); 91#ifndef SMALL_KERNEL 92int nfe_wol(struct ifnet*, int); 93#endif 94 95struct cfattach nfe_ca = { 96 sizeof (struct nfe_softc), nfe_match, nfe_attach, NULL, 97 nfe_activate 98}; 99 100struct cfdriver nfe_cd = { 101 NULL, "nfe", DV_IFNET 102}; 103 104#ifdef NFE_DEBUG 105int nfedebug = 0; 106#define DPRINTF(x) do { if (nfedebug) printf x; } while (0) 107#define DPRINTFN(n,x) do { if (nfedebug >= (n)) printf x; } while (0) 108#else 109#define DPRINTF(x) 110#define DPRINTFN(n,x) 111#endif 112 113const struct pci_matchid nfe_devices[] = { 114 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN }, 115 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN }, 116 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 }, 117 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 }, 118 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 }, 119 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 }, 120 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 }, 121 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1 }, 122 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2 }, 123 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1 }, 124 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2 }, 125 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1 }, 126 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2 }, 127 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1 }, 128 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2 }, 129 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1 }, 130 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2 }, 131 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3 }, 132 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4 }, 133 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1 }, 134 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2 }, 135 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3 }, 136 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4 }, 137 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1 }, 138 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2 }, 139 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3 }, 140 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4 }, 141 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1 }, 142 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2 }, 143 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3 }, 144 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4 }, 145 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1 }, 146 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2 }, 147 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3 }, 148 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4 }, 149 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1 }, 150 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2 }, 151 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3 }, 152 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4 }, 153 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP89_LAN } 154}; 155 156int 157nfe_match(struct device *dev, void *match, void *aux) 158{ 159 return pci_matchbyid((struct pci_attach_args *)aux, nfe_devices, 160 sizeof (nfe_devices) / sizeof (nfe_devices[0])); 161} 162 163int 164nfe_activate(struct device *self, int act) 165{ 166 struct nfe_softc *sc = (struct nfe_softc *)self; 167 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 168 int rv = 0; 169 170 switch (act) { 171 case DVACT_SUSPEND: 172 if (ifp->if_flags & IFF_RUNNING) 173 nfe_stop(ifp, 0); 174 rv = config_activate_children(self, act); 175 break; 176 case DVACT_RESUME: 177 if (ifp->if_flags & IFF_UP) 178 nfe_init(ifp); 179 break; 180 default: 181 rv = config_activate_children(self, act); 182 break; 183 } 184 return (rv); 185} 186 187 188void 189nfe_attach(struct device *parent, struct device *self, void *aux) 190{ 191 struct nfe_softc *sc = (struct nfe_softc *)self; 192 struct pci_attach_args *pa = aux; 193 pci_chipset_tag_t pc = pa->pa_pc; 194 pci_intr_handle_t ih; 195 const char *intrstr; 196 struct ifnet *ifp; 197 bus_size_t memsize; 198 pcireg_t memtype; 199 200 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NFE_PCI_BA); 201 if (pci_mapreg_map(pa, NFE_PCI_BA, memtype, 0, &sc->sc_memt, 202 &sc->sc_memh, NULL, &memsize, 0)) { 203 printf(": can't map mem space\n"); 204 return; 205 } 206 207 if (pci_intr_map(pa, &ih) != 0) { 208 printf(": can't map interrupt\n"); 209 return; 210 } 211 212 intrstr = pci_intr_string(pc, ih); 213 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nfe_intr, sc, 214 sc->sc_dev.dv_xname); 215 if (sc->sc_ih == NULL) { 216 printf(": could not establish interrupt"); 217 if (intrstr != NULL) 218 printf(" at %s", intrstr); 219 printf("\n"); 220 return; 221 } 222 printf(": %s", intrstr); 223 224 sc->sc_dmat = pa->pa_dmat; 225 sc->sc_flags = 0; 226 227 switch (PCI_PRODUCT(pa->pa_id)) { 228 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 229 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 230 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 231 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 232 sc->sc_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 233 break; 234 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 235 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 236 sc->sc_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 237 break; 238 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 239 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 240 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 241 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 242 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 243 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 244 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 245 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 246 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 247 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 248 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 249 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 250 sc->sc_flags |= NFE_40BIT_ADDR | NFE_CORRECT_MACADDR | 251 NFE_PWR_MGMT; 252 break; 253 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 254 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 255 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 256 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 257 sc->sc_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | 258 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 259 break; 260 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 261 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 262 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 263 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 264 case PCI_PRODUCT_NVIDIA_MCP89_LAN: 265 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 266 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 267 break; 268 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 269 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 270 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 271 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 272 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 273 break; 274 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 275 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 276 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 277 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 278 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 279 NFE_CORRECT_MACADDR | NFE_PWR_MGMT; 280 break; 281 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 282 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 283 sc->sc_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 284 NFE_HW_VLAN | NFE_PWR_MGMT; 285 break; 286 } 287 288 if (sc->sc_flags & NFE_PWR_MGMT) { 289 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 290 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 291 DELAY(100); 292 NFE_WRITE(sc, NFE_MAC_RESET, 0); 293 DELAY(100); 294 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 295 NFE_WRITE(sc, NFE_PWR2_CTL, 296 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_WAKEUP_MASK); 297 } 298 299 nfe_get_macaddr(sc, sc->sc_arpcom.ac_enaddr); 300 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 301 302 /* 303 * Allocate Tx and Rx rings. 304 */ 305 if (nfe_alloc_tx_ring(sc, &sc->txq) != 0) { 306 printf("%s: could not allocate Tx ring\n", 307 sc->sc_dev.dv_xname); 308 return; 309 } 310 311 if (nfe_alloc_rx_ring(sc, &sc->rxq) != 0) { 312 printf("%s: could not allocate Rx ring\n", 313 sc->sc_dev.dv_xname); 314 nfe_free_tx_ring(sc, &sc->txq); 315 return; 316 } 317 318 ifp = &sc->sc_arpcom.ac_if; 319 ifp->if_softc = sc; 320 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 321 ifp->if_ioctl = nfe_ioctl; 322 ifp->if_start = nfe_start; 323 ifp->if_watchdog = nfe_watchdog; 324 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_IFQ_MAXLEN); 325 IFQ_SET_READY(&ifp->if_snd); 326 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 327 328 ifp->if_capabilities = IFCAP_VLAN_MTU; 329 330#ifndef SMALL_KERNEL 331 ifp->if_capabilities |= IFCAP_WOL; 332 ifp->if_wol = nfe_wol; 333 nfe_wol(ifp, 0); 334#endif 335 336#if NVLAN > 0 337 if (sc->sc_flags & NFE_HW_VLAN) 338 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 339#endif 340 341 if (sc->sc_flags & NFE_HW_CSUM) { 342 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 343 IFCAP_CSUM_UDPv4; 344 } 345 346 sc->sc_mii.mii_ifp = ifp; 347 sc->sc_mii.mii_readreg = nfe_miibus_readreg; 348 sc->sc_mii.mii_writereg = nfe_miibus_writereg; 349 sc->sc_mii.mii_statchg = nfe_miibus_statchg; 350 351 ifmedia_init(&sc->sc_mii.mii_media, 0, nfe_ifmedia_upd, 352 nfe_ifmedia_sts); 353 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 0, 0); 354 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 355 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 356 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL, 357 0, NULL); 358 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL); 359 } else 360 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 361 362 if_attach(ifp); 363 ether_ifattach(ifp); 364 365 timeout_set(&sc->sc_tick_ch, nfe_tick, sc); 366} 367 368void 369nfe_miibus_statchg(struct device *dev) 370{ 371 struct nfe_softc *sc = (struct nfe_softc *)dev; 372 struct mii_data *mii = &sc->sc_mii; 373 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 374 375 phy = NFE_READ(sc, NFE_PHY_IFACE); 376 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 377 378 seed = NFE_READ(sc, NFE_RNDSEED); 379 seed &= ~NFE_SEED_MASK; 380 381 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 382 phy |= NFE_PHY_HDX; /* half-duplex */ 383 misc |= NFE_MISC1_HDX; 384 } 385 386 switch (IFM_SUBTYPE(mii->mii_media_active)) { 387 case IFM_1000_T: /* full-duplex only */ 388 link |= NFE_MEDIA_1000T; 389 seed |= NFE_SEED_1000T; 390 phy |= NFE_PHY_1000T; 391 break; 392 case IFM_100_TX: 393 link |= NFE_MEDIA_100TX; 394 seed |= NFE_SEED_100TX; 395 phy |= NFE_PHY_100TX; 396 break; 397 case IFM_10_T: 398 link |= NFE_MEDIA_10T; 399 seed |= NFE_SEED_10T; 400 break; 401 } 402 403 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 404 405 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 406 NFE_WRITE(sc, NFE_MISC1, misc); 407 NFE_WRITE(sc, NFE_LINKSPEED, link); 408} 409 410int 411nfe_miibus_readreg(struct device *dev, int phy, int reg) 412{ 413 struct nfe_softc *sc = (struct nfe_softc *)dev; 414 uint32_t val; 415 int ntries; 416 417 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 418 419 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 420 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 421 DELAY(100); 422 } 423 424 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 425 426 for (ntries = 0; ntries < 1000; ntries++) { 427 DELAY(100); 428 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 429 break; 430 } 431 if (ntries == 1000) { 432 DPRINTFN(2, ("%s: timeout waiting for PHY\n", 433 sc->sc_dev.dv_xname)); 434 return 0; 435 } 436 437 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 438 DPRINTFN(2, ("%s: could not read PHY\n", 439 sc->sc_dev.dv_xname)); 440 return 0; 441 } 442 443 val = NFE_READ(sc, NFE_PHY_DATA); 444 if (val != 0xffffffff && val != 0) 445 sc->mii_phyaddr = phy; 446 447 DPRINTFN(2, ("%s: mii read phy %d reg 0x%x ret 0x%x\n", 448 sc->sc_dev.dv_xname, phy, reg, val)); 449 450 return val; 451} 452 453void 454nfe_miibus_writereg(struct device *dev, int phy, int reg, int val) 455{ 456 struct nfe_softc *sc = (struct nfe_softc *)dev; 457 uint32_t ctl; 458 int ntries; 459 460 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 461 462 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 463 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 464 DELAY(100); 465 } 466 467 NFE_WRITE(sc, NFE_PHY_DATA, val); 468 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 469 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 470 471 for (ntries = 0; ntries < 1000; ntries++) { 472 DELAY(100); 473 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 474 break; 475 } 476#ifdef NFE_DEBUG 477 if (nfedebug >= 2 && ntries == 1000) 478 printf("could not write to PHY\n"); 479#endif 480} 481 482int 483nfe_intr(void *arg) 484{ 485 struct nfe_softc *sc = arg; 486 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 487 uint32_t r; 488 489 if ((r = NFE_READ(sc, NFE_IRQ_STATUS) & NFE_IRQ_WANTED) == 0) 490 return 0; /* not for us */ 491 NFE_WRITE(sc, NFE_IRQ_STATUS, r); 492 493 DPRINTFN(5, ("nfe_intr: interrupt register %x\n", r)); 494 495 if (r & NFE_IRQ_LINK) { 496 NFE_READ(sc, NFE_PHY_STATUS); 497 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 498 DPRINTF(("%s: link state changed\n", sc->sc_dev.dv_xname)); 499 } 500 501 if (ifp->if_flags & IFF_RUNNING) { 502 /* check Rx ring */ 503 nfe_rxeof(sc); 504 505 /* check Tx ring */ 506 nfe_txeof(sc); 507 } 508 509 return 1; 510} 511 512int 513nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 514{ 515 struct nfe_softc *sc = ifp->if_softc; 516 struct ifreq *ifr = (struct ifreq *)data; 517 int s, error = 0; 518 519 s = splnet(); 520 521 switch (cmd) { 522 case SIOCSIFADDR: 523 ifp->if_flags |= IFF_UP; 524 if (!(ifp->if_flags & IFF_RUNNING)) 525 nfe_init(ifp); 526 break; 527 528 case SIOCSIFFLAGS: 529 if (ifp->if_flags & IFF_UP) { 530 if (ifp->if_flags & IFF_RUNNING) 531 error = ENETRESET; 532 else 533 nfe_init(ifp); 534 } else { 535 if (ifp->if_flags & IFF_RUNNING) 536 nfe_stop(ifp, 1); 537 } 538 break; 539 540 case SIOCSIFMEDIA: 541 case SIOCGIFMEDIA: 542 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 543 break; 544 545 default: 546 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 547 } 548 549 if (error == ENETRESET) { 550 if (ifp->if_flags & IFF_RUNNING) 551 nfe_iff(sc); 552 error = 0; 553 } 554 555 splx(s); 556 return error; 557} 558 559void 560nfe_txdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 561{ 562 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 563 (caddr_t)desc32 - (caddr_t)sc->txq.desc32, 564 sizeof (struct nfe_desc32), ops); 565} 566 567void 568nfe_txdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 569{ 570 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 571 (caddr_t)desc64 - (caddr_t)sc->txq.desc64, 572 sizeof (struct nfe_desc64), ops); 573} 574 575void 576nfe_txdesc32_rsync(struct nfe_softc *sc, int start, int end, int ops) 577{ 578 if (end > start) { 579 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 580 (caddr_t)&sc->txq.desc32[start] - (caddr_t)sc->txq.desc32, 581 (caddr_t)&sc->txq.desc32[end] - 582 (caddr_t)&sc->txq.desc32[start], ops); 583 return; 584 } 585 /* sync from 'start' to end of ring */ 586 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 587 (caddr_t)&sc->txq.desc32[start] - (caddr_t)sc->txq.desc32, 588 (caddr_t)&sc->txq.desc32[NFE_TX_RING_COUNT] - 589 (caddr_t)&sc->txq.desc32[start], ops); 590 591 /* sync from start of ring to 'end' */ 592 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 593 (caddr_t)&sc->txq.desc32[end] - (caddr_t)sc->txq.desc32, ops); 594} 595 596void 597nfe_txdesc64_rsync(struct nfe_softc *sc, int start, int end, int ops) 598{ 599 if (end > start) { 600 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 601 (caddr_t)&sc->txq.desc64[start] - (caddr_t)sc->txq.desc64, 602 (caddr_t)&sc->txq.desc64[end] - 603 (caddr_t)&sc->txq.desc64[start], ops); 604 return; 605 } 606 /* sync from 'start' to end of ring */ 607 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 608 (caddr_t)&sc->txq.desc64[start] - (caddr_t)sc->txq.desc64, 609 (caddr_t)&sc->txq.desc64[NFE_TX_RING_COUNT] - 610 (caddr_t)&sc->txq.desc64[start], ops); 611 612 /* sync from start of ring to 'end' */ 613 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 0, 614 (caddr_t)&sc->txq.desc64[end] - (caddr_t)sc->txq.desc64, ops); 615} 616 617void 618nfe_rxdesc32_sync(struct nfe_softc *sc, struct nfe_desc32 *desc32, int ops) 619{ 620 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 621 (caddr_t)desc32 - (caddr_t)sc->rxq.desc32, 622 sizeof (struct nfe_desc32), ops); 623} 624 625void 626nfe_rxdesc64_sync(struct nfe_softc *sc, struct nfe_desc64 *desc64, int ops) 627{ 628 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 629 (caddr_t)desc64 - (caddr_t)sc->rxq.desc64, 630 sizeof (struct nfe_desc64), ops); 631} 632 633void 634nfe_rxeof(struct nfe_softc *sc) 635{ 636 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 637 struct nfe_desc32 *desc32; 638 struct nfe_desc64 *desc64; 639 struct nfe_rx_data *data; 640 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 641 struct mbuf *m, *mnew; 642 bus_addr_t physaddr; 643#if NVLAN > 0 644 uint32_t vtag; 645#endif 646 uint16_t flags; 647 int error, len; 648 649 for (;;) { 650 data = &sc->rxq.data[sc->rxq.cur]; 651 652 if (sc->sc_flags & NFE_40BIT_ADDR) { 653 desc64 = &sc->rxq.desc64[sc->rxq.cur]; 654 nfe_rxdesc64_sync(sc, desc64, BUS_DMASYNC_POSTREAD); 655 656 flags = letoh16(desc64->flags); 657 len = letoh16(desc64->length) & 0x3fff; 658#if NVLAN > 0 659 vtag = letoh32(desc64->physaddr[1]); 660#endif 661 } else { 662 desc32 = &sc->rxq.desc32[sc->rxq.cur]; 663 nfe_rxdesc32_sync(sc, desc32, BUS_DMASYNC_POSTREAD); 664 665 flags = letoh16(desc32->flags); 666 len = letoh16(desc32->length) & 0x3fff; 667 } 668 669 if (flags & NFE_RX_READY) 670 break; 671 672 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 673 if (!(flags & NFE_RX_VALID_V1)) 674 goto skip; 675 676 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 677 flags &= ~NFE_RX_ERROR; 678 len--; /* fix buffer length */ 679 } 680 } else { 681 if (!(flags & NFE_RX_VALID_V2)) 682 goto skip; 683 684 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 685 flags &= ~NFE_RX_ERROR; 686 len--; /* fix buffer length */ 687 } 688 } 689 690 if (flags & NFE_RX_ERROR) { 691 ifp->if_ierrors++; 692 goto skip; 693 } 694 695 /* 696 * Try to allocate a new mbuf for this ring element and load 697 * it before processing the current mbuf. If the ring element 698 * cannot be loaded, drop the received packet and reuse the 699 * old mbuf. In the unlikely case that the old mbuf can't be 700 * reloaded either, explicitly panic. 701 */ 702 mnew = MCLGETI(NULL, MCLBYTES, NULL, M_DONTWAIT); 703 if (mnew == NULL) { 704 ifp->if_ierrors++; 705 goto skip; 706 } 707 mnew->m_pkthdr.len = mnew->m_len = MCLBYTES; 708 709 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 710 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 711 bus_dmamap_unload(sc->sc_dmat, data->map); 712 713 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, mnew, 714 BUS_DMA_READ | BUS_DMA_NOWAIT); 715 if (error != 0) { 716 m_freem(mnew); 717 718 /* try to reload the old mbuf */ 719 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, 720 m, BUS_DMA_READ | BUS_DMA_NOWAIT); 721 if (error != 0) { 722 /* very unlikely that it will fail.. */ 723 panic("%s: could not load old rx mbuf", 724 sc->sc_dev.dv_xname); 725 } 726 ifp->if_ierrors++; 727 goto skip; 728 } 729 physaddr = data->map->dm_segs[0].ds_addr; 730 731 /* 732 * New mbuf successfully loaded, update Rx ring and continue 733 * processing. 734 */ 735 m = data->m; 736 data->m = mnew; 737 738 /* finalize mbuf */ 739 m->m_pkthdr.len = m->m_len = len; 740 741 if ((sc->sc_flags & NFE_HW_CSUM) && 742 (flags & NFE_RX_IP_CSUMOK)) { 743 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 744 if (flags & NFE_RX_UDP_CSUMOK) 745 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 746 if (flags & NFE_RX_TCP_CSUMOK) 747 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 748 } 749 750#if NVLAN > 0 751 if ((vtag & NFE_RX_VTAG) && (sc->sc_flags & NFE_HW_VLAN)) { 752 m->m_pkthdr.ether_vtag = vtag & 0xffff; 753 m->m_flags |= M_VLANTAG; 754 } 755#endif 756 757 ml_enqueue(&ml, m); 758 759 /* update mapping address in h/w descriptor */ 760 if (sc->sc_flags & NFE_40BIT_ADDR) { 761#if defined(__LP64__) 762 desc64->physaddr[0] = htole32(physaddr >> 32); 763#endif 764 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 765 } else { 766 desc32->physaddr = htole32(physaddr); 767 } 768 769skip: if (sc->sc_flags & NFE_40BIT_ADDR) { 770 desc64->length = htole16(sc->rxq.bufsz); 771 desc64->flags = htole16(NFE_RX_READY); 772 773 nfe_rxdesc64_sync(sc, desc64, BUS_DMASYNC_PREWRITE); 774 } else { 775 desc32->length = htole16(sc->rxq.bufsz); 776 desc32->flags = htole16(NFE_RX_READY); 777 778 nfe_rxdesc32_sync(sc, desc32, BUS_DMASYNC_PREWRITE); 779 } 780 781 sc->rxq.cur = (sc->rxq.cur + 1) % NFE_RX_RING_COUNT; 782 } 783 if_input(ifp, &ml); 784} 785 786void 787nfe_txeof(struct nfe_softc *sc) 788{ 789 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 790 struct nfe_desc32 *desc32; 791 struct nfe_desc64 *desc64; 792 struct nfe_tx_data *data = NULL; 793 uint16_t flags; 794 795 while (sc->txq.next != sc->txq.cur) { 796 if (sc->sc_flags & NFE_40BIT_ADDR) { 797 desc64 = &sc->txq.desc64[sc->txq.next]; 798 nfe_txdesc64_sync(sc, desc64, BUS_DMASYNC_POSTREAD); 799 800 flags = letoh16(desc64->flags); 801 } else { 802 desc32 = &sc->txq.desc32[sc->txq.next]; 803 nfe_txdesc32_sync(sc, desc32, BUS_DMASYNC_POSTREAD); 804 805 flags = letoh16(desc32->flags); 806 } 807 808 if (flags & NFE_TX_VALID) 809 break; 810 811 data = &sc->txq.data[sc->txq.next]; 812 813 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 814 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL) 815 goto skip; 816 817 if ((flags & NFE_TX_ERROR_V1) != 0) { 818 printf("%s: tx v1 error %b\n", 819 sc->sc_dev.dv_xname, flags, NFE_V1_TXERR); 820 ifp->if_oerrors++; 821 } else 822 ifp->if_opackets++; 823 } else { 824 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL) 825 goto skip; 826 827 if ((flags & NFE_TX_ERROR_V2) != 0) { 828 printf("%s: tx v2 error %b\n", 829 sc->sc_dev.dv_xname, flags, NFE_V2_TXERR); 830 ifp->if_oerrors++; 831 } else 832 ifp->if_opackets++; 833 } 834 835 if (data->m == NULL) { /* should not get there */ 836 printf("%s: last fragment bit w/o associated mbuf!\n", 837 sc->sc_dev.dv_xname); 838 goto skip; 839 } 840 841 /* last fragment of the mbuf chain transmitted */ 842 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 843 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 844 bus_dmamap_unload(sc->sc_dmat, data->active); 845 m_freem(data->m); 846 data->m = NULL; 847 848 ifp->if_timer = 0; 849 850skip: sc->txq.queued--; 851 sc->txq.next = (sc->txq.next + 1) % NFE_TX_RING_COUNT; 852 } 853 854 if (data != NULL) { /* at least one slot freed */ 855 ifp->if_flags &= ~IFF_OACTIVE; 856 nfe_start(ifp); 857 } 858} 859 860int 861nfe_encap(struct nfe_softc *sc, struct mbuf *m0) 862{ 863 struct nfe_desc32 *desc32; 864 struct nfe_desc64 *desc64; 865 struct nfe_tx_data *data; 866 bus_dmamap_t map; 867 uint16_t flags = 0; 868 uint32_t vtag = 0; 869 int error, i, first = sc->txq.cur; 870 871 map = sc->txq.data[first].map; 872 873 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0, BUS_DMA_NOWAIT); 874 if (error != 0) { 875 printf("%s: can't map mbuf (error %d)\n", 876 sc->sc_dev.dv_xname, error); 877 return error; 878 } 879 880 if (sc->txq.queued + map->dm_nsegs >= NFE_TX_RING_COUNT - 1) { 881 bus_dmamap_unload(sc->sc_dmat, map); 882 return ENOBUFS; 883 } 884 885#if NVLAN > 0 886 /* setup h/w VLAN tagging */ 887 if (m0->m_flags & M_VLANTAG) 888 vtag = NFE_TX_VTAG | m0->m_pkthdr.ether_vtag; 889#endif 890 if (m0->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 891 flags |= NFE_TX_IP_CSUM; 892 if (m0->m_pkthdr.csum_flags & (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT)) 893 flags |= NFE_TX_TCP_UDP_CSUM; 894 895 for (i = 0; i < map->dm_nsegs; i++) { 896 data = &sc->txq.data[sc->txq.cur]; 897 898 if (sc->sc_flags & NFE_40BIT_ADDR) { 899 desc64 = &sc->txq.desc64[sc->txq.cur]; 900#if defined(__LP64__) 901 desc64->physaddr[0] = 902 htole32(map->dm_segs[i].ds_addr >> 32); 903#endif 904 desc64->physaddr[1] = 905 htole32(map->dm_segs[i].ds_addr & 0xffffffff); 906 desc64->length = htole16(map->dm_segs[i].ds_len - 1); 907 desc64->flags = htole16(flags); 908 desc64->vtag = htole32(vtag); 909 } else { 910 desc32 = &sc->txq.desc32[sc->txq.cur]; 911 912 desc32->physaddr = htole32(map->dm_segs[i].ds_addr); 913 desc32->length = htole16(map->dm_segs[i].ds_len - 1); 914 desc32->flags = htole16(flags); 915 } 916 917 if (map->dm_nsegs > 1) { 918 /* 919 * Checksum flags and vtag belong to the first fragment 920 * only. 921 */ 922 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_UDP_CSUM); 923 vtag = 0; 924 925 /* 926 * Setting of the valid bit in the first descriptor is 927 * deferred until the whole chain is fully setup. 928 */ 929 flags |= NFE_TX_VALID; 930 } 931 932 sc->txq.queued++; 933 sc->txq.cur = (sc->txq.cur + 1) % NFE_TX_RING_COUNT; 934 } 935 936 /* the whole mbuf chain has been setup */ 937 if (sc->sc_flags & NFE_40BIT_ADDR) { 938 /* fix last descriptor */ 939 flags |= NFE_TX_LASTFRAG_V2; 940 desc64->flags = htole16(flags); 941 942 /* finally, set the valid bit in the first descriptor */ 943 sc->txq.desc64[first].flags |= htole16(NFE_TX_VALID); 944 } else { 945 /* fix last descriptor */ 946 if (sc->sc_flags & NFE_JUMBO_SUP) 947 flags |= NFE_TX_LASTFRAG_V2; 948 else 949 flags |= NFE_TX_LASTFRAG_V1; 950 desc32->flags = htole16(flags); 951 952 /* finally, set the valid bit in the first descriptor */ 953 sc->txq.desc32[first].flags |= htole16(NFE_TX_VALID); 954 } 955 956 data->m = m0; 957 data->active = map; 958 959 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 960 BUS_DMASYNC_PREWRITE); 961 962 return 0; 963} 964 965void 966nfe_start(struct ifnet *ifp) 967{ 968 struct nfe_softc *sc = ifp->if_softc; 969 int old = sc->txq.cur; 970 struct mbuf *m0; 971 972 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 973 return; 974 975 for (;;) { 976 m0 = ifq_deq_begin(&ifp->if_snd); 977 if (m0 == NULL) 978 break; 979 980 if (nfe_encap(sc, m0) != 0) { 981 ifq_deq_rollback(&ifp->if_snd, m0); 982 ifp->if_flags |= IFF_OACTIVE; 983 break; 984 } 985 986 /* packet put in h/w queue, remove from s/w queue */ 987 ifq_deq_commit(&ifp->if_snd, m0); 988 989#if NBPFILTER > 0 990 if (ifp->if_bpf != NULL) 991 bpf_mtap_ether(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 992#endif 993 } 994 if (sc->txq.cur == old) /* nothing sent */ 995 return; 996 997 if (sc->sc_flags & NFE_40BIT_ADDR) 998 nfe_txdesc64_rsync(sc, old, sc->txq.cur, BUS_DMASYNC_PREWRITE); 999 else 1000 nfe_txdesc32_rsync(sc, old, sc->txq.cur, BUS_DMASYNC_PREWRITE); 1001 1002 /* kick Tx */ 1003 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 1004 1005 /* 1006 * Set a timeout in case the chip goes out to lunch. 1007 */ 1008 ifp->if_timer = 5; 1009} 1010 1011void 1012nfe_watchdog(struct ifnet *ifp) 1013{ 1014 struct nfe_softc *sc = ifp->if_softc; 1015 1016 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1017 1018 nfe_init(ifp); 1019 1020 ifp->if_oerrors++; 1021} 1022 1023int 1024nfe_init(struct ifnet *ifp) 1025{ 1026 struct nfe_softc *sc = ifp->if_softc; 1027 uint32_t tmp; 1028 1029 nfe_stop(ifp, 0); 1030 1031 NFE_WRITE(sc, NFE_TX_UNK, 0); 1032 NFE_WRITE(sc, NFE_STATUS, 0); 1033 1034 sc->rxtxctl = NFE_RXTX_BIT2; 1035 if (sc->sc_flags & NFE_40BIT_ADDR) 1036 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 1037 else if (sc->sc_flags & NFE_JUMBO_SUP) 1038 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 1039 1040 if (sc->sc_flags & NFE_HW_CSUM) 1041 sc->rxtxctl |= NFE_RXTX_RXCSUM; 1042 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1043 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT | NFE_RXTX_VTAG_STRIP; 1044 1045 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 1046 DELAY(10); 1047 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1048 1049 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1050 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 1051 else 1052 NFE_WRITE(sc, NFE_VTAG_CTL, 0); 1053 1054 NFE_WRITE(sc, NFE_SETUP_R6, 0); 1055 1056 /* set MAC address */ 1057 nfe_set_macaddr(sc, sc->sc_arpcom.ac_enaddr); 1058 1059 /* tell MAC where rings are in memory */ 1060#ifdef __LP64__ 1061 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32); 1062#endif 1063 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff); 1064#ifdef __LP64__ 1065 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32); 1066#endif 1067 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff); 1068 1069 NFE_WRITE(sc, NFE_RING_SIZE, 1070 (NFE_RX_RING_COUNT - 1) << 16 | 1071 (NFE_TX_RING_COUNT - 1)); 1072 1073 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz); 1074 1075 /* force MAC to wakeup */ 1076 tmp = NFE_READ(sc, NFE_PWR_STATE); 1077 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP); 1078 DELAY(10); 1079 tmp = NFE_READ(sc, NFE_PWR_STATE); 1080 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID); 1081 1082#if 1 1083 /* configure interrupts coalescing/mitigation */ 1084 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 1085#else 1086 /* no interrupt mitigation: one interrupt per packet */ 1087 NFE_WRITE(sc, NFE_IMTIMER, 970); 1088#endif 1089 1090 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC); 1091 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 1092 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 1093 1094 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 1095 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 1096 1097 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 1098 1099 sc->rxtxctl &= ~NFE_RXTX_BIT2; 1100 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 1101 DELAY(10); 1102 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 1103 1104 /* program promiscuous mode and multicast filters */ 1105 nfe_iff(sc); 1106 1107 nfe_ifmedia_upd(ifp); 1108 1109 /* enable Rx */ 1110 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 1111 1112 /* enable Tx */ 1113 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 1114 1115 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1116 1117 /* enable interrupts */ 1118 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1119 1120 timeout_add_sec(&sc->sc_tick_ch, 1); 1121 1122 ifp->if_flags |= IFF_RUNNING; 1123 ifp->if_flags &= ~IFF_OACTIVE; 1124 1125 return 0; 1126} 1127 1128void 1129nfe_stop(struct ifnet *ifp, int disable) 1130{ 1131 struct nfe_softc *sc = ifp->if_softc; 1132 1133 timeout_del(&sc->sc_tick_ch); 1134 1135 ifp->if_timer = 0; 1136 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1137 1138 mii_down(&sc->sc_mii); 1139 1140 /* abort Tx */ 1141 NFE_WRITE(sc, NFE_TX_CTL, 0); 1142 1143 if ((sc->sc_flags & NFE_WOL) == 0) { 1144 /* disable Rx */ 1145 NFE_WRITE(sc, NFE_RX_CTL, 0); 1146 1147 /* disable interrupts */ 1148 NFE_WRITE(sc, NFE_IRQ_MASK, 0); 1149 } 1150 1151 /* reset Tx and Rx rings */ 1152 nfe_reset_tx_ring(sc, &sc->txq); 1153 nfe_reset_rx_ring(sc, &sc->rxq); 1154} 1155 1156int 1157nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1158{ 1159 struct nfe_desc32 *desc32; 1160 struct nfe_desc64 *desc64; 1161 struct nfe_rx_data *data; 1162 void **desc; 1163 bus_addr_t physaddr; 1164 int i, nsegs, error, descsize; 1165 1166 if (sc->sc_flags & NFE_40BIT_ADDR) { 1167 desc = (void **)&ring->desc64; 1168 descsize = sizeof (struct nfe_desc64); 1169 } else { 1170 desc = (void **)&ring->desc32; 1171 descsize = sizeof (struct nfe_desc32); 1172 } 1173 1174 ring->cur = ring->next = 0; 1175 ring->bufsz = MCLBYTES; 1176 1177 error = bus_dmamap_create(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1, 1178 NFE_RX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1179 if (error != 0) { 1180 printf("%s: could not create desc DMA map\n", 1181 sc->sc_dev.dv_xname); 1182 goto fail; 1183 } 1184 1185 error = bus_dmamem_alloc(sc->sc_dmat, NFE_RX_RING_COUNT * descsize, 1186 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1187 if (error != 0) { 1188 printf("%s: could not allocate DMA memory\n", 1189 sc->sc_dev.dv_xname); 1190 goto fail; 1191 } 1192 1193 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1194 NFE_RX_RING_COUNT * descsize, (caddr_t *)desc, BUS_DMA_NOWAIT); 1195 if (error != 0) { 1196 printf("%s: can't map desc DMA memory\n", 1197 sc->sc_dev.dv_xname); 1198 goto fail; 1199 } 1200 1201 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1202 NFE_RX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1203 if (error != 0) { 1204 printf("%s: could not load desc DMA map\n", 1205 sc->sc_dev.dv_xname); 1206 goto fail; 1207 } 1208 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1209 1210 /* 1211 * Pre-allocate Rx buffers and populate Rx ring. 1212 */ 1213 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1214 data = &sc->rxq.data[i]; 1215 1216 data->m = MCLGETI(NULL, MCLBYTES, NULL, M_DONTWAIT); 1217 if (data->m == NULL) { 1218 printf("%s: could not allocate rx mbuf\n", 1219 sc->sc_dev.dv_xname); 1220 error = ENOMEM; 1221 goto fail; 1222 } 1223 data->m->m_pkthdr.len = data->m->m_len = MCLBYTES; 1224 1225 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1226 MCLBYTES, 0, BUS_DMA_NOWAIT, &data->map); 1227 if (error != 0) { 1228 printf("%s: could not create DMA map\n", 1229 sc->sc_dev.dv_xname); 1230 goto fail; 1231 } 1232 1233 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, data->m, 1234 BUS_DMA_READ | BUS_DMA_NOWAIT); 1235 if (error != 0) { 1236 printf("%s: could not load rx buf DMA map", 1237 sc->sc_dev.dv_xname); 1238 goto fail; 1239 } 1240 physaddr = data->map->dm_segs[0].ds_addr; 1241 1242 if (sc->sc_flags & NFE_40BIT_ADDR) { 1243 desc64 = &sc->rxq.desc64[i]; 1244#if defined(__LP64__) 1245 desc64->physaddr[0] = htole32(physaddr >> 32); 1246#endif 1247 desc64->physaddr[1] = htole32(physaddr & 0xffffffff); 1248 desc64->length = htole16(sc->rxq.bufsz); 1249 desc64->flags = htole16(NFE_RX_READY); 1250 } else { 1251 desc32 = &sc->rxq.desc32[i]; 1252 desc32->physaddr = htole32(physaddr); 1253 desc32->length = htole16(sc->rxq.bufsz); 1254 desc32->flags = htole16(NFE_RX_READY); 1255 } 1256 } 1257 1258 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1259 BUS_DMASYNC_PREWRITE); 1260 1261 return 0; 1262 1263fail: nfe_free_rx_ring(sc, ring); 1264 return error; 1265} 1266 1267void 1268nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1269{ 1270 int i; 1271 1272 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1273 if (sc->sc_flags & NFE_40BIT_ADDR) { 1274 ring->desc64[i].length = htole16(ring->bufsz); 1275 ring->desc64[i].flags = htole16(NFE_RX_READY); 1276 } else { 1277 ring->desc32[i].length = htole16(ring->bufsz); 1278 ring->desc32[i].flags = htole16(NFE_RX_READY); 1279 } 1280 } 1281 1282 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1283 BUS_DMASYNC_PREWRITE); 1284 1285 ring->cur = ring->next = 0; 1286} 1287 1288void 1289nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1290{ 1291 struct nfe_rx_data *data; 1292 void *desc; 1293 int i, descsize; 1294 1295 if (sc->sc_flags & NFE_40BIT_ADDR) { 1296 desc = ring->desc64; 1297 descsize = sizeof (struct nfe_desc64); 1298 } else { 1299 desc = ring->desc32; 1300 descsize = sizeof (struct nfe_desc32); 1301 } 1302 1303 if (desc != NULL) { 1304 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1305 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1306 bus_dmamap_unload(sc->sc_dmat, ring->map); 1307 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)desc, 1308 NFE_RX_RING_COUNT * descsize); 1309 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1310 } 1311 1312 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1313 data = &ring->data[i]; 1314 1315 if (data->map != NULL) { 1316 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1317 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1318 bus_dmamap_unload(sc->sc_dmat, data->map); 1319 bus_dmamap_destroy(sc->sc_dmat, data->map); 1320 } 1321 if (data->m != NULL) 1322 m_freem(data->m); 1323 } 1324} 1325 1326int 1327nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1328{ 1329 int i, nsegs, error; 1330 void **desc; 1331 int descsize; 1332 1333 if (sc->sc_flags & NFE_40BIT_ADDR) { 1334 desc = (void **)&ring->desc64; 1335 descsize = sizeof (struct nfe_desc64); 1336 } else { 1337 desc = (void **)&ring->desc32; 1338 descsize = sizeof (struct nfe_desc32); 1339 } 1340 1341 ring->queued = 0; 1342 ring->cur = ring->next = 0; 1343 1344 error = bus_dmamap_create(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1, 1345 NFE_TX_RING_COUNT * descsize, 0, BUS_DMA_NOWAIT, &ring->map); 1346 1347 if (error != 0) { 1348 printf("%s: could not create desc DMA map\n", 1349 sc->sc_dev.dv_xname); 1350 goto fail; 1351 } 1352 1353 error = bus_dmamem_alloc(sc->sc_dmat, NFE_TX_RING_COUNT * descsize, 1354 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1355 if (error != 0) { 1356 printf("%s: could not allocate DMA memory\n", 1357 sc->sc_dev.dv_xname); 1358 goto fail; 1359 } 1360 1361 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 1362 NFE_TX_RING_COUNT * descsize, (caddr_t *)desc, BUS_DMA_NOWAIT); 1363 if (error != 0) { 1364 printf("%s: can't map desc DMA memory\n", 1365 sc->sc_dev.dv_xname); 1366 goto fail; 1367 } 1368 1369 error = bus_dmamap_load(sc->sc_dmat, ring->map, *desc, 1370 NFE_TX_RING_COUNT * descsize, NULL, BUS_DMA_NOWAIT); 1371 if (error != 0) { 1372 printf("%s: could not load desc DMA map\n", 1373 sc->sc_dev.dv_xname); 1374 goto fail; 1375 } 1376 ring->physaddr = ring->map->dm_segs[0].ds_addr; 1377 1378 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1379 error = bus_dmamap_create(sc->sc_dmat, NFE_JBYTES, 1380 NFE_MAX_SCATTER, NFE_JBYTES, 0, BUS_DMA_NOWAIT, 1381 &ring->data[i].map); 1382 if (error != 0) { 1383 printf("%s: could not create DMA map\n", 1384 sc->sc_dev.dv_xname); 1385 goto fail; 1386 } 1387 } 1388 1389 return 0; 1390 1391fail: nfe_free_tx_ring(sc, ring); 1392 return error; 1393} 1394 1395void 1396nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1397{ 1398 struct nfe_tx_data *data; 1399 int i; 1400 1401 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1402 if (sc->sc_flags & NFE_40BIT_ADDR) 1403 ring->desc64[i].flags = 0; 1404 else 1405 ring->desc32[i].flags = 0; 1406 1407 data = &ring->data[i]; 1408 1409 if (data->m != NULL) { 1410 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1411 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1412 bus_dmamap_unload(sc->sc_dmat, data->active); 1413 m_freem(data->m); 1414 data->m = NULL; 1415 } 1416 } 1417 1418 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1419 BUS_DMASYNC_PREWRITE); 1420 1421 ring->queued = 0; 1422 ring->cur = ring->next = 0; 1423} 1424 1425void 1426nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1427{ 1428 struct nfe_tx_data *data; 1429 void *desc; 1430 int i, descsize; 1431 1432 if (sc->sc_flags & NFE_40BIT_ADDR) { 1433 desc = ring->desc64; 1434 descsize = sizeof (struct nfe_desc64); 1435 } else { 1436 desc = ring->desc32; 1437 descsize = sizeof (struct nfe_desc32); 1438 } 1439 1440 if (desc != NULL) { 1441 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 1442 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1443 bus_dmamap_unload(sc->sc_dmat, ring->map); 1444 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)desc, 1445 NFE_TX_RING_COUNT * descsize); 1446 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 1447 } 1448 1449 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1450 data = &ring->data[i]; 1451 1452 if (data->m != NULL) { 1453 bus_dmamap_sync(sc->sc_dmat, data->active, 0, 1454 data->active->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1455 bus_dmamap_unload(sc->sc_dmat, data->active); 1456 m_freem(data->m); 1457 } 1458 } 1459 1460 /* ..and now actually destroy the DMA mappings */ 1461 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1462 data = &ring->data[i]; 1463 if (data->map == NULL) 1464 continue; 1465 bus_dmamap_destroy(sc->sc_dmat, data->map); 1466 } 1467} 1468 1469int 1470nfe_ifmedia_upd(struct ifnet *ifp) 1471{ 1472 struct nfe_softc *sc = ifp->if_softc; 1473 struct mii_data *mii = &sc->sc_mii; 1474 struct mii_softc *miisc; 1475 1476 if (mii->mii_instance != 0) { 1477 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1478 mii_phy_reset(miisc); 1479 } 1480 return mii_mediachg(mii); 1481} 1482 1483void 1484nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1485{ 1486 struct nfe_softc *sc = ifp->if_softc; 1487 struct mii_data *mii = &sc->sc_mii; 1488 1489 mii_pollstat(mii); 1490 ifmr->ifm_status = mii->mii_media_status; 1491 ifmr->ifm_active = mii->mii_media_active; 1492} 1493 1494void 1495nfe_iff(struct nfe_softc *sc) 1496{ 1497 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1498 struct arpcom *ac = &sc->sc_arpcom; 1499 struct ether_multi *enm; 1500 struct ether_multistep step; 1501 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 1502 uint32_t filter; 1503 int i; 1504 1505 filter = NFE_RXFILTER_MAGIC; 1506 ifp->if_flags &= ~IFF_ALLMULTI; 1507 1508 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 1509 ifp->if_flags |= IFF_ALLMULTI; 1510 if (ifp->if_flags & IFF_PROMISC) 1511 filter |= NFE_PROMISC; 1512 else 1513 filter |= NFE_U2M; 1514 bzero(addr, ETHER_ADDR_LEN); 1515 bzero(mask, ETHER_ADDR_LEN); 1516 } else { 1517 filter |= NFE_U2M; 1518 1519 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1520 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 1521 1522 ETHER_FIRST_MULTI(step, ac, enm); 1523 while (enm != NULL) { 1524 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1525 addr[i] &= enm->enm_addrlo[i]; 1526 mask[i] &= ~enm->enm_addrlo[i]; 1527 } 1528 1529 ETHER_NEXT_MULTI(step, enm); 1530 } 1531 1532 for (i = 0; i < ETHER_ADDR_LEN; i++) 1533 mask[i] |= addr[i]; 1534 } 1535 1536 addr[0] |= 0x01; /* make sure multicast bit is set */ 1537 1538 NFE_WRITE(sc, NFE_MULTIADDR_HI, 1539 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1540 NFE_WRITE(sc, NFE_MULTIADDR_LO, 1541 addr[5] << 8 | addr[4]); 1542 NFE_WRITE(sc, NFE_MULTIMASK_HI, 1543 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 1544 NFE_WRITE(sc, NFE_MULTIMASK_LO, 1545 mask[5] << 8 | mask[4]); 1546 NFE_WRITE(sc, NFE_RXFILTER, filter); 1547} 1548 1549void 1550nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 1551{ 1552 uint32_t tmp; 1553 1554 if (sc->sc_flags & NFE_CORRECT_MACADDR) { 1555 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1556 addr[0] = (tmp & 0xff); 1557 addr[1] = (tmp >> 8) & 0xff; 1558 addr[2] = (tmp >> 16) & 0xff; 1559 addr[3] = (tmp >> 24) & 0xff; 1560 1561 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1562 addr[4] = (tmp & 0xff); 1563 addr[5] = (tmp >> 8) & 0xff; 1564 1565 } else { 1566 tmp = NFE_READ(sc, NFE_MACADDR_LO); 1567 addr[0] = (tmp >> 8) & 0xff; 1568 addr[1] = (tmp & 0xff); 1569 1570 tmp = NFE_READ(sc, NFE_MACADDR_HI); 1571 addr[2] = (tmp >> 24) & 0xff; 1572 addr[3] = (tmp >> 16) & 0xff; 1573 addr[4] = (tmp >> 8) & 0xff; 1574 addr[5] = (tmp & 0xff); 1575 } 1576} 1577 1578void 1579nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr) 1580{ 1581 NFE_WRITE(sc, NFE_MACADDR_LO, 1582 addr[5] << 8 | addr[4]); 1583 NFE_WRITE(sc, NFE_MACADDR_HI, 1584 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 1585} 1586 1587void 1588nfe_tick(void *arg) 1589{ 1590 struct nfe_softc *sc = arg; 1591 int s; 1592 1593 s = splnet(); 1594 mii_tick(&sc->sc_mii); 1595 splx(s); 1596 1597 timeout_add_sec(&sc->sc_tick_ch, 1); 1598} 1599 1600#ifndef SMALL_KERNEL 1601int 1602nfe_wol(struct ifnet *ifp, int enable) 1603{ 1604 struct nfe_softc *sc = ifp->if_softc; 1605 1606 if (enable) { 1607 sc->sc_flags |= NFE_WOL; 1608 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_ENABLE); 1609 } else { 1610 sc->sc_flags &= ~NFE_WOL; 1611 NFE_WRITE(sc, NFE_WOL_CTL, 0); 1612 } 1613 1614 return 0; 1615} 1616#endif 1617