1/************************************************************************** 2 3Copyright (c) 2001-2005, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/* $OpenBSD: if_ixgb.h,v 1.19 2015/11/24 17:11:39 mpi Exp $ */ 35 36#ifndef _IXGB_H_DEFINED_ 37#define _IXGB_H_DEFINED_ 38 39#include "bpfilter.h" 40#include "vlan.h" 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/sockio.h> 45#include <sys/mbuf.h> 46#include <sys/malloc.h> 47#include <sys/kernel.h> 48#include <sys/device.h> 49#include <sys/socket.h> 50#include <sys/timeout.h> 51 52#include <net/if.h> 53#include <net/if_media.h> 54 55#include <netinet/in.h> 56#include <netinet/ip.h> 57#include <netinet/if_ether.h> 58#include <netinet/tcp.h> 59#include <netinet/udp.h> 60 61#if NBPFILTER > 0 62#include <net/bpf.h> 63#endif 64 65typedef int boolean_t; 66#define TRUE 1 67#define FALSE 0 68 69#include <dev/pci/pcireg.h> 70#include <dev/pci/pcivar.h> 71#include <dev/pci/pcidevs.h> 72 73#include <dev/pci/ixgb_hw.h> 74#include <dev/pci/ixgb_ee.h> 75#include <dev/pci/ixgb_ids.h> 76 77/* Tunables */ 78 79/* 80 * TxDescriptors Valid Range: 64-4096 Default Value: 2048 This value is the 81 * number of transmit descriptors allocated by the driver. Increasing this 82 * value allows the driver to queue more transmits. Each descriptor is 16 83 * bytes. 84 */ 85#define IXGB_MAX_TXD 2048 86 87/* 88 * RxDescriptors Valid Range: 64-4096 Default Value: 1024 This value is the 89 * number of receive descriptors allocated by the driver. Increasing this 90 * value allows the driver to buffer more incoming packets. Each descriptor 91 * is 16 bytes. A receive buffer is also allocated for each descriptor. The 92 * maximum MTU size is 16110. 93 */ 94#define IXGB_MAX_RXD 1024 95 96/* 97 * TxIntDelay Valid Range: 0-65535 (0=off) Default Value: 32 This value 98 * delays the generation of transmit interrupts in units of 1.024 99 * microseconds. Transmit interrupt reduction can improve CPU efficiency if 100 * properly tuned for specific network traffic. If the system is reporting 101 * dropped transmits, this value may be set too high causing the driver to 102 * run out of available transmit descriptors. 103 */ 104#define TIDV 32 105 106/* 107 * RxIntDelay Valid Range: 0-65535 (0=off) Default Value: 72 This value 108 * delays the generation of receive interrupts in units of 1.024 109 * microseconds. Receive interrupt reduction can improve CPU efficiency if 110 * properly tuned for specific network traffic. Increasing this value adds 111 * extra latency to frame reception and can end up decreasing the throughput 112 * of TCP traffic. If the system is reporting dropped receives, this value 113 * may be set too high, causing the driver to run out of available receive 114 * descriptors. 115 */ 116#define RDTR 72 117 118/* 119 * This parameter controls the duration of transmit watchdog timer. 120 */ 121#define IXGB_TX_TIMEOUT 5 /* set to 5 seconds */ 122 123/* 124 * This parameter controls when the driver calls the routine to reclaim 125 * transmit descriptors. 126 */ 127#define IXGB_TX_CLEANUP_THRESHOLD (sc->num_tx_desc / 8) 128 129/* 130 * Flow Control Types. 131 * 1. ixgb_fc_none - Flow Control Disabled 132 * 2. ixgb_fc_rx_pause - Flow Control Receive Only 133 * 3. ixgb_fc_tx_pause - Flow Control Transmit Only 134 * 4. ixgb_fc_full - Flow Control Enabled 135 */ 136#define FLOW_CONTROL_NONE ixgb_fc_none 137#define FLOW_CONTROL_RX_PAUSE ixgb_fc_rx_pause 138#define FLOW_CONTROL_TX_PAUSE ixgb_fc_tx_pause 139#define FLOW_CONTROL_FULL ixgb_fc_full 140 141/* 142 * Set the flow control type. Assign one of the above flow control types to be enabled. 143 * Default Value: FLOW_CONTROL_FULL 144 */ 145#define FLOW_CONTROL FLOW_CONTROL_FULL 146 147/* 148 * Receive Flow control low threshold (when we send a resume frame) (FCRTL) 149 * Valid Range: 64 - 262,136 (0x40 - 0x3FFF8, 8 byte granularity) must be 150 * less than high threshold by at least 8 bytes Default Value: 163,840 151 * (0x28000) 152 */ 153#define FCRTL 0x28000 154 155/* 156 * Receive Flow control high threshold (when we send a pause frame) (FCRTH) 157 * Valid Range: 1,536 - 262,136 (0x600 - 0x3FFF8, 8 byte granularity) Default 158 * Value: 196,608 (0x30000) 159 */ 160#define FCRTH 0x30000 161 162/* 163 * Flow control request timeout (how long to pause the link partner's tx) 164 * (PAP 15:0) Valid Range: 1 - 65535 Default Value: 256 (0x100) 165 */ 166#define FCPAUSE 0x100 167 168/* Tunables -- End */ 169 170#define IXGB_MMBA 0x0010 /* Mem base address */ 171#define IXGB_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 172 173#define MAX_NUM_MULTICAST_ADDRESSES 128 174 175/* Defines for printing debug information */ 176#define DEBUG_INIT 0 177#define DEBUG_IOCTL 0 178#define DEBUG_HW 0 179 180#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 181#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 182#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 183#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 184#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 185#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 186#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 187#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 188#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 189 190/* Supported RX Buffer Sizes */ 191#define IXGB_RXBUFFER_2048 2048 192#define IXGB_RXBUFFER_4096 4096 193#define IXGB_RXBUFFER_8192 8192 194#define IXGB_RXBUFFER_16384 16384 195 196#define IXGB_MAX_SCATTER 100 197 198struct ixgb_buffer { 199 struct mbuf *m_head; 200 bus_dmamap_t map; /* bus_dma map for packet */ 201}; 202 203/* 204 * Bus dma allocation structure used by 205 * ixgb_dma_malloc and ixgb_dma_free. 206 */ 207struct ixgb_dma_alloc { 208 bus_addr_t dma_paddr; 209 caddr_t dma_vaddr; 210 bus_dma_tag_t dma_tag; 211 bus_dmamap_t dma_map; 212 bus_dma_segment_t dma_seg; 213 bus_size_t dma_size; 214 int dma_nseg; 215}; 216 217typedef enum _XSUM_CONTEXT_T { 218 OFFLOAD_NONE, 219 OFFLOAD_TCP_IP, 220 OFFLOAD_UDP_IP 221} XSUM_CONTEXT_T; 222 223/* Our adapter structure */ 224struct ixgb_softc { 225 struct device sc_dv; 226 struct arpcom interface_data; 227 struct ixgb_hw hw; 228 229 /* OpenBSD operating-system-specific structures */ 230 struct ixgb_osdep osdep; 231 struct ifmedia media; 232 int io_rid; 233 234 void *sc_intrhand; 235 struct timeout ixgb_intr_enable; 236 struct timeout timer_handle; 237 int if_flags; 238 239 /* Info about the board itself */ 240 u_int32_t part_num; 241 u_int8_t link_active; 242 u_int16_t link_speed; 243 u_int16_t link_duplex; 244 u_int32_t tx_int_delay; 245 u_int32_t tx_abs_int_delay; 246 u_int32_t rx_int_delay; 247 u_int32_t rx_abs_int_delay; 248 249 int raidc; 250 251 XSUM_CONTEXT_T active_checksum_context; 252 253 /* 254 * Transmit definitions 255 * 256 * We have an array of num_tx_desc descriptors (handled by the 257 * controller) paired with an array of tx_buffers (at 258 * tx_buffer_area). The index of the next available descriptor is 259 * next_avail_tx_desc. The number of remaining tx_desc is 260 * num_tx_desc_avail. 261 */ 262 struct ixgb_dma_alloc txdma; /* bus_dma glue for tx desc */ 263 struct ixgb_tx_desc *tx_desc_base; 264 u_int32_t next_avail_tx_desc; 265 u_int32_t oldest_used_tx_desc; 266 volatile u_int16_t num_tx_desc_avail; 267 u_int16_t num_tx_desc; 268 u_int32_t txd_cmd; 269 struct ixgb_buffer *tx_buffer_area; 270 bus_dma_tag_t txtag; /* dma tag for tx */ 271 272 /* 273 * Receive definitions 274 * 275 * we have an array of num_rx_desc rx_desc (handled by the controller), 276 * and paired with an array of rx_buffers (at rx_buffer_area). The 277 * next pair to check on receive is at offset next_rx_desc_to_check 278 */ 279 struct ixgb_dma_alloc rxdma; /* bus_dma glue for rx desc */ 280 struct ixgb_rx_desc *rx_desc_base; 281 u_int32_t next_rx_desc_to_check; 282 u_int16_t num_rx_desc; 283 u_int32_t rx_buffer_len; 284 struct ixgb_buffer *rx_buffer_area; 285 bus_dma_tag_t rxtag; /* dma tag for Rx */ 286 u_int32_t next_rx_desc_to_use; 287 288 /* 289 * First/last mbuf pointers, for 290 * collecting multisegment RX packets. 291 */ 292 struct mbuf *fmp; 293 struct mbuf *lmp; 294 295 /* Misc stats maintained by the driver */ 296 unsigned long dropped_pkts; 297 unsigned long mbuf_alloc_failed; 298 unsigned long mbuf_cluster_failed; 299 unsigned long no_tx_desc_avail1; 300 unsigned long no_tx_desc_avail2; 301 unsigned long no_tx_map_avail; 302 unsigned long no_tx_dma_setup; 303 unsigned long watchdog_events; 304 305 struct ixgb_hw_stats stats; 306}; 307 308#endif /* _IXGB_H_DEFINED_ */ 309