if_ipw.c revision 1.99
1/* $OpenBSD: if_ipw.c,v 1.99 2014/03/27 11:32:29 daniel Exp $ */ 2 3/*- 4 * Copyright (c) 2004-2008 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/* 21 * Driver for Intel PRO/Wireless 2100 802.11 network adapters. 22 */ 23 24#include "bpfilter.h" 25 26#include <sys/param.h> 27#include <sys/sockio.h> 28#include <sys/workq.h> 29#include <sys/mbuf.h> 30#include <sys/kernel.h> 31#include <sys/socket.h> 32#include <sys/systm.h> 33#include <sys/conf.h> 34#include <sys/device.h> 35 36#include <machine/bus.h> 37#include <machine/endian.h> 38#include <machine/intr.h> 39 40#include <dev/pci/pcireg.h> 41#include <dev/pci/pcivar.h> 42#include <dev/pci/pcidevs.h> 43 44#if NBPFILTER > 0 45#include <net/bpf.h> 46#endif 47#include <net/if.h> 48#include <net/if_arp.h> 49#include <net/if_dl.h> 50#include <net/if_media.h> 51#include <net/if_types.h> 52 53#include <netinet/in.h> 54#include <netinet/in_systm.h> 55#include <netinet/if_ether.h> 56#include <netinet/ip.h> 57 58#include <net80211/ieee80211_var.h> 59#include <net80211/ieee80211_radiotap.h> 60 61#include <dev/pci/if_ipwreg.h> 62#include <dev/pci/if_ipwvar.h> 63 64int ipw_match(struct device *, void *, void *); 65void ipw_attach(struct device *, struct device *, void *); 66int ipw_activate(struct device *, int); 67void ipw_wakeup(struct ipw_softc *); 68int ipw_dma_alloc(struct ipw_softc *); 69void ipw_release(struct ipw_softc *); 70int ipw_media_change(struct ifnet *); 71void ipw_media_status(struct ifnet *, struct ifmediareq *); 72int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 73uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 74void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 75void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 76void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 77 struct ipw_soft_bd *, struct ipw_soft_buf *); 78void ipw_notification_intr(struct ipw_softc *, 79 struct ipw_soft_buf *); 80void ipw_rx_intr(struct ipw_softc *); 81void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 82void ipw_tx_intr(struct ipw_softc *); 83int ipw_intr(void *); 84int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 85int ipw_send_mgmt(struct ieee80211com *, struct ieee80211_node *, 86 int, int, int); 87int ipw_tx_start(struct ifnet *, struct mbuf *, 88 struct ieee80211_node *); 89void ipw_start(struct ifnet *); 90void ipw_watchdog(struct ifnet *); 91int ipw_ioctl(struct ifnet *, u_long, caddr_t); 92uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 93void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 94int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 95 uint32_t *); 96void ipw_stop_master(struct ipw_softc *); 97int ipw_reset(struct ipw_softc *); 98int ipw_load_ucode(struct ipw_softc *, u_char *, int); 99int ipw_load_firmware(struct ipw_softc *, u_char *, int); 100int ipw_read_firmware(struct ipw_softc *, struct ipw_firmware *); 101void ipw_scan(void *, void *); 102void ipw_auth_and_assoc(void *, void *); 103int ipw_config(struct ipw_softc *); 104int ipw_init(struct ifnet *); 105void ipw_stop(struct ifnet *, int); 106void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 107 bus_size_t); 108void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 109 bus_size_t); 110 111static __inline uint8_t 112MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 113{ 114 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 115 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 116} 117 118static __inline uint32_t 119MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 120{ 121 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 122 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 123} 124 125#ifdef IPW_DEBUG 126#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 127#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 128int ipw_debug = 0; 129#else 130#define DPRINTF(x) 131#define DPRINTFN(n, x) 132#endif 133 134struct cfattach ipw_ca = { 135 sizeof (struct ipw_softc), ipw_match, ipw_attach, NULL, 136 ipw_activate 137}; 138 139int 140ipw_match(struct device *parent, void *match, void *aux) 141{ 142 struct pci_attach_args *pa = aux; 143 144 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 145 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 146 return 1; 147 148 return 0; 149} 150 151/* Base Address Register */ 152#define IPW_PCI_BAR0 0x10 153 154void 155ipw_attach(struct device *parent, struct device *self, void *aux) 156{ 157 struct ipw_softc *sc = (struct ipw_softc *)self; 158 struct ieee80211com *ic = &sc->sc_ic; 159 struct ifnet *ifp = &ic->ic_if; 160 struct pci_attach_args *pa = aux; 161 const char *intrstr; 162 bus_space_tag_t memt; 163 bus_space_handle_t memh; 164 bus_addr_t base; 165 pci_intr_handle_t ih; 166 pcireg_t data; 167 uint16_t val; 168 int error, i; 169 170 sc->sc_pct = pa->pa_pc; 171 sc->sc_pcitag = pa->pa_tag, 172 173 /* clear device specific PCI configuration register 0x41 */ 174 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 175 data &= ~0x0000ff00; 176 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 177 178 /* map the register window */ 179 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 180 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 181 if (error != 0) { 182 printf(": can't map mem space\n"); 183 return; 184 } 185 186 sc->sc_st = memt; 187 sc->sc_sh = memh; 188 sc->sc_dmat = pa->pa_dmat; 189 190 /* disable interrupts */ 191 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 192 193 if (pci_intr_map(pa, &ih) != 0) { 194 printf(": can't map interrupt\n"); 195 return; 196 } 197 198 intrstr = pci_intr_string(sc->sc_pct, ih); 199 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 200 sc->sc_dev.dv_xname); 201 if (sc->sc_ih == NULL) { 202 printf(": can't establish interrupt"); 203 if (intrstr != NULL) 204 printf(" at %s", intrstr); 205 printf("\n"); 206 return; 207 } 208 printf(": %s", intrstr); 209 210 if (ipw_reset(sc) != 0) { 211 printf(": could not reset adapter\n"); 212 return; 213 } 214 215 if (ipw_dma_alloc(sc) != 0) { 216 printf(": failed to allocate DMA resources\n"); 217 return; 218 } 219 220 ic->ic_phytype = IEEE80211_T_DS; 221 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 222 ic->ic_state = IEEE80211_S_INIT; 223 224 /* set device capabilities */ 225 ic->ic_caps = 226#ifndef IEEE80211_STA_ONLY 227 IEEE80211_C_IBSS | /* IBSS mode supported */ 228#endif 229 IEEE80211_C_MONITOR | /* monitor mode supported */ 230 IEEE80211_C_TXPMGT | /* tx power management */ 231 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 232 IEEE80211_C_WEP | /* s/w WEP */ 233 IEEE80211_C_RSN | /* WPA/RSN */ 234 IEEE80211_C_SCANALL; /* h/w scanning */ 235 236 /* read MAC address from EEPROM */ 237 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 238 ic->ic_myaddr[0] = val >> 8; 239 ic->ic_myaddr[1] = val & 0xff; 240 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 241 ic->ic_myaddr[2] = val >> 8; 242 ic->ic_myaddr[3] = val & 0xff; 243 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 244 ic->ic_myaddr[4] = val >> 8; 245 ic->ic_myaddr[5] = val & 0xff; 246 247 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 248 249 /* set supported .11b rates */ 250 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 251 252 /* set supported .11b channels (1 through 14) */ 253 for (i = 1; i <= 14; i++) { 254 ic->ic_channels[i].ic_freq = 255 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 256 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 257 } 258 259 /* IBSS channel undefined for now */ 260 ic->ic_ibss_chan = &ic->ic_channels[0]; 261 262 ifp->if_softc = sc; 263 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 264 ifp->if_ioctl = ipw_ioctl; 265 ifp->if_start = ipw_start; 266 ifp->if_watchdog = ipw_watchdog; 267 IFQ_SET_READY(&ifp->if_snd); 268 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 269 270 if_attach(ifp); 271 ieee80211_ifattach(ifp); 272 /* override state transition machine */ 273 sc->sc_newstate = ic->ic_newstate; 274 ic->ic_newstate = ipw_newstate; 275 ic->ic_send_mgmt = ipw_send_mgmt; 276 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 277 278#if NBPFILTER > 0 279 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 280 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 281 282 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 283 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 284 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 285 286 sc->sc_txtap_len = sizeof sc->sc_txtapu; 287 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 288 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 289#endif 290} 291 292int 293ipw_activate(struct device *self, int act) 294{ 295 struct ipw_softc *sc = (struct ipw_softc *)self; 296 struct ifnet *ifp = &sc->sc_ic.ic_if; 297 298 switch (act) { 299 case DVACT_SUSPEND: 300 if (ifp->if_flags & IFF_RUNNING) 301 ipw_stop(ifp, 0); 302 break; 303 case DVACT_WAKEUP: 304 ipw_wakeup(sc); 305 break; 306 } 307 308 return 0; 309} 310 311void 312ipw_wakeup(struct ipw_softc *sc) 313{ 314 struct ifnet *ifp = &sc->sc_ic.ic_if; 315 pcireg_t data; 316 int s; 317 318 /* clear device specific PCI configuration register 0x41 */ 319 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 320 data &= ~0x0000ff00; 321 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 322 323 s = splnet(); 324 while (sc->sc_flags & IPW_FLAG_BUSY) 325 tsleep(&sc->sc_flags, PZERO, "ipwpwr", 0); 326 sc->sc_flags |= IPW_FLAG_BUSY; 327 328 if (ifp->if_flags & IFF_UP) 329 ipw_init(ifp); 330 331 sc->sc_flags &= ~IPW_FLAG_BUSY; 332 wakeup(&sc->sc_flags); 333 splx(s); 334} 335 336int 337ipw_dma_alloc(struct ipw_softc *sc) 338{ 339 struct ipw_soft_bd *sbd; 340 struct ipw_soft_hdr *shdr; 341 struct ipw_soft_buf *sbuf; 342 int i, nsegs, error; 343 344 /* 345 * Allocate and map tx ring. 346 */ 347 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 348 BUS_DMA_NOWAIT, &sc->tbd_map); 349 if (error != 0) { 350 printf("%s: could not create tx ring DMA map\n", 351 sc->sc_dev.dv_xname); 352 goto fail; 353 } 354 355 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 356 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 357 if (error != 0) { 358 printf("%s: could not allocate tx ring DMA memory\n", 359 sc->sc_dev.dv_xname); 360 goto fail; 361 } 362 363 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 364 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 365 if (error != 0) { 366 printf("%s: can't map tx ring DMA memory\n", 367 sc->sc_dev.dv_xname); 368 goto fail; 369 } 370 371 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 372 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 373 if (error != 0) { 374 printf("%s: could not load tx ring DMA map\n", 375 sc->sc_dev.dv_xname); 376 goto fail; 377 } 378 379 /* 380 * Allocate and map rx ring. 381 */ 382 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 383 BUS_DMA_NOWAIT, &sc->rbd_map); 384 if (error != 0) { 385 printf("%s: could not create rx ring DMA map\n", 386 sc->sc_dev.dv_xname); 387 goto fail; 388 } 389 390 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 391 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 392 if (error != 0) { 393 printf("%s: could not allocate rx ring DMA memory\n", 394 sc->sc_dev.dv_xname); 395 goto fail; 396 } 397 398 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 399 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 400 if (error != 0) { 401 printf("%s: can't map rx ring DMA memory\n", 402 sc->sc_dev.dv_xname); 403 goto fail; 404 } 405 406 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 407 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 408 if (error != 0) { 409 printf("%s: could not load tx ring DMA map\n", 410 sc->sc_dev.dv_xname); 411 goto fail; 412 } 413 414 /* 415 * Allocate and map status ring. 416 */ 417 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 418 0, BUS_DMA_NOWAIT, &sc->status_map); 419 if (error != 0) { 420 printf("%s: could not create status ring DMA map\n", 421 sc->sc_dev.dv_xname); 422 goto fail; 423 } 424 425 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 426 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 427 if (error != 0) { 428 printf("%s: could not allocate status ring DMA memory\n", 429 sc->sc_dev.dv_xname); 430 goto fail; 431 } 432 433 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 434 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 435 if (error != 0) { 436 printf("%s: can't map status ring DMA memory\n", 437 sc->sc_dev.dv_xname); 438 goto fail; 439 } 440 441 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 442 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 443 if (error != 0) { 444 printf("%s: could not load status ring DMA map\n", 445 sc->sc_dev.dv_xname); 446 goto fail; 447 } 448 449 /* 450 * Allocate command DMA map. 451 */ 452 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 453 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 454 if (error != 0) { 455 printf("%s: could not create command DMA map\n", 456 sc->sc_dev.dv_xname); 457 goto fail; 458 } 459 460 /* 461 * Allocate headers DMA maps. 462 */ 463 SLIST_INIT(&sc->free_shdr); 464 for (i = 0; i < IPW_NDATA; i++) { 465 shdr = &sc->shdr_list[i]; 466 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_hdr), 467 1, sizeof (struct ipw_hdr), 0, BUS_DMA_NOWAIT, &shdr->map); 468 if (error != 0) { 469 printf("%s: could not create header DMA map\n", 470 sc->sc_dev.dv_xname); 471 goto fail; 472 } 473 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 474 } 475 476 /* 477 * Allocate tx buffers DMA maps. 478 */ 479 SLIST_INIT(&sc->free_sbuf); 480 for (i = 0; i < IPW_NDATA; i++) { 481 sbuf = &sc->tx_sbuf_list[i]; 482 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, IPW_MAX_NSEG, 483 MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 484 if (error != 0) { 485 printf("%s: could not create tx DMA map\n", 486 sc->sc_dev.dv_xname); 487 goto fail; 488 } 489 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 490 } 491 492 /* 493 * Initialize tx ring. 494 */ 495 for (i = 0; i < IPW_NTBD; i++) { 496 sbd = &sc->stbd_list[i]; 497 sbd->bd = &sc->tbd_list[i]; 498 sbd->type = IPW_SBD_TYPE_NOASSOC; 499 } 500 501 /* 502 * Pre-allocate rx buffers and DMA maps. 503 */ 504 for (i = 0; i < IPW_NRBD; i++) { 505 sbd = &sc->srbd_list[i]; 506 sbuf = &sc->rx_sbuf_list[i]; 507 sbd->bd = &sc->rbd_list[i]; 508 509 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 510 if (sbuf->m == NULL) { 511 printf("%s: could not allocate rx mbuf\n", 512 sc->sc_dev.dv_xname); 513 error = ENOMEM; 514 goto fail; 515 } 516 MCLGET(sbuf->m, M_DONTWAIT); 517 if (!(sbuf->m->m_flags & M_EXT)) { 518 m_freem(sbuf->m); 519 printf("%s: could not allocate rx mbuf cluster\n", 520 sc->sc_dev.dv_xname); 521 error = ENOMEM; 522 goto fail; 523 } 524 525 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 526 0, BUS_DMA_NOWAIT, &sbuf->map); 527 if (error != 0) { 528 printf("%s: could not create rx DMA map\n", 529 sc->sc_dev.dv_xname); 530 goto fail; 531 } 532 533 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 534 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 535 if (error != 0) { 536 printf("%s: can't map rx DMA memory\n", 537 sc->sc_dev.dv_xname); 538 goto fail; 539 } 540 541 sbd->type = IPW_SBD_TYPE_DATA; 542 sbd->priv = sbuf; 543 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 544 sbd->bd->len = htole32(MCLBYTES); 545 } 546 547 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 548 BUS_DMASYNC_PREWRITE); 549 550 return 0; 551 552fail: ipw_release(sc); 553 return error; 554} 555 556void 557ipw_release(struct ipw_softc *sc) 558{ 559 struct ipw_soft_buf *sbuf; 560 int i; 561 562 if (sc->tbd_map != NULL) { 563 if (sc->tbd_list != NULL) { 564 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 565 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 566 IPW_TBD_SZ); 567 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 568 } 569 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 570 } 571 572 if (sc->rbd_map != NULL) { 573 if (sc->rbd_list != NULL) { 574 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 575 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 576 IPW_RBD_SZ); 577 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 578 } 579 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 580 } 581 582 if (sc->status_map != NULL) { 583 if (sc->status_list != NULL) { 584 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 585 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 586 IPW_RBD_SZ); 587 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 588 } 589 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 590 } 591 592 if (sc->cmd_map != NULL) 593 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 594 595 for (i = 0; i < IPW_NDATA; i++) 596 bus_dmamap_destroy(sc->sc_dmat, sc->shdr_list[i].map); 597 598 for (i = 0; i < IPW_NDATA; i++) 599 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 600 601 for (i = 0; i < IPW_NRBD; i++) { 602 sbuf = &sc->rx_sbuf_list[i]; 603 if (sbuf->map != NULL) { 604 if (sbuf->m != NULL) { 605 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 606 m_freem(sbuf->m); 607 } 608 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 609 } 610 } 611} 612 613int 614ipw_media_change(struct ifnet *ifp) 615{ 616 int error; 617 618 error = ieee80211_media_change(ifp); 619 if (error != ENETRESET) 620 return error; 621 622 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 623 ipw_init(ifp); 624 625 return 0; 626} 627 628void 629ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 630{ 631 struct ipw_softc *sc = ifp->if_softc; 632 struct ieee80211com *ic = &sc->sc_ic; 633 static const struct { 634 uint32_t val; 635 int rate; 636 } rates[] = { 637 { IPW_RATE_DS1, 2 }, 638 { IPW_RATE_DS2, 4 }, 639 { IPW_RATE_DS5, 11 }, 640 { IPW_RATE_DS11, 22 }, 641 }; 642 uint32_t val; 643 int rate, i; 644 645 imr->ifm_status = IFM_AVALID; 646 imr->ifm_active = IFM_IEEE80211; 647 if (ic->ic_state == IEEE80211_S_RUN) 648 imr->ifm_status |= IFM_ACTIVE; 649 650 /* read current transmission rate from adapter */ 651 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 652 val &= 0xf; 653 654 /* convert rate to 802.11 rate */ 655 for (i = 0; i < nitems(rates) && rates[i].val != val; i++); 656 rate = (i < nitems(rates)) ? rates[i].rate : 0; 657 658 imr->ifm_active |= IFM_IEEE80211_11B; 659 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 660 switch (ic->ic_opmode) { 661 case IEEE80211_M_STA: 662 break; 663#ifndef IEEE80211_STA_ONLY 664 case IEEE80211_M_IBSS: 665 imr->ifm_active |= IFM_IEEE80211_IBSS; 666 break; 667#endif 668 case IEEE80211_M_MONITOR: 669 imr->ifm_active |= IFM_IEEE80211_MONITOR; 670 break; 671 default: 672 /* should not get there */ 673 break; 674 } 675} 676 677int 678ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 679{ 680 struct ipw_softc *sc = ic->ic_softc; 681 int error; 682 683 switch (nstate) { 684 case IEEE80211_S_SCAN: 685 error = workq_add_task(NULL, 0, ipw_scan, sc, NULL); 686 if (error != 0) 687 return error; 688 break; 689 690 case IEEE80211_S_AUTH: 691 error = workq_add_task(NULL, 0, ipw_auth_and_assoc, sc, NULL); 692 if (error != 0) 693 return error; 694 break; 695 696 case IEEE80211_S_RUN: 697 case IEEE80211_S_INIT: 698 case IEEE80211_S_ASSOC: 699 /* nothing to do */ 700 break; 701 } 702 703 ic->ic_state = nstate; 704 return 0; 705} 706 707/* 708 * Read 16 bits at address 'addr' from the Microwire EEPROM. 709 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 710 */ 711uint16_t 712ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 713{ 714 uint32_t tmp; 715 uint16_t val; 716 int n; 717 718 /* clock C once before the first command */ 719 IPW_EEPROM_CTL(sc, 0); 720 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 721 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 722 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 723 724 /* write start bit (1) */ 725 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 726 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 727 728 /* write READ opcode (10) */ 729 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 730 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 731 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 732 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 733 734 /* write address A7-A0 */ 735 for (n = 7; n >= 0; n--) { 736 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 737 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 738 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 739 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 740 } 741 742 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 743 744 /* read data Q15-Q0 */ 745 val = 0; 746 for (n = 15; n >= 0; n--) { 747 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 748 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 749 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 750 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 751 } 752 753 IPW_EEPROM_CTL(sc, 0); 754 755 /* clear Chip Select and clock C */ 756 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 757 IPW_EEPROM_CTL(sc, 0); 758 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 759 760 return val; 761} 762 763void 764ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 765{ 766 struct ipw_cmd *cmd; 767 768 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 769 BUS_DMASYNC_POSTREAD); 770 771 cmd = mtod(sbuf->m, struct ipw_cmd *); 772 773 DPRINTFN(2, ("received command ack type=%u,status=%u\n", 774 letoh32(cmd->type), letoh32(cmd->status))); 775 776 wakeup(&sc->cmd); 777} 778 779void 780ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 781{ 782 struct ieee80211com *ic = &sc->sc_ic; 783 struct ifnet *ifp = &ic->ic_if; 784 uint32_t state; 785 786 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 787 BUS_DMASYNC_POSTREAD); 788 789 state = letoh32(*mtod(sbuf->m, uint32_t *)); 790 791 DPRINTFN(2, ("firmware state changed to 0x%x\n", state)); 792 793 switch (state) { 794 case IPW_STATE_ASSOCIATED: 795 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 796 break; 797 798 case IPW_STATE_SCANNING: 799 if (ic->ic_state == IEEE80211_S_RUN) 800 ieee80211_begin_scan(ifp); 801 break; 802 803 case IPW_STATE_SCAN_COMPLETE: 804 if (ic->ic_state == IEEE80211_S_SCAN) 805 ieee80211_end_scan(ifp); 806 break; 807 808 case IPW_STATE_ASSOCIATION_LOST: 809 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 810 break; 811 812 case IPW_STATE_DISABLED: 813 wakeup(sc); 814 break; 815 816 case IPW_STATE_RADIO_DISABLED: 817 ifp->if_flags &= ~IFF_UP; 818 ipw_stop(&ic->ic_if, 1); 819 break; 820 } 821} 822 823void 824ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 825 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 826{ 827 struct ieee80211com *ic = &sc->sc_ic; 828 struct ifnet *ifp = &ic->ic_if; 829 struct mbuf *mnew, *m; 830 struct ieee80211_frame *wh; 831 struct ieee80211_rxinfo rxi; 832 struct ieee80211_node *ni; 833 int error; 834 835 DPRINTFN(5, ("received data frame len=%u,rssi=%u\n", 836 letoh32(status->len), status->rssi)); 837 838 /* 839 * Try to allocate a new mbuf for this ring element and load it before 840 * processing the current mbuf. If the ring element cannot be loaded, 841 * drop the received packet and reuse the old mbuf. In the unlikely 842 * case that the old mbuf can't be reloaded either, explicitly panic. 843 */ 844 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 845 if (mnew == NULL) { 846 ifp->if_ierrors++; 847 return; 848 } 849 MCLGET(mnew, M_DONTWAIT); 850 if (!(mnew->m_flags & M_EXT)) { 851 m_freem(mnew); 852 ifp->if_ierrors++; 853 return; 854 } 855 856 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 857 BUS_DMASYNC_POSTREAD); 858 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 859 860 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(mnew, void *), 861 MCLBYTES, NULL, BUS_DMA_NOWAIT); 862 if (error != 0) { 863 m_freem(mnew); 864 865 /* try to reload the old mbuf */ 866 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 867 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 868 if (error != 0) { 869 /* very unlikely that it will fail... */ 870 panic("%s: could not load old rx mbuf", 871 sc->sc_dev.dv_xname); 872 } 873 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 874 ifp->if_ierrors++; 875 return; 876 } 877 878 m = sbuf->m; 879 sbuf->m = mnew; 880 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 881 882 /* finalize mbuf */ 883 m->m_pkthdr.rcvif = ifp; 884 m->m_pkthdr.len = m->m_len = letoh32(status->len); 885 886#if NBPFILTER > 0 887 if (sc->sc_drvbpf != NULL) { 888 struct mbuf mb; 889 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 890 891 tap->wr_flags = 0; 892 tap->wr_antsignal = status->rssi; 893 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 894 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 895 896 mb.m_data = (caddr_t)tap; 897 mb.m_len = sc->sc_rxtap_len; 898 mb.m_next = m; 899 mb.m_nextpkt = NULL; 900 mb.m_type = 0; 901 mb.m_flags = 0; 902 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 903 } 904#endif 905 906 wh = mtod(m, struct ieee80211_frame *); 907 ni = ieee80211_find_rxnode(ic, wh); 908 909 /* send the frame to the upper layer */ 910 rxi.rxi_flags = 0; 911 rxi.rxi_rssi = status->rssi; 912 rxi.rxi_tstamp = 0; /* unused */ 913 ieee80211_input(ifp, m, ni, &rxi); 914 915 ieee80211_release_node(ic, ni); 916} 917 918void 919ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 920{ 921 DPRINTFN(2, ("received notification\n")); 922} 923 924void 925ipw_rx_intr(struct ipw_softc *sc) 926{ 927 struct ipw_status *status; 928 struct ipw_soft_bd *sbd; 929 struct ipw_soft_buf *sbuf; 930 uint32_t r, i; 931 932 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 933 934 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 935 936 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 937 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 938 BUS_DMASYNC_POSTREAD); 939 940 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 941 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 942 BUS_DMASYNC_POSTREAD); 943 944 status = &sc->status_list[i]; 945 sbd = &sc->srbd_list[i]; 946 sbuf = sbd->priv; 947 948 switch (letoh16(status->code) & 0xf) { 949 case IPW_STATUS_CODE_COMMAND: 950 ipw_command_intr(sc, sbuf); 951 break; 952 953 case IPW_STATUS_CODE_NEWSTATE: 954 ipw_newstate_intr(sc, sbuf); 955 break; 956 957 case IPW_STATUS_CODE_DATA_802_3: 958 case IPW_STATUS_CODE_DATA_802_11: 959 ipw_data_intr(sc, status, sbd, sbuf); 960 break; 961 962 case IPW_STATUS_CODE_NOTIFICATION: 963 ipw_notification_intr(sc, sbuf); 964 break; 965 966 default: 967 printf("%s: unknown status code %u\n", 968 sc->sc_dev.dv_xname, letoh16(status->code)); 969 } 970 sbd->bd->flags = 0; 971 972 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 973 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 974 BUS_DMASYNC_PREWRITE); 975 } 976 977 /* tell the firmware what we have processed */ 978 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 979 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 980} 981 982void 983ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 984{ 985 struct ieee80211com *ic = &sc->sc_ic; 986 struct ipw_soft_hdr *shdr; 987 struct ipw_soft_buf *sbuf; 988 989 switch (sbd->type) { 990 case IPW_SBD_TYPE_COMMAND: 991 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 992 break; 993 994 case IPW_SBD_TYPE_HEADER: 995 shdr = sbd->priv; 996 bus_dmamap_unload(sc->sc_dmat, shdr->map); 997 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 998 break; 999 1000 case IPW_SBD_TYPE_DATA: 1001 sbuf = sbd->priv; 1002 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1003 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1004 1005 m_freem(sbuf->m); 1006 1007 if (sbuf->ni != NULL) 1008 ieee80211_release_node(ic, sbuf->ni); 1009 1010 /* kill watchdog timer */ 1011 sc->sc_tx_timer = 0; 1012 break; 1013 } 1014 sbd->type = IPW_SBD_TYPE_NOASSOC; 1015} 1016 1017void 1018ipw_tx_intr(struct ipw_softc *sc) 1019{ 1020 struct ifnet *ifp = &sc->sc_ic.ic_if; 1021 struct ipw_soft_bd *sbd; 1022 uint32_t r, i; 1023 1024 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 1025 1026 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1027 sbd = &sc->stbd_list[i]; 1028 1029 if (sbd->type == IPW_SBD_TYPE_DATA) 1030 ifp->if_opackets++; 1031 1032 ipw_release_sbd(sc, sbd); 1033 sc->txfree++; 1034 } 1035 1036 /* remember what the firmware has processed */ 1037 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1038 1039 /* call start() since some buffer descriptors have been released */ 1040 ifp->if_flags &= ~IFF_OACTIVE; 1041 (*ifp->if_start)(ifp); 1042} 1043 1044int 1045ipw_intr(void *arg) 1046{ 1047 struct ipw_softc *sc = arg; 1048 struct ifnet *ifp = &sc->sc_ic.ic_if; 1049 uint32_t r; 1050 1051 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) 1052 return 0; 1053 1054 /* disable interrupts */ 1055 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1056 1057 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1058 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 1059 ifp->if_flags &= ~IFF_UP; 1060 ipw_stop(ifp, 1); 1061 return 1; 1062 } 1063 1064 if (r & IPW_INTR_FW_INIT_DONE) 1065 wakeup(sc); 1066 1067 if (r & IPW_INTR_RX_TRANSFER) 1068 ipw_rx_intr(sc); 1069 1070 if (r & IPW_INTR_TX_TRANSFER) 1071 ipw_tx_intr(sc); 1072 1073 /* acknowledge interrupts */ 1074 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1075 1076 /* re-enable interrupts */ 1077 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1078 1079 return 1; 1080} 1081 1082int 1083ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1084{ 1085 struct ipw_soft_bd *sbd; 1086 int s, error; 1087 1088 s = splnet(); 1089 1090 sc->cmd.type = htole32(type); 1091 sc->cmd.subtype = htole32(0); 1092 sc->cmd.len = htole32(len); 1093 sc->cmd.seq = htole32(0); 1094 if (data != NULL) 1095 bcopy(data, sc->cmd.data, len); 1096 1097 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 1098 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 1099 if (error != 0) { 1100 printf("%s: can't map command DMA memory\n", 1101 sc->sc_dev.dv_xname); 1102 splx(s); 1103 return error; 1104 } 1105 1106 sbd = &sc->stbd_list[sc->txcur]; 1107 sbd->type = IPW_SBD_TYPE_COMMAND; 1108 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1109 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1110 sbd->bd->nfrag = 1; 1111 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1112 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1113 1114 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1115 BUS_DMASYNC_PREWRITE); 1116 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1117 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1118 BUS_DMASYNC_PREWRITE); 1119 1120 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1121 sc->txfree--; 1122 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1123 1124 DPRINTFN(2, ("sending command type=%u,len=%u\n", type, len)); 1125 1126 /* wait at most one second for command to complete */ 1127 error = tsleep(&sc->cmd, 0, "ipwcmd", hz); 1128 splx(s); 1129 1130 return error; 1131} 1132 1133/* ARGSUSED */ 1134int 1135ipw_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type, 1136 int arg1, int arg2) 1137{ 1138 return EOPNOTSUPP; 1139} 1140 1141int 1142ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 1143{ 1144 struct ipw_softc *sc = ifp->if_softc; 1145 struct ieee80211com *ic = &sc->sc_ic; 1146 struct ieee80211_frame *wh; 1147 struct ieee80211_key *k; 1148 struct mbuf *m1; 1149 struct ipw_soft_bd *sbd; 1150 struct ipw_soft_hdr *shdr; 1151 struct ipw_soft_buf *sbuf; 1152 int error, i; 1153 1154 wh = mtod(m, struct ieee80211_frame *); 1155 1156 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1157 k = ieee80211_get_txkey(ic, wh, ni); 1158 1159 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1160 return ENOBUFS; 1161 1162 /* packet header may have moved, reset our local pointer */ 1163 wh = mtod(m, struct ieee80211_frame *); 1164 } 1165 1166#if NBPFILTER > 0 1167 if (sc->sc_drvbpf != NULL) { 1168 struct mbuf mb; 1169 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1170 1171 tap->wt_flags = 0; 1172 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1173 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1174 1175 mb.m_data = (caddr_t)tap; 1176 mb.m_len = sc->sc_txtap_len; 1177 mb.m_next = m; 1178 mb.m_nextpkt = NULL; 1179 mb.m_type = 0; 1180 mb.m_flags = 0; 1181 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1182 } 1183#endif 1184 1185 shdr = SLIST_FIRST(&sc->free_shdr); 1186 sbuf = SLIST_FIRST(&sc->free_sbuf); 1187 1188 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1189 shdr->hdr.subtype = htole32(0); 1190 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) ? 1 : 0; 1191 shdr->hdr.encrypt = 0; 1192 shdr->hdr.keyidx = 0; 1193 shdr->hdr.keysz = 0; 1194 shdr->hdr.fragmentsz = htole16(0); 1195 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1196 if (ic->ic_opmode == IEEE80211_M_STA) 1197 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1198 else 1199 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1200 1201 /* trim IEEE802.11 header */ 1202 m_adj(m, sizeof (struct ieee80211_frame)); 1203 1204 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 1205 if (error != 0 && error != EFBIG) { 1206 printf("%s: can't map mbuf (error %d)\n", 1207 sc->sc_dev.dv_xname, error); 1208 m_freem(m); 1209 return error; 1210 } 1211 if (error != 0) { 1212 /* too many fragments, linearize */ 1213 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1214 if (m1 == NULL) { 1215 m_freem(m); 1216 return ENOBUFS; 1217 } 1218 if (m->m_pkthdr.len > MHLEN) { 1219 MCLGET(m1, M_DONTWAIT); 1220 if (!(m1->m_flags & M_EXT)) { 1221 m_freem(m); 1222 m_freem(m1); 1223 return ENOBUFS; 1224 } 1225 } 1226 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, caddr_t)); 1227 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 1228 m_freem(m); 1229 m = m1; 1230 1231 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, 1232 BUS_DMA_NOWAIT); 1233 if (error != 0) { 1234 printf("%s: can't map mbuf (error %d)\n", 1235 sc->sc_dev.dv_xname, error); 1236 m_freem(m); 1237 return error; 1238 } 1239 } 1240 1241 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 1242 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 1243 if (error != 0) { 1244 printf("%s: can't map header DMA memory (error %d)\n", 1245 sc->sc_dev.dv_xname, error); 1246 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1247 m_freem(m); 1248 return error; 1249 } 1250 1251 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1252 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1253 1254 sbd = &sc->stbd_list[sc->txcur]; 1255 sbd->type = IPW_SBD_TYPE_HEADER; 1256 sbd->priv = shdr; 1257 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 1258 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1259 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1260 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1261 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1262 1263 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1264 sc->txcur * sizeof (struct ipw_bd), 1265 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1266 1267 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1268 sc->txfree--; 1269 1270 sbuf->m = m; 1271 sbuf->ni = ni; 1272 1273 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1274 sbd = &sc->stbd_list[sc->txcur]; 1275 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1276 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1277 sbd->bd->nfrag = 0; /* used only in first bd */ 1278 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1279 if (i == sbuf->map->dm_nsegs - 1) { 1280 sbd->type = IPW_SBD_TYPE_DATA; 1281 sbd->priv = sbuf; 1282 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1283 } else { 1284 sbd->type = IPW_SBD_TYPE_NOASSOC; 1285 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1286 } 1287 1288 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1289 sc->txcur * sizeof (struct ipw_bd), 1290 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1291 1292 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1293 sc->txfree--; 1294 } 1295 1296 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1297 BUS_DMASYNC_PREWRITE); 1298 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 1299 BUS_DMASYNC_PREWRITE); 1300 1301 /* inform firmware about this new packet */ 1302 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1303 1304 return 0; 1305} 1306 1307void 1308ipw_start(struct ifnet *ifp) 1309{ 1310 struct ipw_softc *sc = ifp->if_softc; 1311 struct ieee80211com *ic = &sc->sc_ic; 1312 struct ieee80211_node *ni; 1313 struct mbuf *m; 1314 1315 if (ic->ic_state != IEEE80211_S_RUN) 1316 return; 1317 1318 for (;;) { 1319 IFQ_POLL(&ifp->if_snd, m); 1320 if (m == NULL) 1321 break; 1322 1323 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1324 ifp->if_flags |= IFF_OACTIVE; 1325 break; 1326 } 1327 IFQ_DEQUEUE(&ifp->if_snd, m); 1328#if NBPFILTER > 0 1329 if (ifp->if_bpf != NULL) 1330 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1331#endif 1332 m = ieee80211_encap(ifp, m, &ni); 1333 if (m == NULL) 1334 continue; 1335#if NBPFILTER > 0 1336 if (ic->ic_rawbpf != NULL) 1337 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1338#endif 1339 if (ipw_tx_start(ifp, m, ni) != 0) { 1340 if (ni != NULL) 1341 ieee80211_release_node(ic, ni); 1342 ifp->if_oerrors++; 1343 break; 1344 } 1345 1346 /* start watchdog timer */ 1347 sc->sc_tx_timer = 5; 1348 ifp->if_timer = 1; 1349 } 1350} 1351 1352void 1353ipw_watchdog(struct ifnet *ifp) 1354{ 1355 struct ipw_softc *sc = ifp->if_softc; 1356 1357 ifp->if_timer = 0; 1358 1359 if (sc->sc_tx_timer > 0) { 1360 if (--sc->sc_tx_timer == 0) { 1361 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1362 ifp->if_flags &= ~IFF_UP; 1363 ipw_stop(ifp, 1); 1364 ifp->if_oerrors++; 1365 return; 1366 } 1367 ifp->if_timer = 1; 1368 } 1369 1370 ieee80211_watchdog(ifp); 1371} 1372 1373int 1374ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1375{ 1376 struct ipw_softc *sc = ifp->if_softc; 1377 struct ieee80211com *ic = &sc->sc_ic; 1378 struct ifaddr *ifa; 1379 struct ifreq *ifr; 1380 int s, error = 0; 1381 1382 s = splnet(); 1383 /* 1384 * Prevent processes from entering this function while another 1385 * process is tsleep'ing in it. 1386 */ 1387 while ((sc->sc_flags & IPW_FLAG_BUSY) && error == 0) 1388 error = tsleep(&sc->sc_flags, PCATCH, "ipwioc", 0); 1389 if (error != 0) { 1390 splx(s); 1391 return error; 1392 } 1393 sc->sc_flags |= IPW_FLAG_BUSY; 1394 1395 switch (cmd) { 1396 case SIOCSIFADDR: 1397 ifa = (struct ifaddr *)data; 1398 ifp->if_flags |= IFF_UP; 1399#ifdef INET 1400 if (ifa->ifa_addr->sa_family == AF_INET) 1401 arp_ifinit(&ic->ic_ac, ifa); 1402#endif 1403 /* FALLTHROUGH */ 1404 case SIOCSIFFLAGS: 1405 if (ifp->if_flags & IFF_UP) { 1406 if (!(ifp->if_flags & IFF_RUNNING)) 1407 ipw_init(ifp); 1408 } else { 1409 if (ifp->if_flags & IFF_RUNNING) 1410 ipw_stop(ifp, 1); 1411 } 1412 break; 1413 1414 case SIOCADDMULTI: 1415 case SIOCDELMULTI: 1416 ifr = (struct ifreq *)data; 1417 error = (cmd == SIOCADDMULTI) ? 1418 ether_addmulti(ifr, &ic->ic_ac) : 1419 ether_delmulti(ifr, &ic->ic_ac); 1420 1421 if (error == ENETRESET) 1422 error = 0; 1423 break; 1424 1425 case SIOCG80211TXPOWER: 1426 /* 1427 * If the hardware radio transmitter switch is off, report a 1428 * tx power of IEEE80211_TXPOWER_MIN to indicate that radio 1429 * transmitter is killed. 1430 */ 1431 ((struct ieee80211_txpower *)data)->i_val = 1432 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 1433 IEEE80211_TXPOWER_MIN : sc->sc_ic.ic_txpower; 1434 break; 1435 1436 default: 1437 error = ieee80211_ioctl(ifp, cmd, data); 1438 } 1439 1440 if (error == ENETRESET) { 1441 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1442 (IFF_UP | IFF_RUNNING)) 1443 ipw_init(ifp); 1444 error = 0; 1445 } 1446 1447 sc->sc_flags &= ~IPW_FLAG_BUSY; 1448 wakeup(&sc->sc_flags); 1449 splx(s); 1450 return error; 1451} 1452 1453uint32_t 1454ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1455{ 1456 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1457} 1458 1459void 1460ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1461{ 1462 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1463} 1464 1465int 1466ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1467{ 1468 uint32_t addr, info; 1469 uint16_t count, size; 1470 uint32_t total; 1471 1472 /* addr[4] + count[2] + size[2] */ 1473 addr = MEM_READ_4(sc, sc->table2_base + off); 1474 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1475 1476 count = info >> 16; 1477 size = info & 0xffff; 1478 total = count * size; 1479 1480 if (total > *len) { 1481 *len = total; 1482 return EINVAL; 1483 } 1484 *len = total; 1485 ipw_read_mem_1(sc, addr, buf, total); 1486 1487 return 0; 1488} 1489 1490void 1491ipw_stop_master(struct ipw_softc *sc) 1492{ 1493 uint32_t tmp; 1494 int ntries; 1495 1496 /* disable interrupts */ 1497 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1498 1499 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1500 for (ntries = 0; ntries < 50; ntries++) { 1501 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1502 break; 1503 DELAY(10); 1504 } 1505 if (ntries == 50) 1506 printf("%s: timeout waiting for master\n", 1507 sc->sc_dev.dv_xname); 1508 1509 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1510 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1511 1512 sc->sc_flags &= ~IPW_FLAG_FW_INITED; 1513} 1514 1515int 1516ipw_reset(struct ipw_softc *sc) 1517{ 1518 uint32_t tmp; 1519 int ntries; 1520 1521 ipw_stop_master(sc); 1522 1523 /* move adapter to D0 state */ 1524 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1525 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1526 1527 /* wait for clock stabilization */ 1528 for (ntries = 0; ntries < 1000; ntries++) { 1529 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1530 break; 1531 DELAY(200); 1532 } 1533 if (ntries == 1000) 1534 return EIO; 1535 1536 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1537 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1538 1539 DELAY(10); 1540 1541 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1542 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1543 1544 return 0; 1545} 1546 1547int 1548ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1549{ 1550 int ntries; 1551 1552 /* voodoo from the Intel Linux driver */ 1553 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1554 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1555 1556 MEM_WRITE_2(sc, 0x220000, 0x0703); 1557 MEM_WRITE_2(sc, 0x220000, 0x0707); 1558 1559 MEM_WRITE_1(sc, 0x210014, 0x72); 1560 MEM_WRITE_1(sc, 0x210014, 0x72); 1561 1562 MEM_WRITE_1(sc, 0x210000, 0x40); 1563 MEM_WRITE_1(sc, 0x210000, 0x00); 1564 MEM_WRITE_1(sc, 0x210000, 0x40); 1565 1566 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1567 1568 MEM_WRITE_1(sc, 0x210000, 0x00); 1569 MEM_WRITE_1(sc, 0x210000, 0x00); 1570 MEM_WRITE_1(sc, 0x210000, 0x80); 1571 1572 MEM_WRITE_2(sc, 0x220000, 0x0703); 1573 MEM_WRITE_2(sc, 0x220000, 0x0707); 1574 1575 MEM_WRITE_1(sc, 0x210014, 0x72); 1576 MEM_WRITE_1(sc, 0x210014, 0x72); 1577 1578 MEM_WRITE_1(sc, 0x210000, 0x00); 1579 MEM_WRITE_1(sc, 0x210000, 0x80); 1580 1581 for (ntries = 0; ntries < 100; ntries++) { 1582 if (MEM_READ_1(sc, 0x210000) & 1) 1583 break; 1584 DELAY(1000); 1585 } 1586 if (ntries == 100) { 1587 printf("%s: timeout waiting for ucode to initialize\n", 1588 sc->sc_dev.dv_xname); 1589 return EIO; 1590 } 1591 1592 MEM_WRITE_4(sc, 0x3000e0, 0); 1593 1594 return 0; 1595} 1596 1597/* set of macros to handle unaligned little endian data in firmware image */ 1598#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1599#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1600int 1601ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1602{ 1603 u_char *p, *end; 1604 uint32_t tmp, dst; 1605 uint16_t len; 1606 int error; 1607 1608 p = fw; 1609 end = fw + size; 1610 while (p < end) { 1611 if (p + 6 > end) 1612 return EINVAL; 1613 1614 dst = GETLE32(p); p += 4; 1615 len = GETLE16(p); p += 2; 1616 1617 if (p + len > end) 1618 return EINVAL; 1619 1620 ipw_write_mem_1(sc, dst, p, len); 1621 p += len; 1622 } 1623 1624 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1625 IPW_IO_LED_OFF); 1626 1627 /* allow interrupts so we know when the firmware is inited */ 1628 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1629 1630 /* tell the adapter to initialize the firmware */ 1631 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1632 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1633 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1634 1635 /* wait at most one second for firmware initialization to complete */ 1636 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1637 printf("%s: timeout waiting for firmware initialization to " 1638 "complete\n", sc->sc_dev.dv_xname); 1639 return error; 1640 } 1641 1642 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1643 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1644 IPW_IO_GPIO3_MASK); 1645 1646 return 0; 1647} 1648 1649int 1650ipw_read_firmware(struct ipw_softc *sc, struct ipw_firmware *fw) 1651{ 1652 const struct ipw_firmware_hdr *hdr; 1653 const char *name; 1654 size_t size; 1655 int error; 1656 1657 switch (sc->sc_ic.ic_opmode) { 1658 case IEEE80211_M_STA: 1659 name = "ipw-bss"; 1660 break; 1661#ifndef IEEE80211_STA_ONLY 1662 case IEEE80211_M_IBSS: 1663 name = "ipw-ibss"; 1664 break; 1665#endif 1666 case IEEE80211_M_MONITOR: 1667 name = "ipw-monitor"; 1668 break; 1669 default: 1670 /* should not get there */ 1671 return ENODEV; 1672 } 1673 if ((error = loadfirmware(name, &fw->data, &size)) != 0) 1674 return error; 1675 1676 if (size < sizeof (*hdr)) { 1677 error = EINVAL; 1678 goto fail; 1679 } 1680 hdr = (const struct ipw_firmware_hdr *)fw->data; 1681 fw->main_size = letoh32(hdr->main_size); 1682 fw->ucode_size = letoh32(hdr->ucode_size); 1683 1684 if (size < sizeof (*hdr) + fw->main_size + fw->ucode_size) { 1685 error = EINVAL; 1686 goto fail; 1687 } 1688 fw->main = fw->data + sizeof (*hdr); 1689 fw->ucode = fw->main + fw->main_size; 1690 1691 return 0; 1692 1693fail: free(fw->data, M_DEVBUF); 1694 return error; 1695} 1696 1697void 1698ipw_scan(void *arg1, void *arg2) 1699{ 1700 struct ipw_softc *sc = arg1; 1701 struct ifnet *ifp = &sc->sc_ic.ic_if; 1702 struct ipw_scan_options scan; 1703 uint8_t ssid[IEEE80211_NWID_LEN]; 1704 int error; 1705 1706 /* 1707 * Firmware has a bug and does not honour the ``do not associate 1708 * after scan'' bit in the scan command. To prevent the firmware 1709 * from associating after the scan, we set the ESSID to something 1710 * unlikely to be used by a real AP. 1711 * XXX would setting the desired BSSID to a multicast address work? 1712 */ 1713 memset(ssid, '\r', sizeof ssid); 1714 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ssid, sizeof ssid); 1715 if (error != 0) 1716 goto fail; 1717 1718 /* no mandatory BSSID */ 1719 DPRINTF(("Setting mandatory BSSID to null\n")); 1720 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1721 if (error != 0) 1722 goto fail; 1723 1724 scan.flags = htole32(IPW_SCAN_DO_NOT_ASSOCIATE | IPW_SCAN_MIXED_CELL); 1725 scan.channels = htole32(0x3fff); /* scan channels 1-14 */ 1726 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1727 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1728 if (error != 0) 1729 goto fail; 1730 1731 /* start scanning */ 1732 DPRINTF(("Enabling adapter\n")); 1733 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1734 if (error != 0) 1735 goto fail; 1736 1737 return; 1738fail: 1739 printf("%s: scan request failed (error=%d)\n", sc->sc_dev.dv_xname, 1740 error); 1741 ieee80211_end_scan(ifp); 1742} 1743 1744void 1745ipw_auth_and_assoc(void *arg1, void *arg2) 1746{ 1747 struct ipw_softc *sc = arg1; 1748 struct ieee80211com *ic = &sc->sc_ic; 1749 struct ieee80211_node *ni = ic->ic_bss; 1750 struct ipw_scan_options scan; 1751 struct ipw_security security; 1752 struct ipw_assoc_req assoc; 1753 uint32_t data; 1754 uint8_t chan; 1755 int s, error; 1756 1757 DPRINTF(("Disabling adapter\n")); 1758 error = ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1759 if (error != 0) 1760 goto fail; 1761#if 1 1762 /* wait at most one second for card to be disabled */ 1763 s = splnet(); 1764 error = tsleep(sc, 0, "ipwdis", hz); 1765 splx(s); 1766 if (error != 0) { 1767 printf("%s: timeout waiting for disabled state\n", 1768 sc->sc_dev.dv_xname); 1769 goto fail; 1770 } 1771#else 1772 /* Intel's Linux driver polls for the DISABLED state instead.. */ 1773 for (ntries = 0; ntries < 1000; ntries++) { 1774 if (ipw_read_table1(sc, IPW_INFO_CARD_DISABLED) == 1) 1775 break; 1776 DELAY(10); 1777 } 1778 if (ntries == 1000) { 1779 printf("%s: timeout waiting for disabled state\n", 1780 sc->sc_dev.dv_xname); 1781 goto fail; 1782 } 1783#endif 1784 1785 bzero(&security, sizeof security); 1786 security.authmode = IPW_AUTH_OPEN; 1787 security.ciphers = htole32(IPW_CIPHER_NONE); 1788 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1789 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1790 sizeof security); 1791 if (error != 0) 1792 goto fail; 1793 1794#ifdef IPW_DEBUG 1795 if (ipw_debug > 0) { 1796 printf("Setting ESSID to "); 1797 ieee80211_print_essid(ni->ni_essid, ni->ni_esslen); 1798 printf("\n"); 1799 } 1800#endif 1801 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ni->ni_essid, ni->ni_esslen); 1802 if (error != 0) 1803 goto fail; 1804 1805 DPRINTF(("Setting BSSID to %s\n", ether_sprintf(ni->ni_bssid))); 1806 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, ni->ni_bssid, 1807 IEEE80211_ADDR_LEN); 1808 if (error != 0) 1809 goto fail; 1810 1811 data = htole32((ic->ic_flags & (IEEE80211_F_WEPON | 1812 IEEE80211_F_RSNON)) ? IPW_PRIVACYON : 0); 1813 DPRINTF(("Setting privacy flags to 0x%x\n", letoh32(data))); 1814 error = ipw_cmd(sc, IPW_CMD_SET_PRIVACY_FLAGS, &data, sizeof data); 1815 if (error != 0) 1816 goto fail; 1817 1818 /* let firmware set the capinfo, lintval, and bssid fixed fields */ 1819 bzero(&assoc, sizeof assoc); 1820 if (ic->ic_flags & IEEE80211_F_RSNON) { 1821 uint8_t *frm = assoc.optie; 1822 1823 /* tell firmware to add a WPA or RSN IE in (Re)Assoc req */ 1824 if (ni->ni_rsnprotos & IEEE80211_PROTO_RSN) 1825 frm = ieee80211_add_rsn(frm, ic, ni); 1826 else if (ni->ni_rsnprotos & IEEE80211_PROTO_WPA) 1827 frm = ieee80211_add_wpa(frm, ic, ni); 1828 assoc.optie_len = htole32(frm - assoc.optie); 1829 } 1830 DPRINTF(("Preparing assocation request (optional IE length=%d)\n", 1831 letoh32(assoc.optie_len))); 1832 error = ipw_cmd(sc, IPW_CMD_SET_ASSOC_REQ, &assoc, sizeof assoc); 1833 if (error != 0) 1834 goto fail; 1835 1836 scan.flags = htole32(IPW_SCAN_MIXED_CELL); 1837 chan = ieee80211_chan2ieee(ic, ni->ni_chan); 1838 scan.channels = htole32(1 << (chan - 1)); 1839 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1840 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1841 if (error != 0) 1842 goto fail; 1843 1844 /* trigger scan+association */ 1845 DPRINTF(("Enabling adapter\n")); 1846 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1847 if (error != 0) 1848 goto fail; 1849 1850 return; 1851fail: 1852 printf("%s: association failed (error=%d)\n", sc->sc_dev.dv_xname, 1853 error); 1854 ieee80211_begin_scan(&ic->ic_if); 1855} 1856 1857int 1858ipw_config(struct ipw_softc *sc) 1859{ 1860 struct ieee80211com *ic = &sc->sc_ic; 1861 struct ifnet *ifp = &ic->ic_if; 1862 struct ipw_configuration config; 1863 uint32_t data; 1864 int error; 1865 1866 switch (ic->ic_opmode) { 1867 case IEEE80211_M_STA: 1868 data = htole32(IPW_MODE_BSS); 1869 break; 1870#ifndef IEEE80211_STA_ONLY 1871 case IEEE80211_M_IBSS: 1872 data = htole32(IPW_MODE_IBSS); 1873 break; 1874#endif 1875 case IEEE80211_M_MONITOR: 1876 data = htole32(IPW_MODE_MONITOR); 1877 break; 1878 default: 1879 /* should not get there */ 1880 return ENODEV; 1881 } 1882 DPRINTF(("Setting mode to %u\n", letoh32(data))); 1883 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1884 if (error != 0) 1885 return error; 1886 1887 if ( 1888#ifndef IEEE80211_STA_ONLY 1889 ic->ic_opmode == IEEE80211_M_IBSS || 1890#endif 1891 ic->ic_opmode == IEEE80211_M_MONITOR) { 1892 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1893 DPRINTF(("Setting channel to %u\n", letoh32(data))); 1894 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1895 if (error != 0) 1896 return error; 1897 } 1898 1899 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1900 DPRINTF(("Enabling adapter\n")); 1901 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1902 } 1903 1904 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 1905 DPRINTF(("Setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 1906 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1907 IEEE80211_ADDR_LEN); 1908 if (error != 0) 1909 return error; 1910 1911 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1912 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1X_ENABLE); 1913#ifndef IEEE80211_STA_ONLY 1914 if (ic->ic_opmode == IEEE80211_M_IBSS) 1915 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1916#endif 1917 if (ifp->if_flags & IFF_PROMISC) 1918 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1919 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1920 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1921 DPRINTF(("Setting configuration 0x%x\n", config.flags)); 1922 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1923 if (error != 0) 1924 return error; 1925 1926 data = htole32(ic->ic_rtsthreshold); 1927 DPRINTF(("Setting RTS threshold to %u\n", letoh32(data))); 1928 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1929 if (error != 0) 1930 return error; 1931 1932 data = htole32(ic->ic_fragthreshold); 1933 DPRINTF(("Setting frag threshold to %u\n", letoh32(data))); 1934 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1935 if (error != 0) 1936 return error; 1937 1938 data = htole32(0x3); /* 1, 2 */ 1939 DPRINTF(("Setting basic tx rates to 0x%x\n", letoh32(data))); 1940 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1941 if (error != 0) 1942 return error; 1943 1944 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1945 DPRINTF(("Setting tx rates to 0x%x\n", letoh32(data))); 1946 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1947 if (error != 0) 1948 return error; 1949 1950 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1951 DPRINTF(("Setting MSDU tx rates to 0x%x\n", letoh32(data))); 1952 error = ipw_cmd(sc, IPW_CMD_SET_MSDU_TX_RATES, &data, sizeof data); 1953 if (error != 0) 1954 return error; 1955 1956 data = htole32(IPW_POWER_MODE_CAM); 1957 DPRINTF(("Setting power mode to %u\n", letoh32(data))); 1958 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1959 if (error != 0) 1960 return error; 1961 1962#ifndef IEEE80211_STA_ONLY 1963 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1964 data = htole32(32); /* default value */ 1965 DPRINTF(("Setting tx power index to %u\n", letoh32(data))); 1966 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1967 sizeof data); 1968 if (error != 0) 1969 return error; 1970 1971 data = htole32(ic->ic_lintval); 1972 DPRINTF(("Setting beacon interval to %u\n", letoh32(data))); 1973 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1974 sizeof data); 1975 if (error != 0) 1976 return error; 1977 } 1978#endif 1979 return 0; 1980} 1981 1982int 1983ipw_init(struct ifnet *ifp) 1984{ 1985 struct ipw_softc *sc = ifp->if_softc; 1986 struct ieee80211com *ic = &sc->sc_ic; 1987 struct ipw_firmware fw; 1988 int error; 1989 1990 ipw_stop(ifp, 0); 1991 1992 if ((error = ipw_reset(sc)) != 0) { 1993 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 1994 goto fail1; 1995 } 1996 1997 if ((error = ipw_read_firmware(sc, &fw)) != 0) { 1998 printf("%s: error %d, could not read firmware\n", 1999 sc->sc_dev.dv_xname, error); 2000 goto fail1; 2001 } 2002 if ((error = ipw_load_ucode(sc, fw.ucode, fw.ucode_size)) != 0) { 2003 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 2004 goto fail2; 2005 } 2006 2007 ipw_stop_master(sc); 2008 2009 /* 2010 * Setup tx, rx and status rings. 2011 */ 2012 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2013 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 2014 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 2015 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 2016 sc->txold = IPW_NTBD - 1; /* latest bd index ack by firmware */ 2017 sc->txcur = 0; /* bd index to write to */ 2018 sc->txfree = IPW_NTBD - 2; 2019 2020 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2021 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 2022 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 2023 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 2024 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 2025 2026 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 2027 sc->status_map->dm_segs[0].ds_addr); 2028 2029 if ((error = ipw_load_firmware(sc, fw.main, fw.main_size)) != 0) { 2030 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 2031 goto fail2; 2032 } 2033 sc->sc_flags |= IPW_FLAG_FW_INITED; 2034 free(fw.data, M_DEVBUF); 2035 fw.data = NULL; 2036 2037 /* retrieve information tables base addresses */ 2038 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2039 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2040 2041 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2042 2043 if ((error = ipw_config(sc)) != 0) { 2044 printf("%s: device configuration failed\n", 2045 sc->sc_dev.dv_xname); 2046 goto fail1; 2047 } 2048 2049 ifp->if_flags &= ~IFF_OACTIVE; 2050 ifp->if_flags |= IFF_RUNNING; 2051 2052 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2053 ieee80211_begin_scan(ifp); 2054 else 2055 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2056 2057 return 0; 2058 2059fail2: free(fw.data, M_DEVBUF); 2060 fw.data = NULL; 2061fail1: ipw_stop(ifp, 0); 2062 return error; 2063} 2064 2065void 2066ipw_stop(struct ifnet *ifp, int disable) 2067{ 2068 struct ipw_softc *sc = ifp->if_softc; 2069 struct ieee80211com *ic = &sc->sc_ic; 2070 int i; 2071 2072 ipw_stop_master(sc); 2073 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2074 2075 ifp->if_timer = 0; 2076 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2077 2078 /* 2079 * Release tx buffers. 2080 */ 2081 for (i = 0; i < IPW_NTBD; i++) 2082 ipw_release_sbd(sc, &sc->stbd_list[i]); 2083 2084 /* in case we were scanning, release the scan "lock" */ 2085 ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; 2086 2087 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2088} 2089 2090void 2091ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2092 bus_size_t count) 2093{ 2094 for (; count > 0; offset++, datap++, count--) { 2095 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2096 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2097 } 2098} 2099 2100void 2101ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2102 bus_size_t count) 2103{ 2104 for (; count > 0; offset++, datap++, count--) { 2105 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2106 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2107 } 2108} 2109 2110struct cfdriver ipw_cd = { 2111 NULL, "ipw", DV_IFNET 2112}; 2113