if_ipw.c revision 1.97
1/* $OpenBSD: if_ipw.c,v 1.97 2013/11/14 12:41:14 dlg Exp $ */ 2 3/*- 4 * Copyright (c) 2004-2008 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/* 21 * Driver for Intel PRO/Wireless 2100 802.11 network adapters. 22 */ 23 24#include "bpfilter.h" 25 26#include <sys/param.h> 27#include <sys/sockio.h> 28#include <sys/task.h> 29#include <sys/workq.h> 30#include <sys/mbuf.h> 31#include <sys/kernel.h> 32#include <sys/socket.h> 33#include <sys/systm.h> 34#include <sys/conf.h> 35#include <sys/device.h> 36 37#include <machine/bus.h> 38#include <machine/endian.h> 39#include <machine/intr.h> 40 41#include <dev/pci/pcireg.h> 42#include <dev/pci/pcivar.h> 43#include <dev/pci/pcidevs.h> 44 45#if NBPFILTER > 0 46#include <net/bpf.h> 47#endif 48#include <net/if.h> 49#include <net/if_arp.h> 50#include <net/if_dl.h> 51#include <net/if_media.h> 52#include <net/if_types.h> 53 54#include <netinet/in.h> 55#include <netinet/in_systm.h> 56#include <netinet/if_ether.h> 57#include <netinet/ip.h> 58 59#include <net80211/ieee80211_var.h> 60#include <net80211/ieee80211_radiotap.h> 61 62#include <dev/pci/if_ipwreg.h> 63#include <dev/pci/if_ipwvar.h> 64 65int ipw_match(struct device *, void *, void *); 66void ipw_attach(struct device *, struct device *, void *); 67int ipw_activate(struct device *, int); 68void ipw_resume(void *, void *); 69int ipw_dma_alloc(struct ipw_softc *); 70void ipw_release(struct ipw_softc *); 71int ipw_media_change(struct ifnet *); 72void ipw_media_status(struct ifnet *, struct ifmediareq *); 73int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 74uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 75void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 76void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 77void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 78 struct ipw_soft_bd *, struct ipw_soft_buf *); 79void ipw_notification_intr(struct ipw_softc *, 80 struct ipw_soft_buf *); 81void ipw_rx_intr(struct ipw_softc *); 82void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 83void ipw_tx_intr(struct ipw_softc *); 84int ipw_intr(void *); 85int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 86int ipw_send_mgmt(struct ieee80211com *, struct ieee80211_node *, 87 int, int, int); 88int ipw_tx_start(struct ifnet *, struct mbuf *, 89 struct ieee80211_node *); 90void ipw_start(struct ifnet *); 91void ipw_watchdog(struct ifnet *); 92int ipw_ioctl(struct ifnet *, u_long, caddr_t); 93uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 94void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 95int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 96 uint32_t *); 97void ipw_stop_master(struct ipw_softc *); 98int ipw_reset(struct ipw_softc *); 99int ipw_load_ucode(struct ipw_softc *, u_char *, int); 100int ipw_load_firmware(struct ipw_softc *, u_char *, int); 101int ipw_read_firmware(struct ipw_softc *, struct ipw_firmware *); 102void ipw_scan(void *, void *); 103void ipw_auth_and_assoc(void *, void *); 104int ipw_config(struct ipw_softc *); 105int ipw_init(struct ifnet *); 106void ipw_stop(struct ifnet *, int); 107void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 108 bus_size_t); 109void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 110 bus_size_t); 111 112static __inline uint8_t 113MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 114{ 115 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 116 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 117} 118 119static __inline uint32_t 120MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 121{ 122 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 123 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 124} 125 126#ifdef IPW_DEBUG 127#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 128#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 129int ipw_debug = 0; 130#else 131#define DPRINTF(x) 132#define DPRINTFN(n, x) 133#endif 134 135struct cfattach ipw_ca = { 136 sizeof (struct ipw_softc), ipw_match, ipw_attach, NULL, 137 ipw_activate 138}; 139 140int 141ipw_match(struct device *parent, void *match, void *aux) 142{ 143 struct pci_attach_args *pa = aux; 144 145 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 146 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 147 return 1; 148 149 return 0; 150} 151 152/* Base Address Register */ 153#define IPW_PCI_BAR0 0x10 154 155void 156ipw_attach(struct device *parent, struct device *self, void *aux) 157{ 158 struct ipw_softc *sc = (struct ipw_softc *)self; 159 struct ieee80211com *ic = &sc->sc_ic; 160 struct ifnet *ifp = &ic->ic_if; 161 struct pci_attach_args *pa = aux; 162 const char *intrstr; 163 bus_space_tag_t memt; 164 bus_space_handle_t memh; 165 bus_addr_t base; 166 pci_intr_handle_t ih; 167 pcireg_t data; 168 uint16_t val; 169 int error, i; 170 171 sc->sc_pct = pa->pa_pc; 172 sc->sc_pcitag = pa->pa_tag, 173 174 task_set(&sc->sc_resume_t, ipw_resume, sc, NULL); 175 176 /* clear device specific PCI configuration register 0x41 */ 177 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 178 data &= ~0x0000ff00; 179 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 180 181 /* map the register window */ 182 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 183 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 184 if (error != 0) { 185 printf(": can't map mem space\n"); 186 return; 187 } 188 189 sc->sc_st = memt; 190 sc->sc_sh = memh; 191 sc->sc_dmat = pa->pa_dmat; 192 193 /* disable interrupts */ 194 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 195 196 if (pci_intr_map(pa, &ih) != 0) { 197 printf(": can't map interrupt\n"); 198 return; 199 } 200 201 intrstr = pci_intr_string(sc->sc_pct, ih); 202 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 203 sc->sc_dev.dv_xname); 204 if (sc->sc_ih == NULL) { 205 printf(": can't establish interrupt"); 206 if (intrstr != NULL) 207 printf(" at %s", intrstr); 208 printf("\n"); 209 return; 210 } 211 printf(": %s", intrstr); 212 213 if (ipw_reset(sc) != 0) { 214 printf(": could not reset adapter\n"); 215 return; 216 } 217 218 if (ipw_dma_alloc(sc) != 0) { 219 printf(": failed to allocate DMA resources\n"); 220 return; 221 } 222 223 ic->ic_phytype = IEEE80211_T_DS; 224 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 225 ic->ic_state = IEEE80211_S_INIT; 226 227 /* set device capabilities */ 228 ic->ic_caps = 229#ifndef IEEE80211_STA_ONLY 230 IEEE80211_C_IBSS | /* IBSS mode supported */ 231#endif 232 IEEE80211_C_MONITOR | /* monitor mode supported */ 233 IEEE80211_C_TXPMGT | /* tx power management */ 234 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 235 IEEE80211_C_WEP | /* s/w WEP */ 236 IEEE80211_C_RSN | /* WPA/RSN */ 237 IEEE80211_C_SCANALL; /* h/w scanning */ 238 239 /* read MAC address from EEPROM */ 240 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 241 ic->ic_myaddr[0] = val >> 8; 242 ic->ic_myaddr[1] = val & 0xff; 243 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 244 ic->ic_myaddr[2] = val >> 8; 245 ic->ic_myaddr[3] = val & 0xff; 246 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 247 ic->ic_myaddr[4] = val >> 8; 248 ic->ic_myaddr[5] = val & 0xff; 249 250 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 251 252 /* set supported .11b rates */ 253 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 254 255 /* set supported .11b channels (1 through 14) */ 256 for (i = 1; i <= 14; i++) { 257 ic->ic_channels[i].ic_freq = 258 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 259 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 260 } 261 262 /* IBSS channel undefined for now */ 263 ic->ic_ibss_chan = &ic->ic_channels[0]; 264 265 ifp->if_softc = sc; 266 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 267 ifp->if_ioctl = ipw_ioctl; 268 ifp->if_start = ipw_start; 269 ifp->if_watchdog = ipw_watchdog; 270 IFQ_SET_READY(&ifp->if_snd); 271 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 272 273 if_attach(ifp); 274 ieee80211_ifattach(ifp); 275 /* override state transition machine */ 276 sc->sc_newstate = ic->ic_newstate; 277 ic->ic_newstate = ipw_newstate; 278 ic->ic_send_mgmt = ipw_send_mgmt; 279 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 280 281#if NBPFILTER > 0 282 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 283 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 284 285 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 286 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 287 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 288 289 sc->sc_txtap_len = sizeof sc->sc_txtapu; 290 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 291 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 292#endif 293} 294 295int 296ipw_activate(struct device *self, int act) 297{ 298 struct ipw_softc *sc = (struct ipw_softc *)self; 299 struct ifnet *ifp = &sc->sc_ic.ic_if; 300 301 switch (act) { 302 case DVACT_SUSPEND: 303 if (ifp->if_flags & IFF_RUNNING) 304 ipw_stop(ifp, 0); 305 break; 306 case DVACT_RESUME: 307 task_add(systq, &sc->sc_resume_t); 308 break; 309 } 310 311 return 0; 312} 313 314void 315ipw_resume(void *arg1, void *arg2) 316{ 317 struct ipw_softc *sc = arg1; 318 struct ifnet *ifp = &sc->sc_ic.ic_if; 319 pcireg_t data; 320 int s; 321 322 /* clear device specific PCI configuration register 0x41 */ 323 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 324 data &= ~0x0000ff00; 325 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 326 327 s = splnet(); 328 while (sc->sc_flags & IPW_FLAG_BUSY) 329 tsleep(&sc->sc_flags, PZERO, "ipwpwr", 0); 330 sc->sc_flags |= IPW_FLAG_BUSY; 331 332 if (ifp->if_flags & IFF_UP) 333 ipw_init(ifp); 334 335 sc->sc_flags &= ~IPW_FLAG_BUSY; 336 wakeup(&sc->sc_flags); 337 splx(s); 338} 339 340int 341ipw_dma_alloc(struct ipw_softc *sc) 342{ 343 struct ipw_soft_bd *sbd; 344 struct ipw_soft_hdr *shdr; 345 struct ipw_soft_buf *sbuf; 346 int i, nsegs, error; 347 348 /* 349 * Allocate and map tx ring. 350 */ 351 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 352 BUS_DMA_NOWAIT, &sc->tbd_map); 353 if (error != 0) { 354 printf("%s: could not create tx ring DMA map\n", 355 sc->sc_dev.dv_xname); 356 goto fail; 357 } 358 359 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 360 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 361 if (error != 0) { 362 printf("%s: could not allocate tx ring DMA memory\n", 363 sc->sc_dev.dv_xname); 364 goto fail; 365 } 366 367 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 368 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 369 if (error != 0) { 370 printf("%s: can't map tx ring DMA memory\n", 371 sc->sc_dev.dv_xname); 372 goto fail; 373 } 374 375 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 376 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 377 if (error != 0) { 378 printf("%s: could not load tx ring DMA map\n", 379 sc->sc_dev.dv_xname); 380 goto fail; 381 } 382 383 /* 384 * Allocate and map rx ring. 385 */ 386 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 387 BUS_DMA_NOWAIT, &sc->rbd_map); 388 if (error != 0) { 389 printf("%s: could not create rx ring DMA map\n", 390 sc->sc_dev.dv_xname); 391 goto fail; 392 } 393 394 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 395 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 396 if (error != 0) { 397 printf("%s: could not allocate rx ring DMA memory\n", 398 sc->sc_dev.dv_xname); 399 goto fail; 400 } 401 402 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 403 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 404 if (error != 0) { 405 printf("%s: can't map rx ring DMA memory\n", 406 sc->sc_dev.dv_xname); 407 goto fail; 408 } 409 410 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 411 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 412 if (error != 0) { 413 printf("%s: could not load tx ring DMA map\n", 414 sc->sc_dev.dv_xname); 415 goto fail; 416 } 417 418 /* 419 * Allocate and map status ring. 420 */ 421 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 422 0, BUS_DMA_NOWAIT, &sc->status_map); 423 if (error != 0) { 424 printf("%s: could not create status ring DMA map\n", 425 sc->sc_dev.dv_xname); 426 goto fail; 427 } 428 429 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 430 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 431 if (error != 0) { 432 printf("%s: could not allocate status ring DMA memory\n", 433 sc->sc_dev.dv_xname); 434 goto fail; 435 } 436 437 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 438 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 439 if (error != 0) { 440 printf("%s: can't map status ring DMA memory\n", 441 sc->sc_dev.dv_xname); 442 goto fail; 443 } 444 445 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 446 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 447 if (error != 0) { 448 printf("%s: could not load status ring DMA map\n", 449 sc->sc_dev.dv_xname); 450 goto fail; 451 } 452 453 /* 454 * Allocate command DMA map. 455 */ 456 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 457 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 458 if (error != 0) { 459 printf("%s: could not create command DMA map\n", 460 sc->sc_dev.dv_xname); 461 goto fail; 462 } 463 464 /* 465 * Allocate headers DMA maps. 466 */ 467 SLIST_INIT(&sc->free_shdr); 468 for (i = 0; i < IPW_NDATA; i++) { 469 shdr = &sc->shdr_list[i]; 470 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_hdr), 471 1, sizeof (struct ipw_hdr), 0, BUS_DMA_NOWAIT, &shdr->map); 472 if (error != 0) { 473 printf("%s: could not create header DMA map\n", 474 sc->sc_dev.dv_xname); 475 goto fail; 476 } 477 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 478 } 479 480 /* 481 * Allocate tx buffers DMA maps. 482 */ 483 SLIST_INIT(&sc->free_sbuf); 484 for (i = 0; i < IPW_NDATA; i++) { 485 sbuf = &sc->tx_sbuf_list[i]; 486 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, IPW_MAX_NSEG, 487 MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 488 if (error != 0) { 489 printf("%s: could not create tx DMA map\n", 490 sc->sc_dev.dv_xname); 491 goto fail; 492 } 493 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 494 } 495 496 /* 497 * Initialize tx ring. 498 */ 499 for (i = 0; i < IPW_NTBD; i++) { 500 sbd = &sc->stbd_list[i]; 501 sbd->bd = &sc->tbd_list[i]; 502 sbd->type = IPW_SBD_TYPE_NOASSOC; 503 } 504 505 /* 506 * Pre-allocate rx buffers and DMA maps. 507 */ 508 for (i = 0; i < IPW_NRBD; i++) { 509 sbd = &sc->srbd_list[i]; 510 sbuf = &sc->rx_sbuf_list[i]; 511 sbd->bd = &sc->rbd_list[i]; 512 513 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 514 if (sbuf->m == NULL) { 515 printf("%s: could not allocate rx mbuf\n", 516 sc->sc_dev.dv_xname); 517 error = ENOMEM; 518 goto fail; 519 } 520 MCLGET(sbuf->m, M_DONTWAIT); 521 if (!(sbuf->m->m_flags & M_EXT)) { 522 m_freem(sbuf->m); 523 printf("%s: could not allocate rx mbuf cluster\n", 524 sc->sc_dev.dv_xname); 525 error = ENOMEM; 526 goto fail; 527 } 528 529 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 530 0, BUS_DMA_NOWAIT, &sbuf->map); 531 if (error != 0) { 532 printf("%s: could not create rx DMA map\n", 533 sc->sc_dev.dv_xname); 534 goto fail; 535 } 536 537 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 538 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 539 if (error != 0) { 540 printf("%s: can't map rx DMA memory\n", 541 sc->sc_dev.dv_xname); 542 goto fail; 543 } 544 545 sbd->type = IPW_SBD_TYPE_DATA; 546 sbd->priv = sbuf; 547 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 548 sbd->bd->len = htole32(MCLBYTES); 549 } 550 551 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 552 BUS_DMASYNC_PREWRITE); 553 554 return 0; 555 556fail: ipw_release(sc); 557 return error; 558} 559 560void 561ipw_release(struct ipw_softc *sc) 562{ 563 struct ipw_soft_buf *sbuf; 564 int i; 565 566 if (sc->tbd_map != NULL) { 567 if (sc->tbd_list != NULL) { 568 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 569 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 570 IPW_TBD_SZ); 571 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 572 } 573 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 574 } 575 576 if (sc->rbd_map != NULL) { 577 if (sc->rbd_list != NULL) { 578 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 579 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 580 IPW_RBD_SZ); 581 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 582 } 583 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 584 } 585 586 if (sc->status_map != NULL) { 587 if (sc->status_list != NULL) { 588 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 589 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 590 IPW_RBD_SZ); 591 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 592 } 593 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 594 } 595 596 if (sc->cmd_map != NULL) 597 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 598 599 for (i = 0; i < IPW_NDATA; i++) 600 bus_dmamap_destroy(sc->sc_dmat, sc->shdr_list[i].map); 601 602 for (i = 0; i < IPW_NDATA; i++) 603 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 604 605 for (i = 0; i < IPW_NRBD; i++) { 606 sbuf = &sc->rx_sbuf_list[i]; 607 if (sbuf->map != NULL) { 608 if (sbuf->m != NULL) { 609 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 610 m_freem(sbuf->m); 611 } 612 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 613 } 614 } 615} 616 617int 618ipw_media_change(struct ifnet *ifp) 619{ 620 int error; 621 622 error = ieee80211_media_change(ifp); 623 if (error != ENETRESET) 624 return error; 625 626 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 627 ipw_init(ifp); 628 629 return 0; 630} 631 632void 633ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 634{ 635 struct ipw_softc *sc = ifp->if_softc; 636 struct ieee80211com *ic = &sc->sc_ic; 637 static const struct { 638 uint32_t val; 639 int rate; 640 } rates[] = { 641 { IPW_RATE_DS1, 2 }, 642 { IPW_RATE_DS2, 4 }, 643 { IPW_RATE_DS5, 11 }, 644 { IPW_RATE_DS11, 22 }, 645 }; 646 uint32_t val; 647 int rate, i; 648 649 imr->ifm_status = IFM_AVALID; 650 imr->ifm_active = IFM_IEEE80211; 651 if (ic->ic_state == IEEE80211_S_RUN) 652 imr->ifm_status |= IFM_ACTIVE; 653 654 /* read current transmission rate from adapter */ 655 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 656 val &= 0xf; 657 658 /* convert rate to 802.11 rate */ 659 for (i = 0; i < nitems(rates) && rates[i].val != val; i++); 660 rate = (i < nitems(rates)) ? rates[i].rate : 0; 661 662 imr->ifm_active |= IFM_IEEE80211_11B; 663 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 664 switch (ic->ic_opmode) { 665 case IEEE80211_M_STA: 666 break; 667#ifndef IEEE80211_STA_ONLY 668 case IEEE80211_M_IBSS: 669 imr->ifm_active |= IFM_IEEE80211_IBSS; 670 break; 671#endif 672 case IEEE80211_M_MONITOR: 673 imr->ifm_active |= IFM_IEEE80211_MONITOR; 674 break; 675 default: 676 /* should not get there */ 677 break; 678 } 679} 680 681int 682ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 683{ 684 struct ipw_softc *sc = ic->ic_softc; 685 int error; 686 687 switch (nstate) { 688 case IEEE80211_S_SCAN: 689 error = workq_add_task(NULL, 0, ipw_scan, sc, NULL); 690 if (error != 0) 691 return error; 692 break; 693 694 case IEEE80211_S_AUTH: 695 error = workq_add_task(NULL, 0, ipw_auth_and_assoc, sc, NULL); 696 if (error != 0) 697 return error; 698 break; 699 700 case IEEE80211_S_RUN: 701 case IEEE80211_S_INIT: 702 case IEEE80211_S_ASSOC: 703 /* nothing to do */ 704 break; 705 } 706 707 ic->ic_state = nstate; 708 return 0; 709} 710 711/* 712 * Read 16 bits at address 'addr' from the Microwire EEPROM. 713 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 714 */ 715uint16_t 716ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 717{ 718 uint32_t tmp; 719 uint16_t val; 720 int n; 721 722 /* clock C once before the first command */ 723 IPW_EEPROM_CTL(sc, 0); 724 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 725 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 726 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 727 728 /* write start bit (1) */ 729 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 730 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 731 732 /* write READ opcode (10) */ 733 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 734 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 735 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 736 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 737 738 /* write address A7-A0 */ 739 for (n = 7; n >= 0; n--) { 740 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 741 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 742 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 743 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 744 } 745 746 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 747 748 /* read data Q15-Q0 */ 749 val = 0; 750 for (n = 15; n >= 0; n--) { 751 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 752 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 753 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 754 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 755 } 756 757 IPW_EEPROM_CTL(sc, 0); 758 759 /* clear Chip Select and clock C */ 760 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 761 IPW_EEPROM_CTL(sc, 0); 762 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 763 764 return val; 765} 766 767void 768ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 769{ 770 struct ipw_cmd *cmd; 771 772 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 773 BUS_DMASYNC_POSTREAD); 774 775 cmd = mtod(sbuf->m, struct ipw_cmd *); 776 777 DPRINTFN(2, ("received command ack type=%u,status=%u\n", 778 letoh32(cmd->type), letoh32(cmd->status))); 779 780 wakeup(&sc->cmd); 781} 782 783void 784ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 785{ 786 struct ieee80211com *ic = &sc->sc_ic; 787 struct ifnet *ifp = &ic->ic_if; 788 uint32_t state; 789 790 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 791 BUS_DMASYNC_POSTREAD); 792 793 state = letoh32(*mtod(sbuf->m, uint32_t *)); 794 795 DPRINTFN(2, ("firmware state changed to 0x%x\n", state)); 796 797 switch (state) { 798 case IPW_STATE_ASSOCIATED: 799 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 800 break; 801 802 case IPW_STATE_SCANNING: 803 if (ic->ic_state == IEEE80211_S_RUN) 804 ieee80211_begin_scan(ifp); 805 break; 806 807 case IPW_STATE_SCAN_COMPLETE: 808 if (ic->ic_state == IEEE80211_S_SCAN) 809 ieee80211_end_scan(ifp); 810 break; 811 812 case IPW_STATE_ASSOCIATION_LOST: 813 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 814 break; 815 816 case IPW_STATE_DISABLED: 817 wakeup(sc); 818 break; 819 820 case IPW_STATE_RADIO_DISABLED: 821 ifp->if_flags &= ~IFF_UP; 822 ipw_stop(&ic->ic_if, 1); 823 break; 824 } 825} 826 827void 828ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 829 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 830{ 831 struct ieee80211com *ic = &sc->sc_ic; 832 struct ifnet *ifp = &ic->ic_if; 833 struct mbuf *mnew, *m; 834 struct ieee80211_frame *wh; 835 struct ieee80211_rxinfo rxi; 836 struct ieee80211_node *ni; 837 int error; 838 839 DPRINTFN(5, ("received data frame len=%u,rssi=%u\n", 840 letoh32(status->len), status->rssi)); 841 842 /* 843 * Try to allocate a new mbuf for this ring element and load it before 844 * processing the current mbuf. If the ring element cannot be loaded, 845 * drop the received packet and reuse the old mbuf. In the unlikely 846 * case that the old mbuf can't be reloaded either, explicitly panic. 847 */ 848 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 849 if (mnew == NULL) { 850 ifp->if_ierrors++; 851 return; 852 } 853 MCLGET(mnew, M_DONTWAIT); 854 if (!(mnew->m_flags & M_EXT)) { 855 m_freem(mnew); 856 ifp->if_ierrors++; 857 return; 858 } 859 860 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 861 BUS_DMASYNC_POSTREAD); 862 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 863 864 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(mnew, void *), 865 MCLBYTES, NULL, BUS_DMA_NOWAIT); 866 if (error != 0) { 867 m_freem(mnew); 868 869 /* try to reload the old mbuf */ 870 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 871 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 872 if (error != 0) { 873 /* very unlikely that it will fail... */ 874 panic("%s: could not load old rx mbuf", 875 sc->sc_dev.dv_xname); 876 } 877 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 878 ifp->if_ierrors++; 879 return; 880 } 881 882 m = sbuf->m; 883 sbuf->m = mnew; 884 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 885 886 /* finalize mbuf */ 887 m->m_pkthdr.rcvif = ifp; 888 m->m_pkthdr.len = m->m_len = letoh32(status->len); 889 890#if NBPFILTER > 0 891 if (sc->sc_drvbpf != NULL) { 892 struct mbuf mb; 893 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 894 895 tap->wr_flags = 0; 896 tap->wr_antsignal = status->rssi; 897 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 898 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 899 900 mb.m_data = (caddr_t)tap; 901 mb.m_len = sc->sc_rxtap_len; 902 mb.m_next = m; 903 mb.m_nextpkt = NULL; 904 mb.m_type = 0; 905 mb.m_flags = 0; 906 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 907 } 908#endif 909 910 wh = mtod(m, struct ieee80211_frame *); 911 ni = ieee80211_find_rxnode(ic, wh); 912 913 /* send the frame to the upper layer */ 914 rxi.rxi_flags = 0; 915 rxi.rxi_rssi = status->rssi; 916 rxi.rxi_tstamp = 0; /* unused */ 917 ieee80211_input(ifp, m, ni, &rxi); 918 919 ieee80211_release_node(ic, ni); 920} 921 922void 923ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 924{ 925 DPRINTFN(2, ("received notification\n")); 926} 927 928void 929ipw_rx_intr(struct ipw_softc *sc) 930{ 931 struct ipw_status *status; 932 struct ipw_soft_bd *sbd; 933 struct ipw_soft_buf *sbuf; 934 uint32_t r, i; 935 936 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 937 938 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 939 940 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 941 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 942 BUS_DMASYNC_POSTREAD); 943 944 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 945 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 946 BUS_DMASYNC_POSTREAD); 947 948 status = &sc->status_list[i]; 949 sbd = &sc->srbd_list[i]; 950 sbuf = sbd->priv; 951 952 switch (letoh16(status->code) & 0xf) { 953 case IPW_STATUS_CODE_COMMAND: 954 ipw_command_intr(sc, sbuf); 955 break; 956 957 case IPW_STATUS_CODE_NEWSTATE: 958 ipw_newstate_intr(sc, sbuf); 959 break; 960 961 case IPW_STATUS_CODE_DATA_802_3: 962 case IPW_STATUS_CODE_DATA_802_11: 963 ipw_data_intr(sc, status, sbd, sbuf); 964 break; 965 966 case IPW_STATUS_CODE_NOTIFICATION: 967 ipw_notification_intr(sc, sbuf); 968 break; 969 970 default: 971 printf("%s: unknown status code %u\n", 972 sc->sc_dev.dv_xname, letoh16(status->code)); 973 } 974 sbd->bd->flags = 0; 975 976 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 977 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 978 BUS_DMASYNC_PREWRITE); 979 } 980 981 /* tell the firmware what we have processed */ 982 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 983 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 984} 985 986void 987ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 988{ 989 struct ieee80211com *ic = &sc->sc_ic; 990 struct ipw_soft_hdr *shdr; 991 struct ipw_soft_buf *sbuf; 992 993 switch (sbd->type) { 994 case IPW_SBD_TYPE_COMMAND: 995 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 996 break; 997 998 case IPW_SBD_TYPE_HEADER: 999 shdr = sbd->priv; 1000 bus_dmamap_unload(sc->sc_dmat, shdr->map); 1001 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 1002 break; 1003 1004 case IPW_SBD_TYPE_DATA: 1005 sbuf = sbd->priv; 1006 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1007 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1008 1009 m_freem(sbuf->m); 1010 1011 if (sbuf->ni != NULL) 1012 ieee80211_release_node(ic, sbuf->ni); 1013 1014 /* kill watchdog timer */ 1015 sc->sc_tx_timer = 0; 1016 break; 1017 } 1018 sbd->type = IPW_SBD_TYPE_NOASSOC; 1019} 1020 1021void 1022ipw_tx_intr(struct ipw_softc *sc) 1023{ 1024 struct ifnet *ifp = &sc->sc_ic.ic_if; 1025 struct ipw_soft_bd *sbd; 1026 uint32_t r, i; 1027 1028 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 1029 1030 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1031 sbd = &sc->stbd_list[i]; 1032 1033 if (sbd->type == IPW_SBD_TYPE_DATA) 1034 ifp->if_opackets++; 1035 1036 ipw_release_sbd(sc, sbd); 1037 sc->txfree++; 1038 } 1039 1040 /* remember what the firmware has processed */ 1041 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1042 1043 /* call start() since some buffer descriptors have been released */ 1044 ifp->if_flags &= ~IFF_OACTIVE; 1045 (*ifp->if_start)(ifp); 1046} 1047 1048int 1049ipw_intr(void *arg) 1050{ 1051 struct ipw_softc *sc = arg; 1052 struct ifnet *ifp = &sc->sc_ic.ic_if; 1053 uint32_t r; 1054 1055 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) 1056 return 0; 1057 1058 /* disable interrupts */ 1059 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1060 1061 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1062 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 1063 ifp->if_flags &= ~IFF_UP; 1064 ipw_stop(ifp, 1); 1065 return 1; 1066 } 1067 1068 if (r & IPW_INTR_FW_INIT_DONE) 1069 wakeup(sc); 1070 1071 if (r & IPW_INTR_RX_TRANSFER) 1072 ipw_rx_intr(sc); 1073 1074 if (r & IPW_INTR_TX_TRANSFER) 1075 ipw_tx_intr(sc); 1076 1077 /* acknowledge interrupts */ 1078 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1079 1080 /* re-enable interrupts */ 1081 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1082 1083 return 1; 1084} 1085 1086int 1087ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1088{ 1089 struct ipw_soft_bd *sbd; 1090 int s, error; 1091 1092 s = splnet(); 1093 1094 sc->cmd.type = htole32(type); 1095 sc->cmd.subtype = htole32(0); 1096 sc->cmd.len = htole32(len); 1097 sc->cmd.seq = htole32(0); 1098 if (data != NULL) 1099 bcopy(data, sc->cmd.data, len); 1100 1101 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 1102 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 1103 if (error != 0) { 1104 printf("%s: can't map command DMA memory\n", 1105 sc->sc_dev.dv_xname); 1106 splx(s); 1107 return error; 1108 } 1109 1110 sbd = &sc->stbd_list[sc->txcur]; 1111 sbd->type = IPW_SBD_TYPE_COMMAND; 1112 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1113 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1114 sbd->bd->nfrag = 1; 1115 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1116 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1117 1118 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1119 BUS_DMASYNC_PREWRITE); 1120 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1121 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1122 BUS_DMASYNC_PREWRITE); 1123 1124 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1125 sc->txfree--; 1126 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1127 1128 DPRINTFN(2, ("sending command type=%u,len=%u\n", type, len)); 1129 1130 /* wait at most one second for command to complete */ 1131 error = tsleep(&sc->cmd, 0, "ipwcmd", hz); 1132 splx(s); 1133 1134 return error; 1135} 1136 1137/* ARGSUSED */ 1138int 1139ipw_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type, 1140 int arg1, int arg2) 1141{ 1142 return EOPNOTSUPP; 1143} 1144 1145int 1146ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 1147{ 1148 struct ipw_softc *sc = ifp->if_softc; 1149 struct ieee80211com *ic = &sc->sc_ic; 1150 struct ieee80211_frame *wh; 1151 struct ieee80211_key *k; 1152 struct mbuf *m1; 1153 struct ipw_soft_bd *sbd; 1154 struct ipw_soft_hdr *shdr; 1155 struct ipw_soft_buf *sbuf; 1156 int error, i; 1157 1158 wh = mtod(m, struct ieee80211_frame *); 1159 1160 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1161 k = ieee80211_get_txkey(ic, wh, ni); 1162 1163 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1164 return ENOBUFS; 1165 1166 /* packet header may have moved, reset our local pointer */ 1167 wh = mtod(m, struct ieee80211_frame *); 1168 } 1169 1170#if NBPFILTER > 0 1171 if (sc->sc_drvbpf != NULL) { 1172 struct mbuf mb; 1173 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1174 1175 tap->wt_flags = 0; 1176 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1177 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1178 1179 mb.m_data = (caddr_t)tap; 1180 mb.m_len = sc->sc_txtap_len; 1181 mb.m_next = m; 1182 mb.m_nextpkt = NULL; 1183 mb.m_type = 0; 1184 mb.m_flags = 0; 1185 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1186 } 1187#endif 1188 1189 shdr = SLIST_FIRST(&sc->free_shdr); 1190 sbuf = SLIST_FIRST(&sc->free_sbuf); 1191 1192 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1193 shdr->hdr.subtype = htole32(0); 1194 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) ? 1 : 0; 1195 shdr->hdr.encrypt = 0; 1196 shdr->hdr.keyidx = 0; 1197 shdr->hdr.keysz = 0; 1198 shdr->hdr.fragmentsz = htole16(0); 1199 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1200 if (ic->ic_opmode == IEEE80211_M_STA) 1201 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1202 else 1203 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1204 1205 /* trim IEEE802.11 header */ 1206 m_adj(m, sizeof (struct ieee80211_frame)); 1207 1208 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 1209 if (error != 0 && error != EFBIG) { 1210 printf("%s: can't map mbuf (error %d)\n", 1211 sc->sc_dev.dv_xname, error); 1212 m_freem(m); 1213 return error; 1214 } 1215 if (error != 0) { 1216 /* too many fragments, linearize */ 1217 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1218 if (m1 == NULL) { 1219 m_freem(m); 1220 return ENOBUFS; 1221 } 1222 if (m->m_pkthdr.len > MHLEN) { 1223 MCLGET(m1, M_DONTWAIT); 1224 if (!(m1->m_flags & M_EXT)) { 1225 m_freem(m); 1226 m_freem(m1); 1227 return ENOBUFS; 1228 } 1229 } 1230 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, caddr_t)); 1231 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 1232 m_freem(m); 1233 m = m1; 1234 1235 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, 1236 BUS_DMA_NOWAIT); 1237 if (error != 0) { 1238 printf("%s: can't map mbuf (error %d)\n", 1239 sc->sc_dev.dv_xname, error); 1240 m_freem(m); 1241 return error; 1242 } 1243 } 1244 1245 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 1246 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 1247 if (error != 0) { 1248 printf("%s: can't map header DMA memory (error %d)\n", 1249 sc->sc_dev.dv_xname, error); 1250 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1251 m_freem(m); 1252 return error; 1253 } 1254 1255 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1256 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1257 1258 sbd = &sc->stbd_list[sc->txcur]; 1259 sbd->type = IPW_SBD_TYPE_HEADER; 1260 sbd->priv = shdr; 1261 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 1262 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1263 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1264 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1265 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1266 1267 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1268 sc->txcur * sizeof (struct ipw_bd), 1269 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1270 1271 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1272 sc->txfree--; 1273 1274 sbuf->m = m; 1275 sbuf->ni = ni; 1276 1277 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1278 sbd = &sc->stbd_list[sc->txcur]; 1279 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1280 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1281 sbd->bd->nfrag = 0; /* used only in first bd */ 1282 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1283 if (i == sbuf->map->dm_nsegs - 1) { 1284 sbd->type = IPW_SBD_TYPE_DATA; 1285 sbd->priv = sbuf; 1286 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1287 } else { 1288 sbd->type = IPW_SBD_TYPE_NOASSOC; 1289 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1290 } 1291 1292 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1293 sc->txcur * sizeof (struct ipw_bd), 1294 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1295 1296 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1297 sc->txfree--; 1298 } 1299 1300 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1301 BUS_DMASYNC_PREWRITE); 1302 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 1303 BUS_DMASYNC_PREWRITE); 1304 1305 /* inform firmware about this new packet */ 1306 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1307 1308 return 0; 1309} 1310 1311void 1312ipw_start(struct ifnet *ifp) 1313{ 1314 struct ipw_softc *sc = ifp->if_softc; 1315 struct ieee80211com *ic = &sc->sc_ic; 1316 struct ieee80211_node *ni; 1317 struct mbuf *m; 1318 1319 if (ic->ic_state != IEEE80211_S_RUN) 1320 return; 1321 1322 for (;;) { 1323 IFQ_POLL(&ifp->if_snd, m); 1324 if (m == NULL) 1325 break; 1326 1327 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1328 ifp->if_flags |= IFF_OACTIVE; 1329 break; 1330 } 1331 IFQ_DEQUEUE(&ifp->if_snd, m); 1332#if NBPFILTER > 0 1333 if (ifp->if_bpf != NULL) 1334 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1335#endif 1336 m = ieee80211_encap(ifp, m, &ni); 1337 if (m == NULL) 1338 continue; 1339#if NBPFILTER > 0 1340 if (ic->ic_rawbpf != NULL) 1341 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1342#endif 1343 if (ipw_tx_start(ifp, m, ni) != 0) { 1344 if (ni != NULL) 1345 ieee80211_release_node(ic, ni); 1346 ifp->if_oerrors++; 1347 break; 1348 } 1349 1350 /* start watchdog timer */ 1351 sc->sc_tx_timer = 5; 1352 ifp->if_timer = 1; 1353 } 1354} 1355 1356void 1357ipw_watchdog(struct ifnet *ifp) 1358{ 1359 struct ipw_softc *sc = ifp->if_softc; 1360 1361 ifp->if_timer = 0; 1362 1363 if (sc->sc_tx_timer > 0) { 1364 if (--sc->sc_tx_timer == 0) { 1365 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1366 ifp->if_flags &= ~IFF_UP; 1367 ipw_stop(ifp, 1); 1368 ifp->if_oerrors++; 1369 return; 1370 } 1371 ifp->if_timer = 1; 1372 } 1373 1374 ieee80211_watchdog(ifp); 1375} 1376 1377int 1378ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1379{ 1380 struct ipw_softc *sc = ifp->if_softc; 1381 struct ieee80211com *ic = &sc->sc_ic; 1382 struct ifaddr *ifa; 1383 struct ifreq *ifr; 1384 int s, error = 0; 1385 1386 s = splnet(); 1387 /* 1388 * Prevent processes from entering this function while another 1389 * process is tsleep'ing in it. 1390 */ 1391 while ((sc->sc_flags & IPW_FLAG_BUSY) && error == 0) 1392 error = tsleep(&sc->sc_flags, PCATCH, "ipwioc", 0); 1393 if (error != 0) { 1394 splx(s); 1395 return error; 1396 } 1397 sc->sc_flags |= IPW_FLAG_BUSY; 1398 1399 switch (cmd) { 1400 case SIOCSIFADDR: 1401 ifa = (struct ifaddr *)data; 1402 ifp->if_flags |= IFF_UP; 1403#ifdef INET 1404 if (ifa->ifa_addr->sa_family == AF_INET) 1405 arp_ifinit(&ic->ic_ac, ifa); 1406#endif 1407 /* FALLTHROUGH */ 1408 case SIOCSIFFLAGS: 1409 if (ifp->if_flags & IFF_UP) { 1410 if (!(ifp->if_flags & IFF_RUNNING)) 1411 ipw_init(ifp); 1412 } else { 1413 if (ifp->if_flags & IFF_RUNNING) 1414 ipw_stop(ifp, 1); 1415 } 1416 break; 1417 1418 case SIOCADDMULTI: 1419 case SIOCDELMULTI: 1420 ifr = (struct ifreq *)data; 1421 error = (cmd == SIOCADDMULTI) ? 1422 ether_addmulti(ifr, &ic->ic_ac) : 1423 ether_delmulti(ifr, &ic->ic_ac); 1424 1425 if (error == ENETRESET) 1426 error = 0; 1427 break; 1428 1429 case SIOCG80211TXPOWER: 1430 /* 1431 * If the hardware radio transmitter switch is off, report a 1432 * tx power of IEEE80211_TXPOWER_MIN to indicate that radio 1433 * transmitter is killed. 1434 */ 1435 ((struct ieee80211_txpower *)data)->i_val = 1436 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 1437 IEEE80211_TXPOWER_MIN : sc->sc_ic.ic_txpower; 1438 break; 1439 1440 default: 1441 error = ieee80211_ioctl(ifp, cmd, data); 1442 } 1443 1444 if (error == ENETRESET) { 1445 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1446 (IFF_UP | IFF_RUNNING)) 1447 ipw_init(ifp); 1448 error = 0; 1449 } 1450 1451 sc->sc_flags &= ~IPW_FLAG_BUSY; 1452 wakeup(&sc->sc_flags); 1453 splx(s); 1454 return error; 1455} 1456 1457uint32_t 1458ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1459{ 1460 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1461} 1462 1463void 1464ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1465{ 1466 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1467} 1468 1469int 1470ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1471{ 1472 uint32_t addr, info; 1473 uint16_t count, size; 1474 uint32_t total; 1475 1476 /* addr[4] + count[2] + size[2] */ 1477 addr = MEM_READ_4(sc, sc->table2_base + off); 1478 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1479 1480 count = info >> 16; 1481 size = info & 0xffff; 1482 total = count * size; 1483 1484 if (total > *len) { 1485 *len = total; 1486 return EINVAL; 1487 } 1488 *len = total; 1489 ipw_read_mem_1(sc, addr, buf, total); 1490 1491 return 0; 1492} 1493 1494void 1495ipw_stop_master(struct ipw_softc *sc) 1496{ 1497 uint32_t tmp; 1498 int ntries; 1499 1500 /* disable interrupts */ 1501 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1502 1503 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1504 for (ntries = 0; ntries < 50; ntries++) { 1505 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1506 break; 1507 DELAY(10); 1508 } 1509 if (ntries == 50) 1510 printf("%s: timeout waiting for master\n", 1511 sc->sc_dev.dv_xname); 1512 1513 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1514 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1515 1516 sc->sc_flags &= ~IPW_FLAG_FW_INITED; 1517} 1518 1519int 1520ipw_reset(struct ipw_softc *sc) 1521{ 1522 uint32_t tmp; 1523 int ntries; 1524 1525 ipw_stop_master(sc); 1526 1527 /* move adapter to D0 state */ 1528 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1529 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1530 1531 /* wait for clock stabilization */ 1532 for (ntries = 0; ntries < 1000; ntries++) { 1533 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1534 break; 1535 DELAY(200); 1536 } 1537 if (ntries == 1000) 1538 return EIO; 1539 1540 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1541 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1542 1543 DELAY(10); 1544 1545 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1546 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1547 1548 return 0; 1549} 1550 1551int 1552ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1553{ 1554 int ntries; 1555 1556 /* voodoo from the Intel Linux driver */ 1557 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1558 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1559 1560 MEM_WRITE_2(sc, 0x220000, 0x0703); 1561 MEM_WRITE_2(sc, 0x220000, 0x0707); 1562 1563 MEM_WRITE_1(sc, 0x210014, 0x72); 1564 MEM_WRITE_1(sc, 0x210014, 0x72); 1565 1566 MEM_WRITE_1(sc, 0x210000, 0x40); 1567 MEM_WRITE_1(sc, 0x210000, 0x00); 1568 MEM_WRITE_1(sc, 0x210000, 0x40); 1569 1570 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1571 1572 MEM_WRITE_1(sc, 0x210000, 0x00); 1573 MEM_WRITE_1(sc, 0x210000, 0x00); 1574 MEM_WRITE_1(sc, 0x210000, 0x80); 1575 1576 MEM_WRITE_2(sc, 0x220000, 0x0703); 1577 MEM_WRITE_2(sc, 0x220000, 0x0707); 1578 1579 MEM_WRITE_1(sc, 0x210014, 0x72); 1580 MEM_WRITE_1(sc, 0x210014, 0x72); 1581 1582 MEM_WRITE_1(sc, 0x210000, 0x00); 1583 MEM_WRITE_1(sc, 0x210000, 0x80); 1584 1585 for (ntries = 0; ntries < 100; ntries++) { 1586 if (MEM_READ_1(sc, 0x210000) & 1) 1587 break; 1588 DELAY(1000); 1589 } 1590 if (ntries == 100) { 1591 printf("%s: timeout waiting for ucode to initialize\n", 1592 sc->sc_dev.dv_xname); 1593 return EIO; 1594 } 1595 1596 MEM_WRITE_4(sc, 0x3000e0, 0); 1597 1598 return 0; 1599} 1600 1601/* set of macros to handle unaligned little endian data in firmware image */ 1602#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1603#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1604int 1605ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1606{ 1607 u_char *p, *end; 1608 uint32_t tmp, dst; 1609 uint16_t len; 1610 int error; 1611 1612 p = fw; 1613 end = fw + size; 1614 while (p < end) { 1615 if (p + 6 > end) 1616 return EINVAL; 1617 1618 dst = GETLE32(p); p += 4; 1619 len = GETLE16(p); p += 2; 1620 1621 if (p + len > end) 1622 return EINVAL; 1623 1624 ipw_write_mem_1(sc, dst, p, len); 1625 p += len; 1626 } 1627 1628 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1629 IPW_IO_LED_OFF); 1630 1631 /* allow interrupts so we know when the firmware is inited */ 1632 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1633 1634 /* tell the adapter to initialize the firmware */ 1635 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1636 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1637 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1638 1639 /* wait at most one second for firmware initialization to complete */ 1640 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1641 printf("%s: timeout waiting for firmware initialization to " 1642 "complete\n", sc->sc_dev.dv_xname); 1643 return error; 1644 } 1645 1646 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1647 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1648 IPW_IO_GPIO3_MASK); 1649 1650 return 0; 1651} 1652 1653int 1654ipw_read_firmware(struct ipw_softc *sc, struct ipw_firmware *fw) 1655{ 1656 const struct ipw_firmware_hdr *hdr; 1657 const char *name; 1658 size_t size; 1659 int error; 1660 1661 switch (sc->sc_ic.ic_opmode) { 1662 case IEEE80211_M_STA: 1663 name = "ipw-bss"; 1664 break; 1665#ifndef IEEE80211_STA_ONLY 1666 case IEEE80211_M_IBSS: 1667 name = "ipw-ibss"; 1668 break; 1669#endif 1670 case IEEE80211_M_MONITOR: 1671 name = "ipw-monitor"; 1672 break; 1673 default: 1674 /* should not get there */ 1675 return ENODEV; 1676 } 1677 if ((error = loadfirmware(name, &fw->data, &size)) != 0) 1678 return error; 1679 1680 if (size < sizeof (*hdr)) { 1681 error = EINVAL; 1682 goto fail; 1683 } 1684 hdr = (const struct ipw_firmware_hdr *)fw->data; 1685 fw->main_size = letoh32(hdr->main_size); 1686 fw->ucode_size = letoh32(hdr->ucode_size); 1687 1688 if (size < sizeof (*hdr) + fw->main_size + fw->ucode_size) { 1689 error = EINVAL; 1690 goto fail; 1691 } 1692 fw->main = fw->data + sizeof (*hdr); 1693 fw->ucode = fw->main + fw->main_size; 1694 1695 return 0; 1696 1697fail: free(fw->data, M_DEVBUF); 1698 return error; 1699} 1700 1701void 1702ipw_scan(void *arg1, void *arg2) 1703{ 1704 struct ipw_softc *sc = arg1; 1705 struct ifnet *ifp = &sc->sc_ic.ic_if; 1706 struct ipw_scan_options scan; 1707 uint8_t ssid[IEEE80211_NWID_LEN]; 1708 int error; 1709 1710 /* 1711 * Firmware has a bug and does not honour the ``do not associate 1712 * after scan'' bit in the scan command. To prevent the firmware 1713 * from associating after the scan, we set the ESSID to something 1714 * unlikely to be used by a real AP. 1715 * XXX would setting the desired BSSID to a multicast address work? 1716 */ 1717 memset(ssid, '\r', sizeof ssid); 1718 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ssid, sizeof ssid); 1719 if (error != 0) 1720 goto fail; 1721 1722 /* no mandatory BSSID */ 1723 DPRINTF(("Setting mandatory BSSID to null\n")); 1724 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1725 if (error != 0) 1726 goto fail; 1727 1728 scan.flags = htole32(IPW_SCAN_DO_NOT_ASSOCIATE | IPW_SCAN_MIXED_CELL); 1729 scan.channels = htole32(0x3fff); /* scan channels 1-14 */ 1730 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1731 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1732 if (error != 0) 1733 goto fail; 1734 1735 /* start scanning */ 1736 DPRINTF(("Enabling adapter\n")); 1737 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1738 if (error != 0) 1739 goto fail; 1740 1741 return; 1742fail: 1743 printf("%s: scan request failed (error=%d)\n", sc->sc_dev.dv_xname, 1744 error); 1745 ieee80211_end_scan(ifp); 1746} 1747 1748void 1749ipw_auth_and_assoc(void *arg1, void *arg2) 1750{ 1751 struct ipw_softc *sc = arg1; 1752 struct ieee80211com *ic = &sc->sc_ic; 1753 struct ieee80211_node *ni = ic->ic_bss; 1754 struct ipw_scan_options scan; 1755 struct ipw_security security; 1756 struct ipw_assoc_req assoc; 1757 uint32_t data; 1758 uint8_t chan; 1759 int s, error; 1760 1761 DPRINTF(("Disabling adapter\n")); 1762 error = ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1763 if (error != 0) 1764 goto fail; 1765#if 1 1766 /* wait at most one second for card to be disabled */ 1767 s = splnet(); 1768 error = tsleep(sc, 0, "ipwdis", hz); 1769 splx(s); 1770 if (error != 0) { 1771 printf("%s: timeout waiting for disabled state\n", 1772 sc->sc_dev.dv_xname); 1773 goto fail; 1774 } 1775#else 1776 /* Intel's Linux driver polls for the DISABLED state instead.. */ 1777 for (ntries = 0; ntries < 1000; ntries++) { 1778 if (ipw_read_table1(sc, IPW_INFO_CARD_DISABLED) == 1) 1779 break; 1780 DELAY(10); 1781 } 1782 if (ntries == 1000) { 1783 printf("%s: timeout waiting for disabled state\n", 1784 sc->sc_dev.dv_xname); 1785 goto fail; 1786 } 1787#endif 1788 1789 bzero(&security, sizeof security); 1790 security.authmode = IPW_AUTH_OPEN; 1791 security.ciphers = htole32(IPW_CIPHER_NONE); 1792 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1793 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1794 sizeof security); 1795 if (error != 0) 1796 goto fail; 1797 1798#ifdef IPW_DEBUG 1799 if (ipw_debug > 0) { 1800 printf("Setting ESSID to "); 1801 ieee80211_print_essid(ni->ni_essid, ni->ni_esslen); 1802 printf("\n"); 1803 } 1804#endif 1805 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ni->ni_essid, ni->ni_esslen); 1806 if (error != 0) 1807 goto fail; 1808 1809 DPRINTF(("Setting BSSID to %s\n", ether_sprintf(ni->ni_bssid))); 1810 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, ni->ni_bssid, 1811 IEEE80211_ADDR_LEN); 1812 if (error != 0) 1813 goto fail; 1814 1815 data = htole32((ic->ic_flags & (IEEE80211_F_WEPON | 1816 IEEE80211_F_RSNON)) ? IPW_PRIVACYON : 0); 1817 DPRINTF(("Setting privacy flags to 0x%x\n", letoh32(data))); 1818 error = ipw_cmd(sc, IPW_CMD_SET_PRIVACY_FLAGS, &data, sizeof data); 1819 if (error != 0) 1820 goto fail; 1821 1822 /* let firmware set the capinfo, lintval, and bssid fixed fields */ 1823 bzero(&assoc, sizeof assoc); 1824 if (ic->ic_flags & IEEE80211_F_RSNON) { 1825 uint8_t *frm = assoc.optie; 1826 1827 /* tell firmware to add a WPA or RSN IE in (Re)Assoc req */ 1828 if (ni->ni_rsnprotos & IEEE80211_PROTO_RSN) 1829 frm = ieee80211_add_rsn(frm, ic, ni); 1830 else if (ni->ni_rsnprotos & IEEE80211_PROTO_WPA) 1831 frm = ieee80211_add_wpa(frm, ic, ni); 1832 assoc.optie_len = htole32(frm - assoc.optie); 1833 } 1834 DPRINTF(("Preparing assocation request (optional IE length=%d)\n", 1835 letoh32(assoc.optie_len))); 1836 error = ipw_cmd(sc, IPW_CMD_SET_ASSOC_REQ, &assoc, sizeof assoc); 1837 if (error != 0) 1838 goto fail; 1839 1840 scan.flags = htole32(IPW_SCAN_MIXED_CELL); 1841 chan = ieee80211_chan2ieee(ic, ni->ni_chan); 1842 scan.channels = htole32(1 << (chan - 1)); 1843 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1844 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1845 if (error != 0) 1846 goto fail; 1847 1848 /* trigger scan+association */ 1849 DPRINTF(("Enabling adapter\n")); 1850 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1851 if (error != 0) 1852 goto fail; 1853 1854 return; 1855fail: 1856 printf("%s: association failed (error=%d)\n", sc->sc_dev.dv_xname, 1857 error); 1858 ieee80211_begin_scan(&ic->ic_if); 1859} 1860 1861int 1862ipw_config(struct ipw_softc *sc) 1863{ 1864 struct ieee80211com *ic = &sc->sc_ic; 1865 struct ifnet *ifp = &ic->ic_if; 1866 struct ipw_configuration config; 1867 uint32_t data; 1868 int error; 1869 1870 switch (ic->ic_opmode) { 1871 case IEEE80211_M_STA: 1872 data = htole32(IPW_MODE_BSS); 1873 break; 1874#ifndef IEEE80211_STA_ONLY 1875 case IEEE80211_M_IBSS: 1876 data = htole32(IPW_MODE_IBSS); 1877 break; 1878#endif 1879 case IEEE80211_M_MONITOR: 1880 data = htole32(IPW_MODE_MONITOR); 1881 break; 1882 default: 1883 /* should not get there */ 1884 return ENODEV; 1885 } 1886 DPRINTF(("Setting mode to %u\n", letoh32(data))); 1887 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1888 if (error != 0) 1889 return error; 1890 1891 if ( 1892#ifndef IEEE80211_STA_ONLY 1893 ic->ic_opmode == IEEE80211_M_IBSS || 1894#endif 1895 ic->ic_opmode == IEEE80211_M_MONITOR) { 1896 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1897 DPRINTF(("Setting channel to %u\n", letoh32(data))); 1898 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1899 if (error != 0) 1900 return error; 1901 } 1902 1903 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1904 DPRINTF(("Enabling adapter\n")); 1905 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1906 } 1907 1908 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 1909 DPRINTF(("Setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 1910 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1911 IEEE80211_ADDR_LEN); 1912 if (error != 0) 1913 return error; 1914 1915 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1916 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1X_ENABLE); 1917#ifndef IEEE80211_STA_ONLY 1918 if (ic->ic_opmode == IEEE80211_M_IBSS) 1919 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1920#endif 1921 if (ifp->if_flags & IFF_PROMISC) 1922 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1923 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1924 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1925 DPRINTF(("Setting configuration 0x%x\n", config.flags)); 1926 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1927 if (error != 0) 1928 return error; 1929 1930 data = htole32(ic->ic_rtsthreshold); 1931 DPRINTF(("Setting RTS threshold to %u\n", letoh32(data))); 1932 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1933 if (error != 0) 1934 return error; 1935 1936 data = htole32(ic->ic_fragthreshold); 1937 DPRINTF(("Setting frag threshold to %u\n", letoh32(data))); 1938 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1939 if (error != 0) 1940 return error; 1941 1942 data = htole32(0x3); /* 1, 2 */ 1943 DPRINTF(("Setting basic tx rates to 0x%x\n", letoh32(data))); 1944 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1945 if (error != 0) 1946 return error; 1947 1948 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1949 DPRINTF(("Setting tx rates to 0x%x\n", letoh32(data))); 1950 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1951 if (error != 0) 1952 return error; 1953 1954 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1955 DPRINTF(("Setting MSDU tx rates to 0x%x\n", letoh32(data))); 1956 error = ipw_cmd(sc, IPW_CMD_SET_MSDU_TX_RATES, &data, sizeof data); 1957 if (error != 0) 1958 return error; 1959 1960 data = htole32(IPW_POWER_MODE_CAM); 1961 DPRINTF(("Setting power mode to %u\n", letoh32(data))); 1962 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1963 if (error != 0) 1964 return error; 1965 1966#ifndef IEEE80211_STA_ONLY 1967 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1968 data = htole32(32); /* default value */ 1969 DPRINTF(("Setting tx power index to %u\n", letoh32(data))); 1970 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1971 sizeof data); 1972 if (error != 0) 1973 return error; 1974 1975 data = htole32(ic->ic_lintval); 1976 DPRINTF(("Setting beacon interval to %u\n", letoh32(data))); 1977 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1978 sizeof data); 1979 if (error != 0) 1980 return error; 1981 } 1982#endif 1983 return 0; 1984} 1985 1986int 1987ipw_init(struct ifnet *ifp) 1988{ 1989 struct ipw_softc *sc = ifp->if_softc; 1990 struct ieee80211com *ic = &sc->sc_ic; 1991 struct ipw_firmware fw; 1992 int error; 1993 1994 ipw_stop(ifp, 0); 1995 1996 if ((error = ipw_reset(sc)) != 0) { 1997 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 1998 goto fail1; 1999 } 2000 2001 if ((error = ipw_read_firmware(sc, &fw)) != 0) { 2002 printf("%s: error %d, could not read firmware\n", 2003 sc->sc_dev.dv_xname, error); 2004 goto fail1; 2005 } 2006 if ((error = ipw_load_ucode(sc, fw.ucode, fw.ucode_size)) != 0) { 2007 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 2008 goto fail2; 2009 } 2010 2011 ipw_stop_master(sc); 2012 2013 /* 2014 * Setup tx, rx and status rings. 2015 */ 2016 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2017 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 2018 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 2019 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 2020 sc->txold = IPW_NTBD - 1; /* latest bd index ack by firmware */ 2021 sc->txcur = 0; /* bd index to write to */ 2022 sc->txfree = IPW_NTBD - 2; 2023 2024 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2025 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 2026 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 2027 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 2028 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 2029 2030 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 2031 sc->status_map->dm_segs[0].ds_addr); 2032 2033 if ((error = ipw_load_firmware(sc, fw.main, fw.main_size)) != 0) { 2034 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 2035 goto fail2; 2036 } 2037 sc->sc_flags |= IPW_FLAG_FW_INITED; 2038 free(fw.data, M_DEVBUF); 2039 2040 /* retrieve information tables base addresses */ 2041 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2042 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2043 2044 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2045 2046 if ((error = ipw_config(sc)) != 0) { 2047 printf("%s: device configuration failed\n", 2048 sc->sc_dev.dv_xname); 2049 goto fail2; 2050 } 2051 2052 ifp->if_flags &= ~IFF_OACTIVE; 2053 ifp->if_flags |= IFF_RUNNING; 2054 2055 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2056 ieee80211_begin_scan(ifp); 2057 else 2058 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2059 2060 return 0; 2061 2062fail2: free(fw.data, M_DEVBUF); 2063fail1: ipw_stop(ifp, 0); 2064 return error; 2065} 2066 2067void 2068ipw_stop(struct ifnet *ifp, int disable) 2069{ 2070 struct ipw_softc *sc = ifp->if_softc; 2071 struct ieee80211com *ic = &sc->sc_ic; 2072 int i; 2073 2074 ipw_stop_master(sc); 2075 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2076 2077 ifp->if_timer = 0; 2078 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2079 2080 /* 2081 * Release tx buffers. 2082 */ 2083 for (i = 0; i < IPW_NTBD; i++) 2084 ipw_release_sbd(sc, &sc->stbd_list[i]); 2085 2086 /* in case we were scanning, release the scan "lock" */ 2087 ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; 2088 2089 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2090} 2091 2092void 2093ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2094 bus_size_t count) 2095{ 2096 for (; count > 0; offset++, datap++, count--) { 2097 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2098 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2099 } 2100} 2101 2102void 2103ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2104 bus_size_t count) 2105{ 2106 for (; count > 0; offset++, datap++, count--) { 2107 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2108 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2109 } 2110} 2111 2112struct cfdriver ipw_cd = { 2113 NULL, "ipw", DV_IFNET 2114}; 2115