if_ipw.c revision 1.95
1/* $OpenBSD: if_ipw.c,v 1.95 2011/04/07 15:30:16 miod Exp $ */ 2 3/*- 4 * Copyright (c) 2004-2008 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/* 21 * Driver for Intel PRO/Wireless 2100 802.11 network adapters. 22 */ 23 24#include "bpfilter.h" 25 26#include <sys/param.h> 27#include <sys/sockio.h> 28#include <sys/workq.h> 29#include <sys/mbuf.h> 30#include <sys/kernel.h> 31#include <sys/socket.h> 32#include <sys/systm.h> 33#include <sys/conf.h> 34#include <sys/device.h> 35 36#include <machine/bus.h> 37#include <machine/endian.h> 38#include <machine/intr.h> 39 40#include <dev/pci/pcireg.h> 41#include <dev/pci/pcivar.h> 42#include <dev/pci/pcidevs.h> 43 44#if NBPFILTER > 0 45#include <net/bpf.h> 46#endif 47#include <net/if.h> 48#include <net/if_arp.h> 49#include <net/if_dl.h> 50#include <net/if_media.h> 51#include <net/if_types.h> 52 53#include <netinet/in.h> 54#include <netinet/in_systm.h> 55#include <netinet/in_var.h> 56#include <netinet/if_ether.h> 57#include <netinet/ip.h> 58 59#include <net80211/ieee80211_var.h> 60#include <net80211/ieee80211_radiotap.h> 61 62#include <dev/pci/if_ipwreg.h> 63#include <dev/pci/if_ipwvar.h> 64 65int ipw_match(struct device *, void *, void *); 66void ipw_attach(struct device *, struct device *, void *); 67int ipw_activate(struct device *, int); 68void ipw_resume(void *, void *); 69int ipw_dma_alloc(struct ipw_softc *); 70void ipw_release(struct ipw_softc *); 71int ipw_media_change(struct ifnet *); 72void ipw_media_status(struct ifnet *, struct ifmediareq *); 73int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 74uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 75void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 76void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 77void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 78 struct ipw_soft_bd *, struct ipw_soft_buf *); 79void ipw_notification_intr(struct ipw_softc *, 80 struct ipw_soft_buf *); 81void ipw_rx_intr(struct ipw_softc *); 82void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 83void ipw_tx_intr(struct ipw_softc *); 84int ipw_intr(void *); 85int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 86int ipw_send_mgmt(struct ieee80211com *, struct ieee80211_node *, 87 int, int, int); 88int ipw_tx_start(struct ifnet *, struct mbuf *, 89 struct ieee80211_node *); 90void ipw_start(struct ifnet *); 91void ipw_watchdog(struct ifnet *); 92int ipw_ioctl(struct ifnet *, u_long, caddr_t); 93uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 94void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 95int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 96 uint32_t *); 97void ipw_stop_master(struct ipw_softc *); 98int ipw_reset(struct ipw_softc *); 99int ipw_load_ucode(struct ipw_softc *, u_char *, int); 100int ipw_load_firmware(struct ipw_softc *, u_char *, int); 101int ipw_read_firmware(struct ipw_softc *, struct ipw_firmware *); 102void ipw_scan(void *, void *); 103void ipw_auth_and_assoc(void *, void *); 104int ipw_config(struct ipw_softc *); 105int ipw_init(struct ifnet *); 106void ipw_stop(struct ifnet *, int); 107void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 108 bus_size_t); 109void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 110 bus_size_t); 111 112static __inline uint8_t 113MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 114{ 115 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 116 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 117} 118 119static __inline uint32_t 120MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 121{ 122 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 123 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 124} 125 126#ifdef IPW_DEBUG 127#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 128#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 129int ipw_debug = 0; 130#else 131#define DPRINTF(x) 132#define DPRINTFN(n, x) 133#endif 134 135struct cfattach ipw_ca = { 136 sizeof (struct ipw_softc), ipw_match, ipw_attach, NULL, 137 ipw_activate 138}; 139 140int 141ipw_match(struct device *parent, void *match, void *aux) 142{ 143 struct pci_attach_args *pa = aux; 144 145 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 146 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 147 return 1; 148 149 return 0; 150} 151 152/* Base Address Register */ 153#define IPW_PCI_BAR0 0x10 154 155void 156ipw_attach(struct device *parent, struct device *self, void *aux) 157{ 158 struct ipw_softc *sc = (struct ipw_softc *)self; 159 struct ieee80211com *ic = &sc->sc_ic; 160 struct ifnet *ifp = &ic->ic_if; 161 struct pci_attach_args *pa = aux; 162 const char *intrstr; 163 bus_space_tag_t memt; 164 bus_space_handle_t memh; 165 bus_addr_t base; 166 pci_intr_handle_t ih; 167 pcireg_t data; 168 uint16_t val; 169 int error, i; 170 171 sc->sc_pct = pa->pa_pc; 172 sc->sc_pcitag = pa->pa_tag, 173 174 /* clear device specific PCI configuration register 0x41 */ 175 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 176 data &= ~0x0000ff00; 177 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 178 179 /* map the register window */ 180 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 181 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 182 if (error != 0) { 183 printf(": can't map mem space\n"); 184 return; 185 } 186 187 sc->sc_st = memt; 188 sc->sc_sh = memh; 189 sc->sc_dmat = pa->pa_dmat; 190 191 /* disable interrupts */ 192 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 193 194 if (pci_intr_map(pa, &ih) != 0) { 195 printf(": can't map interrupt\n"); 196 return; 197 } 198 199 intrstr = pci_intr_string(sc->sc_pct, ih); 200 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 201 sc->sc_dev.dv_xname); 202 if (sc->sc_ih == NULL) { 203 printf(": can't establish interrupt"); 204 if (intrstr != NULL) 205 printf(" at %s", intrstr); 206 printf("\n"); 207 return; 208 } 209 printf(": %s", intrstr); 210 211 if (ipw_reset(sc) != 0) { 212 printf(": could not reset adapter\n"); 213 return; 214 } 215 216 if (ipw_dma_alloc(sc) != 0) { 217 printf(": failed to allocate DMA resources\n"); 218 return; 219 } 220 221 ic->ic_phytype = IEEE80211_T_DS; 222 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 223 ic->ic_state = IEEE80211_S_INIT; 224 225 /* set device capabilities */ 226 ic->ic_caps = 227#ifndef IEEE80211_STA_ONLY 228 IEEE80211_C_IBSS | /* IBSS mode supported */ 229#endif 230 IEEE80211_C_MONITOR | /* monitor mode supported */ 231 IEEE80211_C_TXPMGT | /* tx power management */ 232 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 233 IEEE80211_C_WEP | /* s/w WEP */ 234 IEEE80211_C_RSN | /* WPA/RSN */ 235 IEEE80211_C_SCANALL; /* h/w scanning */ 236 237 /* read MAC address from EEPROM */ 238 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 239 ic->ic_myaddr[0] = val >> 8; 240 ic->ic_myaddr[1] = val & 0xff; 241 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 242 ic->ic_myaddr[2] = val >> 8; 243 ic->ic_myaddr[3] = val & 0xff; 244 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 245 ic->ic_myaddr[4] = val >> 8; 246 ic->ic_myaddr[5] = val & 0xff; 247 248 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 249 250 /* set supported .11b rates */ 251 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 252 253 /* set supported .11b channels (1 through 14) */ 254 for (i = 1; i <= 14; i++) { 255 ic->ic_channels[i].ic_freq = 256 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 257 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 258 } 259 260 /* IBSS channel undefined for now */ 261 ic->ic_ibss_chan = &ic->ic_channels[0]; 262 263 ifp->if_softc = sc; 264 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 265 ifp->if_ioctl = ipw_ioctl; 266 ifp->if_start = ipw_start; 267 ifp->if_watchdog = ipw_watchdog; 268 IFQ_SET_READY(&ifp->if_snd); 269 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 270 271 if_attach(ifp); 272 ieee80211_ifattach(ifp); 273 /* override state transition machine */ 274 sc->sc_newstate = ic->ic_newstate; 275 ic->ic_newstate = ipw_newstate; 276 ic->ic_send_mgmt = ipw_send_mgmt; 277 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 278 279#if NBPFILTER > 0 280 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 281 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 282 283 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 284 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 285 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 286 287 sc->sc_txtap_len = sizeof sc->sc_txtapu; 288 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 289 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 290#endif 291} 292 293int 294ipw_activate(struct device *self, int act) 295{ 296 struct ipw_softc *sc = (struct ipw_softc *)self; 297 struct ifnet *ifp = &sc->sc_ic.ic_if; 298 299 switch (act) { 300 case DVACT_SUSPEND: 301 if (ifp->if_flags & IFF_RUNNING) 302 ipw_stop(ifp, 0); 303 break; 304 case DVACT_RESUME: 305 workq_queue_task(NULL, &sc->sc_resume_wqt, 0, 306 ipw_resume, sc, NULL); 307 break; 308 } 309 310 return 0; 311} 312 313void 314ipw_resume(void *arg1, void *arg2) 315{ 316 struct ipw_softc *sc = arg1; 317 struct ifnet *ifp = &sc->sc_ic.ic_if; 318 pcireg_t data; 319 int s; 320 321 /* clear device specific PCI configuration register 0x41 */ 322 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 323 data &= ~0x0000ff00; 324 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 325 326 s = splnet(); 327 while (sc->sc_flags & IPW_FLAG_BUSY) 328 tsleep(&sc->sc_flags, PZERO, "ipwpwr", 0); 329 sc->sc_flags |= IPW_FLAG_BUSY; 330 331 if (ifp->if_flags & IFF_UP) 332 ipw_init(ifp); 333 334 sc->sc_flags &= ~IPW_FLAG_BUSY; 335 wakeup(&sc->sc_flags); 336 splx(s); 337} 338 339int 340ipw_dma_alloc(struct ipw_softc *sc) 341{ 342 struct ipw_soft_bd *sbd; 343 struct ipw_soft_hdr *shdr; 344 struct ipw_soft_buf *sbuf; 345 int i, nsegs, error; 346 347 /* 348 * Allocate and map tx ring. 349 */ 350 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 351 BUS_DMA_NOWAIT, &sc->tbd_map); 352 if (error != 0) { 353 printf("%s: could not create tx ring DMA map\n", 354 sc->sc_dev.dv_xname); 355 goto fail; 356 } 357 358 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 359 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 360 if (error != 0) { 361 printf("%s: could not allocate tx ring DMA memory\n", 362 sc->sc_dev.dv_xname); 363 goto fail; 364 } 365 366 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 367 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 368 if (error != 0) { 369 printf("%s: can't map tx ring DMA memory\n", 370 sc->sc_dev.dv_xname); 371 goto fail; 372 } 373 374 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 375 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 376 if (error != 0) { 377 printf("%s: could not load tx ring DMA map\n", 378 sc->sc_dev.dv_xname); 379 goto fail; 380 } 381 382 /* 383 * Allocate and map rx ring. 384 */ 385 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 386 BUS_DMA_NOWAIT, &sc->rbd_map); 387 if (error != 0) { 388 printf("%s: could not create rx ring DMA map\n", 389 sc->sc_dev.dv_xname); 390 goto fail; 391 } 392 393 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 394 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 395 if (error != 0) { 396 printf("%s: could not allocate rx ring DMA memory\n", 397 sc->sc_dev.dv_xname); 398 goto fail; 399 } 400 401 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 402 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 403 if (error != 0) { 404 printf("%s: can't map rx ring DMA memory\n", 405 sc->sc_dev.dv_xname); 406 goto fail; 407 } 408 409 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 410 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 411 if (error != 0) { 412 printf("%s: could not load tx ring DMA map\n", 413 sc->sc_dev.dv_xname); 414 goto fail; 415 } 416 417 /* 418 * Allocate and map status ring. 419 */ 420 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 421 0, BUS_DMA_NOWAIT, &sc->status_map); 422 if (error != 0) { 423 printf("%s: could not create status ring DMA map\n", 424 sc->sc_dev.dv_xname); 425 goto fail; 426 } 427 428 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 429 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 430 if (error != 0) { 431 printf("%s: could not allocate status ring DMA memory\n", 432 sc->sc_dev.dv_xname); 433 goto fail; 434 } 435 436 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 437 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 438 if (error != 0) { 439 printf("%s: can't map status ring DMA memory\n", 440 sc->sc_dev.dv_xname); 441 goto fail; 442 } 443 444 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 445 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 446 if (error != 0) { 447 printf("%s: could not load status ring DMA map\n", 448 sc->sc_dev.dv_xname); 449 goto fail; 450 } 451 452 /* 453 * Allocate command DMA map. 454 */ 455 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 456 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 457 if (error != 0) { 458 printf("%s: could not create command DMA map\n", 459 sc->sc_dev.dv_xname); 460 goto fail; 461 } 462 463 /* 464 * Allocate headers DMA maps. 465 */ 466 SLIST_INIT(&sc->free_shdr); 467 for (i = 0; i < IPW_NDATA; i++) { 468 shdr = &sc->shdr_list[i]; 469 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_hdr), 470 1, sizeof (struct ipw_hdr), 0, BUS_DMA_NOWAIT, &shdr->map); 471 if (error != 0) { 472 printf("%s: could not create header DMA map\n", 473 sc->sc_dev.dv_xname); 474 goto fail; 475 } 476 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 477 } 478 479 /* 480 * Allocate tx buffers DMA maps. 481 */ 482 SLIST_INIT(&sc->free_sbuf); 483 for (i = 0; i < IPW_NDATA; i++) { 484 sbuf = &sc->tx_sbuf_list[i]; 485 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, IPW_MAX_NSEG, 486 MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 487 if (error != 0) { 488 printf("%s: could not create tx DMA map\n", 489 sc->sc_dev.dv_xname); 490 goto fail; 491 } 492 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 493 } 494 495 /* 496 * Initialize tx ring. 497 */ 498 for (i = 0; i < IPW_NTBD; i++) { 499 sbd = &sc->stbd_list[i]; 500 sbd->bd = &sc->tbd_list[i]; 501 sbd->type = IPW_SBD_TYPE_NOASSOC; 502 } 503 504 /* 505 * Pre-allocate rx buffers and DMA maps. 506 */ 507 for (i = 0; i < IPW_NRBD; i++) { 508 sbd = &sc->srbd_list[i]; 509 sbuf = &sc->rx_sbuf_list[i]; 510 sbd->bd = &sc->rbd_list[i]; 511 512 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 513 if (sbuf->m == NULL) { 514 printf("%s: could not allocate rx mbuf\n", 515 sc->sc_dev.dv_xname); 516 error = ENOMEM; 517 goto fail; 518 } 519 MCLGET(sbuf->m, M_DONTWAIT); 520 if (!(sbuf->m->m_flags & M_EXT)) { 521 m_freem(sbuf->m); 522 printf("%s: could not allocate rx mbuf cluster\n", 523 sc->sc_dev.dv_xname); 524 error = ENOMEM; 525 goto fail; 526 } 527 528 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 529 0, BUS_DMA_NOWAIT, &sbuf->map); 530 if (error != 0) { 531 printf("%s: could not create rx DMA map\n", 532 sc->sc_dev.dv_xname); 533 goto fail; 534 } 535 536 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 537 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 538 if (error != 0) { 539 printf("%s: can't map rx DMA memory\n", 540 sc->sc_dev.dv_xname); 541 goto fail; 542 } 543 544 sbd->type = IPW_SBD_TYPE_DATA; 545 sbd->priv = sbuf; 546 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 547 sbd->bd->len = htole32(MCLBYTES); 548 } 549 550 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 551 BUS_DMASYNC_PREWRITE); 552 553 return 0; 554 555fail: ipw_release(sc); 556 return error; 557} 558 559void 560ipw_release(struct ipw_softc *sc) 561{ 562 struct ipw_soft_buf *sbuf; 563 int i; 564 565 if (sc->tbd_map != NULL) { 566 if (sc->tbd_list != NULL) { 567 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 568 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 569 IPW_TBD_SZ); 570 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 571 } 572 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 573 } 574 575 if (sc->rbd_map != NULL) { 576 if (sc->rbd_list != NULL) { 577 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 578 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 579 IPW_RBD_SZ); 580 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 581 } 582 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 583 } 584 585 if (sc->status_map != NULL) { 586 if (sc->status_list != NULL) { 587 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 588 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 589 IPW_RBD_SZ); 590 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 591 } 592 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 593 } 594 595 if (sc->cmd_map != NULL) 596 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 597 598 for (i = 0; i < IPW_NDATA; i++) 599 bus_dmamap_destroy(sc->sc_dmat, sc->shdr_list[i].map); 600 601 for (i = 0; i < IPW_NDATA; i++) 602 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 603 604 for (i = 0; i < IPW_NRBD; i++) { 605 sbuf = &sc->rx_sbuf_list[i]; 606 if (sbuf->map != NULL) { 607 if (sbuf->m != NULL) { 608 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 609 m_freem(sbuf->m); 610 } 611 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 612 } 613 } 614} 615 616int 617ipw_media_change(struct ifnet *ifp) 618{ 619 int error; 620 621 error = ieee80211_media_change(ifp); 622 if (error != ENETRESET) 623 return error; 624 625 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 626 ipw_init(ifp); 627 628 return 0; 629} 630 631void 632ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 633{ 634 struct ipw_softc *sc = ifp->if_softc; 635 struct ieee80211com *ic = &sc->sc_ic; 636 static const struct { 637 uint32_t val; 638 int rate; 639 } rates[] = { 640 { IPW_RATE_DS1, 2 }, 641 { IPW_RATE_DS2, 4 }, 642 { IPW_RATE_DS5, 11 }, 643 { IPW_RATE_DS11, 22 }, 644 }; 645 uint32_t val; 646 int rate, i; 647 648 imr->ifm_status = IFM_AVALID; 649 imr->ifm_active = IFM_IEEE80211; 650 if (ic->ic_state == IEEE80211_S_RUN) 651 imr->ifm_status |= IFM_ACTIVE; 652 653 /* read current transmission rate from adapter */ 654 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 655 val &= 0xf; 656 657 /* convert rate to 802.11 rate */ 658 for (i = 0; i < nitems(rates) && rates[i].val != val; i++); 659 rate = (i < nitems(rates)) ? rates[i].rate : 0; 660 661 imr->ifm_active |= IFM_IEEE80211_11B; 662 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 663 switch (ic->ic_opmode) { 664 case IEEE80211_M_STA: 665 break; 666#ifndef IEEE80211_STA_ONLY 667 case IEEE80211_M_IBSS: 668 imr->ifm_active |= IFM_IEEE80211_IBSS; 669 break; 670#endif 671 case IEEE80211_M_MONITOR: 672 imr->ifm_active |= IFM_IEEE80211_MONITOR; 673 break; 674 default: 675 /* should not get there */ 676 break; 677 } 678} 679 680int 681ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 682{ 683 struct ipw_softc *sc = ic->ic_softc; 684 int error; 685 686 switch (nstate) { 687 case IEEE80211_S_SCAN: 688 error = workq_add_task(NULL, 0, ipw_scan, sc, NULL); 689 if (error != 0) 690 return error; 691 break; 692 693 case IEEE80211_S_AUTH: 694 error = workq_add_task(NULL, 0, ipw_auth_and_assoc, sc, NULL); 695 if (error != 0) 696 return error; 697 break; 698 699 case IEEE80211_S_RUN: 700 case IEEE80211_S_INIT: 701 case IEEE80211_S_ASSOC: 702 /* nothing to do */ 703 break; 704 } 705 706 ic->ic_state = nstate; 707 return 0; 708} 709 710/* 711 * Read 16 bits at address 'addr' from the Microwire EEPROM. 712 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 713 */ 714uint16_t 715ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 716{ 717 uint32_t tmp; 718 uint16_t val; 719 int n; 720 721 /* clock C once before the first command */ 722 IPW_EEPROM_CTL(sc, 0); 723 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 724 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 725 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 726 727 /* write start bit (1) */ 728 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 729 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 730 731 /* write READ opcode (10) */ 732 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 733 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 734 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 735 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 736 737 /* write address A7-A0 */ 738 for (n = 7; n >= 0; n--) { 739 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 740 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 741 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 742 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 743 } 744 745 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 746 747 /* read data Q15-Q0 */ 748 val = 0; 749 for (n = 15; n >= 0; n--) { 750 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 751 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 752 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 753 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 754 } 755 756 IPW_EEPROM_CTL(sc, 0); 757 758 /* clear Chip Select and clock C */ 759 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 760 IPW_EEPROM_CTL(sc, 0); 761 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 762 763 return val; 764} 765 766void 767ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 768{ 769 struct ipw_cmd *cmd; 770 771 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 772 BUS_DMASYNC_POSTREAD); 773 774 cmd = mtod(sbuf->m, struct ipw_cmd *); 775 776 DPRINTFN(2, ("received command ack type=%u,status=%u\n", 777 letoh32(cmd->type), letoh32(cmd->status))); 778 779 wakeup(&sc->cmd); 780} 781 782void 783ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 784{ 785 struct ieee80211com *ic = &sc->sc_ic; 786 struct ifnet *ifp = &ic->ic_if; 787 uint32_t state; 788 789 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 790 BUS_DMASYNC_POSTREAD); 791 792 state = letoh32(*mtod(sbuf->m, uint32_t *)); 793 794 DPRINTFN(2, ("firmware state changed to 0x%x\n", state)); 795 796 switch (state) { 797 case IPW_STATE_ASSOCIATED: 798 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 799 break; 800 801 case IPW_STATE_SCANNING: 802 if (ic->ic_state == IEEE80211_S_RUN) 803 ieee80211_begin_scan(ifp); 804 break; 805 806 case IPW_STATE_SCAN_COMPLETE: 807 if (ic->ic_state == IEEE80211_S_SCAN) 808 ieee80211_end_scan(ifp); 809 break; 810 811 case IPW_STATE_ASSOCIATION_LOST: 812 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 813 break; 814 815 case IPW_STATE_DISABLED: 816 wakeup(sc); 817 break; 818 819 case IPW_STATE_RADIO_DISABLED: 820 ifp->if_flags &= ~IFF_UP; 821 ipw_stop(&ic->ic_if, 1); 822 break; 823 } 824} 825 826void 827ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 828 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 829{ 830 struct ieee80211com *ic = &sc->sc_ic; 831 struct ifnet *ifp = &ic->ic_if; 832 struct mbuf *mnew, *m; 833 struct ieee80211_frame *wh; 834 struct ieee80211_rxinfo rxi; 835 struct ieee80211_node *ni; 836 int error; 837 838 DPRINTFN(5, ("received data frame len=%u,rssi=%u\n", 839 letoh32(status->len), status->rssi)); 840 841 /* 842 * Try to allocate a new mbuf for this ring element and load it before 843 * processing the current mbuf. If the ring element cannot be loaded, 844 * drop the received packet and reuse the old mbuf. In the unlikely 845 * case that the old mbuf can't be reloaded either, explicitly panic. 846 */ 847 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 848 if (mnew == NULL) { 849 ifp->if_ierrors++; 850 return; 851 } 852 MCLGET(mnew, M_DONTWAIT); 853 if (!(mnew->m_flags & M_EXT)) { 854 m_freem(mnew); 855 ifp->if_ierrors++; 856 return; 857 } 858 859 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 860 BUS_DMASYNC_POSTREAD); 861 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 862 863 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(mnew, void *), 864 MCLBYTES, NULL, BUS_DMA_NOWAIT); 865 if (error != 0) { 866 m_freem(mnew); 867 868 /* try to reload the old mbuf */ 869 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 870 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 871 if (error != 0) { 872 /* very unlikely that it will fail... */ 873 panic("%s: could not load old rx mbuf", 874 sc->sc_dev.dv_xname); 875 } 876 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 877 ifp->if_ierrors++; 878 return; 879 } 880 881 m = sbuf->m; 882 sbuf->m = mnew; 883 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 884 885 /* finalize mbuf */ 886 m->m_pkthdr.rcvif = ifp; 887 m->m_pkthdr.len = m->m_len = letoh32(status->len); 888 889#if NBPFILTER > 0 890 if (sc->sc_drvbpf != NULL) { 891 struct mbuf mb; 892 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 893 894 tap->wr_flags = 0; 895 tap->wr_antsignal = status->rssi; 896 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 897 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 898 899 mb.m_data = (caddr_t)tap; 900 mb.m_len = sc->sc_rxtap_len; 901 mb.m_next = m; 902 mb.m_nextpkt = NULL; 903 mb.m_type = 0; 904 mb.m_flags = 0; 905 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 906 } 907#endif 908 909 wh = mtod(m, struct ieee80211_frame *); 910 ni = ieee80211_find_rxnode(ic, wh); 911 912 /* send the frame to the upper layer */ 913 rxi.rxi_flags = 0; 914 rxi.rxi_rssi = status->rssi; 915 rxi.rxi_tstamp = 0; /* unused */ 916 ieee80211_input(ifp, m, ni, &rxi); 917 918 ieee80211_release_node(ic, ni); 919} 920 921void 922ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 923{ 924 DPRINTFN(2, ("received notification\n")); 925} 926 927void 928ipw_rx_intr(struct ipw_softc *sc) 929{ 930 struct ipw_status *status; 931 struct ipw_soft_bd *sbd; 932 struct ipw_soft_buf *sbuf; 933 uint32_t r, i; 934 935 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 936 937 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 938 939 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 940 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 941 BUS_DMASYNC_POSTREAD); 942 943 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 944 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 945 BUS_DMASYNC_POSTREAD); 946 947 status = &sc->status_list[i]; 948 sbd = &sc->srbd_list[i]; 949 sbuf = sbd->priv; 950 951 switch (letoh16(status->code) & 0xf) { 952 case IPW_STATUS_CODE_COMMAND: 953 ipw_command_intr(sc, sbuf); 954 break; 955 956 case IPW_STATUS_CODE_NEWSTATE: 957 ipw_newstate_intr(sc, sbuf); 958 break; 959 960 case IPW_STATUS_CODE_DATA_802_3: 961 case IPW_STATUS_CODE_DATA_802_11: 962 ipw_data_intr(sc, status, sbd, sbuf); 963 break; 964 965 case IPW_STATUS_CODE_NOTIFICATION: 966 ipw_notification_intr(sc, sbuf); 967 break; 968 969 default: 970 printf("%s: unknown status code %u\n", 971 sc->sc_dev.dv_xname, letoh16(status->code)); 972 } 973 sbd->bd->flags = 0; 974 975 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 976 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 977 BUS_DMASYNC_PREWRITE); 978 } 979 980 /* tell the firmware what we have processed */ 981 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 982 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 983} 984 985void 986ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 987{ 988 struct ieee80211com *ic = &sc->sc_ic; 989 struct ipw_soft_hdr *shdr; 990 struct ipw_soft_buf *sbuf; 991 992 switch (sbd->type) { 993 case IPW_SBD_TYPE_COMMAND: 994 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 995 break; 996 997 case IPW_SBD_TYPE_HEADER: 998 shdr = sbd->priv; 999 bus_dmamap_unload(sc->sc_dmat, shdr->map); 1000 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 1001 break; 1002 1003 case IPW_SBD_TYPE_DATA: 1004 sbuf = sbd->priv; 1005 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1006 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1007 1008 m_freem(sbuf->m); 1009 1010 if (sbuf->ni != NULL) 1011 ieee80211_release_node(ic, sbuf->ni); 1012 1013 /* kill watchdog timer */ 1014 sc->sc_tx_timer = 0; 1015 break; 1016 } 1017 sbd->type = IPW_SBD_TYPE_NOASSOC; 1018} 1019 1020void 1021ipw_tx_intr(struct ipw_softc *sc) 1022{ 1023 struct ifnet *ifp = &sc->sc_ic.ic_if; 1024 struct ipw_soft_bd *sbd; 1025 uint32_t r, i; 1026 1027 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 1028 1029 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1030 sbd = &sc->stbd_list[i]; 1031 1032 if (sbd->type == IPW_SBD_TYPE_DATA) 1033 ifp->if_opackets++; 1034 1035 ipw_release_sbd(sc, sbd); 1036 sc->txfree++; 1037 } 1038 1039 /* remember what the firmware has processed */ 1040 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1041 1042 /* call start() since some buffer descriptors have been released */ 1043 ifp->if_flags &= ~IFF_OACTIVE; 1044 (*ifp->if_start)(ifp); 1045} 1046 1047int 1048ipw_intr(void *arg) 1049{ 1050 struct ipw_softc *sc = arg; 1051 struct ifnet *ifp = &sc->sc_ic.ic_if; 1052 uint32_t r; 1053 1054 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) 1055 return 0; 1056 1057 /* disable interrupts */ 1058 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1059 1060 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1061 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 1062 ifp->if_flags &= ~IFF_UP; 1063 ipw_stop(ifp, 1); 1064 return 1; 1065 } 1066 1067 if (r & IPW_INTR_FW_INIT_DONE) 1068 wakeup(sc); 1069 1070 if (r & IPW_INTR_RX_TRANSFER) 1071 ipw_rx_intr(sc); 1072 1073 if (r & IPW_INTR_TX_TRANSFER) 1074 ipw_tx_intr(sc); 1075 1076 /* acknowledge interrupts */ 1077 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1078 1079 /* re-enable interrupts */ 1080 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1081 1082 return 1; 1083} 1084 1085int 1086ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1087{ 1088 struct ipw_soft_bd *sbd; 1089 int s, error; 1090 1091 s = splnet(); 1092 1093 sc->cmd.type = htole32(type); 1094 sc->cmd.subtype = htole32(0); 1095 sc->cmd.len = htole32(len); 1096 sc->cmd.seq = htole32(0); 1097 if (data != NULL) 1098 bcopy(data, sc->cmd.data, len); 1099 1100 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 1101 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 1102 if (error != 0) { 1103 printf("%s: can't map command DMA memory\n", 1104 sc->sc_dev.dv_xname); 1105 splx(s); 1106 return error; 1107 } 1108 1109 sbd = &sc->stbd_list[sc->txcur]; 1110 sbd->type = IPW_SBD_TYPE_COMMAND; 1111 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1112 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1113 sbd->bd->nfrag = 1; 1114 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1115 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1116 1117 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1118 BUS_DMASYNC_PREWRITE); 1119 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1120 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1121 BUS_DMASYNC_PREWRITE); 1122 1123 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1124 sc->txfree--; 1125 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1126 1127 DPRINTFN(2, ("sending command type=%u,len=%u\n", type, len)); 1128 1129 /* wait at most one second for command to complete */ 1130 error = tsleep(&sc->cmd, 0, "ipwcmd", hz); 1131 splx(s); 1132 1133 return error; 1134} 1135 1136/* ARGSUSED */ 1137int 1138ipw_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type, 1139 int arg1, int arg2) 1140{ 1141 return EOPNOTSUPP; 1142} 1143 1144int 1145ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 1146{ 1147 struct ipw_softc *sc = ifp->if_softc; 1148 struct ieee80211com *ic = &sc->sc_ic; 1149 struct ieee80211_frame *wh; 1150 struct ieee80211_key *k; 1151 struct mbuf *m1; 1152 struct ipw_soft_bd *sbd; 1153 struct ipw_soft_hdr *shdr; 1154 struct ipw_soft_buf *sbuf; 1155 int error, i; 1156 1157 wh = mtod(m, struct ieee80211_frame *); 1158 1159 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1160 k = ieee80211_get_txkey(ic, wh, ni); 1161 1162 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1163 return ENOBUFS; 1164 1165 /* packet header may have moved, reset our local pointer */ 1166 wh = mtod(m, struct ieee80211_frame *); 1167 } 1168 1169#if NBPFILTER > 0 1170 if (sc->sc_drvbpf != NULL) { 1171 struct mbuf mb; 1172 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1173 1174 tap->wt_flags = 0; 1175 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1176 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1177 1178 mb.m_data = (caddr_t)tap; 1179 mb.m_len = sc->sc_txtap_len; 1180 mb.m_next = m; 1181 mb.m_nextpkt = NULL; 1182 mb.m_type = 0; 1183 mb.m_flags = 0; 1184 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1185 } 1186#endif 1187 1188 shdr = SLIST_FIRST(&sc->free_shdr); 1189 sbuf = SLIST_FIRST(&sc->free_sbuf); 1190 1191 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1192 shdr->hdr.subtype = htole32(0); 1193 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) ? 1 : 0; 1194 shdr->hdr.encrypt = 0; 1195 shdr->hdr.keyidx = 0; 1196 shdr->hdr.keysz = 0; 1197 shdr->hdr.fragmentsz = htole16(0); 1198 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1199 if (ic->ic_opmode == IEEE80211_M_STA) 1200 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1201 else 1202 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1203 1204 /* trim IEEE802.11 header */ 1205 m_adj(m, sizeof (struct ieee80211_frame)); 1206 1207 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 1208 if (error != 0 && error != EFBIG) { 1209 printf("%s: can't map mbuf (error %d)\n", 1210 sc->sc_dev.dv_xname, error); 1211 m_freem(m); 1212 return error; 1213 } 1214 if (error != 0) { 1215 /* too many fragments, linearize */ 1216 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1217 if (m1 == NULL) { 1218 m_freem(m); 1219 return ENOBUFS; 1220 } 1221 if (m->m_pkthdr.len > MHLEN) { 1222 MCLGET(m1, M_DONTWAIT); 1223 if (!(m1->m_flags & M_EXT)) { 1224 m_freem(m); 1225 m_freem(m1); 1226 return ENOBUFS; 1227 } 1228 } 1229 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, caddr_t)); 1230 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 1231 m_freem(m); 1232 m = m1; 1233 1234 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, 1235 BUS_DMA_NOWAIT); 1236 if (error != 0) { 1237 printf("%s: can't map mbuf (error %d)\n", 1238 sc->sc_dev.dv_xname, error); 1239 m_freem(m); 1240 return error; 1241 } 1242 } 1243 1244 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 1245 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 1246 if (error != 0) { 1247 printf("%s: can't map header DMA memory (error %d)\n", 1248 sc->sc_dev.dv_xname, error); 1249 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1250 m_freem(m); 1251 return error; 1252 } 1253 1254 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1255 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1256 1257 sbd = &sc->stbd_list[sc->txcur]; 1258 sbd->type = IPW_SBD_TYPE_HEADER; 1259 sbd->priv = shdr; 1260 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 1261 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1262 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1263 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1264 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1265 1266 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1267 sc->txcur * sizeof (struct ipw_bd), 1268 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1269 1270 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1271 sc->txfree--; 1272 1273 sbuf->m = m; 1274 sbuf->ni = ni; 1275 1276 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1277 sbd = &sc->stbd_list[sc->txcur]; 1278 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1279 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1280 sbd->bd->nfrag = 0; /* used only in first bd */ 1281 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1282 if (i == sbuf->map->dm_nsegs - 1) { 1283 sbd->type = IPW_SBD_TYPE_DATA; 1284 sbd->priv = sbuf; 1285 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1286 } else { 1287 sbd->type = IPW_SBD_TYPE_NOASSOC; 1288 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1289 } 1290 1291 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1292 sc->txcur * sizeof (struct ipw_bd), 1293 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1294 1295 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1296 sc->txfree--; 1297 } 1298 1299 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1300 BUS_DMASYNC_PREWRITE); 1301 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 1302 BUS_DMASYNC_PREWRITE); 1303 1304 /* inform firmware about this new packet */ 1305 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1306 1307 return 0; 1308} 1309 1310void 1311ipw_start(struct ifnet *ifp) 1312{ 1313 struct ipw_softc *sc = ifp->if_softc; 1314 struct ieee80211com *ic = &sc->sc_ic; 1315 struct ieee80211_node *ni; 1316 struct mbuf *m; 1317 1318 if (ic->ic_state != IEEE80211_S_RUN) 1319 return; 1320 1321 for (;;) { 1322 IFQ_POLL(&ifp->if_snd, m); 1323 if (m == NULL) 1324 break; 1325 1326 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1327 ifp->if_flags |= IFF_OACTIVE; 1328 break; 1329 } 1330 IFQ_DEQUEUE(&ifp->if_snd, m); 1331#if NBPFILTER > 0 1332 if (ifp->if_bpf != NULL) 1333 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1334#endif 1335 m = ieee80211_encap(ifp, m, &ni); 1336 if (m == NULL) 1337 continue; 1338#if NBPFILTER > 0 1339 if (ic->ic_rawbpf != NULL) 1340 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1341#endif 1342 if (ipw_tx_start(ifp, m, ni) != 0) { 1343 if (ni != NULL) 1344 ieee80211_release_node(ic, ni); 1345 ifp->if_oerrors++; 1346 break; 1347 } 1348 1349 /* start watchdog timer */ 1350 sc->sc_tx_timer = 5; 1351 ifp->if_timer = 1; 1352 } 1353} 1354 1355void 1356ipw_watchdog(struct ifnet *ifp) 1357{ 1358 struct ipw_softc *sc = ifp->if_softc; 1359 1360 ifp->if_timer = 0; 1361 1362 if (sc->sc_tx_timer > 0) { 1363 if (--sc->sc_tx_timer == 0) { 1364 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1365 ifp->if_flags &= ~IFF_UP; 1366 ipw_stop(ifp, 1); 1367 ifp->if_oerrors++; 1368 return; 1369 } 1370 ifp->if_timer = 1; 1371 } 1372 1373 ieee80211_watchdog(ifp); 1374} 1375 1376int 1377ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1378{ 1379 struct ipw_softc *sc = ifp->if_softc; 1380 struct ieee80211com *ic = &sc->sc_ic; 1381 struct ifaddr *ifa; 1382 struct ifreq *ifr; 1383 int s, error = 0; 1384 1385 s = splnet(); 1386 /* 1387 * Prevent processes from entering this function while another 1388 * process is tsleep'ing in it. 1389 */ 1390 while ((sc->sc_flags & IPW_FLAG_BUSY) && error == 0) 1391 error = tsleep(&sc->sc_flags, PCATCH, "ipwioc", 0); 1392 if (error != 0) { 1393 splx(s); 1394 return error; 1395 } 1396 sc->sc_flags |= IPW_FLAG_BUSY; 1397 1398 switch (cmd) { 1399 case SIOCSIFADDR: 1400 ifa = (struct ifaddr *)data; 1401 ifp->if_flags |= IFF_UP; 1402#ifdef INET 1403 if (ifa->ifa_addr->sa_family == AF_INET) 1404 arp_ifinit(&ic->ic_ac, ifa); 1405#endif 1406 /* FALLTHROUGH */ 1407 case SIOCSIFFLAGS: 1408 if (ifp->if_flags & IFF_UP) { 1409 if (!(ifp->if_flags & IFF_RUNNING)) 1410 ipw_init(ifp); 1411 } else { 1412 if (ifp->if_flags & IFF_RUNNING) 1413 ipw_stop(ifp, 1); 1414 } 1415 break; 1416 1417 case SIOCADDMULTI: 1418 case SIOCDELMULTI: 1419 ifr = (struct ifreq *)data; 1420 error = (cmd == SIOCADDMULTI) ? 1421 ether_addmulti(ifr, &ic->ic_ac) : 1422 ether_delmulti(ifr, &ic->ic_ac); 1423 1424 if (error == ENETRESET) 1425 error = 0; 1426 break; 1427 1428 case SIOCG80211TXPOWER: 1429 /* 1430 * If the hardware radio transmitter switch is off, report a 1431 * tx power of IEEE80211_TXPOWER_MIN to indicate that radio 1432 * transmitter is killed. 1433 */ 1434 ((struct ieee80211_txpower *)data)->i_val = 1435 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 1436 IEEE80211_TXPOWER_MIN : sc->sc_ic.ic_txpower; 1437 break; 1438 1439 default: 1440 error = ieee80211_ioctl(ifp, cmd, data); 1441 } 1442 1443 if (error == ENETRESET) { 1444 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1445 (IFF_UP | IFF_RUNNING)) 1446 ipw_init(ifp); 1447 error = 0; 1448 } 1449 1450 sc->sc_flags &= ~IPW_FLAG_BUSY; 1451 wakeup(&sc->sc_flags); 1452 splx(s); 1453 return error; 1454} 1455 1456uint32_t 1457ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1458{ 1459 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1460} 1461 1462void 1463ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1464{ 1465 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1466} 1467 1468int 1469ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1470{ 1471 uint32_t addr, info; 1472 uint16_t count, size; 1473 uint32_t total; 1474 1475 /* addr[4] + count[2] + size[2] */ 1476 addr = MEM_READ_4(sc, sc->table2_base + off); 1477 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1478 1479 count = info >> 16; 1480 size = info & 0xffff; 1481 total = count * size; 1482 1483 if (total > *len) { 1484 *len = total; 1485 return EINVAL; 1486 } 1487 *len = total; 1488 ipw_read_mem_1(sc, addr, buf, total); 1489 1490 return 0; 1491} 1492 1493void 1494ipw_stop_master(struct ipw_softc *sc) 1495{ 1496 uint32_t tmp; 1497 int ntries; 1498 1499 /* disable interrupts */ 1500 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1501 1502 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1503 for (ntries = 0; ntries < 50; ntries++) { 1504 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1505 break; 1506 DELAY(10); 1507 } 1508 if (ntries == 50) 1509 printf("%s: timeout waiting for master\n", 1510 sc->sc_dev.dv_xname); 1511 1512 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1513 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1514 1515 sc->sc_flags &= ~IPW_FLAG_FW_INITED; 1516} 1517 1518int 1519ipw_reset(struct ipw_softc *sc) 1520{ 1521 uint32_t tmp; 1522 int ntries; 1523 1524 ipw_stop_master(sc); 1525 1526 /* move adapter to D0 state */ 1527 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1528 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1529 1530 /* wait for clock stabilization */ 1531 for (ntries = 0; ntries < 1000; ntries++) { 1532 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1533 break; 1534 DELAY(200); 1535 } 1536 if (ntries == 1000) 1537 return EIO; 1538 1539 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1540 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1541 1542 DELAY(10); 1543 1544 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1545 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1546 1547 return 0; 1548} 1549 1550int 1551ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1552{ 1553 int ntries; 1554 1555 /* voodoo from the Intel Linux driver */ 1556 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1557 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1558 1559 MEM_WRITE_2(sc, 0x220000, 0x0703); 1560 MEM_WRITE_2(sc, 0x220000, 0x0707); 1561 1562 MEM_WRITE_1(sc, 0x210014, 0x72); 1563 MEM_WRITE_1(sc, 0x210014, 0x72); 1564 1565 MEM_WRITE_1(sc, 0x210000, 0x40); 1566 MEM_WRITE_1(sc, 0x210000, 0x00); 1567 MEM_WRITE_1(sc, 0x210000, 0x40); 1568 1569 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1570 1571 MEM_WRITE_1(sc, 0x210000, 0x00); 1572 MEM_WRITE_1(sc, 0x210000, 0x00); 1573 MEM_WRITE_1(sc, 0x210000, 0x80); 1574 1575 MEM_WRITE_2(sc, 0x220000, 0x0703); 1576 MEM_WRITE_2(sc, 0x220000, 0x0707); 1577 1578 MEM_WRITE_1(sc, 0x210014, 0x72); 1579 MEM_WRITE_1(sc, 0x210014, 0x72); 1580 1581 MEM_WRITE_1(sc, 0x210000, 0x00); 1582 MEM_WRITE_1(sc, 0x210000, 0x80); 1583 1584 for (ntries = 0; ntries < 100; ntries++) { 1585 if (MEM_READ_1(sc, 0x210000) & 1) 1586 break; 1587 DELAY(1000); 1588 } 1589 if (ntries == 100) { 1590 printf("%s: timeout waiting for ucode to initialize\n", 1591 sc->sc_dev.dv_xname); 1592 return EIO; 1593 } 1594 1595 MEM_WRITE_4(sc, 0x3000e0, 0); 1596 1597 return 0; 1598} 1599 1600/* set of macros to handle unaligned little endian data in firmware image */ 1601#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1602#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1603int 1604ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1605{ 1606 u_char *p, *end; 1607 uint32_t tmp, dst; 1608 uint16_t len; 1609 int error; 1610 1611 p = fw; 1612 end = fw + size; 1613 while (p < end) { 1614 if (p + 6 > end) 1615 return EINVAL; 1616 1617 dst = GETLE32(p); p += 4; 1618 len = GETLE16(p); p += 2; 1619 1620 if (p + len > end) 1621 return EINVAL; 1622 1623 ipw_write_mem_1(sc, dst, p, len); 1624 p += len; 1625 } 1626 1627 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1628 IPW_IO_LED_OFF); 1629 1630 /* allow interrupts so we know when the firmware is inited */ 1631 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1632 1633 /* tell the adapter to initialize the firmware */ 1634 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1635 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1636 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1637 1638 /* wait at most one second for firmware initialization to complete */ 1639 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1640 printf("%s: timeout waiting for firmware initialization to " 1641 "complete\n", sc->sc_dev.dv_xname); 1642 return error; 1643 } 1644 1645 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1646 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1647 IPW_IO_GPIO3_MASK); 1648 1649 return 0; 1650} 1651 1652int 1653ipw_read_firmware(struct ipw_softc *sc, struct ipw_firmware *fw) 1654{ 1655 const struct ipw_firmware_hdr *hdr; 1656 const char *name; 1657 size_t size; 1658 int error; 1659 1660 switch (sc->sc_ic.ic_opmode) { 1661 case IEEE80211_M_STA: 1662 name = "ipw-bss"; 1663 break; 1664#ifndef IEEE80211_STA_ONLY 1665 case IEEE80211_M_IBSS: 1666 name = "ipw-ibss"; 1667 break; 1668#endif 1669 case IEEE80211_M_MONITOR: 1670 name = "ipw-monitor"; 1671 break; 1672 default: 1673 /* should not get there */ 1674 return ENODEV; 1675 } 1676 if ((error = loadfirmware(name, &fw->data, &size)) != 0) 1677 return error; 1678 1679 if (size < sizeof (*hdr)) { 1680 error = EINVAL; 1681 goto fail; 1682 } 1683 hdr = (const struct ipw_firmware_hdr *)fw->data; 1684 fw->main_size = letoh32(hdr->main_size); 1685 fw->ucode_size = letoh32(hdr->ucode_size); 1686 1687 if (size < sizeof (*hdr) + fw->main_size + fw->ucode_size) { 1688 error = EINVAL; 1689 goto fail; 1690 } 1691 fw->main = fw->data + sizeof (*hdr); 1692 fw->ucode = fw->main + fw->main_size; 1693 1694 return 0; 1695 1696fail: free(fw->data, M_DEVBUF); 1697 return error; 1698} 1699 1700void 1701ipw_scan(void *arg1, void *arg2) 1702{ 1703 struct ipw_softc *sc = arg1; 1704 struct ifnet *ifp = &sc->sc_ic.ic_if; 1705 struct ipw_scan_options scan; 1706 uint8_t ssid[IEEE80211_NWID_LEN]; 1707 int error; 1708 1709 /* 1710 * Firmware has a bug and does not honour the ``do not associate 1711 * after scan'' bit in the scan command. To prevent the firmware 1712 * from associating after the scan, we set the ESSID to something 1713 * unlikely to be used by a real AP. 1714 * XXX would setting the desired BSSID to a multicast address work? 1715 */ 1716 memset(ssid, '\r', sizeof ssid); 1717 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ssid, sizeof ssid); 1718 if (error != 0) 1719 goto fail; 1720 1721 /* no mandatory BSSID */ 1722 DPRINTF(("Setting mandatory BSSID to null\n")); 1723 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1724 if (error != 0) 1725 goto fail; 1726 1727 scan.flags = htole32(IPW_SCAN_DO_NOT_ASSOCIATE | IPW_SCAN_MIXED_CELL); 1728 scan.channels = htole32(0x3fff); /* scan channels 1-14 */ 1729 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1730 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1731 if (error != 0) 1732 goto fail; 1733 1734 /* start scanning */ 1735 DPRINTF(("Enabling adapter\n")); 1736 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1737 if (error != 0) 1738 goto fail; 1739 1740 return; 1741fail: 1742 printf("%s: scan request failed (error=%d)\n", sc->sc_dev.dv_xname, 1743 error); 1744 ieee80211_end_scan(ifp); 1745} 1746 1747void 1748ipw_auth_and_assoc(void *arg1, void *arg2) 1749{ 1750 struct ipw_softc *sc = arg1; 1751 struct ieee80211com *ic = &sc->sc_ic; 1752 struct ieee80211_node *ni = ic->ic_bss; 1753 struct ipw_scan_options scan; 1754 struct ipw_security security; 1755 struct ipw_assoc_req assoc; 1756 uint32_t data; 1757 uint8_t chan; 1758 int s, error; 1759 1760 DPRINTF(("Disabling adapter\n")); 1761 error = ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1762 if (error != 0) 1763 goto fail; 1764#if 1 1765 /* wait at most one second for card to be disabled */ 1766 s = splnet(); 1767 error = tsleep(sc, 0, "ipwdis", hz); 1768 splx(s); 1769 if (error != 0) { 1770 printf("%s: timeout waiting for disabled state\n", 1771 sc->sc_dev.dv_xname); 1772 goto fail; 1773 } 1774#else 1775 /* Intel's Linux driver polls for the DISABLED state instead.. */ 1776 for (ntries = 0; ntries < 1000; ntries++) { 1777 if (ipw_read_table1(sc, IPW_INFO_CARD_DISABLED) == 1) 1778 break; 1779 DELAY(10); 1780 } 1781 if (ntries == 1000) { 1782 printf("%s: timeout waiting for disabled state\n", 1783 sc->sc_dev.dv_xname); 1784 goto fail; 1785 } 1786#endif 1787 1788 bzero(&security, sizeof security); 1789 security.authmode = IPW_AUTH_OPEN; 1790 security.ciphers = htole32(IPW_CIPHER_NONE); 1791 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1792 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1793 sizeof security); 1794 if (error != 0) 1795 goto fail; 1796 1797#ifdef IPW_DEBUG 1798 if (ipw_debug > 0) { 1799 printf("Setting ESSID to "); 1800 ieee80211_print_essid(ni->ni_essid, ni->ni_esslen); 1801 printf("\n"); 1802 } 1803#endif 1804 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ni->ni_essid, ni->ni_esslen); 1805 if (error != 0) 1806 goto fail; 1807 1808 DPRINTF(("Setting BSSID to %s\n", ether_sprintf(ni->ni_bssid))); 1809 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, ni->ni_bssid, 1810 IEEE80211_ADDR_LEN); 1811 if (error != 0) 1812 goto fail; 1813 1814 data = htole32((ic->ic_flags & (IEEE80211_F_WEPON | 1815 IEEE80211_F_RSNON)) ? IPW_PRIVACYON : 0); 1816 DPRINTF(("Setting privacy flags to 0x%x\n", letoh32(data))); 1817 error = ipw_cmd(sc, IPW_CMD_SET_PRIVACY_FLAGS, &data, sizeof data); 1818 if (error != 0) 1819 goto fail; 1820 1821 /* let firmware set the capinfo, lintval, and bssid fixed fields */ 1822 bzero(&assoc, sizeof assoc); 1823 if (ic->ic_flags & IEEE80211_F_RSNON) { 1824 uint8_t *frm = assoc.optie; 1825 1826 /* tell firmware to add a WPA or RSN IE in (Re)Assoc req */ 1827 if (ni->ni_rsnprotos & IEEE80211_PROTO_RSN) 1828 frm = ieee80211_add_rsn(frm, ic, ni); 1829 else if (ni->ni_rsnprotos & IEEE80211_PROTO_WPA) 1830 frm = ieee80211_add_wpa(frm, ic, ni); 1831 assoc.optie_len = htole32(frm - assoc.optie); 1832 } 1833 DPRINTF(("Preparing assocation request (optional IE length=%d)\n", 1834 letoh32(assoc.optie_len))); 1835 error = ipw_cmd(sc, IPW_CMD_SET_ASSOC_REQ, &assoc, sizeof assoc); 1836 if (error != 0) 1837 goto fail; 1838 1839 scan.flags = htole32(IPW_SCAN_MIXED_CELL); 1840 chan = ieee80211_chan2ieee(ic, ni->ni_chan); 1841 scan.channels = htole32(1 << (chan - 1)); 1842 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1843 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1844 if (error != 0) 1845 goto fail; 1846 1847 /* trigger scan+association */ 1848 DPRINTF(("Enabling adapter\n")); 1849 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1850 if (error != 0) 1851 goto fail; 1852 1853 return; 1854fail: 1855 printf("%s: association failed (error=%d)\n", sc->sc_dev.dv_xname, 1856 error); 1857 ieee80211_begin_scan(&ic->ic_if); 1858} 1859 1860int 1861ipw_config(struct ipw_softc *sc) 1862{ 1863 struct ieee80211com *ic = &sc->sc_ic; 1864 struct ifnet *ifp = &ic->ic_if; 1865 struct ipw_configuration config; 1866 uint32_t data; 1867 int error; 1868 1869 switch (ic->ic_opmode) { 1870 case IEEE80211_M_STA: 1871 data = htole32(IPW_MODE_BSS); 1872 break; 1873#ifndef IEEE80211_STA_ONLY 1874 case IEEE80211_M_IBSS: 1875 data = htole32(IPW_MODE_IBSS); 1876 break; 1877#endif 1878 case IEEE80211_M_MONITOR: 1879 data = htole32(IPW_MODE_MONITOR); 1880 break; 1881 default: 1882 /* should not get there */ 1883 return ENODEV; 1884 } 1885 DPRINTF(("Setting mode to %u\n", letoh32(data))); 1886 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1887 if (error != 0) 1888 return error; 1889 1890 if ( 1891#ifndef IEEE80211_STA_ONLY 1892 ic->ic_opmode == IEEE80211_M_IBSS || 1893#endif 1894 ic->ic_opmode == IEEE80211_M_MONITOR) { 1895 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1896 DPRINTF(("Setting channel to %u\n", letoh32(data))); 1897 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1898 if (error != 0) 1899 return error; 1900 } 1901 1902 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1903 DPRINTF(("Enabling adapter\n")); 1904 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1905 } 1906 1907 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 1908 DPRINTF(("Setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 1909 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1910 IEEE80211_ADDR_LEN); 1911 if (error != 0) 1912 return error; 1913 1914 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1915 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1X_ENABLE); 1916#ifndef IEEE80211_STA_ONLY 1917 if (ic->ic_opmode == IEEE80211_M_IBSS) 1918 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1919#endif 1920 if (ifp->if_flags & IFF_PROMISC) 1921 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1922 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1923 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1924 DPRINTF(("Setting configuration 0x%x\n", config.flags)); 1925 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1926 if (error != 0) 1927 return error; 1928 1929 data = htole32(ic->ic_rtsthreshold); 1930 DPRINTF(("Setting RTS threshold to %u\n", letoh32(data))); 1931 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1932 if (error != 0) 1933 return error; 1934 1935 data = htole32(ic->ic_fragthreshold); 1936 DPRINTF(("Setting frag threshold to %u\n", letoh32(data))); 1937 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1938 if (error != 0) 1939 return error; 1940 1941 data = htole32(0x3); /* 1, 2 */ 1942 DPRINTF(("Setting basic tx rates to 0x%x\n", letoh32(data))); 1943 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1944 if (error != 0) 1945 return error; 1946 1947 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1948 DPRINTF(("Setting tx rates to 0x%x\n", letoh32(data))); 1949 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1950 if (error != 0) 1951 return error; 1952 1953 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1954 DPRINTF(("Setting MSDU tx rates to 0x%x\n", letoh32(data))); 1955 error = ipw_cmd(sc, IPW_CMD_SET_MSDU_TX_RATES, &data, sizeof data); 1956 if (error != 0) 1957 return error; 1958 1959 data = htole32(IPW_POWER_MODE_CAM); 1960 DPRINTF(("Setting power mode to %u\n", letoh32(data))); 1961 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1962 if (error != 0) 1963 return error; 1964 1965#ifndef IEEE80211_STA_ONLY 1966 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1967 data = htole32(32); /* default value */ 1968 DPRINTF(("Setting tx power index to %u\n", letoh32(data))); 1969 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1970 sizeof data); 1971 if (error != 0) 1972 return error; 1973 1974 data = htole32(ic->ic_lintval); 1975 DPRINTF(("Setting beacon interval to %u\n", letoh32(data))); 1976 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1977 sizeof data); 1978 if (error != 0) 1979 return error; 1980 } 1981#endif 1982 return 0; 1983} 1984 1985int 1986ipw_init(struct ifnet *ifp) 1987{ 1988 struct ipw_softc *sc = ifp->if_softc; 1989 struct ieee80211com *ic = &sc->sc_ic; 1990 struct ipw_firmware fw; 1991 int error; 1992 1993 ipw_stop(ifp, 0); 1994 1995 if ((error = ipw_reset(sc)) != 0) { 1996 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 1997 goto fail1; 1998 } 1999 2000 if ((error = ipw_read_firmware(sc, &fw)) != 0) { 2001 printf("%s: error %d, could not read firmware\n", 2002 sc->sc_dev.dv_xname, error); 2003 goto fail1; 2004 } 2005 if ((error = ipw_load_ucode(sc, fw.ucode, fw.ucode_size)) != 0) { 2006 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 2007 goto fail2; 2008 } 2009 2010 ipw_stop_master(sc); 2011 2012 /* 2013 * Setup tx, rx and status rings. 2014 */ 2015 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2016 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 2017 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 2018 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 2019 sc->txold = IPW_NTBD - 1; /* latest bd index ack by firmware */ 2020 sc->txcur = 0; /* bd index to write to */ 2021 sc->txfree = IPW_NTBD - 2; 2022 2023 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2024 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 2025 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 2026 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 2027 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 2028 2029 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 2030 sc->status_map->dm_segs[0].ds_addr); 2031 2032 if ((error = ipw_load_firmware(sc, fw.main, fw.main_size)) != 0) { 2033 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 2034 goto fail2; 2035 } 2036 sc->sc_flags |= IPW_FLAG_FW_INITED; 2037 free(fw.data, M_DEVBUF); 2038 2039 /* retrieve information tables base addresses */ 2040 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2041 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2042 2043 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2044 2045 if ((error = ipw_config(sc)) != 0) { 2046 printf("%s: device configuration failed\n", 2047 sc->sc_dev.dv_xname); 2048 goto fail2; 2049 } 2050 2051 ifp->if_flags &= ~IFF_OACTIVE; 2052 ifp->if_flags |= IFF_RUNNING; 2053 2054 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2055 ieee80211_begin_scan(ifp); 2056 else 2057 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2058 2059 return 0; 2060 2061fail2: free(fw.data, M_DEVBUF); 2062fail1: ipw_stop(ifp, 0); 2063 return error; 2064} 2065 2066void 2067ipw_stop(struct ifnet *ifp, int disable) 2068{ 2069 struct ipw_softc *sc = ifp->if_softc; 2070 struct ieee80211com *ic = &sc->sc_ic; 2071 int i; 2072 2073 ipw_stop_master(sc); 2074 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2075 2076 ifp->if_timer = 0; 2077 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2078 2079 /* 2080 * Release tx buffers. 2081 */ 2082 for (i = 0; i < IPW_NTBD; i++) 2083 ipw_release_sbd(sc, &sc->stbd_list[i]); 2084 2085 /* in case we were scanning, release the scan "lock" */ 2086 ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; 2087 2088 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2089} 2090 2091void 2092ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2093 bus_size_t count) 2094{ 2095 for (; count > 0; offset++, datap++, count--) { 2096 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2097 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2098 } 2099} 2100 2101void 2102ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2103 bus_size_t count) 2104{ 2105 for (; count > 0; offset++, datap++, count--) { 2106 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2107 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2108 } 2109} 2110 2111struct cfdriver ipw_cd = { 2112 NULL, "ipw", DV_IFNET 2113}; 2114