if_ipw.c revision 1.92
1/* $OpenBSD: if_ipw.c,v 1.92 2010/08/27 20:09:01 deraadt Exp $ */ 2 3/*- 4 * Copyright (c) 2004-2008 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/* 21 * Driver for Intel PRO/Wireless 2100 802.11 network adapters. 22 */ 23 24#include "bpfilter.h" 25 26#include <sys/param.h> 27#include <sys/sockio.h> 28#include <sys/workq.h> 29#include <sys/mbuf.h> 30#include <sys/kernel.h> 31#include <sys/socket.h> 32#include <sys/systm.h> 33#include <sys/conf.h> 34#include <sys/device.h> 35 36#include <machine/bus.h> 37#include <machine/endian.h> 38#include <machine/intr.h> 39 40#include <dev/pci/pcireg.h> 41#include <dev/pci/pcivar.h> 42#include <dev/pci/pcidevs.h> 43 44#if NBPFILTER > 0 45#include <net/bpf.h> 46#endif 47#include <net/if.h> 48#include <net/if_arp.h> 49#include <net/if_dl.h> 50#include <net/if_media.h> 51#include <net/if_types.h> 52 53#include <netinet/in.h> 54#include <netinet/in_systm.h> 55#include <netinet/in_var.h> 56#include <netinet/if_ether.h> 57#include <netinet/ip.h> 58 59#include <net80211/ieee80211_var.h> 60#include <net80211/ieee80211_radiotap.h> 61 62#include <dev/pci/if_ipwreg.h> 63#include <dev/pci/if_ipwvar.h> 64 65int ipw_match(struct device *, void *, void *); 66void ipw_attach(struct device *, struct device *, void *); 67int ipw_activate(struct device *, int); 68void ipw_resume(void *, void *); 69void ipw_powerhook(int, void *); 70int ipw_dma_alloc(struct ipw_softc *); 71void ipw_release(struct ipw_softc *); 72int ipw_media_change(struct ifnet *); 73void ipw_media_status(struct ifnet *, struct ifmediareq *); 74int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 75uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 76void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 77void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 78void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 79 struct ipw_soft_bd *, struct ipw_soft_buf *); 80void ipw_notification_intr(struct ipw_softc *, 81 struct ipw_soft_buf *); 82void ipw_rx_intr(struct ipw_softc *); 83void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 84void ipw_tx_intr(struct ipw_softc *); 85int ipw_intr(void *); 86int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 87int ipw_send_mgmt(struct ieee80211com *, struct ieee80211_node *, 88 int, int, int); 89int ipw_tx_start(struct ifnet *, struct mbuf *, 90 struct ieee80211_node *); 91void ipw_start(struct ifnet *); 92void ipw_watchdog(struct ifnet *); 93int ipw_ioctl(struct ifnet *, u_long, caddr_t); 94uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 95void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 96int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 97 uint32_t *); 98void ipw_stop_master(struct ipw_softc *); 99int ipw_reset(struct ipw_softc *); 100int ipw_load_ucode(struct ipw_softc *, u_char *, int); 101int ipw_load_firmware(struct ipw_softc *, u_char *, int); 102int ipw_read_firmware(struct ipw_softc *, struct ipw_firmware *); 103void ipw_scan(void *, void *); 104void ipw_auth_and_assoc(void *, void *); 105int ipw_config(struct ipw_softc *); 106int ipw_init(struct ifnet *); 107void ipw_stop(struct ifnet *, int); 108void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 109 bus_size_t); 110void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 111 bus_size_t); 112 113static __inline uint8_t 114MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 115{ 116 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 117 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 118} 119 120static __inline uint32_t 121MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 122{ 123 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 124 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 125} 126 127#ifdef IPW_DEBUG 128#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 129#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 130int ipw_debug = 0; 131#else 132#define DPRINTF(x) 133#define DPRINTFN(n, x) 134#endif 135 136struct cfattach ipw_ca = { 137 sizeof (struct ipw_softc), ipw_match, ipw_attach, NULL, 138 ipw_activate 139}; 140 141int 142ipw_match(struct device *parent, void *match, void *aux) 143{ 144 struct pci_attach_args *pa = aux; 145 146 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 147 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 148 return 1; 149 150 return 0; 151} 152 153/* Base Address Register */ 154#define IPW_PCI_BAR0 0x10 155 156void 157ipw_attach(struct device *parent, struct device *self, void *aux) 158{ 159 struct ipw_softc *sc = (struct ipw_softc *)self; 160 struct ieee80211com *ic = &sc->sc_ic; 161 struct ifnet *ifp = &ic->ic_if; 162 struct pci_attach_args *pa = aux; 163 const char *intrstr; 164 bus_space_tag_t memt; 165 bus_space_handle_t memh; 166 bus_addr_t base; 167 pci_intr_handle_t ih; 168 pcireg_t data; 169 uint16_t val; 170 int error, i; 171 172 sc->sc_pct = pa->pa_pc; 173 sc->sc_pcitag = pa->pa_tag, 174 175 /* clear device specific PCI configuration register 0x41 */ 176 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 177 data &= ~0x0000ff00; 178 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 179 180 /* map the register window */ 181 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 182 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 183 if (error != 0) { 184 printf(": can't map mem space\n"); 185 return; 186 } 187 188 sc->sc_st = memt; 189 sc->sc_sh = memh; 190 sc->sc_dmat = pa->pa_dmat; 191 192 /* disable interrupts */ 193 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 194 195 if (pci_intr_map(pa, &ih) != 0) { 196 printf(": can't map interrupt\n"); 197 return; 198 } 199 200 intrstr = pci_intr_string(sc->sc_pct, ih); 201 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 202 sc->sc_dev.dv_xname); 203 if (sc->sc_ih == NULL) { 204 printf(": can't establish interrupt"); 205 if (intrstr != NULL) 206 printf(" at %s", intrstr); 207 printf("\n"); 208 return; 209 } 210 printf(": %s", intrstr); 211 212 if (ipw_reset(sc) != 0) { 213 printf(": could not reset adapter\n"); 214 return; 215 } 216 217 if (ipw_dma_alloc(sc) != 0) { 218 printf(": failed to allocate DMA resources\n"); 219 return; 220 } 221 222 ic->ic_phytype = IEEE80211_T_DS; 223 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 224 ic->ic_state = IEEE80211_S_INIT; 225 226 /* set device capabilities */ 227 ic->ic_caps = 228#ifndef IEEE80211_STA_ONLY 229 IEEE80211_C_IBSS | /* IBSS mode supported */ 230#endif 231 IEEE80211_C_MONITOR | /* monitor mode supported */ 232 IEEE80211_C_TXPMGT | /* tx power management */ 233 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 234 IEEE80211_C_WEP | /* s/w WEP */ 235 IEEE80211_C_RSN | /* WPA/RSN */ 236 IEEE80211_C_SCANALL; /* h/w scanning */ 237 238 /* read MAC address from EEPROM */ 239 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 240 ic->ic_myaddr[0] = val >> 8; 241 ic->ic_myaddr[1] = val & 0xff; 242 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 243 ic->ic_myaddr[2] = val >> 8; 244 ic->ic_myaddr[3] = val & 0xff; 245 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 246 ic->ic_myaddr[4] = val >> 8; 247 ic->ic_myaddr[5] = val & 0xff; 248 249 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 250 251 /* set supported .11b rates */ 252 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 253 254 /* set supported .11b channels (1 through 14) */ 255 for (i = 1; i <= 14; i++) { 256 ic->ic_channels[i].ic_freq = 257 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 258 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 259 } 260 261 /* IBSS channel undefined for now */ 262 ic->ic_ibss_chan = &ic->ic_channels[0]; 263 264 ifp->if_softc = sc; 265 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 266 ifp->if_ioctl = ipw_ioctl; 267 ifp->if_start = ipw_start; 268 ifp->if_watchdog = ipw_watchdog; 269 IFQ_SET_READY(&ifp->if_snd); 270 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 271 272 if_attach(ifp); 273 ieee80211_ifattach(ifp); 274 /* override state transition machine */ 275 sc->sc_newstate = ic->ic_newstate; 276 ic->ic_newstate = ipw_newstate; 277 ic->ic_send_mgmt = ipw_send_mgmt; 278 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 279 280 sc->powerhook = powerhook_establish(ipw_powerhook, sc); 281 282#if NBPFILTER > 0 283 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 284 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 285 286 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 287 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 288 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 289 290 sc->sc_txtap_len = sizeof sc->sc_txtapu; 291 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 292 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 293#endif 294} 295 296int 297ipw_activate(struct device *self, int act) 298{ 299 struct ipw_softc *sc = (struct ipw_softc *)self; 300 struct ifnet *ifp = &sc->sc_ic.ic_if; 301 302 switch (act) { 303 case DVACT_SUSPEND: 304 if (ifp->if_flags & IFF_RUNNING) 305 ipw_stop(ifp, 0); 306 break; 307 case DVACT_RESUME: 308 workq_queue_task(NULL, &sc->sc_resume_wqt, 0, 309 ipw_resume, sc, NULL); 310 break; 311 } 312 313 return 0; 314} 315 316void 317ipw_resume(void *arg1, void *arg2) 318{ 319 struct ipw_softc *sc = arg1; 320 struct ifnet *ifp = &sc->sc_ic.ic_if; 321 pcireg_t data; 322 int s; 323 324 /* clear device specific PCI configuration register 0x41 */ 325 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 326 data &= ~0x0000ff00; 327 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 328 329 s = splnet(); 330 while (sc->sc_flags & IPW_FLAG_BUSY) 331 tsleep(&sc->sc_flags, PZERO, "ipwpwr", 0); 332 sc->sc_flags |= IPW_FLAG_BUSY; 333 334 if (ifp->if_flags & IFF_UP) 335 ipw_init(ifp); 336 337 sc->sc_flags &= ~IPW_FLAG_BUSY; 338 wakeup(&sc->sc_flags); 339 splx(s); 340} 341 342void 343ipw_powerhook(int why, void *arg) 344{ 345 ipw_activate(arg, why); 346} 347 348int 349ipw_dma_alloc(struct ipw_softc *sc) 350{ 351 struct ipw_soft_bd *sbd; 352 struct ipw_soft_hdr *shdr; 353 struct ipw_soft_buf *sbuf; 354 int i, nsegs, error; 355 356 /* 357 * Allocate and map tx ring. 358 */ 359 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 360 BUS_DMA_NOWAIT, &sc->tbd_map); 361 if (error != 0) { 362 printf("%s: could not create tx ring DMA map\n", 363 sc->sc_dev.dv_xname); 364 goto fail; 365 } 366 367 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 368 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 369 if (error != 0) { 370 printf("%s: could not allocate tx ring DMA memory\n", 371 sc->sc_dev.dv_xname); 372 goto fail; 373 } 374 375 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 376 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 377 if (error != 0) { 378 printf("%s: can't map tx ring DMA memory\n", 379 sc->sc_dev.dv_xname); 380 goto fail; 381 } 382 383 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 384 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 385 if (error != 0) { 386 printf("%s: could not load tx ring DMA map\n", 387 sc->sc_dev.dv_xname); 388 goto fail; 389 } 390 391 /* 392 * Allocate and map rx ring. 393 */ 394 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 395 BUS_DMA_NOWAIT, &sc->rbd_map); 396 if (error != 0) { 397 printf("%s: could not create rx ring DMA map\n", 398 sc->sc_dev.dv_xname); 399 goto fail; 400 } 401 402 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 403 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 404 if (error != 0) { 405 printf("%s: could not allocate rx ring DMA memory\n", 406 sc->sc_dev.dv_xname); 407 goto fail; 408 } 409 410 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 411 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 412 if (error != 0) { 413 printf("%s: can't map rx ring DMA memory\n", 414 sc->sc_dev.dv_xname); 415 goto fail; 416 } 417 418 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 419 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 420 if (error != 0) { 421 printf("%s: could not load tx ring DMA map\n", 422 sc->sc_dev.dv_xname); 423 goto fail; 424 } 425 426 /* 427 * Allocate and map status ring. 428 */ 429 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 430 0, BUS_DMA_NOWAIT, &sc->status_map); 431 if (error != 0) { 432 printf("%s: could not create status ring DMA map\n", 433 sc->sc_dev.dv_xname); 434 goto fail; 435 } 436 437 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 438 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 439 if (error != 0) { 440 printf("%s: could not allocate status ring DMA memory\n", 441 sc->sc_dev.dv_xname); 442 goto fail; 443 } 444 445 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 446 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 447 if (error != 0) { 448 printf("%s: can't map status ring DMA memory\n", 449 sc->sc_dev.dv_xname); 450 goto fail; 451 } 452 453 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 454 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 455 if (error != 0) { 456 printf("%s: could not load status ring DMA map\n", 457 sc->sc_dev.dv_xname); 458 goto fail; 459 } 460 461 /* 462 * Allocate command DMA map. 463 */ 464 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 465 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 466 if (error != 0) { 467 printf("%s: could not create command DMA map\n", 468 sc->sc_dev.dv_xname); 469 goto fail; 470 } 471 472 /* 473 * Allocate headers DMA maps. 474 */ 475 SLIST_INIT(&sc->free_shdr); 476 for (i = 0; i < IPW_NDATA; i++) { 477 shdr = &sc->shdr_list[i]; 478 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_hdr), 479 1, sizeof (struct ipw_hdr), 0, BUS_DMA_NOWAIT, &shdr->map); 480 if (error != 0) { 481 printf("%s: could not create header DMA map\n", 482 sc->sc_dev.dv_xname); 483 goto fail; 484 } 485 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 486 } 487 488 /* 489 * Allocate tx buffers DMA maps. 490 */ 491 SLIST_INIT(&sc->free_sbuf); 492 for (i = 0; i < IPW_NDATA; i++) { 493 sbuf = &sc->tx_sbuf_list[i]; 494 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, IPW_MAX_NSEG, 495 MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 496 if (error != 0) { 497 printf("%s: could not create tx DMA map\n", 498 sc->sc_dev.dv_xname); 499 goto fail; 500 } 501 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 502 } 503 504 /* 505 * Initialize tx ring. 506 */ 507 for (i = 0; i < IPW_NTBD; i++) { 508 sbd = &sc->stbd_list[i]; 509 sbd->bd = &sc->tbd_list[i]; 510 sbd->type = IPW_SBD_TYPE_NOASSOC; 511 } 512 513 /* 514 * Pre-allocate rx buffers and DMA maps. 515 */ 516 for (i = 0; i < IPW_NRBD; i++) { 517 sbd = &sc->srbd_list[i]; 518 sbuf = &sc->rx_sbuf_list[i]; 519 sbd->bd = &sc->rbd_list[i]; 520 521 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 522 if (sbuf->m == NULL) { 523 printf("%s: could not allocate rx mbuf\n", 524 sc->sc_dev.dv_xname); 525 error = ENOMEM; 526 goto fail; 527 } 528 MCLGET(sbuf->m, M_DONTWAIT); 529 if (!(sbuf->m->m_flags & M_EXT)) { 530 m_freem(sbuf->m); 531 printf("%s: could not allocate rx mbuf cluster\n", 532 sc->sc_dev.dv_xname); 533 error = ENOMEM; 534 goto fail; 535 } 536 537 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 538 0, BUS_DMA_NOWAIT, &sbuf->map); 539 if (error != 0) { 540 printf("%s: could not create rx DMA map\n", 541 sc->sc_dev.dv_xname); 542 goto fail; 543 } 544 545 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 546 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 547 if (error != 0) { 548 printf("%s: can't map rx DMA memory\n", 549 sc->sc_dev.dv_xname); 550 goto fail; 551 } 552 553 sbd->type = IPW_SBD_TYPE_DATA; 554 sbd->priv = sbuf; 555 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 556 sbd->bd->len = htole32(MCLBYTES); 557 } 558 559 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 560 BUS_DMASYNC_PREWRITE); 561 562 return 0; 563 564fail: ipw_release(sc); 565 return error; 566} 567 568void 569ipw_release(struct ipw_softc *sc) 570{ 571 struct ipw_soft_buf *sbuf; 572 int i; 573 574 if (sc->tbd_map != NULL) { 575 if (sc->tbd_list != NULL) { 576 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 577 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 578 IPW_TBD_SZ); 579 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 580 } 581 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 582 } 583 584 if (sc->rbd_map != NULL) { 585 if (sc->rbd_list != NULL) { 586 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 587 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 588 IPW_RBD_SZ); 589 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 590 } 591 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 592 } 593 594 if (sc->status_map != NULL) { 595 if (sc->status_list != NULL) { 596 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 597 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 598 IPW_RBD_SZ); 599 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 600 } 601 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 602 } 603 604 if (sc->cmd_map != NULL) 605 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 606 607 for (i = 0; i < IPW_NDATA; i++) 608 bus_dmamap_destroy(sc->sc_dmat, sc->shdr_list[i].map); 609 610 for (i = 0; i < IPW_NDATA; i++) 611 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 612 613 for (i = 0; i < IPW_NRBD; i++) { 614 sbuf = &sc->rx_sbuf_list[i]; 615 if (sbuf->map != NULL) { 616 if (sbuf->m != NULL) { 617 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 618 m_freem(sbuf->m); 619 } 620 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 621 } 622 } 623} 624 625int 626ipw_media_change(struct ifnet *ifp) 627{ 628 int error; 629 630 error = ieee80211_media_change(ifp); 631 if (error != ENETRESET) 632 return error; 633 634 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 635 ipw_init(ifp); 636 637 return 0; 638} 639 640void 641ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 642{ 643 struct ipw_softc *sc = ifp->if_softc; 644 struct ieee80211com *ic = &sc->sc_ic; 645 static const struct { 646 uint32_t val; 647 int rate; 648 } rates[] = { 649 { IPW_RATE_DS1, 2 }, 650 { IPW_RATE_DS2, 4 }, 651 { IPW_RATE_DS5, 11 }, 652 { IPW_RATE_DS11, 22 }, 653 }; 654 uint32_t val; 655 int rate, i; 656 657 imr->ifm_status = IFM_AVALID; 658 imr->ifm_active = IFM_IEEE80211; 659 if (ic->ic_state == IEEE80211_S_RUN) 660 imr->ifm_status |= IFM_ACTIVE; 661 662 /* read current transmission rate from adapter */ 663 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 664 val &= 0xf; 665 666 /* convert rate to 802.11 rate */ 667 for (i = 0; i < nitems(rates) && rates[i].val != val; i++); 668 rate = (i < nitems(rates)) ? rates[i].rate : 0; 669 670 imr->ifm_active |= IFM_IEEE80211_11B; 671 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 672 switch (ic->ic_opmode) { 673 case IEEE80211_M_STA: 674 break; 675#ifndef IEEE80211_STA_ONLY 676 case IEEE80211_M_IBSS: 677 imr->ifm_active |= IFM_IEEE80211_IBSS; 678 break; 679#endif 680 case IEEE80211_M_MONITOR: 681 imr->ifm_active |= IFM_IEEE80211_MONITOR; 682 break; 683 default: 684 /* should not get there */ 685 break; 686 } 687} 688 689int 690ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 691{ 692 struct ipw_softc *sc = ic->ic_softc; 693 int error; 694 695 switch (nstate) { 696 case IEEE80211_S_SCAN: 697 error = workq_add_task(NULL, 0, ipw_scan, sc, NULL); 698 if (error != 0) 699 return error; 700 break; 701 702 case IEEE80211_S_AUTH: 703 error = workq_add_task(NULL, 0, ipw_auth_and_assoc, sc, NULL); 704 if (error != 0) 705 return error; 706 break; 707 708 case IEEE80211_S_RUN: 709 case IEEE80211_S_INIT: 710 case IEEE80211_S_ASSOC: 711 /* nothing to do */ 712 break; 713 } 714 715 ic->ic_state = nstate; 716 return 0; 717} 718 719/* 720 * Read 16 bits at address 'addr' from the Microwire EEPROM. 721 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 722 */ 723uint16_t 724ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 725{ 726 uint32_t tmp; 727 uint16_t val; 728 int n; 729 730 /* clock C once before the first command */ 731 IPW_EEPROM_CTL(sc, 0); 732 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 733 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 734 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 735 736 /* write start bit (1) */ 737 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 738 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 739 740 /* write READ opcode (10) */ 741 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 742 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 743 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 744 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 745 746 /* write address A7-A0 */ 747 for (n = 7; n >= 0; n--) { 748 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 749 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 750 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 751 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 752 } 753 754 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 755 756 /* read data Q15-Q0 */ 757 val = 0; 758 for (n = 15; n >= 0; n--) { 759 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 760 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 761 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 762 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 763 } 764 765 IPW_EEPROM_CTL(sc, 0); 766 767 /* clear Chip Select and clock C */ 768 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 769 IPW_EEPROM_CTL(sc, 0); 770 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 771 772 return val; 773} 774 775void 776ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 777{ 778 struct ipw_cmd *cmd; 779 780 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 781 BUS_DMASYNC_POSTREAD); 782 783 cmd = mtod(sbuf->m, struct ipw_cmd *); 784 785 DPRINTFN(2, ("received command ack type=%u,status=%u\n", 786 letoh32(cmd->type), letoh32(cmd->status))); 787 788 wakeup(&sc->cmd); 789} 790 791void 792ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 793{ 794 struct ieee80211com *ic = &sc->sc_ic; 795 struct ifnet *ifp = &ic->ic_if; 796 uint32_t state; 797 798 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 799 BUS_DMASYNC_POSTREAD); 800 801 state = letoh32(*mtod(sbuf->m, uint32_t *)); 802 803 DPRINTFN(2, ("firmware state changed to 0x%x\n", state)); 804 805 switch (state) { 806 case IPW_STATE_ASSOCIATED: 807 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 808 break; 809 810 case IPW_STATE_SCANNING: 811 if (ic->ic_state == IEEE80211_S_RUN) 812 ieee80211_begin_scan(ifp); 813 break; 814 815 case IPW_STATE_SCAN_COMPLETE: 816 if (ic->ic_state == IEEE80211_S_SCAN) 817 ieee80211_end_scan(ifp); 818 break; 819 820 case IPW_STATE_ASSOCIATION_LOST: 821 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 822 break; 823 824 case IPW_STATE_DISABLED: 825 wakeup(sc); 826 break; 827 828 case IPW_STATE_RADIO_DISABLED: 829 ifp->if_flags &= ~IFF_UP; 830 ipw_stop(&ic->ic_if, 1); 831 break; 832 } 833} 834 835void 836ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 837 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 838{ 839 struct ieee80211com *ic = &sc->sc_ic; 840 struct ifnet *ifp = &ic->ic_if; 841 struct mbuf *mnew, *m; 842 struct ieee80211_frame *wh; 843 struct ieee80211_rxinfo rxi; 844 struct ieee80211_node *ni; 845 int error; 846 847 DPRINTFN(5, ("received data frame len=%u,rssi=%u\n", 848 letoh32(status->len), status->rssi)); 849 850 /* 851 * Try to allocate a new mbuf for this ring element and load it before 852 * processing the current mbuf. If the ring element cannot be loaded, 853 * drop the received packet and reuse the old mbuf. In the unlikely 854 * case that the old mbuf can't be reloaded either, explicitly panic. 855 */ 856 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 857 if (mnew == NULL) { 858 ifp->if_ierrors++; 859 return; 860 } 861 MCLGET(mnew, M_DONTWAIT); 862 if (!(mnew->m_flags & M_EXT)) { 863 m_freem(mnew); 864 ifp->if_ierrors++; 865 return; 866 } 867 868 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 869 BUS_DMASYNC_POSTREAD); 870 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 871 872 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(mnew, void *), 873 MCLBYTES, NULL, BUS_DMA_NOWAIT); 874 if (error != 0) { 875 m_freem(mnew); 876 877 /* try to reload the old mbuf */ 878 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 879 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 880 if (error != 0) { 881 /* very unlikely that it will fail... */ 882 panic("%s: could not load old rx mbuf", 883 sc->sc_dev.dv_xname); 884 } 885 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 886 ifp->if_ierrors++; 887 return; 888 } 889 890 m = sbuf->m; 891 sbuf->m = mnew; 892 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 893 894 /* finalize mbuf */ 895 m->m_pkthdr.rcvif = ifp; 896 m->m_pkthdr.len = m->m_len = letoh32(status->len); 897 898#if NBPFILTER > 0 899 if (sc->sc_drvbpf != NULL) { 900 struct mbuf mb; 901 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 902 903 tap->wr_flags = 0; 904 tap->wr_antsignal = status->rssi; 905 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 906 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 907 908 mb.m_data = (caddr_t)tap; 909 mb.m_len = sc->sc_rxtap_len; 910 mb.m_next = m; 911 mb.m_nextpkt = NULL; 912 mb.m_type = 0; 913 mb.m_flags = 0; 914 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 915 } 916#endif 917 918 wh = mtod(m, struct ieee80211_frame *); 919 ni = ieee80211_find_rxnode(ic, wh); 920 921 /* send the frame to the upper layer */ 922 rxi.rxi_flags = 0; 923 rxi.rxi_rssi = status->rssi; 924 rxi.rxi_tstamp = 0; /* unused */ 925 ieee80211_input(ifp, m, ni, &rxi); 926 927 ieee80211_release_node(ic, ni); 928} 929 930void 931ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 932{ 933 DPRINTFN(2, ("received notification\n")); 934} 935 936void 937ipw_rx_intr(struct ipw_softc *sc) 938{ 939 struct ipw_status *status; 940 struct ipw_soft_bd *sbd; 941 struct ipw_soft_buf *sbuf; 942 uint32_t r, i; 943 944 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 945 946 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 947 948 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 949 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 950 BUS_DMASYNC_POSTREAD); 951 952 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 953 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 954 BUS_DMASYNC_POSTREAD); 955 956 status = &sc->status_list[i]; 957 sbd = &sc->srbd_list[i]; 958 sbuf = sbd->priv; 959 960 switch (letoh16(status->code) & 0xf) { 961 case IPW_STATUS_CODE_COMMAND: 962 ipw_command_intr(sc, sbuf); 963 break; 964 965 case IPW_STATUS_CODE_NEWSTATE: 966 ipw_newstate_intr(sc, sbuf); 967 break; 968 969 case IPW_STATUS_CODE_DATA_802_3: 970 case IPW_STATUS_CODE_DATA_802_11: 971 ipw_data_intr(sc, status, sbd, sbuf); 972 break; 973 974 case IPW_STATUS_CODE_NOTIFICATION: 975 ipw_notification_intr(sc, sbuf); 976 break; 977 978 default: 979 printf("%s: unknown status code %u\n", 980 sc->sc_dev.dv_xname, letoh16(status->code)); 981 } 982 sbd->bd->flags = 0; 983 984 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 985 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 986 BUS_DMASYNC_PREWRITE); 987 } 988 989 /* tell the firmware what we have processed */ 990 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 991 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 992} 993 994void 995ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 996{ 997 struct ieee80211com *ic = &sc->sc_ic; 998 struct ipw_soft_hdr *shdr; 999 struct ipw_soft_buf *sbuf; 1000 1001 switch (sbd->type) { 1002 case IPW_SBD_TYPE_COMMAND: 1003 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 1004 break; 1005 1006 case IPW_SBD_TYPE_HEADER: 1007 shdr = sbd->priv; 1008 bus_dmamap_unload(sc->sc_dmat, shdr->map); 1009 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 1010 break; 1011 1012 case IPW_SBD_TYPE_DATA: 1013 sbuf = sbd->priv; 1014 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1015 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1016 1017 m_freem(sbuf->m); 1018 1019 if (sbuf->ni != NULL) 1020 ieee80211_release_node(ic, sbuf->ni); 1021 1022 /* kill watchdog timer */ 1023 sc->sc_tx_timer = 0; 1024 break; 1025 } 1026 sbd->type = IPW_SBD_TYPE_NOASSOC; 1027} 1028 1029void 1030ipw_tx_intr(struct ipw_softc *sc) 1031{ 1032 struct ifnet *ifp = &sc->sc_ic.ic_if; 1033 struct ipw_soft_bd *sbd; 1034 uint32_t r, i; 1035 1036 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 1037 1038 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1039 sbd = &sc->stbd_list[i]; 1040 1041 if (sbd->type == IPW_SBD_TYPE_DATA) 1042 ifp->if_opackets++; 1043 1044 ipw_release_sbd(sc, sbd); 1045 sc->txfree++; 1046 } 1047 1048 /* remember what the firmware has processed */ 1049 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1050 1051 /* call start() since some buffer descriptors have been released */ 1052 ifp->if_flags &= ~IFF_OACTIVE; 1053 (*ifp->if_start)(ifp); 1054} 1055 1056int 1057ipw_intr(void *arg) 1058{ 1059 struct ipw_softc *sc = arg; 1060 struct ifnet *ifp = &sc->sc_ic.ic_if; 1061 uint32_t r; 1062 1063 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) 1064 return 0; 1065 1066 /* disable interrupts */ 1067 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1068 1069 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1070 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 1071 ifp->if_flags &= ~IFF_UP; 1072 ipw_stop(ifp, 1); 1073 return 1; 1074 } 1075 1076 if (r & IPW_INTR_FW_INIT_DONE) 1077 wakeup(sc); 1078 1079 if (r & IPW_INTR_RX_TRANSFER) 1080 ipw_rx_intr(sc); 1081 1082 if (r & IPW_INTR_TX_TRANSFER) 1083 ipw_tx_intr(sc); 1084 1085 /* acknowledge interrupts */ 1086 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1087 1088 /* re-enable interrupts */ 1089 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1090 1091 return 1; 1092} 1093 1094int 1095ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1096{ 1097 struct ipw_soft_bd *sbd; 1098 int s, error; 1099 1100 s = splnet(); 1101 1102 sc->cmd.type = htole32(type); 1103 sc->cmd.subtype = htole32(0); 1104 sc->cmd.len = htole32(len); 1105 sc->cmd.seq = htole32(0); 1106 if (data != NULL) 1107 bcopy(data, sc->cmd.data, len); 1108 1109 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 1110 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 1111 if (error != 0) { 1112 printf("%s: can't map command DMA memory\n", 1113 sc->sc_dev.dv_xname); 1114 splx(s); 1115 return error; 1116 } 1117 1118 sbd = &sc->stbd_list[sc->txcur]; 1119 sbd->type = IPW_SBD_TYPE_COMMAND; 1120 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1121 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1122 sbd->bd->nfrag = 1; 1123 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1124 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1125 1126 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1127 BUS_DMASYNC_PREWRITE); 1128 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1129 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1130 BUS_DMASYNC_PREWRITE); 1131 1132 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1133 sc->txfree--; 1134 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1135 1136 DPRINTFN(2, ("sending command type=%u,len=%u\n", type, len)); 1137 1138 /* wait at most one second for command to complete */ 1139 error = tsleep(&sc->cmd, 0, "ipwcmd", hz); 1140 splx(s); 1141 1142 return error; 1143} 1144 1145/* ARGSUSED */ 1146int 1147ipw_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type, 1148 int arg1, int arg2) 1149{ 1150 return EOPNOTSUPP; 1151} 1152 1153int 1154ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 1155{ 1156 struct ipw_softc *sc = ifp->if_softc; 1157 struct ieee80211com *ic = &sc->sc_ic; 1158 struct ieee80211_frame *wh; 1159 struct ieee80211_key *k; 1160 struct mbuf *m1; 1161 struct ipw_soft_bd *sbd; 1162 struct ipw_soft_hdr *shdr; 1163 struct ipw_soft_buf *sbuf; 1164 int error, i; 1165 1166 wh = mtod(m, struct ieee80211_frame *); 1167 1168 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1169 k = ieee80211_get_txkey(ic, wh, ni); 1170 1171 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1172 return ENOBUFS; 1173 1174 /* packet header may have moved, reset our local pointer */ 1175 wh = mtod(m, struct ieee80211_frame *); 1176 } 1177 1178#if NBPFILTER > 0 1179 if (sc->sc_drvbpf != NULL) { 1180 struct mbuf mb; 1181 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1182 1183 tap->wt_flags = 0; 1184 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1185 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1186 1187 mb.m_data = (caddr_t)tap; 1188 mb.m_len = sc->sc_txtap_len; 1189 mb.m_next = m; 1190 mb.m_nextpkt = NULL; 1191 mb.m_type = 0; 1192 mb.m_flags = 0; 1193 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1194 } 1195#endif 1196 1197 shdr = SLIST_FIRST(&sc->free_shdr); 1198 sbuf = SLIST_FIRST(&sc->free_sbuf); 1199 1200 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1201 shdr->hdr.subtype = htole32(0); 1202 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) ? 1 : 0; 1203 shdr->hdr.encrypt = 0; 1204 shdr->hdr.keyidx = 0; 1205 shdr->hdr.keysz = 0; 1206 shdr->hdr.fragmentsz = htole16(0); 1207 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1208 if (ic->ic_opmode == IEEE80211_M_STA) 1209 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1210 else 1211 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1212 1213 /* trim IEEE802.11 header */ 1214 m_adj(m, sizeof (struct ieee80211_frame)); 1215 1216 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 1217 if (error != 0 && error != EFBIG) { 1218 printf("%s: can't map mbuf (error %d)\n", 1219 sc->sc_dev.dv_xname, error); 1220 m_freem(m); 1221 return error; 1222 } 1223 if (error != 0) { 1224 /* too many fragments, linearize */ 1225 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1226 if (m1 == NULL) { 1227 m_freem(m); 1228 return ENOBUFS; 1229 } 1230 if (m->m_pkthdr.len > MHLEN) { 1231 MCLGET(m1, M_DONTWAIT); 1232 if (!(m1->m_flags & M_EXT)) { 1233 m_freem(m); 1234 m_freem(m1); 1235 return ENOBUFS; 1236 } 1237 } 1238 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, caddr_t)); 1239 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 1240 m_freem(m); 1241 m = m1; 1242 1243 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, 1244 BUS_DMA_NOWAIT); 1245 if (error != 0) { 1246 printf("%s: can't map mbuf (error %d)\n", 1247 sc->sc_dev.dv_xname, error); 1248 m_freem(m); 1249 return error; 1250 } 1251 } 1252 1253 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 1254 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 1255 if (error != 0) { 1256 printf("%s: can't map header DMA memory (error %d)\n", 1257 sc->sc_dev.dv_xname, error); 1258 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1259 m_freem(m); 1260 return error; 1261 } 1262 1263 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1264 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1265 1266 sbd = &sc->stbd_list[sc->txcur]; 1267 sbd->type = IPW_SBD_TYPE_HEADER; 1268 sbd->priv = shdr; 1269 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 1270 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1271 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1272 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1273 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1274 1275 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1276 sc->txcur * sizeof (struct ipw_bd), 1277 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1278 1279 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1280 sc->txfree--; 1281 1282 sbuf->m = m; 1283 sbuf->ni = ni; 1284 1285 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1286 sbd = &sc->stbd_list[sc->txcur]; 1287 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1288 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1289 sbd->bd->nfrag = 0; /* used only in first bd */ 1290 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1291 if (i == sbuf->map->dm_nsegs - 1) { 1292 sbd->type = IPW_SBD_TYPE_DATA; 1293 sbd->priv = sbuf; 1294 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1295 } else { 1296 sbd->type = IPW_SBD_TYPE_NOASSOC; 1297 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1298 } 1299 1300 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1301 sc->txcur * sizeof (struct ipw_bd), 1302 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1303 1304 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1305 sc->txfree--; 1306 } 1307 1308 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1309 BUS_DMASYNC_PREWRITE); 1310 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 1311 BUS_DMASYNC_PREWRITE); 1312 1313 /* inform firmware about this new packet */ 1314 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1315 1316 return 0; 1317} 1318 1319void 1320ipw_start(struct ifnet *ifp) 1321{ 1322 struct ipw_softc *sc = ifp->if_softc; 1323 struct ieee80211com *ic = &sc->sc_ic; 1324 struct ieee80211_node *ni; 1325 struct mbuf *m; 1326 1327 if (ic->ic_state != IEEE80211_S_RUN) 1328 return; 1329 1330 for (;;) { 1331 IFQ_POLL(&ifp->if_snd, m); 1332 if (m == NULL) 1333 break; 1334 1335 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1336 ifp->if_flags |= IFF_OACTIVE; 1337 break; 1338 } 1339 IFQ_DEQUEUE(&ifp->if_snd, m); 1340#if NBPFILTER > 0 1341 if (ifp->if_bpf != NULL) 1342 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1343#endif 1344 m = ieee80211_encap(ifp, m, &ni); 1345 if (m == NULL) 1346 continue; 1347#if NBPFILTER > 0 1348 if (ic->ic_rawbpf != NULL) 1349 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1350#endif 1351 if (ipw_tx_start(ifp, m, ni) != 0) { 1352 if (ni != NULL) 1353 ieee80211_release_node(ic, ni); 1354 ifp->if_oerrors++; 1355 break; 1356 } 1357 1358 /* start watchdog timer */ 1359 sc->sc_tx_timer = 5; 1360 ifp->if_timer = 1; 1361 } 1362} 1363 1364void 1365ipw_watchdog(struct ifnet *ifp) 1366{ 1367 struct ipw_softc *sc = ifp->if_softc; 1368 1369 ifp->if_timer = 0; 1370 1371 if (sc->sc_tx_timer > 0) { 1372 if (--sc->sc_tx_timer == 0) { 1373 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1374 ifp->if_flags &= ~IFF_UP; 1375 ipw_stop(ifp, 1); 1376 ifp->if_oerrors++; 1377 return; 1378 } 1379 ifp->if_timer = 1; 1380 } 1381 1382 ieee80211_watchdog(ifp); 1383} 1384 1385int 1386ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1387{ 1388 struct ipw_softc *sc = ifp->if_softc; 1389 struct ieee80211com *ic = &sc->sc_ic; 1390 struct ifaddr *ifa; 1391 struct ifreq *ifr; 1392 int s, error = 0; 1393 1394 s = splnet(); 1395 /* 1396 * Prevent processes from entering this function while another 1397 * process is tsleep'ing in it. 1398 */ 1399 while ((sc->sc_flags & IPW_FLAG_BUSY) && error == 0) 1400 error = tsleep(&sc->sc_flags, PCATCH, "ipwioc", 0); 1401 if (error != 0) { 1402 splx(s); 1403 return error; 1404 } 1405 sc->sc_flags |= IPW_FLAG_BUSY; 1406 1407 switch (cmd) { 1408 case SIOCSIFADDR: 1409 ifa = (struct ifaddr *)data; 1410 ifp->if_flags |= IFF_UP; 1411#ifdef INET 1412 if (ifa->ifa_addr->sa_family == AF_INET) 1413 arp_ifinit(&ic->ic_ac, ifa); 1414#endif 1415 /* FALLTHROUGH */ 1416 case SIOCSIFFLAGS: 1417 if (ifp->if_flags & IFF_UP) { 1418 if (!(ifp->if_flags & IFF_RUNNING)) 1419 ipw_init(ifp); 1420 } else { 1421 if (ifp->if_flags & IFF_RUNNING) 1422 ipw_stop(ifp, 1); 1423 } 1424 break; 1425 1426 case SIOCADDMULTI: 1427 case SIOCDELMULTI: 1428 ifr = (struct ifreq *)data; 1429 error = (cmd == SIOCADDMULTI) ? 1430 ether_addmulti(ifr, &ic->ic_ac) : 1431 ether_delmulti(ifr, &ic->ic_ac); 1432 1433 if (error == ENETRESET) 1434 error = 0; 1435 break; 1436 1437 case SIOCG80211TXPOWER: 1438 /* 1439 * If the hardware radio transmitter switch is off, report a 1440 * tx power of IEEE80211_TXPOWER_MIN to indicate that radio 1441 * transmitter is killed. 1442 */ 1443 ((struct ieee80211_txpower *)data)->i_val = 1444 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 1445 IEEE80211_TXPOWER_MIN : sc->sc_ic.ic_txpower; 1446 break; 1447 1448 default: 1449 error = ieee80211_ioctl(ifp, cmd, data); 1450 } 1451 1452 if (error == ENETRESET) { 1453 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1454 (IFF_UP | IFF_RUNNING)) 1455 ipw_init(ifp); 1456 error = 0; 1457 } 1458 1459 sc->sc_flags &= ~IPW_FLAG_BUSY; 1460 wakeup(&sc->sc_flags); 1461 splx(s); 1462 return error; 1463} 1464 1465uint32_t 1466ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1467{ 1468 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1469} 1470 1471void 1472ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1473{ 1474 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1475} 1476 1477int 1478ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1479{ 1480 uint32_t addr, info; 1481 uint16_t count, size; 1482 uint32_t total; 1483 1484 /* addr[4] + count[2] + size[2] */ 1485 addr = MEM_READ_4(sc, sc->table2_base + off); 1486 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1487 1488 count = info >> 16; 1489 size = info & 0xffff; 1490 total = count * size; 1491 1492 if (total > *len) { 1493 *len = total; 1494 return EINVAL; 1495 } 1496 *len = total; 1497 ipw_read_mem_1(sc, addr, buf, total); 1498 1499 return 0; 1500} 1501 1502void 1503ipw_stop_master(struct ipw_softc *sc) 1504{ 1505 uint32_t tmp; 1506 int ntries; 1507 1508 /* disable interrupts */ 1509 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1510 1511 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1512 for (ntries = 0; ntries < 50; ntries++) { 1513 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1514 break; 1515 DELAY(10); 1516 } 1517 if (ntries == 50) 1518 printf("%s: timeout waiting for master\n", 1519 sc->sc_dev.dv_xname); 1520 1521 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1522 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1523 1524 sc->sc_flags &= ~IPW_FLAG_FW_INITED; 1525} 1526 1527int 1528ipw_reset(struct ipw_softc *sc) 1529{ 1530 uint32_t tmp; 1531 int ntries; 1532 1533 ipw_stop_master(sc); 1534 1535 /* move adapter to D0 state */ 1536 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1537 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1538 1539 /* wait for clock stabilization */ 1540 for (ntries = 0; ntries < 1000; ntries++) { 1541 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1542 break; 1543 DELAY(200); 1544 } 1545 if (ntries == 1000) 1546 return EIO; 1547 1548 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1549 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1550 1551 DELAY(10); 1552 1553 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1554 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1555 1556 return 0; 1557} 1558 1559int 1560ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1561{ 1562 int ntries; 1563 1564 /* voodoo from the Intel Linux driver */ 1565 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1566 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1567 1568 MEM_WRITE_2(sc, 0x220000, 0x0703); 1569 MEM_WRITE_2(sc, 0x220000, 0x0707); 1570 1571 MEM_WRITE_1(sc, 0x210014, 0x72); 1572 MEM_WRITE_1(sc, 0x210014, 0x72); 1573 1574 MEM_WRITE_1(sc, 0x210000, 0x40); 1575 MEM_WRITE_1(sc, 0x210000, 0x00); 1576 MEM_WRITE_1(sc, 0x210000, 0x40); 1577 1578 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1579 1580 MEM_WRITE_1(sc, 0x210000, 0x00); 1581 MEM_WRITE_1(sc, 0x210000, 0x00); 1582 MEM_WRITE_1(sc, 0x210000, 0x80); 1583 1584 MEM_WRITE_2(sc, 0x220000, 0x0703); 1585 MEM_WRITE_2(sc, 0x220000, 0x0707); 1586 1587 MEM_WRITE_1(sc, 0x210014, 0x72); 1588 MEM_WRITE_1(sc, 0x210014, 0x72); 1589 1590 MEM_WRITE_1(sc, 0x210000, 0x00); 1591 MEM_WRITE_1(sc, 0x210000, 0x80); 1592 1593 for (ntries = 0; ntries < 100; ntries++) { 1594 if (MEM_READ_1(sc, 0x210000) & 1) 1595 break; 1596 DELAY(1000); 1597 } 1598 if (ntries == 100) { 1599 printf("%s: timeout waiting for ucode to initialize\n", 1600 sc->sc_dev.dv_xname); 1601 return EIO; 1602 } 1603 1604 MEM_WRITE_4(sc, 0x3000e0, 0); 1605 1606 return 0; 1607} 1608 1609/* set of macros to handle unaligned little endian data in firmware image */ 1610#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1611#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1612int 1613ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1614{ 1615 u_char *p, *end; 1616 uint32_t tmp, dst; 1617 uint16_t len; 1618 int error; 1619 1620 p = fw; 1621 end = fw + size; 1622 while (p < end) { 1623 if (p + 6 > end) 1624 return EINVAL; 1625 1626 dst = GETLE32(p); p += 4; 1627 len = GETLE16(p); p += 2; 1628 1629 if (p + len > end) 1630 return EINVAL; 1631 1632 ipw_write_mem_1(sc, dst, p, len); 1633 p += len; 1634 } 1635 1636 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1637 IPW_IO_LED_OFF); 1638 1639 /* allow interrupts so we know when the firmware is inited */ 1640 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1641 1642 /* tell the adapter to initialize the firmware */ 1643 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1644 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1645 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1646 1647 /* wait at most one second for firmware initialization to complete */ 1648 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1649 printf("%s: timeout waiting for firmware initialization to " 1650 "complete\n", sc->sc_dev.dv_xname); 1651 return error; 1652 } 1653 1654 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1655 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1656 IPW_IO_GPIO3_MASK); 1657 1658 return 0; 1659} 1660 1661int 1662ipw_read_firmware(struct ipw_softc *sc, struct ipw_firmware *fw) 1663{ 1664 const struct ipw_firmware_hdr *hdr; 1665 const char *name; 1666 size_t size; 1667 int error; 1668 1669 switch (sc->sc_ic.ic_opmode) { 1670 case IEEE80211_M_STA: 1671 name = "ipw-bss"; 1672 break; 1673#ifndef IEEE80211_STA_ONLY 1674 case IEEE80211_M_IBSS: 1675 name = "ipw-ibss"; 1676 break; 1677#endif 1678 case IEEE80211_M_MONITOR: 1679 name = "ipw-monitor"; 1680 break; 1681 default: 1682 /* should not get there */ 1683 return ENODEV; 1684 } 1685 if ((error = loadfirmware(name, &fw->data, &size)) != 0) 1686 return error; 1687 1688 if (size < sizeof (*hdr)) { 1689 error = EINVAL; 1690 goto fail; 1691 } 1692 hdr = (const struct ipw_firmware_hdr *)fw->data; 1693 fw->main_size = letoh32(hdr->main_size); 1694 fw->ucode_size = letoh32(hdr->ucode_size); 1695 1696 if (size < sizeof (*hdr) + fw->main_size + fw->ucode_size) { 1697 error = EINVAL; 1698 goto fail; 1699 } 1700 fw->main = fw->data + sizeof (*hdr); 1701 fw->ucode = fw->main + fw->main_size; 1702 1703 return 0; 1704 1705fail: free(fw->data, M_DEVBUF); 1706 return error; 1707} 1708 1709void 1710ipw_scan(void *arg1, void *arg2) 1711{ 1712 struct ipw_softc *sc = arg1; 1713 struct ifnet *ifp = &sc->sc_ic.ic_if; 1714 struct ipw_scan_options scan; 1715 uint8_t ssid[IEEE80211_NWID_LEN]; 1716 int error; 1717 1718 /* 1719 * Firmware has a bug and does not honour the ``do not associate 1720 * after scan'' bit in the scan command. To prevent the firmware 1721 * from associating after the scan, we set the ESSID to something 1722 * unlikely to be used by a real AP. 1723 * XXX would setting the desired BSSID to a multicast address work? 1724 */ 1725 memset(ssid, '\r', sizeof ssid); 1726 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ssid, sizeof ssid); 1727 if (error != 0) 1728 goto fail; 1729 1730 /* no mandatory BSSID */ 1731 DPRINTF(("Setting mandatory BSSID to null\n")); 1732 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1733 if (error != 0) 1734 goto fail; 1735 1736 scan.flags = htole32(IPW_SCAN_DO_NOT_ASSOCIATE | IPW_SCAN_MIXED_CELL); 1737 scan.channels = htole32(0x3fff); /* scan channels 1-14 */ 1738 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1739 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1740 if (error != 0) 1741 goto fail; 1742 1743 /* start scanning */ 1744 DPRINTF(("Enabling adapter\n")); 1745 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1746 if (error != 0) 1747 goto fail; 1748 1749 return; 1750fail: 1751 printf("%s: scan request failed (error=%d)\n", sc->sc_dev.dv_xname, 1752 error); 1753 ieee80211_end_scan(ifp); 1754} 1755 1756void 1757ipw_auth_and_assoc(void *arg1, void *arg2) 1758{ 1759 struct ipw_softc *sc = arg1; 1760 struct ieee80211com *ic = &sc->sc_ic; 1761 struct ieee80211_node *ni = ic->ic_bss; 1762 struct ipw_scan_options scan; 1763 struct ipw_security security; 1764 struct ipw_assoc_req assoc; 1765 uint32_t data; 1766 uint8_t chan; 1767 int s, error; 1768 1769 DPRINTF(("Disabling adapter\n")); 1770 error = ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1771 if (error != 0) 1772 goto fail; 1773#if 1 1774 /* wait at most one second for card to be disabled */ 1775 s = splnet(); 1776 error = tsleep(sc, 0, "ipwdis", hz); 1777 splx(s); 1778 if (error != 0) { 1779 printf("%s: timeout waiting for disabled state\n", 1780 sc->sc_dev.dv_xname); 1781 goto fail; 1782 } 1783#else 1784 /* Intel's Linux driver polls for the DISABLED state instead.. */ 1785 for (ntries = 0; ntries < 1000; ntries++) { 1786 if (ipw_read_table1(sc, IPW_INFO_CARD_DISABLED) == 1) 1787 break; 1788 DELAY(10); 1789 } 1790 if (ntries == 1000) { 1791 printf("%s: timeout waiting for disabled state\n", 1792 sc->sc_dev.dv_xname); 1793 goto fail; 1794 } 1795#endif 1796 1797 bzero(&security, sizeof security); 1798 security.authmode = IPW_AUTH_OPEN; 1799 security.ciphers = htole32(IPW_CIPHER_NONE); 1800 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1801 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1802 sizeof security); 1803 if (error != 0) 1804 goto fail; 1805 1806#ifdef IPW_DEBUG 1807 if (ipw_debug > 0) { 1808 printf("Setting ESSID to "); 1809 ieee80211_print_essid(ni->ni_essid, ni->ni_esslen); 1810 printf("\n"); 1811 } 1812#endif 1813 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ni->ni_essid, ni->ni_esslen); 1814 if (error != 0) 1815 goto fail; 1816 1817 DPRINTF(("Setting BSSID to %s\n", ether_sprintf(ni->ni_bssid))); 1818 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, ni->ni_bssid, 1819 IEEE80211_ADDR_LEN); 1820 if (error != 0) 1821 goto fail; 1822 1823 data = htole32((ic->ic_flags & (IEEE80211_F_WEPON | 1824 IEEE80211_F_RSNON)) ? IPW_PRIVACYON : 0); 1825 DPRINTF(("Setting privacy flags to 0x%x\n", letoh32(data))); 1826 error = ipw_cmd(sc, IPW_CMD_SET_PRIVACY_FLAGS, &data, sizeof data); 1827 if (error != 0) 1828 goto fail; 1829 1830 /* let firmware set the capinfo, lintval, and bssid fixed fields */ 1831 bzero(&assoc, sizeof assoc); 1832 if (ic->ic_flags & IEEE80211_F_RSNON) { 1833 uint8_t *frm = assoc.optie; 1834 1835 /* tell firmware to add a WPA or RSN IE in (Re)Assoc req */ 1836 if (ni->ni_rsnprotos & IEEE80211_PROTO_RSN) 1837 frm = ieee80211_add_rsn(frm, ic, ni); 1838 else if (ni->ni_rsnprotos & IEEE80211_PROTO_WPA) 1839 frm = ieee80211_add_wpa(frm, ic, ni); 1840 assoc.optie_len = htole32(frm - assoc.optie); 1841 } 1842 DPRINTF(("Preparing assocation request (optional IE length=%d)\n", 1843 letoh32(assoc.optie_len))); 1844 error = ipw_cmd(sc, IPW_CMD_SET_ASSOC_REQ, &assoc, sizeof assoc); 1845 if (error != 0) 1846 goto fail; 1847 1848 scan.flags = htole32(IPW_SCAN_MIXED_CELL); 1849 chan = ieee80211_chan2ieee(ic, ni->ni_chan); 1850 scan.channels = htole32(1 << (chan - 1)); 1851 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1852 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1853 if (error != 0) 1854 goto fail; 1855 1856 /* trigger scan+association */ 1857 DPRINTF(("Enabling adapter\n")); 1858 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1859 if (error != 0) 1860 goto fail; 1861 1862 return; 1863fail: 1864 printf("%s: association failed (error=%d)\n", sc->sc_dev.dv_xname, 1865 error); 1866 ieee80211_begin_scan(&ic->ic_if); 1867} 1868 1869int 1870ipw_config(struct ipw_softc *sc) 1871{ 1872 struct ieee80211com *ic = &sc->sc_ic; 1873 struct ifnet *ifp = &ic->ic_if; 1874 struct ipw_configuration config; 1875 uint32_t data; 1876 int error; 1877 1878 switch (ic->ic_opmode) { 1879 case IEEE80211_M_STA: 1880 data = htole32(IPW_MODE_BSS); 1881 break; 1882#ifndef IEEE80211_STA_ONLY 1883 case IEEE80211_M_IBSS: 1884 data = htole32(IPW_MODE_IBSS); 1885 break; 1886#endif 1887 case IEEE80211_M_MONITOR: 1888 data = htole32(IPW_MODE_MONITOR); 1889 break; 1890 default: 1891 /* should not get there */ 1892 return ENODEV; 1893 } 1894 DPRINTF(("Setting mode to %u\n", letoh32(data))); 1895 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1896 if (error != 0) 1897 return error; 1898 1899 if ( 1900#ifndef IEEE80211_STA_ONLY 1901 ic->ic_opmode == IEEE80211_M_IBSS || 1902#endif 1903 ic->ic_opmode == IEEE80211_M_MONITOR) { 1904 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1905 DPRINTF(("Setting channel to %u\n", letoh32(data))); 1906 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1907 if (error != 0) 1908 return error; 1909 } 1910 1911 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1912 DPRINTF(("Enabling adapter\n")); 1913 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1914 } 1915 1916 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 1917 DPRINTF(("Setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 1918 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1919 IEEE80211_ADDR_LEN); 1920 if (error != 0) 1921 return error; 1922 1923 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1924 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1X_ENABLE); 1925#ifndef IEEE80211_STA_ONLY 1926 if (ic->ic_opmode == IEEE80211_M_IBSS) 1927 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1928#endif 1929 if (ifp->if_flags & IFF_PROMISC) 1930 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1931 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1932 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1933 DPRINTF(("Setting configuration 0x%x\n", config.flags)); 1934 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1935 if (error != 0) 1936 return error; 1937 1938 data = htole32(ic->ic_rtsthreshold); 1939 DPRINTF(("Setting RTS threshold to %u\n", letoh32(data))); 1940 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1941 if (error != 0) 1942 return error; 1943 1944 data = htole32(ic->ic_fragthreshold); 1945 DPRINTF(("Setting frag threshold to %u\n", letoh32(data))); 1946 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1947 if (error != 0) 1948 return error; 1949 1950 data = htole32(0x3); /* 1, 2 */ 1951 DPRINTF(("Setting basic tx rates to 0x%x\n", letoh32(data))); 1952 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1953 if (error != 0) 1954 return error; 1955 1956 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1957 DPRINTF(("Setting tx rates to 0x%x\n", letoh32(data))); 1958 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1959 if (error != 0) 1960 return error; 1961 1962 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1963 DPRINTF(("Setting MSDU tx rates to 0x%x\n", letoh32(data))); 1964 error = ipw_cmd(sc, IPW_CMD_SET_MSDU_TX_RATES, &data, sizeof data); 1965 if (error != 0) 1966 return error; 1967 1968 data = htole32(IPW_POWER_MODE_CAM); 1969 DPRINTF(("Setting power mode to %u\n", letoh32(data))); 1970 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1971 if (error != 0) 1972 return error; 1973 1974#ifndef IEEE80211_STA_ONLY 1975 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1976 data = htole32(32); /* default value */ 1977 DPRINTF(("Setting tx power index to %u\n", letoh32(data))); 1978 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1979 sizeof data); 1980 if (error != 0) 1981 return error; 1982 1983 data = htole32(ic->ic_lintval); 1984 DPRINTF(("Setting beacon interval to %u\n", letoh32(data))); 1985 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1986 sizeof data); 1987 if (error != 0) 1988 return error; 1989 } 1990#endif 1991 return 0; 1992} 1993 1994int 1995ipw_init(struct ifnet *ifp) 1996{ 1997 struct ipw_softc *sc = ifp->if_softc; 1998 struct ieee80211com *ic = &sc->sc_ic; 1999 struct ipw_firmware fw; 2000 int error; 2001 2002 ipw_stop(ifp, 0); 2003 2004 if ((error = ipw_reset(sc)) != 0) { 2005 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 2006 goto fail1; 2007 } 2008 2009 if ((error = ipw_read_firmware(sc, &fw)) != NULL) { 2010 printf("%s: error %d, could not read firmware\n", 2011 sc->sc_dev.dv_xname, error); 2012 goto fail1; 2013 } 2014 if ((error = ipw_load_ucode(sc, fw.ucode, fw.ucode_size)) != 0) { 2015 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 2016 goto fail2; 2017 } 2018 2019 ipw_stop_master(sc); 2020 2021 /* 2022 * Setup tx, rx and status rings. 2023 */ 2024 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2025 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 2026 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 2027 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 2028 sc->txold = IPW_NTBD - 1; /* latest bd index ack by firmware */ 2029 sc->txcur = 0; /* bd index to write to */ 2030 sc->txfree = IPW_NTBD - 2; 2031 2032 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2033 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 2034 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 2035 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 2036 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 2037 2038 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 2039 sc->status_map->dm_segs[0].ds_addr); 2040 2041 if ((error = ipw_load_firmware(sc, fw.main, fw.main_size)) != 0) { 2042 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 2043 goto fail2; 2044 } 2045 sc->sc_flags |= IPW_FLAG_FW_INITED; 2046 free(fw.data, M_DEVBUF); 2047 2048 /* retrieve information tables base addresses */ 2049 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2050 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2051 2052 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2053 2054 if ((error = ipw_config(sc)) != 0) { 2055 printf("%s: device configuration failed\n", 2056 sc->sc_dev.dv_xname); 2057 goto fail2; 2058 } 2059 2060 ifp->if_flags &= ~IFF_OACTIVE; 2061 ifp->if_flags |= IFF_RUNNING; 2062 2063 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2064 ieee80211_begin_scan(ifp); 2065 else 2066 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2067 2068 return 0; 2069 2070fail2: free(fw.data, M_DEVBUF); 2071fail1: ipw_stop(ifp, 0); 2072 return error; 2073} 2074 2075void 2076ipw_stop(struct ifnet *ifp, int disable) 2077{ 2078 struct ipw_softc *sc = ifp->if_softc; 2079 struct ieee80211com *ic = &sc->sc_ic; 2080 int i; 2081 2082 ipw_stop_master(sc); 2083 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2084 2085 ifp->if_timer = 0; 2086 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2087 2088 /* 2089 * Release tx buffers. 2090 */ 2091 for (i = 0; i < IPW_NTBD; i++) 2092 ipw_release_sbd(sc, &sc->stbd_list[i]); 2093 2094 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2095} 2096 2097void 2098ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2099 bus_size_t count) 2100{ 2101 for (; count > 0; offset++, datap++, count--) { 2102 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2103 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2104 } 2105} 2106 2107void 2108ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2109 bus_size_t count) 2110{ 2111 for (; count > 0; offset++, datap++, count--) { 2112 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2113 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2114 } 2115} 2116 2117struct cfdriver ipw_cd = { 2118 NULL, "ipw", DV_IFNET 2119}; 2120