if_ipw.c revision 1.88
1/* $OpenBSD: if_ipw.c,v 1.88 2010/08/03 18:26:25 kettenis Exp $ */ 2 3/*- 4 * Copyright (c) 2004-2008 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/* 21 * Driver for Intel PRO/Wireless 2100 802.11 network adapters. 22 */ 23 24#include "bpfilter.h" 25 26#include <sys/param.h> 27#include <sys/sockio.h> 28#include <sys/workq.h> 29#include <sys/mbuf.h> 30#include <sys/kernel.h> 31#include <sys/socket.h> 32#include <sys/systm.h> 33#include <sys/conf.h> 34#include <sys/device.h> 35 36#include <machine/bus.h> 37#include <machine/endian.h> 38#include <machine/intr.h> 39 40#include <dev/pci/pcireg.h> 41#include <dev/pci/pcivar.h> 42#include <dev/pci/pcidevs.h> 43 44#if NBPFILTER > 0 45#include <net/bpf.h> 46#endif 47#include <net/if.h> 48#include <net/if_arp.h> 49#include <net/if_dl.h> 50#include <net/if_media.h> 51#include <net/if_types.h> 52 53#include <netinet/in.h> 54#include <netinet/in_systm.h> 55#include <netinet/in_var.h> 56#include <netinet/if_ether.h> 57#include <netinet/ip.h> 58 59#include <net80211/ieee80211_var.h> 60#include <net80211/ieee80211_radiotap.h> 61 62#include <dev/pci/if_ipwreg.h> 63#include <dev/pci/if_ipwvar.h> 64 65int ipw_match(struct device *, void *, void *); 66void ipw_attach(struct device *, struct device *, void *); 67int ipw_activate(struct device *, int); 68void ipw_resume(void *, void *); 69void ipw_power(int, void *); 70int ipw_dma_alloc(struct ipw_softc *); 71void ipw_release(struct ipw_softc *); 72int ipw_media_change(struct ifnet *); 73void ipw_media_status(struct ifnet *, struct ifmediareq *); 74int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 75uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 76void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 77void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 78void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 79 struct ipw_soft_bd *, struct ipw_soft_buf *); 80void ipw_notification_intr(struct ipw_softc *, 81 struct ipw_soft_buf *); 82void ipw_rx_intr(struct ipw_softc *); 83void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 84void ipw_tx_intr(struct ipw_softc *); 85int ipw_intr(void *); 86int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 87int ipw_send_mgmt(struct ieee80211com *, struct ieee80211_node *, 88 int, int, int); 89int ipw_tx_start(struct ifnet *, struct mbuf *, 90 struct ieee80211_node *); 91void ipw_start(struct ifnet *); 92void ipw_watchdog(struct ifnet *); 93int ipw_ioctl(struct ifnet *, u_long, caddr_t); 94uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 95void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 96int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 97 uint32_t *); 98void ipw_stop_master(struct ipw_softc *); 99int ipw_reset(struct ipw_softc *); 100int ipw_load_ucode(struct ipw_softc *, u_char *, int); 101int ipw_load_firmware(struct ipw_softc *, u_char *, int); 102int ipw_read_firmware(struct ipw_softc *, struct ipw_firmware *); 103void ipw_scan(void *, void *); 104void ipw_auth_and_assoc(void *, void *); 105int ipw_config(struct ipw_softc *); 106int ipw_init(struct ifnet *); 107void ipw_stop(struct ifnet *, int); 108void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 109 bus_size_t); 110void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 111 bus_size_t); 112 113static __inline uint8_t 114MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 115{ 116 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 117 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 118} 119 120static __inline uint32_t 121MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 122{ 123 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 124 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 125} 126 127#ifdef IPW_DEBUG 128#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 129#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 130int ipw_debug = 0; 131#else 132#define DPRINTF(x) 133#define DPRINTFN(n, x) 134#endif 135 136struct cfattach ipw_ca = { 137 sizeof (struct ipw_softc), ipw_match, ipw_attach, NULL, 138 ipw_activate 139}; 140 141int 142ipw_match(struct device *parent, void *match, void *aux) 143{ 144 struct pci_attach_args *pa = aux; 145 146 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 147 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 148 return 1; 149 150 return 0; 151} 152 153/* Base Address Register */ 154#define IPW_PCI_BAR0 0x10 155 156void 157ipw_attach(struct device *parent, struct device *self, void *aux) 158{ 159 struct ipw_softc *sc = (struct ipw_softc *)self; 160 struct ieee80211com *ic = &sc->sc_ic; 161 struct ifnet *ifp = &ic->ic_if; 162 struct pci_attach_args *pa = aux; 163 const char *intrstr; 164 bus_space_tag_t memt; 165 bus_space_handle_t memh; 166 bus_addr_t base; 167 pci_intr_handle_t ih; 168 pcireg_t data; 169 uint16_t val; 170 int error, i; 171 172 sc->sc_pct = pa->pa_pc; 173 sc->sc_pcitag = pa->pa_tag, 174 175 /* clear device specific PCI configuration register 0x41 */ 176 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 177 data &= ~0x0000ff00; 178 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 179 180 /* map the register window */ 181 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 182 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 183 if (error != 0) { 184 printf(": can't map mem space\n"); 185 return; 186 } 187 188 sc->sc_st = memt; 189 sc->sc_sh = memh; 190 sc->sc_dmat = pa->pa_dmat; 191 192 /* disable interrupts */ 193 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 194 195 if (pci_intr_map(pa, &ih) != 0) { 196 printf(": can't map interrupt\n"); 197 return; 198 } 199 200 intrstr = pci_intr_string(sc->sc_pct, ih); 201 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 202 sc->sc_dev.dv_xname); 203 if (sc->sc_ih == NULL) { 204 printf(": can't establish interrupt"); 205 if (intrstr != NULL) 206 printf(" at %s", intrstr); 207 printf("\n"); 208 return; 209 } 210 printf(": %s", intrstr); 211 212 if (ipw_reset(sc) != 0) { 213 printf(": could not reset adapter\n"); 214 return; 215 } 216 217 if (ipw_dma_alloc(sc) != 0) { 218 printf(": failed to allocate DMA resources\n"); 219 return; 220 } 221 222 ic->ic_phytype = IEEE80211_T_DS; 223 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 224 ic->ic_state = IEEE80211_S_INIT; 225 226 /* set device capabilities */ 227 ic->ic_caps = 228#ifndef IEEE80211_STA_ONLY 229 IEEE80211_C_IBSS | /* IBSS mode supported */ 230#endif 231 IEEE80211_C_MONITOR | /* monitor mode supported */ 232 IEEE80211_C_TXPMGT | /* tx power management */ 233 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 234 IEEE80211_C_WEP | /* s/w WEP */ 235 IEEE80211_C_RSN | /* WPA/RSN */ 236 IEEE80211_C_SCANALL; /* h/w scanning */ 237 238 /* read MAC address from EEPROM */ 239 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 240 ic->ic_myaddr[0] = val >> 8; 241 ic->ic_myaddr[1] = val & 0xff; 242 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 243 ic->ic_myaddr[2] = val >> 8; 244 ic->ic_myaddr[3] = val & 0xff; 245 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 246 ic->ic_myaddr[4] = val >> 8; 247 ic->ic_myaddr[5] = val & 0xff; 248 249 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 250 251 /* set supported .11b rates */ 252 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 253 254 /* set supported .11b channels (1 through 14) */ 255 for (i = 1; i <= 14; i++) { 256 ic->ic_channels[i].ic_freq = 257 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 258 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 259 } 260 261 /* IBSS channel undefined for now */ 262 ic->ic_ibss_chan = &ic->ic_channels[0]; 263 264 ifp->if_softc = sc; 265 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 266 ifp->if_init = ipw_init; 267 ifp->if_ioctl = ipw_ioctl; 268 ifp->if_start = ipw_start; 269 ifp->if_watchdog = ipw_watchdog; 270 IFQ_SET_READY(&ifp->if_snd); 271 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 272 273 if_attach(ifp); 274 ieee80211_ifattach(ifp); 275 /* override state transition machine */ 276 sc->sc_newstate = ic->ic_newstate; 277 ic->ic_newstate = ipw_newstate; 278 ic->ic_send_mgmt = ipw_send_mgmt; 279 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 280 281 sc->powerhook = powerhook_establish(ipw_power, sc); 282 283#if NBPFILTER > 0 284 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 285 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 286 287 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 288 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 289 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 290 291 sc->sc_txtap_len = sizeof sc->sc_txtapu; 292 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 293 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 294#endif 295} 296 297int 298ipw_activate(struct device *self, int act) 299{ 300 struct ipw_softc *sc = (struct ipw_softc *)self; 301 struct ifnet *ifp = &sc->sc_ic.ic_if; 302 303 switch (act) { 304 case DVACT_SUSPEND: 305 if (ifp->if_flags & IFF_RUNNING) 306 ipw_stop(ifp, 0); 307 break; 308 case DVACT_RESUME: 309 workq_queue_task(NULL, &sc->sc_resume_wqt, 0, 310 ipw_resume, sc, NULL); 311 break; 312 } 313 314 return (0); 315} 316 317void 318ipw_resume(void *arg1, void *arg2) 319{ 320 ipw_power(PWR_RESUME, arg1); 321} 322 323void 324ipw_power(int why, void *arg) 325{ 326 struct ipw_softc *sc = arg; 327 struct ifnet *ifp = &sc->sc_ic.ic_if; 328 pcireg_t data; 329 int s; 330 331 if (why != PWR_RESUME) { 332 ipw_stop(ifp, 0); 333 return; 334 } 335 336 /* clear device specific PCI configuration register 0x41 */ 337 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 338 data &= ~0x0000ff00; 339 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 340 341 s = splnet(); 342 sc->sc_flags |= IPW_FLAG_BUSY; 343 344 if (ifp->if_flags & IFF_UP) 345 ipw_init(ifp); 346 347 sc->sc_flags &= ~IPW_FLAG_BUSY; 348 splx(s); 349} 350 351int 352ipw_dma_alloc(struct ipw_softc *sc) 353{ 354 struct ipw_soft_bd *sbd; 355 struct ipw_soft_hdr *shdr; 356 struct ipw_soft_buf *sbuf; 357 int i, nsegs, error; 358 359 /* 360 * Allocate and map tx ring. 361 */ 362 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 363 BUS_DMA_NOWAIT, &sc->tbd_map); 364 if (error != 0) { 365 printf("%s: could not create tx ring DMA map\n", 366 sc->sc_dev.dv_xname); 367 goto fail; 368 } 369 370 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 371 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 372 if (error != 0) { 373 printf("%s: could not allocate tx ring DMA memory\n", 374 sc->sc_dev.dv_xname); 375 goto fail; 376 } 377 378 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 379 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 380 if (error != 0) { 381 printf("%s: can't map tx ring DMA memory\n", 382 sc->sc_dev.dv_xname); 383 goto fail; 384 } 385 386 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 387 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 388 if (error != 0) { 389 printf("%s: could not load tx ring DMA map\n", 390 sc->sc_dev.dv_xname); 391 goto fail; 392 } 393 394 /* 395 * Allocate and map rx ring. 396 */ 397 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 398 BUS_DMA_NOWAIT, &sc->rbd_map); 399 if (error != 0) { 400 printf("%s: could not create rx ring DMA map\n", 401 sc->sc_dev.dv_xname); 402 goto fail; 403 } 404 405 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 406 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 407 if (error != 0) { 408 printf("%s: could not allocate rx ring DMA memory\n", 409 sc->sc_dev.dv_xname); 410 goto fail; 411 } 412 413 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 414 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 415 if (error != 0) { 416 printf("%s: can't map rx ring DMA memory\n", 417 sc->sc_dev.dv_xname); 418 goto fail; 419 } 420 421 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 422 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 423 if (error != 0) { 424 printf("%s: could not load tx ring DMA map\n", 425 sc->sc_dev.dv_xname); 426 goto fail; 427 } 428 429 /* 430 * Allocate and map status ring. 431 */ 432 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 433 0, BUS_DMA_NOWAIT, &sc->status_map); 434 if (error != 0) { 435 printf("%s: could not create status ring DMA map\n", 436 sc->sc_dev.dv_xname); 437 goto fail; 438 } 439 440 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 441 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 442 if (error != 0) { 443 printf("%s: could not allocate status ring DMA memory\n", 444 sc->sc_dev.dv_xname); 445 goto fail; 446 } 447 448 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 449 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 450 if (error != 0) { 451 printf("%s: can't map status ring DMA memory\n", 452 sc->sc_dev.dv_xname); 453 goto fail; 454 } 455 456 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 457 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 458 if (error != 0) { 459 printf("%s: could not load status ring DMA map\n", 460 sc->sc_dev.dv_xname); 461 goto fail; 462 } 463 464 /* 465 * Allocate command DMA map. 466 */ 467 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 468 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 469 if (error != 0) { 470 printf("%s: could not create command DMA map\n", 471 sc->sc_dev.dv_xname); 472 goto fail; 473 } 474 475 /* 476 * Allocate headers DMA maps. 477 */ 478 SLIST_INIT(&sc->free_shdr); 479 for (i = 0; i < IPW_NDATA; i++) { 480 shdr = &sc->shdr_list[i]; 481 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_hdr), 482 1, sizeof (struct ipw_hdr), 0, BUS_DMA_NOWAIT, &shdr->map); 483 if (error != 0) { 484 printf("%s: could not create header DMA map\n", 485 sc->sc_dev.dv_xname); 486 goto fail; 487 } 488 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 489 } 490 491 /* 492 * Allocate tx buffers DMA maps. 493 */ 494 SLIST_INIT(&sc->free_sbuf); 495 for (i = 0; i < IPW_NDATA; i++) { 496 sbuf = &sc->tx_sbuf_list[i]; 497 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, IPW_MAX_NSEG, 498 MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 499 if (error != 0) { 500 printf("%s: could not create tx DMA map\n", 501 sc->sc_dev.dv_xname); 502 goto fail; 503 } 504 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 505 } 506 507 /* 508 * Initialize tx ring. 509 */ 510 for (i = 0; i < IPW_NTBD; i++) { 511 sbd = &sc->stbd_list[i]; 512 sbd->bd = &sc->tbd_list[i]; 513 sbd->type = IPW_SBD_TYPE_NOASSOC; 514 } 515 516 /* 517 * Pre-allocate rx buffers and DMA maps. 518 */ 519 for (i = 0; i < IPW_NRBD; i++) { 520 sbd = &sc->srbd_list[i]; 521 sbuf = &sc->rx_sbuf_list[i]; 522 sbd->bd = &sc->rbd_list[i]; 523 524 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 525 if (sbuf->m == NULL) { 526 printf("%s: could not allocate rx mbuf\n", 527 sc->sc_dev.dv_xname); 528 error = ENOMEM; 529 goto fail; 530 } 531 MCLGET(sbuf->m, M_DONTWAIT); 532 if (!(sbuf->m->m_flags & M_EXT)) { 533 m_freem(sbuf->m); 534 printf("%s: could not allocate rx mbuf cluster\n", 535 sc->sc_dev.dv_xname); 536 error = ENOMEM; 537 goto fail; 538 } 539 540 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 541 0, BUS_DMA_NOWAIT, &sbuf->map); 542 if (error != 0) { 543 printf("%s: could not create rx DMA map\n", 544 sc->sc_dev.dv_xname); 545 goto fail; 546 } 547 548 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 549 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 550 if (error != 0) { 551 printf("%s: can't map rx DMA memory\n", 552 sc->sc_dev.dv_xname); 553 goto fail; 554 } 555 556 sbd->type = IPW_SBD_TYPE_DATA; 557 sbd->priv = sbuf; 558 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 559 sbd->bd->len = htole32(MCLBYTES); 560 } 561 562 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 563 BUS_DMASYNC_PREWRITE); 564 565 return 0; 566 567fail: ipw_release(sc); 568 return error; 569} 570 571void 572ipw_release(struct ipw_softc *sc) 573{ 574 struct ipw_soft_buf *sbuf; 575 int i; 576 577 if (sc->tbd_map != NULL) { 578 if (sc->tbd_list != NULL) { 579 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 580 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 581 IPW_TBD_SZ); 582 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 583 } 584 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 585 } 586 587 if (sc->rbd_map != NULL) { 588 if (sc->rbd_list != NULL) { 589 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 590 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 591 IPW_RBD_SZ); 592 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 593 } 594 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 595 } 596 597 if (sc->status_map != NULL) { 598 if (sc->status_list != NULL) { 599 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 600 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 601 IPW_RBD_SZ); 602 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 603 } 604 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 605 } 606 607 if (sc->cmd_map != NULL) 608 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 609 610 for (i = 0; i < IPW_NDATA; i++) 611 bus_dmamap_destroy(sc->sc_dmat, sc->shdr_list[i].map); 612 613 for (i = 0; i < IPW_NDATA; i++) 614 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 615 616 for (i = 0; i < IPW_NRBD; i++) { 617 sbuf = &sc->rx_sbuf_list[i]; 618 if (sbuf->map != NULL) { 619 if (sbuf->m != NULL) { 620 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 621 m_freem(sbuf->m); 622 } 623 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 624 } 625 } 626} 627 628int 629ipw_media_change(struct ifnet *ifp) 630{ 631 int error; 632 633 error = ieee80211_media_change(ifp); 634 if (error != ENETRESET) 635 return error; 636 637 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 638 ipw_init(ifp); 639 640 return 0; 641} 642 643void 644ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 645{ 646 struct ipw_softc *sc = ifp->if_softc; 647 struct ieee80211com *ic = &sc->sc_ic; 648 static const struct { 649 uint32_t val; 650 int rate; 651 } rates[] = { 652 { IPW_RATE_DS1, 2 }, 653 { IPW_RATE_DS2, 4 }, 654 { IPW_RATE_DS5, 11 }, 655 { IPW_RATE_DS11, 22 }, 656 }; 657 uint32_t val; 658 int rate, i; 659 660 imr->ifm_status = IFM_AVALID; 661 imr->ifm_active = IFM_IEEE80211; 662 if (ic->ic_state == IEEE80211_S_RUN) 663 imr->ifm_status |= IFM_ACTIVE; 664 665 /* read current transmission rate from adapter */ 666 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 667 val &= 0xf; 668 669 /* convert rate to 802.11 rate */ 670 for (i = 0; i < nitems(rates) && rates[i].val != val; i++); 671 rate = (i < nitems(rates)) ? rates[i].rate : 0; 672 673 imr->ifm_active |= IFM_IEEE80211_11B; 674 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 675 switch (ic->ic_opmode) { 676 case IEEE80211_M_STA: 677 break; 678#ifndef IEEE80211_STA_ONLY 679 case IEEE80211_M_IBSS: 680 imr->ifm_active |= IFM_IEEE80211_IBSS; 681 break; 682#endif 683 case IEEE80211_M_MONITOR: 684 imr->ifm_active |= IFM_IEEE80211_MONITOR; 685 break; 686 default: 687 /* should not get there */ 688 break; 689 } 690} 691 692int 693ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 694{ 695 struct ipw_softc *sc = ic->ic_softc; 696 int error; 697 698 switch (nstate) { 699 case IEEE80211_S_SCAN: 700 error = workq_add_task(NULL, 0, ipw_scan, sc, NULL); 701 if (error != 0) 702 return error; 703 break; 704 705 case IEEE80211_S_AUTH: 706 error = workq_add_task(NULL, 0, ipw_auth_and_assoc, sc, NULL); 707 if (error != 0) 708 return error; 709 break; 710 711 case IEEE80211_S_RUN: 712 case IEEE80211_S_INIT: 713 case IEEE80211_S_ASSOC: 714 /* nothing to do */ 715 break; 716 } 717 718 ic->ic_state = nstate; 719 return 0; 720} 721 722/* 723 * Read 16 bits at address 'addr' from the Microwire EEPROM. 724 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 725 */ 726uint16_t 727ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 728{ 729 uint32_t tmp; 730 uint16_t val; 731 int n; 732 733 /* clock C once before the first command */ 734 IPW_EEPROM_CTL(sc, 0); 735 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 736 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 737 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 738 739 /* write start bit (1) */ 740 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 741 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 742 743 /* write READ opcode (10) */ 744 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 745 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 746 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 747 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 748 749 /* write address A7-A0 */ 750 for (n = 7; n >= 0; n--) { 751 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 752 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 753 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 754 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 755 } 756 757 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 758 759 /* read data Q15-Q0 */ 760 val = 0; 761 for (n = 15; n >= 0; n--) { 762 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 763 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 764 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 765 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 766 } 767 768 IPW_EEPROM_CTL(sc, 0); 769 770 /* clear Chip Select and clock C */ 771 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 772 IPW_EEPROM_CTL(sc, 0); 773 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 774 775 return val; 776} 777 778void 779ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 780{ 781 struct ipw_cmd *cmd; 782 783 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 784 BUS_DMASYNC_POSTREAD); 785 786 cmd = mtod(sbuf->m, struct ipw_cmd *); 787 788 DPRINTFN(2, ("received command ack type=%u,status=%u\n", 789 letoh32(cmd->type), letoh32(cmd->status))); 790 791 wakeup(&sc->cmd); 792} 793 794void 795ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 796{ 797 struct ieee80211com *ic = &sc->sc_ic; 798 struct ifnet *ifp = &ic->ic_if; 799 uint32_t state; 800 801 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 802 BUS_DMASYNC_POSTREAD); 803 804 state = letoh32(*mtod(sbuf->m, uint32_t *)); 805 806 DPRINTFN(2, ("firmware state changed to 0x%x\n", state)); 807 808 switch (state) { 809 case IPW_STATE_ASSOCIATED: 810 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 811 break; 812 813 case IPW_STATE_SCANNING: 814 if (ic->ic_state == IEEE80211_S_RUN) 815 ieee80211_begin_scan(ifp); 816 break; 817 818 case IPW_STATE_SCAN_COMPLETE: 819 if (ic->ic_state == IEEE80211_S_SCAN) 820 ieee80211_end_scan(ifp); 821 break; 822 823 case IPW_STATE_ASSOCIATION_LOST: 824 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 825 break; 826 827 case IPW_STATE_DISABLED: 828 wakeup(sc); 829 break; 830 831 case IPW_STATE_RADIO_DISABLED: 832 ifp->if_flags &= ~IFF_UP; 833 ipw_stop(&ic->ic_if, 1); 834 break; 835 } 836} 837 838void 839ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 840 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 841{ 842 struct ieee80211com *ic = &sc->sc_ic; 843 struct ifnet *ifp = &ic->ic_if; 844 struct mbuf *mnew, *m; 845 struct ieee80211_frame *wh; 846 struct ieee80211_rxinfo rxi; 847 struct ieee80211_node *ni; 848 int error; 849 850 DPRINTFN(5, ("received data frame len=%u,rssi=%u\n", 851 letoh32(status->len), status->rssi)); 852 853 /* 854 * Try to allocate a new mbuf for this ring element and load it before 855 * processing the current mbuf. If the ring element cannot be loaded, 856 * drop the received packet and reuse the old mbuf. In the unlikely 857 * case that the old mbuf can't be reloaded either, explicitly panic. 858 */ 859 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 860 if (mnew == NULL) { 861 ifp->if_ierrors++; 862 return; 863 } 864 MCLGET(mnew, M_DONTWAIT); 865 if (!(mnew->m_flags & M_EXT)) { 866 m_freem(mnew); 867 ifp->if_ierrors++; 868 return; 869 } 870 871 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 872 BUS_DMASYNC_POSTREAD); 873 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 874 875 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(mnew, void *), 876 MCLBYTES, NULL, BUS_DMA_NOWAIT); 877 if (error != 0) { 878 m_freem(mnew); 879 880 /* try to reload the old mbuf */ 881 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 882 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 883 if (error != 0) { 884 /* very unlikely that it will fail... */ 885 panic("%s: could not load old rx mbuf", 886 sc->sc_dev.dv_xname); 887 } 888 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 889 ifp->if_ierrors++; 890 return; 891 } 892 893 m = sbuf->m; 894 sbuf->m = mnew; 895 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 896 897 /* finalize mbuf */ 898 m->m_pkthdr.rcvif = ifp; 899 m->m_pkthdr.len = m->m_len = letoh32(status->len); 900 901#if NBPFILTER > 0 902 if (sc->sc_drvbpf != NULL) { 903 struct mbuf mb; 904 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 905 906 tap->wr_flags = 0; 907 tap->wr_antsignal = status->rssi; 908 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 909 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 910 911 mb.m_data = (caddr_t)tap; 912 mb.m_len = sc->sc_rxtap_len; 913 mb.m_next = m; 914 mb.m_nextpkt = NULL; 915 mb.m_type = 0; 916 mb.m_flags = 0; 917 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 918 } 919#endif 920 921 wh = mtod(m, struct ieee80211_frame *); 922 ni = ieee80211_find_rxnode(ic, wh); 923 924 /* send the frame to the upper layer */ 925 rxi.rxi_flags = 0; 926 rxi.rxi_rssi = status->rssi; 927 rxi.rxi_tstamp = 0; /* unused */ 928 ieee80211_input(ifp, m, ni, &rxi); 929 930 ieee80211_release_node(ic, ni); 931} 932 933void 934ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 935{ 936 DPRINTFN(2, ("received notification\n")); 937} 938 939void 940ipw_rx_intr(struct ipw_softc *sc) 941{ 942 struct ipw_status *status; 943 struct ipw_soft_bd *sbd; 944 struct ipw_soft_buf *sbuf; 945 uint32_t r, i; 946 947 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 948 949 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 950 951 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 952 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 953 BUS_DMASYNC_POSTREAD); 954 955 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 956 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 957 BUS_DMASYNC_POSTREAD); 958 959 status = &sc->status_list[i]; 960 sbd = &sc->srbd_list[i]; 961 sbuf = sbd->priv; 962 963 switch (letoh16(status->code) & 0xf) { 964 case IPW_STATUS_CODE_COMMAND: 965 ipw_command_intr(sc, sbuf); 966 break; 967 968 case IPW_STATUS_CODE_NEWSTATE: 969 ipw_newstate_intr(sc, sbuf); 970 break; 971 972 case IPW_STATUS_CODE_DATA_802_3: 973 case IPW_STATUS_CODE_DATA_802_11: 974 ipw_data_intr(sc, status, sbd, sbuf); 975 break; 976 977 case IPW_STATUS_CODE_NOTIFICATION: 978 ipw_notification_intr(sc, sbuf); 979 break; 980 981 default: 982 printf("%s: unknown status code %u\n", 983 sc->sc_dev.dv_xname, letoh16(status->code)); 984 } 985 sbd->bd->flags = 0; 986 987 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 988 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 989 BUS_DMASYNC_PREWRITE); 990 } 991 992 /* tell the firmware what we have processed */ 993 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 994 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 995} 996 997void 998ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 999{ 1000 struct ieee80211com *ic = &sc->sc_ic; 1001 struct ipw_soft_hdr *shdr; 1002 struct ipw_soft_buf *sbuf; 1003 1004 switch (sbd->type) { 1005 case IPW_SBD_TYPE_COMMAND: 1006 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 1007 break; 1008 1009 case IPW_SBD_TYPE_HEADER: 1010 shdr = sbd->priv; 1011 bus_dmamap_unload(sc->sc_dmat, shdr->map); 1012 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 1013 break; 1014 1015 case IPW_SBD_TYPE_DATA: 1016 sbuf = sbd->priv; 1017 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1018 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1019 1020 m_freem(sbuf->m); 1021 1022 if (sbuf->ni != NULL) 1023 ieee80211_release_node(ic, sbuf->ni); 1024 1025 /* kill watchdog timer */ 1026 sc->sc_tx_timer = 0; 1027 break; 1028 } 1029 sbd->type = IPW_SBD_TYPE_NOASSOC; 1030} 1031 1032void 1033ipw_tx_intr(struct ipw_softc *sc) 1034{ 1035 struct ifnet *ifp = &sc->sc_ic.ic_if; 1036 struct ipw_soft_bd *sbd; 1037 uint32_t r, i; 1038 1039 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 1040 1041 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1042 sbd = &sc->stbd_list[i]; 1043 1044 if (sbd->type == IPW_SBD_TYPE_DATA) 1045 ifp->if_opackets++; 1046 1047 ipw_release_sbd(sc, sbd); 1048 sc->txfree++; 1049 } 1050 1051 /* remember what the firmware has processed */ 1052 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1053 1054 /* call start() since some buffer descriptors have been released */ 1055 ifp->if_flags &= ~IFF_OACTIVE; 1056 (*ifp->if_start)(ifp); 1057} 1058 1059int 1060ipw_intr(void *arg) 1061{ 1062 struct ipw_softc *sc = arg; 1063 struct ifnet *ifp = &sc->sc_ic.ic_if; 1064 uint32_t r; 1065 1066 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) 1067 return 0; 1068 1069 /* disable interrupts */ 1070 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1071 1072 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1073 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 1074 ifp->if_flags &= ~IFF_UP; 1075 ipw_stop(ifp, 1); 1076 return 1; 1077 } 1078 1079 if (r & IPW_INTR_FW_INIT_DONE) 1080 wakeup(sc); 1081 1082 if (r & IPW_INTR_RX_TRANSFER) 1083 ipw_rx_intr(sc); 1084 1085 if (r & IPW_INTR_TX_TRANSFER) 1086 ipw_tx_intr(sc); 1087 1088 /* acknowledge interrupts */ 1089 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1090 1091 /* re-enable interrupts */ 1092 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1093 1094 return 1; 1095} 1096 1097int 1098ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1099{ 1100 struct ipw_soft_bd *sbd; 1101 int s, error; 1102 1103 s = splnet(); 1104 1105 sc->cmd.type = htole32(type); 1106 sc->cmd.subtype = htole32(0); 1107 sc->cmd.len = htole32(len); 1108 sc->cmd.seq = htole32(0); 1109 if (data != NULL) 1110 bcopy(data, sc->cmd.data, len); 1111 1112 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 1113 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 1114 if (error != 0) { 1115 printf("%s: can't map command DMA memory\n", 1116 sc->sc_dev.dv_xname); 1117 splx(s); 1118 return error; 1119 } 1120 1121 sbd = &sc->stbd_list[sc->txcur]; 1122 sbd->type = IPW_SBD_TYPE_COMMAND; 1123 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1124 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1125 sbd->bd->nfrag = 1; 1126 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1127 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1128 1129 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1130 BUS_DMASYNC_PREWRITE); 1131 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1132 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1133 BUS_DMASYNC_PREWRITE); 1134 1135 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1136 sc->txfree--; 1137 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1138 1139 DPRINTFN(2, ("sending command type=%u,len=%u\n", type, len)); 1140 1141 /* wait at most one second for command to complete */ 1142 error = tsleep(&sc->cmd, 0, "ipwcmd", hz); 1143 splx(s); 1144 1145 return error; 1146} 1147 1148/* ARGSUSED */ 1149int 1150ipw_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type, 1151 int arg1, int arg2) 1152{ 1153 return EOPNOTSUPP; 1154} 1155 1156int 1157ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 1158{ 1159 struct ipw_softc *sc = ifp->if_softc; 1160 struct ieee80211com *ic = &sc->sc_ic; 1161 struct ieee80211_frame *wh; 1162 struct ieee80211_key *k; 1163 struct mbuf *m1; 1164 struct ipw_soft_bd *sbd; 1165 struct ipw_soft_hdr *shdr; 1166 struct ipw_soft_buf *sbuf; 1167 int error, i; 1168 1169 wh = mtod(m, struct ieee80211_frame *); 1170 1171 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1172 k = ieee80211_get_txkey(ic, wh, ni); 1173 1174 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1175 return ENOBUFS; 1176 1177 /* packet header may have moved, reset our local pointer */ 1178 wh = mtod(m, struct ieee80211_frame *); 1179 } 1180 1181#if NBPFILTER > 0 1182 if (sc->sc_drvbpf != NULL) { 1183 struct mbuf mb; 1184 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1185 1186 tap->wt_flags = 0; 1187 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1188 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1189 1190 mb.m_data = (caddr_t)tap; 1191 mb.m_len = sc->sc_txtap_len; 1192 mb.m_next = m; 1193 mb.m_nextpkt = NULL; 1194 mb.m_type = 0; 1195 mb.m_flags = 0; 1196 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1197 } 1198#endif 1199 1200 shdr = SLIST_FIRST(&sc->free_shdr); 1201 sbuf = SLIST_FIRST(&sc->free_sbuf); 1202 1203 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1204 shdr->hdr.subtype = htole32(0); 1205 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) ? 1 : 0; 1206 shdr->hdr.encrypt = 0; 1207 shdr->hdr.keyidx = 0; 1208 shdr->hdr.keysz = 0; 1209 shdr->hdr.fragmentsz = htole16(0); 1210 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1211 if (ic->ic_opmode == IEEE80211_M_STA) 1212 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1213 else 1214 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1215 1216 /* trim IEEE802.11 header */ 1217 m_adj(m, sizeof (struct ieee80211_frame)); 1218 1219 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 1220 if (error != 0 && error != EFBIG) { 1221 printf("%s: can't map mbuf (error %d)\n", 1222 sc->sc_dev.dv_xname, error); 1223 m_freem(m); 1224 return error; 1225 } 1226 if (error != 0) { 1227 /* too many fragments, linearize */ 1228 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1229 if (m1 == NULL) { 1230 m_freem(m); 1231 return ENOBUFS; 1232 } 1233 if (m->m_pkthdr.len > MHLEN) { 1234 MCLGET(m1, M_DONTWAIT); 1235 if (!(m1->m_flags & M_EXT)) { 1236 m_freem(m); 1237 m_freem(m1); 1238 return ENOBUFS; 1239 } 1240 } 1241 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, caddr_t)); 1242 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 1243 m_freem(m); 1244 m = m1; 1245 1246 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, 1247 BUS_DMA_NOWAIT); 1248 if (error != 0) { 1249 printf("%s: can't map mbuf (error %d)\n", 1250 sc->sc_dev.dv_xname, error); 1251 m_freem(m); 1252 return error; 1253 } 1254 } 1255 1256 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 1257 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 1258 if (error != 0) { 1259 printf("%s: can't map header DMA memory (error %d)\n", 1260 sc->sc_dev.dv_xname, error); 1261 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1262 m_freem(m); 1263 return error; 1264 } 1265 1266 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1267 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1268 1269 sbd = &sc->stbd_list[sc->txcur]; 1270 sbd->type = IPW_SBD_TYPE_HEADER; 1271 sbd->priv = shdr; 1272 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 1273 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1274 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1275 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1276 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1277 1278 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1279 sc->txcur * sizeof (struct ipw_bd), 1280 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1281 1282 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1283 sc->txfree--; 1284 1285 sbuf->m = m; 1286 sbuf->ni = ni; 1287 1288 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1289 sbd = &sc->stbd_list[sc->txcur]; 1290 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1291 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1292 sbd->bd->nfrag = 0; /* used only in first bd */ 1293 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1294 if (i == sbuf->map->dm_nsegs - 1) { 1295 sbd->type = IPW_SBD_TYPE_DATA; 1296 sbd->priv = sbuf; 1297 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1298 } else { 1299 sbd->type = IPW_SBD_TYPE_NOASSOC; 1300 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1301 } 1302 1303 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1304 sc->txcur * sizeof (struct ipw_bd), 1305 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1306 1307 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1308 sc->txfree--; 1309 } 1310 1311 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1312 BUS_DMASYNC_PREWRITE); 1313 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 1314 BUS_DMASYNC_PREWRITE); 1315 1316 /* inform firmware about this new packet */ 1317 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1318 1319 return 0; 1320} 1321 1322void 1323ipw_start(struct ifnet *ifp) 1324{ 1325 struct ipw_softc *sc = ifp->if_softc; 1326 struct ieee80211com *ic = &sc->sc_ic; 1327 struct ieee80211_node *ni; 1328 struct mbuf *m; 1329 1330 if (ic->ic_state != IEEE80211_S_RUN) 1331 return; 1332 1333 for (;;) { 1334 IFQ_POLL(&ifp->if_snd, m); 1335 if (m == NULL) 1336 break; 1337 1338 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1339 ifp->if_flags |= IFF_OACTIVE; 1340 break; 1341 } 1342 IFQ_DEQUEUE(&ifp->if_snd, m); 1343#if NBPFILTER > 0 1344 if (ifp->if_bpf != NULL) 1345 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1346#endif 1347 m = ieee80211_encap(ifp, m, &ni); 1348 if (m == NULL) 1349 continue; 1350#if NBPFILTER > 0 1351 if (ic->ic_rawbpf != NULL) 1352 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1353#endif 1354 if (ipw_tx_start(ifp, m, ni) != 0) { 1355 if (ni != NULL) 1356 ieee80211_release_node(ic, ni); 1357 ifp->if_oerrors++; 1358 break; 1359 } 1360 1361 /* start watchdog timer */ 1362 sc->sc_tx_timer = 5; 1363 ifp->if_timer = 1; 1364 } 1365} 1366 1367void 1368ipw_watchdog(struct ifnet *ifp) 1369{ 1370 struct ipw_softc *sc = ifp->if_softc; 1371 1372 ifp->if_timer = 0; 1373 1374 if (sc->sc_tx_timer > 0) { 1375 if (--sc->sc_tx_timer == 0) { 1376 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1377 ifp->if_flags &= ~IFF_UP; 1378 ipw_stop(ifp, 1); 1379 ifp->if_oerrors++; 1380 return; 1381 } 1382 ifp->if_timer = 1; 1383 } 1384 1385 ieee80211_watchdog(ifp); 1386} 1387 1388int 1389ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1390{ 1391 struct ipw_softc *sc = ifp->if_softc; 1392 struct ieee80211com *ic = &sc->sc_ic; 1393 struct ifaddr *ifa; 1394 struct ifreq *ifr; 1395 int s, error = 0; 1396 1397 s = splnet(); 1398 /* 1399 * Prevent processes from entering this function while another 1400 * process is tsleep'ing in it. 1401 */ 1402 if (sc->sc_flags & IPW_FLAG_BUSY) { 1403 splx(s); 1404 return EBUSY; 1405 } 1406 sc->sc_flags |= IPW_FLAG_BUSY; 1407 1408 switch (cmd) { 1409 case SIOCSIFADDR: 1410 ifa = (struct ifaddr *)data; 1411 ifp->if_flags |= IFF_UP; 1412#ifdef INET 1413 if (ifa->ifa_addr->sa_family == AF_INET) 1414 arp_ifinit(&ic->ic_ac, ifa); 1415#endif 1416 /* FALLTHROUGH */ 1417 case SIOCSIFFLAGS: 1418 if (ifp->if_flags & IFF_UP) { 1419 if (!(ifp->if_flags & IFF_RUNNING)) 1420 ipw_init(ifp); 1421 } else { 1422 if (ifp->if_flags & IFF_RUNNING) 1423 ipw_stop(ifp, 1); 1424 } 1425 break; 1426 1427 case SIOCADDMULTI: 1428 case SIOCDELMULTI: 1429 ifr = (struct ifreq *)data; 1430 error = (cmd == SIOCADDMULTI) ? 1431 ether_addmulti(ifr, &ic->ic_ac) : 1432 ether_delmulti(ifr, &ic->ic_ac); 1433 1434 if (error == ENETRESET) 1435 error = 0; 1436 break; 1437 1438 case SIOCG80211TXPOWER: 1439 /* 1440 * If the hardware radio transmitter switch is off, report a 1441 * tx power of IEEE80211_TXPOWER_MIN to indicate that radio 1442 * transmitter is killed. 1443 */ 1444 ((struct ieee80211_txpower *)data)->i_val = 1445 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 1446 IEEE80211_TXPOWER_MIN : sc->sc_ic.ic_txpower; 1447 break; 1448 1449 default: 1450 error = ieee80211_ioctl(ifp, cmd, data); 1451 } 1452 1453 if (error == ENETRESET) { 1454 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1455 (IFF_UP | IFF_RUNNING)) 1456 ipw_init(ifp); 1457 error = 0; 1458 } 1459 1460 sc->sc_flags &= ~IPW_FLAG_BUSY; 1461 splx(s); 1462 return error; 1463} 1464 1465uint32_t 1466ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1467{ 1468 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1469} 1470 1471void 1472ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1473{ 1474 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1475} 1476 1477int 1478ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1479{ 1480 uint32_t addr, info; 1481 uint16_t count, size; 1482 uint32_t total; 1483 1484 /* addr[4] + count[2] + size[2] */ 1485 addr = MEM_READ_4(sc, sc->table2_base + off); 1486 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1487 1488 count = info >> 16; 1489 size = info & 0xffff; 1490 total = count * size; 1491 1492 if (total > *len) { 1493 *len = total; 1494 return EINVAL; 1495 } 1496 *len = total; 1497 ipw_read_mem_1(sc, addr, buf, total); 1498 1499 return 0; 1500} 1501 1502void 1503ipw_stop_master(struct ipw_softc *sc) 1504{ 1505 uint32_t tmp; 1506 int ntries; 1507 1508 /* disable interrupts */ 1509 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1510 1511 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1512 for (ntries = 0; ntries < 50; ntries++) { 1513 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1514 break; 1515 DELAY(10); 1516 } 1517 if (ntries == 50) 1518 printf("%s: timeout waiting for master\n", 1519 sc->sc_dev.dv_xname); 1520 1521 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1522 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1523 1524 sc->sc_flags &= ~IPW_FLAG_FW_INITED; 1525} 1526 1527int 1528ipw_reset(struct ipw_softc *sc) 1529{ 1530 uint32_t tmp; 1531 int ntries; 1532 1533 ipw_stop_master(sc); 1534 1535 /* move adapter to D0 state */ 1536 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1537 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1538 1539 /* wait for clock stabilization */ 1540 for (ntries = 0; ntries < 1000; ntries++) { 1541 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1542 break; 1543 DELAY(200); 1544 } 1545 if (ntries == 1000) 1546 return EIO; 1547 1548 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1549 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1550 1551 DELAY(10); 1552 1553 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1554 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1555 1556 return 0; 1557} 1558 1559int 1560ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1561{ 1562 int ntries; 1563 1564 /* voodoo from the Intel Linux driver */ 1565 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1566 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1567 1568 MEM_WRITE_2(sc, 0x220000, 0x0703); 1569 MEM_WRITE_2(sc, 0x220000, 0x0707); 1570 1571 MEM_WRITE_1(sc, 0x210014, 0x72); 1572 MEM_WRITE_1(sc, 0x210014, 0x72); 1573 1574 MEM_WRITE_1(sc, 0x210000, 0x40); 1575 MEM_WRITE_1(sc, 0x210000, 0x00); 1576 MEM_WRITE_1(sc, 0x210000, 0x40); 1577 1578 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1579 1580 MEM_WRITE_1(sc, 0x210000, 0x00); 1581 MEM_WRITE_1(sc, 0x210000, 0x00); 1582 MEM_WRITE_1(sc, 0x210000, 0x80); 1583 1584 MEM_WRITE_2(sc, 0x220000, 0x0703); 1585 MEM_WRITE_2(sc, 0x220000, 0x0707); 1586 1587 MEM_WRITE_1(sc, 0x210014, 0x72); 1588 MEM_WRITE_1(sc, 0x210014, 0x72); 1589 1590 MEM_WRITE_1(sc, 0x210000, 0x00); 1591 MEM_WRITE_1(sc, 0x210000, 0x80); 1592 1593 for (ntries = 0; ntries < 100; ntries++) { 1594 if (MEM_READ_1(sc, 0x210000) & 1) 1595 break; 1596 DELAY(1000); 1597 } 1598 if (ntries == 100) { 1599 printf("%s: timeout waiting for ucode to initialize\n", 1600 sc->sc_dev.dv_xname); 1601 return EIO; 1602 } 1603 1604 MEM_WRITE_4(sc, 0x3000e0, 0); 1605 1606 return 0; 1607} 1608 1609/* set of macros to handle unaligned little endian data in firmware image */ 1610#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1611#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1612int 1613ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1614{ 1615 u_char *p, *end; 1616 uint32_t tmp, dst; 1617 uint16_t len; 1618 int error; 1619 1620 p = fw; 1621 end = fw + size; 1622 while (p < end) { 1623 if (p + 6 > end) 1624 return EINVAL; 1625 1626 dst = GETLE32(p); p += 4; 1627 len = GETLE16(p); p += 2; 1628 1629 if (p + len > end) 1630 return EINVAL; 1631 1632 ipw_write_mem_1(sc, dst, p, len); 1633 p += len; 1634 } 1635 1636 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1637 IPW_IO_LED_OFF); 1638 1639 /* allow interrupts so we know when the firmware is inited */ 1640 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1641 1642 /* tell the adapter to initialize the firmware */ 1643 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1644 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1645 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1646 1647 /* wait at most one second for firmware initialization to complete */ 1648 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1649 printf("%s: timeout waiting for firmware initialization to " 1650 "complete\n", sc->sc_dev.dv_xname); 1651 return error; 1652 } 1653 1654 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1655 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1656 IPW_IO_GPIO3_MASK); 1657 1658 return 0; 1659} 1660 1661int 1662ipw_read_firmware(struct ipw_softc *sc, struct ipw_firmware *fw) 1663{ 1664 const struct ipw_firmware_hdr *hdr; 1665 const char *name; 1666 size_t size; 1667 int error; 1668 1669 switch (sc->sc_ic.ic_opmode) { 1670 case IEEE80211_M_STA: 1671 name = "ipw-bss"; 1672 break; 1673#ifndef IEEE80211_STA_ONLY 1674 case IEEE80211_M_IBSS: 1675 name = "ipw-ibss"; 1676 break; 1677#endif 1678 case IEEE80211_M_MONITOR: 1679 name = "ipw-monitor"; 1680 break; 1681 default: 1682 /* should not get there */ 1683 return ENODEV; 1684 } 1685 if ((error = loadfirmware(name, &fw->data, &size)) != 0) 1686 return error; 1687 1688 if (size < sizeof (*hdr)) { 1689 error = EINVAL; 1690 goto fail; 1691 } 1692 hdr = (const struct ipw_firmware_hdr *)fw->data; 1693 fw->main_size = letoh32(hdr->main_size); 1694 fw->ucode_size = letoh32(hdr->ucode_size); 1695 1696 if (size < sizeof (*hdr) + fw->main_size + fw->ucode_size) { 1697 error = EINVAL; 1698 goto fail; 1699 } 1700 fw->main = fw->data + sizeof (*hdr); 1701 fw->ucode = fw->main + fw->main_size; 1702 1703 return 0; 1704 1705fail: free(fw->data, M_DEVBUF); 1706 return error; 1707} 1708 1709void 1710ipw_scan(void *arg1, void *arg2) 1711{ 1712 struct ipw_softc *sc = arg1; 1713 struct ifnet *ifp = &sc->sc_ic.ic_if; 1714 struct ipw_scan_options scan; 1715 uint8_t ssid[IEEE80211_NWID_LEN]; 1716 int error; 1717 1718 /* 1719 * Firmware has a bug and does not honour the ``do not associate 1720 * after scan'' bit in the scan command. To prevent the firmware 1721 * from associating after the scan, we set the ESSID to something 1722 * unlikely to be used by a real AP. 1723 * XXX would setting the desired BSSID to a multicast address work? 1724 */ 1725 memset(ssid, '\r', sizeof ssid); 1726 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ssid, sizeof ssid); 1727 if (error != 0) 1728 goto fail; 1729 1730 /* no mandatory BSSID */ 1731 DPRINTF(("Setting mandatory BSSID to null\n")); 1732 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1733 if (error != 0) 1734 goto fail; 1735 1736 scan.flags = htole32(IPW_SCAN_DO_NOT_ASSOCIATE | IPW_SCAN_MIXED_CELL); 1737 scan.channels = htole32(0x3fff); /* scan channels 1-14 */ 1738 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1739 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1740 if (error != 0) 1741 goto fail; 1742 1743 /* start scanning */ 1744 DPRINTF(("Enabling adapter\n")); 1745 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1746 if (error != 0) 1747 goto fail; 1748 1749 return; 1750fail: 1751 printf("%s: scan request failed (error=%d)\n", sc->sc_dev.dv_xname, 1752 error); 1753 ieee80211_end_scan(ifp); 1754} 1755 1756void 1757ipw_auth_and_assoc(void *arg1, void *arg2) 1758{ 1759 struct ipw_softc *sc = arg1; 1760 struct ieee80211com *ic = &sc->sc_ic; 1761 struct ieee80211_node *ni = ic->ic_bss; 1762 struct ipw_scan_options scan; 1763 struct ipw_security security; 1764 struct ipw_assoc_req assoc; 1765 uint32_t data; 1766 uint8_t chan; 1767 int s, error; 1768 1769 DPRINTF(("Disabling adapter\n")); 1770 error = ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1771 if (error != 0) 1772 goto fail; 1773#if 1 1774 /* wait at most one second for card to be disabled */ 1775 s = splnet(); 1776 error = tsleep(sc, 0, "ipwdis", hz); 1777 splx(s); 1778 if (error != 0) { 1779 printf("%s: timeout waiting for disabled state\n", 1780 sc->sc_dev.dv_xname); 1781 goto fail; 1782 } 1783#else 1784 /* Intel's Linux driver polls for the DISABLED state instead.. */ 1785 for (ntries = 0; ntries < 1000; ntries++) { 1786 if (ipw_read_table1(sc, IPW_INFO_CARD_DISABLED) == 1) 1787 break; 1788 DELAY(10); 1789 } 1790 if (ntries == 1000) { 1791 printf("%s: timeout waiting for disabled state\n", 1792 sc->sc_dev.dv_xname); 1793 goto fail; 1794 } 1795#endif 1796 1797 bzero(&security, sizeof security); 1798 security.authmode = IPW_AUTH_OPEN; 1799 security.ciphers = htole32(IPW_CIPHER_NONE); 1800 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1801 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1802 sizeof security); 1803 if (error != 0) 1804 goto fail; 1805 1806#ifdef IPW_DEBUG 1807 if (ipw_debug > 0) { 1808 printf("Setting ESSID to "); 1809 ieee80211_print_essid(ni->ni_essid, ni->ni_esslen); 1810 printf("\n"); 1811 } 1812#endif 1813 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ni->ni_essid, ni->ni_esslen); 1814 if (error != 0) 1815 goto fail; 1816 1817 DPRINTF(("Setting BSSID to %s\n", ether_sprintf(ni->ni_bssid))); 1818 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, ni->ni_bssid, 1819 IEEE80211_ADDR_LEN); 1820 if (error != 0) 1821 goto fail; 1822 1823 data = htole32((ic->ic_flags & (IEEE80211_F_WEPON | 1824 IEEE80211_F_RSNON)) ? IPW_PRIVACYON : 0); 1825 DPRINTF(("Setting privacy flags to 0x%x\n", letoh32(data))); 1826 error = ipw_cmd(sc, IPW_CMD_SET_PRIVACY_FLAGS, &data, sizeof data); 1827 if (error != 0) 1828 goto fail; 1829 1830 /* let firmware set the capinfo, lintval, and bssid fixed fields */ 1831 bzero(&assoc, sizeof assoc); 1832 if (ic->ic_flags & IEEE80211_F_RSNON) { 1833 uint8_t *frm = assoc.optie; 1834 1835 /* tell firmware to add a WPA or RSN IE in (Re)Assoc req */ 1836 if (ni->ni_rsnprotos & IEEE80211_PROTO_RSN) 1837 frm = ieee80211_add_rsn(frm, ic, ni); 1838 else if (ni->ni_rsnprotos & IEEE80211_PROTO_WPA) 1839 frm = ieee80211_add_wpa(frm, ic, ni); 1840 assoc.optie_len = htole32(frm - assoc.optie); 1841 } 1842 DPRINTF(("Preparing assocation request (optional IE length=%d)\n", 1843 letoh32(assoc.optie_len))); 1844 error = ipw_cmd(sc, IPW_CMD_SET_ASSOC_REQ, &assoc, sizeof assoc); 1845 if (error != 0) 1846 goto fail; 1847 1848 scan.flags = htole32(IPW_SCAN_MIXED_CELL); 1849 chan = ieee80211_chan2ieee(ic, ni->ni_chan); 1850 scan.channels = htole32(1 << (chan - 1)); 1851 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1852 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1853 if (error != 0) 1854 goto fail; 1855 1856 /* trigger scan+association */ 1857 DPRINTF(("Enabling adapter\n")); 1858 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1859 if (error != 0) 1860 goto fail; 1861 1862 return; 1863fail: 1864 printf("%s: association failed (error=%d)\n", sc->sc_dev.dv_xname, 1865 error); 1866 ieee80211_begin_scan(&ic->ic_if); 1867} 1868 1869int 1870ipw_config(struct ipw_softc *sc) 1871{ 1872 struct ieee80211com *ic = &sc->sc_ic; 1873 struct ifnet *ifp = &ic->ic_if; 1874 struct ipw_configuration config; 1875 uint32_t data; 1876 int error; 1877 1878 switch (ic->ic_opmode) { 1879 case IEEE80211_M_STA: 1880 data = htole32(IPW_MODE_BSS); 1881 break; 1882#ifndef IEEE80211_STA_ONLY 1883 case IEEE80211_M_IBSS: 1884 data = htole32(IPW_MODE_IBSS); 1885 break; 1886#endif 1887 case IEEE80211_M_MONITOR: 1888 data = htole32(IPW_MODE_MONITOR); 1889 break; 1890 default: 1891 /* should not get there */ 1892 return ENODEV; 1893 } 1894 DPRINTF(("Setting mode to %u\n", letoh32(data))); 1895 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1896 if (error != 0) 1897 return error; 1898 1899 if ( 1900#ifndef IEEE80211_STA_ONLY 1901 ic->ic_opmode == IEEE80211_M_IBSS || 1902#endif 1903 ic->ic_opmode == IEEE80211_M_MONITOR) { 1904 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1905 DPRINTF(("Setting channel to %u\n", letoh32(data))); 1906 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1907 if (error != 0) 1908 return error; 1909 } 1910 1911 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1912 DPRINTF(("Enabling adapter\n")); 1913 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1914 } 1915 1916 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 1917 DPRINTF(("Setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 1918 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1919 IEEE80211_ADDR_LEN); 1920 if (error != 0) 1921 return error; 1922 1923 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1924 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1X_ENABLE); 1925#ifndef IEEE80211_STA_ONLY 1926 if (ic->ic_opmode == IEEE80211_M_IBSS) 1927 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1928#endif 1929 if (ifp->if_flags & IFF_PROMISC) 1930 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1931 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1932 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1933 DPRINTF(("Setting configuration 0x%x\n", config.flags)); 1934 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1935 if (error != 0) 1936 return error; 1937 1938 data = htole32(ic->ic_rtsthreshold); 1939 DPRINTF(("Setting RTS threshold to %u\n", letoh32(data))); 1940 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1941 if (error != 0) 1942 return error; 1943 1944 data = htole32(ic->ic_fragthreshold); 1945 DPRINTF(("Setting frag threshold to %u\n", letoh32(data))); 1946 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1947 if (error != 0) 1948 return error; 1949 1950 data = htole32(0x3); /* 1, 2 */ 1951 DPRINTF(("Setting basic tx rates to 0x%x\n", letoh32(data))); 1952 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1953 if (error != 0) 1954 return error; 1955 1956 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1957 DPRINTF(("Setting tx rates to 0x%x\n", letoh32(data))); 1958 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1959 if (error != 0) 1960 return error; 1961 1962 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1963 DPRINTF(("Setting MSDU tx rates to 0x%x\n", letoh32(data))); 1964 error = ipw_cmd(sc, IPW_CMD_SET_MSDU_TX_RATES, &data, sizeof data); 1965 if (error != 0) 1966 return error; 1967 1968 data = htole32(IPW_POWER_MODE_CAM); 1969 DPRINTF(("Setting power mode to %u\n", letoh32(data))); 1970 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1971 if (error != 0) 1972 return error; 1973 1974#ifndef IEEE80211_STA_ONLY 1975 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1976 data = htole32(32); /* default value */ 1977 DPRINTF(("Setting tx power index to %u\n", letoh32(data))); 1978 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1979 sizeof data); 1980 if (error != 0) 1981 return error; 1982 1983 data = htole32(ic->ic_lintval); 1984 DPRINTF(("Setting beacon interval to %u\n", letoh32(data))); 1985 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1986 sizeof data); 1987 if (error != 0) 1988 return error; 1989 } 1990#endif 1991 return 0; 1992} 1993 1994int 1995ipw_init(struct ifnet *ifp) 1996{ 1997 struct ipw_softc *sc = ifp->if_softc; 1998 struct ieee80211com *ic = &sc->sc_ic; 1999 struct ipw_firmware fw; 2000 int error; 2001 2002 ipw_stop(ifp, 0); 2003 2004 if ((error = ipw_reset(sc)) != 0) { 2005 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 2006 goto fail1; 2007 } 2008 2009 if ((error = ipw_read_firmware(sc, &fw)) != NULL) { 2010 printf("%s: error %d, could not read firmware\n", 2011 sc->sc_dev.dv_xname, error); 2012 goto fail1; 2013 } 2014 if ((error = ipw_load_ucode(sc, fw.ucode, fw.ucode_size)) != 0) { 2015 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 2016 goto fail2; 2017 } 2018 2019 ipw_stop_master(sc); 2020 2021 /* 2022 * Setup tx, rx and status rings. 2023 */ 2024 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2025 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 2026 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 2027 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 2028 sc->txold = IPW_NTBD - 1; /* latest bd index ack by firmware */ 2029 sc->txcur = 0; /* bd index to write to */ 2030 sc->txfree = IPW_NTBD - 2; 2031 2032 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2033 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 2034 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 2035 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 2036 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 2037 2038 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 2039 sc->status_map->dm_segs[0].ds_addr); 2040 2041 if ((error = ipw_load_firmware(sc, fw.main, fw.main_size)) != 0) { 2042 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 2043 goto fail2; 2044 } 2045 sc->sc_flags |= IPW_FLAG_FW_INITED; 2046 free(fw.data, M_DEVBUF); 2047 2048 /* retrieve information tables base addresses */ 2049 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2050 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2051 2052 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2053 2054 if ((error = ipw_config(sc)) != 0) { 2055 printf("%s: device configuration failed\n", 2056 sc->sc_dev.dv_xname); 2057 goto fail2; 2058 } 2059 2060 ifp->if_flags &= ~IFF_OACTIVE; 2061 ifp->if_flags |= IFF_RUNNING; 2062 2063 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2064 ieee80211_begin_scan(ifp); 2065 else 2066 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2067 2068 return 0; 2069 2070fail2: free(fw.data, M_DEVBUF); 2071fail1: ipw_stop(ifp, 0); 2072 return error; 2073} 2074 2075void 2076ipw_stop(struct ifnet *ifp, int disable) 2077{ 2078 struct ipw_softc *sc = ifp->if_softc; 2079 struct ieee80211com *ic = &sc->sc_ic; 2080 int i; 2081 2082 ipw_stop_master(sc); 2083 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2084 2085 ifp->if_timer = 0; 2086 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2087 2088 /* 2089 * Release tx buffers. 2090 */ 2091 for (i = 0; i < IPW_NTBD; i++) 2092 ipw_release_sbd(sc, &sc->stbd_list[i]); 2093 2094 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2095} 2096 2097void 2098ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2099 bus_size_t count) 2100{ 2101 for (; count > 0; offset++, datap++, count--) { 2102 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2103 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2104 } 2105} 2106 2107void 2108ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2109 bus_size_t count) 2110{ 2111 for (; count > 0; offset++, datap++, count--) { 2112 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2113 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2114 } 2115} 2116 2117struct cfdriver ipw_cd = { 2118 NULL, "ipw", DV_IFNET 2119}; 2120