if_ipw.c revision 1.87
1/* $OpenBSD: if_ipw.c,v 1.87 2010/07/28 21:21:38 deraadt Exp $ */ 2 3/*- 4 * Copyright (c) 2004-2008 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/* 21 * Driver for Intel PRO/Wireless 2100 802.11 network adapters. 22 */ 23 24#include "bpfilter.h" 25 26#include <sys/param.h> 27#include <sys/sockio.h> 28#include <sys/workq.h> 29#include <sys/mbuf.h> 30#include <sys/kernel.h> 31#include <sys/socket.h> 32#include <sys/systm.h> 33#include <sys/conf.h> 34#include <sys/device.h> 35 36#include <machine/bus.h> 37#include <machine/endian.h> 38#include <machine/intr.h> 39 40#include <dev/pci/pcireg.h> 41#include <dev/pci/pcivar.h> 42#include <dev/pci/pcidevs.h> 43 44#if NBPFILTER > 0 45#include <net/bpf.h> 46#endif 47#include <net/if.h> 48#include <net/if_arp.h> 49#include <net/if_dl.h> 50#include <net/if_media.h> 51#include <net/if_types.h> 52 53#include <netinet/in.h> 54#include <netinet/in_systm.h> 55#include <netinet/in_var.h> 56#include <netinet/if_ether.h> 57#include <netinet/ip.h> 58 59#include <net80211/ieee80211_var.h> 60#include <net80211/ieee80211_radiotap.h> 61 62#include <dev/pci/if_ipwreg.h> 63#include <dev/pci/if_ipwvar.h> 64 65int ipw_match(struct device *, void *, void *); 66void ipw_attach(struct device *, struct device *, void *); 67int ipw_activate(struct device *, int); 68void ipw_resume(void *, void *); 69void ipw_power(int, void *); 70int ipw_dma_alloc(struct ipw_softc *); 71void ipw_release(struct ipw_softc *); 72int ipw_media_change(struct ifnet *); 73void ipw_media_status(struct ifnet *, struct ifmediareq *); 74int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 75uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 76void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 77void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 78void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 79 struct ipw_soft_bd *, struct ipw_soft_buf *); 80void ipw_notification_intr(struct ipw_softc *, 81 struct ipw_soft_buf *); 82void ipw_rx_intr(struct ipw_softc *); 83void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 84void ipw_tx_intr(struct ipw_softc *); 85int ipw_intr(void *); 86int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 87int ipw_send_mgmt(struct ieee80211com *, struct ieee80211_node *, 88 int, int, int); 89int ipw_tx_start(struct ifnet *, struct mbuf *, 90 struct ieee80211_node *); 91void ipw_start(struct ifnet *); 92void ipw_watchdog(struct ifnet *); 93int ipw_ioctl(struct ifnet *, u_long, caddr_t); 94uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 95void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 96int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 97 uint32_t *); 98void ipw_stop_master(struct ipw_softc *); 99int ipw_reset(struct ipw_softc *); 100int ipw_load_ucode(struct ipw_softc *, u_char *, int); 101int ipw_load_firmware(struct ipw_softc *, u_char *, int); 102int ipw_read_firmware(struct ipw_softc *, struct ipw_firmware *); 103void ipw_scan(void *, void *); 104void ipw_auth_and_assoc(void *, void *); 105int ipw_config(struct ipw_softc *); 106int ipw_init(struct ifnet *); 107void ipw_stop(struct ifnet *, int); 108void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 109 bus_size_t); 110void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 111 bus_size_t); 112 113static __inline uint8_t 114MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 115{ 116 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 117 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 118} 119 120static __inline uint32_t 121MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 122{ 123 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 124 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 125} 126 127#ifdef IPW_DEBUG 128#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 129#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 130int ipw_debug = 0; 131#else 132#define DPRINTF(x) 133#define DPRINTFN(n, x) 134#endif 135 136struct cfattach ipw_ca = { 137 sizeof (struct ipw_softc), ipw_match, ipw_attach, NULL, 138 ipw_activate 139}; 140 141int 142ipw_match(struct device *parent, void *match, void *aux) 143{ 144 struct pci_attach_args *pa = aux; 145 146 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 147 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 148 return 1; 149 150 return 0; 151} 152 153/* Base Address Register */ 154#define IPW_PCI_BAR0 0x10 155 156void 157ipw_attach(struct device *parent, struct device *self, void *aux) 158{ 159 struct ipw_softc *sc = (struct ipw_softc *)self; 160 struct ieee80211com *ic = &sc->sc_ic; 161 struct ifnet *ifp = &ic->ic_if; 162 struct pci_attach_args *pa = aux; 163 const char *intrstr; 164 bus_space_tag_t memt; 165 bus_space_handle_t memh; 166 bus_addr_t base; 167 pci_intr_handle_t ih; 168 pcireg_t data; 169 uint16_t val; 170 int error, i; 171 172 sc->sc_pct = pa->pa_pc; 173 sc->sc_pcitag = pa->pa_tag, 174 175 /* clear device specific PCI configuration register 0x41 */ 176 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 177 data &= ~0x0000ff00; 178 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 179 180 /* map the register window */ 181 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 182 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 183 if (error != 0) { 184 printf(": can't map mem space\n"); 185 return; 186 } 187 188 sc->sc_st = memt; 189 sc->sc_sh = memh; 190 sc->sc_dmat = pa->pa_dmat; 191 192 /* disable interrupts */ 193 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 194 195 if (pci_intr_map(pa, &ih) != 0) { 196 printf(": can't map interrupt\n"); 197 return; 198 } 199 200 intrstr = pci_intr_string(sc->sc_pct, ih); 201 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 202 sc->sc_dev.dv_xname); 203 if (sc->sc_ih == NULL) { 204 printf(": can't establish interrupt"); 205 if (intrstr != NULL) 206 printf(" at %s", intrstr); 207 printf("\n"); 208 return; 209 } 210 printf(": %s", intrstr); 211 212 if (ipw_reset(sc) != 0) { 213 printf(": could not reset adapter\n"); 214 return; 215 } 216 217 if (ipw_dma_alloc(sc) != 0) { 218 printf(": failed to allocate DMA resources\n"); 219 return; 220 } 221 222 ic->ic_phytype = IEEE80211_T_DS; 223 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 224 ic->ic_state = IEEE80211_S_INIT; 225 226 /* set device capabilities */ 227 ic->ic_caps = 228#ifndef IEEE80211_STA_ONLY 229 IEEE80211_C_IBSS | /* IBSS mode supported */ 230#endif 231 IEEE80211_C_MONITOR | /* monitor mode supported */ 232 IEEE80211_C_TXPMGT | /* tx power management */ 233 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 234 IEEE80211_C_WEP | /* s/w WEP */ 235 IEEE80211_C_RSN | /* WPA/RSN */ 236 IEEE80211_C_SCANALL; /* h/w scanning */ 237 238 /* read MAC address from EEPROM */ 239 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 240 ic->ic_myaddr[0] = val >> 8; 241 ic->ic_myaddr[1] = val & 0xff; 242 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 243 ic->ic_myaddr[2] = val >> 8; 244 ic->ic_myaddr[3] = val & 0xff; 245 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 246 ic->ic_myaddr[4] = val >> 8; 247 ic->ic_myaddr[5] = val & 0xff; 248 249 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 250 251 /* set supported .11b rates */ 252 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 253 254 /* set supported .11b channels (1 through 14) */ 255 for (i = 1; i <= 14; i++) { 256 ic->ic_channels[i].ic_freq = 257 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 258 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 259 } 260 261 /* IBSS channel undefined for now */ 262 ic->ic_ibss_chan = &ic->ic_channels[0]; 263 264 ifp->if_softc = sc; 265 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 266 ifp->if_init = ipw_init; 267 ifp->if_ioctl = ipw_ioctl; 268 ifp->if_start = ipw_start; 269 ifp->if_watchdog = ipw_watchdog; 270 IFQ_SET_READY(&ifp->if_snd); 271 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 272 273 if_attach(ifp); 274 ieee80211_ifattach(ifp); 275 /* override state transition machine */ 276 sc->sc_newstate = ic->ic_newstate; 277 ic->ic_newstate = ipw_newstate; 278 ic->ic_send_mgmt = ipw_send_mgmt; 279 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 280 281 sc->powerhook = powerhook_establish(ipw_power, sc); 282 283#if NBPFILTER > 0 284 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 285 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 286 287 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 288 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 289 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 290 291 sc->sc_txtap_len = sizeof sc->sc_txtapu; 292 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 293 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 294#endif 295} 296 297int 298ipw_activate(struct device *self, int act) 299{ 300 struct ipw_softc *sc = (struct ipw_softc *)self; 301 struct ifnet *ifp = &sc->sc_ic.ic_if; 302 303 switch (act) { 304 case DVACT_SUSPEND: 305 if (ifp->if_flags & IFF_RUNNING) 306 ipw_stop(ifp, 0); 307 break; 308 case DVACT_RESUME: 309 workq_queue_task(NULL, &sc->sc_resume_wqt, 0, 310 ipw_resume, sc, NULL); 311 break; 312 } 313 314 return (0); 315} 316 317void 318ipw_resume(void *arg1, void *arg2) 319{ 320 ipw_power(PWR_RESUME, arg1); 321} 322 323void 324ipw_power(int why, void *arg) 325{ 326 struct ipw_softc *sc = arg; 327 struct ifnet *ifp = &sc->sc_ic.ic_if; 328 pcireg_t data; 329 330 if (why != PWR_RESUME) { 331 ipw_stop(ifp, 0); 332 return; 333 } 334 335 /* clear device specific PCI configuration register 0x41 */ 336 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 337 data &= ~0x0000ff00; 338 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 339 340 if (ifp->if_flags & IFF_UP) 341 ipw_init(ifp); 342} 343 344int 345ipw_dma_alloc(struct ipw_softc *sc) 346{ 347 struct ipw_soft_bd *sbd; 348 struct ipw_soft_hdr *shdr; 349 struct ipw_soft_buf *sbuf; 350 int i, nsegs, error; 351 352 /* 353 * Allocate and map tx ring. 354 */ 355 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 356 BUS_DMA_NOWAIT, &sc->tbd_map); 357 if (error != 0) { 358 printf("%s: could not create tx ring DMA map\n", 359 sc->sc_dev.dv_xname); 360 goto fail; 361 } 362 363 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 364 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 365 if (error != 0) { 366 printf("%s: could not allocate tx ring DMA memory\n", 367 sc->sc_dev.dv_xname); 368 goto fail; 369 } 370 371 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 372 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 373 if (error != 0) { 374 printf("%s: can't map tx ring DMA memory\n", 375 sc->sc_dev.dv_xname); 376 goto fail; 377 } 378 379 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 380 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 381 if (error != 0) { 382 printf("%s: could not load tx ring DMA map\n", 383 sc->sc_dev.dv_xname); 384 goto fail; 385 } 386 387 /* 388 * Allocate and map rx ring. 389 */ 390 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 391 BUS_DMA_NOWAIT, &sc->rbd_map); 392 if (error != 0) { 393 printf("%s: could not create rx ring DMA map\n", 394 sc->sc_dev.dv_xname); 395 goto fail; 396 } 397 398 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 399 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 400 if (error != 0) { 401 printf("%s: could not allocate rx ring DMA memory\n", 402 sc->sc_dev.dv_xname); 403 goto fail; 404 } 405 406 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 407 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 408 if (error != 0) { 409 printf("%s: can't map rx ring DMA memory\n", 410 sc->sc_dev.dv_xname); 411 goto fail; 412 } 413 414 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 415 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 416 if (error != 0) { 417 printf("%s: could not load tx ring DMA map\n", 418 sc->sc_dev.dv_xname); 419 goto fail; 420 } 421 422 /* 423 * Allocate and map status ring. 424 */ 425 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 426 0, BUS_DMA_NOWAIT, &sc->status_map); 427 if (error != 0) { 428 printf("%s: could not create status ring DMA map\n", 429 sc->sc_dev.dv_xname); 430 goto fail; 431 } 432 433 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 434 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 435 if (error != 0) { 436 printf("%s: could not allocate status ring DMA memory\n", 437 sc->sc_dev.dv_xname); 438 goto fail; 439 } 440 441 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 442 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 443 if (error != 0) { 444 printf("%s: can't map status ring DMA memory\n", 445 sc->sc_dev.dv_xname); 446 goto fail; 447 } 448 449 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 450 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 451 if (error != 0) { 452 printf("%s: could not load status ring DMA map\n", 453 sc->sc_dev.dv_xname); 454 goto fail; 455 } 456 457 /* 458 * Allocate command DMA map. 459 */ 460 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 461 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 462 if (error != 0) { 463 printf("%s: could not create command DMA map\n", 464 sc->sc_dev.dv_xname); 465 goto fail; 466 } 467 468 /* 469 * Allocate headers DMA maps. 470 */ 471 SLIST_INIT(&sc->free_shdr); 472 for (i = 0; i < IPW_NDATA; i++) { 473 shdr = &sc->shdr_list[i]; 474 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_hdr), 475 1, sizeof (struct ipw_hdr), 0, BUS_DMA_NOWAIT, &shdr->map); 476 if (error != 0) { 477 printf("%s: could not create header DMA map\n", 478 sc->sc_dev.dv_xname); 479 goto fail; 480 } 481 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 482 } 483 484 /* 485 * Allocate tx buffers DMA maps. 486 */ 487 SLIST_INIT(&sc->free_sbuf); 488 for (i = 0; i < IPW_NDATA; i++) { 489 sbuf = &sc->tx_sbuf_list[i]; 490 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, IPW_MAX_NSEG, 491 MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 492 if (error != 0) { 493 printf("%s: could not create tx DMA map\n", 494 sc->sc_dev.dv_xname); 495 goto fail; 496 } 497 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 498 } 499 500 /* 501 * Initialize tx ring. 502 */ 503 for (i = 0; i < IPW_NTBD; i++) { 504 sbd = &sc->stbd_list[i]; 505 sbd->bd = &sc->tbd_list[i]; 506 sbd->type = IPW_SBD_TYPE_NOASSOC; 507 } 508 509 /* 510 * Pre-allocate rx buffers and DMA maps. 511 */ 512 for (i = 0; i < IPW_NRBD; i++) { 513 sbd = &sc->srbd_list[i]; 514 sbuf = &sc->rx_sbuf_list[i]; 515 sbd->bd = &sc->rbd_list[i]; 516 517 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 518 if (sbuf->m == NULL) { 519 printf("%s: could not allocate rx mbuf\n", 520 sc->sc_dev.dv_xname); 521 error = ENOMEM; 522 goto fail; 523 } 524 MCLGET(sbuf->m, M_DONTWAIT); 525 if (!(sbuf->m->m_flags & M_EXT)) { 526 m_freem(sbuf->m); 527 printf("%s: could not allocate rx mbuf cluster\n", 528 sc->sc_dev.dv_xname); 529 error = ENOMEM; 530 goto fail; 531 } 532 533 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 534 0, BUS_DMA_NOWAIT, &sbuf->map); 535 if (error != 0) { 536 printf("%s: could not create rx DMA map\n", 537 sc->sc_dev.dv_xname); 538 goto fail; 539 } 540 541 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 542 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 543 if (error != 0) { 544 printf("%s: can't map rx DMA memory\n", 545 sc->sc_dev.dv_xname); 546 goto fail; 547 } 548 549 sbd->type = IPW_SBD_TYPE_DATA; 550 sbd->priv = sbuf; 551 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 552 sbd->bd->len = htole32(MCLBYTES); 553 } 554 555 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 556 BUS_DMASYNC_PREWRITE); 557 558 return 0; 559 560fail: ipw_release(sc); 561 return error; 562} 563 564void 565ipw_release(struct ipw_softc *sc) 566{ 567 struct ipw_soft_buf *sbuf; 568 int i; 569 570 if (sc->tbd_map != NULL) { 571 if (sc->tbd_list != NULL) { 572 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 573 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 574 IPW_TBD_SZ); 575 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 576 } 577 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 578 } 579 580 if (sc->rbd_map != NULL) { 581 if (sc->rbd_list != NULL) { 582 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 583 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 584 IPW_RBD_SZ); 585 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 586 } 587 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 588 } 589 590 if (sc->status_map != NULL) { 591 if (sc->status_list != NULL) { 592 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 593 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 594 IPW_RBD_SZ); 595 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 596 } 597 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 598 } 599 600 if (sc->cmd_map != NULL) 601 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 602 603 for (i = 0; i < IPW_NDATA; i++) 604 bus_dmamap_destroy(sc->sc_dmat, sc->shdr_list[i].map); 605 606 for (i = 0; i < IPW_NDATA; i++) 607 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 608 609 for (i = 0; i < IPW_NRBD; i++) { 610 sbuf = &sc->rx_sbuf_list[i]; 611 if (sbuf->map != NULL) { 612 if (sbuf->m != NULL) { 613 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 614 m_freem(sbuf->m); 615 } 616 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 617 } 618 } 619} 620 621int 622ipw_media_change(struct ifnet *ifp) 623{ 624 int error; 625 626 error = ieee80211_media_change(ifp); 627 if (error != ENETRESET) 628 return error; 629 630 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 631 ipw_init(ifp); 632 633 return 0; 634} 635 636void 637ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 638{ 639 struct ipw_softc *sc = ifp->if_softc; 640 struct ieee80211com *ic = &sc->sc_ic; 641 static const struct { 642 uint32_t val; 643 int rate; 644 } rates[] = { 645 { IPW_RATE_DS1, 2 }, 646 { IPW_RATE_DS2, 4 }, 647 { IPW_RATE_DS5, 11 }, 648 { IPW_RATE_DS11, 22 }, 649 }; 650 uint32_t val; 651 int rate, i; 652 653 imr->ifm_status = IFM_AVALID; 654 imr->ifm_active = IFM_IEEE80211; 655 if (ic->ic_state == IEEE80211_S_RUN) 656 imr->ifm_status |= IFM_ACTIVE; 657 658 /* read current transmission rate from adapter */ 659 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 660 val &= 0xf; 661 662 /* convert rate to 802.11 rate */ 663 for (i = 0; i < nitems(rates) && rates[i].val != val; i++); 664 rate = (i < nitems(rates)) ? rates[i].rate : 0; 665 666 imr->ifm_active |= IFM_IEEE80211_11B; 667 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 668 switch (ic->ic_opmode) { 669 case IEEE80211_M_STA: 670 break; 671#ifndef IEEE80211_STA_ONLY 672 case IEEE80211_M_IBSS: 673 imr->ifm_active |= IFM_IEEE80211_IBSS; 674 break; 675#endif 676 case IEEE80211_M_MONITOR: 677 imr->ifm_active |= IFM_IEEE80211_MONITOR; 678 break; 679 default: 680 /* should not get there */ 681 break; 682 } 683} 684 685int 686ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 687{ 688 struct ipw_softc *sc = ic->ic_softc; 689 int error; 690 691 switch (nstate) { 692 case IEEE80211_S_SCAN: 693 error = workq_add_task(NULL, 0, ipw_scan, sc, NULL); 694 if (error != 0) 695 return error; 696 break; 697 698 case IEEE80211_S_AUTH: 699 error = workq_add_task(NULL, 0, ipw_auth_and_assoc, sc, NULL); 700 if (error != 0) 701 return error; 702 break; 703 704 case IEEE80211_S_RUN: 705 case IEEE80211_S_INIT: 706 case IEEE80211_S_ASSOC: 707 /* nothing to do */ 708 break; 709 } 710 711 ic->ic_state = nstate; 712 return 0; 713} 714 715/* 716 * Read 16 bits at address 'addr' from the Microwire EEPROM. 717 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 718 */ 719uint16_t 720ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 721{ 722 uint32_t tmp; 723 uint16_t val; 724 int n; 725 726 /* clock C once before the first command */ 727 IPW_EEPROM_CTL(sc, 0); 728 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 729 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 730 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 731 732 /* write start bit (1) */ 733 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 734 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 735 736 /* write READ opcode (10) */ 737 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 738 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 739 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 740 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 741 742 /* write address A7-A0 */ 743 for (n = 7; n >= 0; n--) { 744 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 745 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 746 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 747 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 748 } 749 750 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 751 752 /* read data Q15-Q0 */ 753 val = 0; 754 for (n = 15; n >= 0; n--) { 755 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 756 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 757 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 758 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 759 } 760 761 IPW_EEPROM_CTL(sc, 0); 762 763 /* clear Chip Select and clock C */ 764 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 765 IPW_EEPROM_CTL(sc, 0); 766 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 767 768 return val; 769} 770 771void 772ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 773{ 774 struct ipw_cmd *cmd; 775 776 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 777 BUS_DMASYNC_POSTREAD); 778 779 cmd = mtod(sbuf->m, struct ipw_cmd *); 780 781 DPRINTFN(2, ("received command ack type=%u,status=%u\n", 782 letoh32(cmd->type), letoh32(cmd->status))); 783 784 wakeup(&sc->cmd); 785} 786 787void 788ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 789{ 790 struct ieee80211com *ic = &sc->sc_ic; 791 struct ifnet *ifp = &ic->ic_if; 792 uint32_t state; 793 794 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 795 BUS_DMASYNC_POSTREAD); 796 797 state = letoh32(*mtod(sbuf->m, uint32_t *)); 798 799 DPRINTFN(2, ("firmware state changed to 0x%x\n", state)); 800 801 switch (state) { 802 case IPW_STATE_ASSOCIATED: 803 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 804 break; 805 806 case IPW_STATE_SCANNING: 807 if (ic->ic_state == IEEE80211_S_RUN) 808 ieee80211_begin_scan(ifp); 809 break; 810 811 case IPW_STATE_SCAN_COMPLETE: 812 if (ic->ic_state == IEEE80211_S_SCAN) 813 ieee80211_end_scan(ifp); 814 break; 815 816 case IPW_STATE_ASSOCIATION_LOST: 817 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 818 break; 819 820 case IPW_STATE_DISABLED: 821 wakeup(sc); 822 break; 823 824 case IPW_STATE_RADIO_DISABLED: 825 ifp->if_flags &= ~IFF_UP; 826 ipw_stop(&ic->ic_if, 1); 827 break; 828 } 829} 830 831void 832ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 833 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 834{ 835 struct ieee80211com *ic = &sc->sc_ic; 836 struct ifnet *ifp = &ic->ic_if; 837 struct mbuf *mnew, *m; 838 struct ieee80211_frame *wh; 839 struct ieee80211_rxinfo rxi; 840 struct ieee80211_node *ni; 841 int error; 842 843 DPRINTFN(5, ("received data frame len=%u,rssi=%u\n", 844 letoh32(status->len), status->rssi)); 845 846 /* 847 * Try to allocate a new mbuf for this ring element and load it before 848 * processing the current mbuf. If the ring element cannot be loaded, 849 * drop the received packet and reuse the old mbuf. In the unlikely 850 * case that the old mbuf can't be reloaded either, explicitly panic. 851 */ 852 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 853 if (mnew == NULL) { 854 ifp->if_ierrors++; 855 return; 856 } 857 MCLGET(mnew, M_DONTWAIT); 858 if (!(mnew->m_flags & M_EXT)) { 859 m_freem(mnew); 860 ifp->if_ierrors++; 861 return; 862 } 863 864 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 865 BUS_DMASYNC_POSTREAD); 866 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 867 868 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(mnew, void *), 869 MCLBYTES, NULL, BUS_DMA_NOWAIT); 870 if (error != 0) { 871 m_freem(mnew); 872 873 /* try to reload the old mbuf */ 874 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 875 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 876 if (error != 0) { 877 /* very unlikely that it will fail... */ 878 panic("%s: could not load old rx mbuf", 879 sc->sc_dev.dv_xname); 880 } 881 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 882 ifp->if_ierrors++; 883 return; 884 } 885 886 m = sbuf->m; 887 sbuf->m = mnew; 888 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 889 890 /* finalize mbuf */ 891 m->m_pkthdr.rcvif = ifp; 892 m->m_pkthdr.len = m->m_len = letoh32(status->len); 893 894#if NBPFILTER > 0 895 if (sc->sc_drvbpf != NULL) { 896 struct mbuf mb; 897 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 898 899 tap->wr_flags = 0; 900 tap->wr_antsignal = status->rssi; 901 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 902 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 903 904 mb.m_data = (caddr_t)tap; 905 mb.m_len = sc->sc_rxtap_len; 906 mb.m_next = m; 907 mb.m_nextpkt = NULL; 908 mb.m_type = 0; 909 mb.m_flags = 0; 910 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 911 } 912#endif 913 914 wh = mtod(m, struct ieee80211_frame *); 915 ni = ieee80211_find_rxnode(ic, wh); 916 917 /* send the frame to the upper layer */ 918 rxi.rxi_flags = 0; 919 rxi.rxi_rssi = status->rssi; 920 rxi.rxi_tstamp = 0; /* unused */ 921 ieee80211_input(ifp, m, ni, &rxi); 922 923 ieee80211_release_node(ic, ni); 924} 925 926void 927ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 928{ 929 DPRINTFN(2, ("received notification\n")); 930} 931 932void 933ipw_rx_intr(struct ipw_softc *sc) 934{ 935 struct ipw_status *status; 936 struct ipw_soft_bd *sbd; 937 struct ipw_soft_buf *sbuf; 938 uint32_t r, i; 939 940 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 941 942 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 943 944 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 945 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 946 BUS_DMASYNC_POSTREAD); 947 948 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 949 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 950 BUS_DMASYNC_POSTREAD); 951 952 status = &sc->status_list[i]; 953 sbd = &sc->srbd_list[i]; 954 sbuf = sbd->priv; 955 956 switch (letoh16(status->code) & 0xf) { 957 case IPW_STATUS_CODE_COMMAND: 958 ipw_command_intr(sc, sbuf); 959 break; 960 961 case IPW_STATUS_CODE_NEWSTATE: 962 ipw_newstate_intr(sc, sbuf); 963 break; 964 965 case IPW_STATUS_CODE_DATA_802_3: 966 case IPW_STATUS_CODE_DATA_802_11: 967 ipw_data_intr(sc, status, sbd, sbuf); 968 break; 969 970 case IPW_STATUS_CODE_NOTIFICATION: 971 ipw_notification_intr(sc, sbuf); 972 break; 973 974 default: 975 printf("%s: unknown status code %u\n", 976 sc->sc_dev.dv_xname, letoh16(status->code)); 977 } 978 sbd->bd->flags = 0; 979 980 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 981 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 982 BUS_DMASYNC_PREWRITE); 983 } 984 985 /* tell the firmware what we have processed */ 986 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 987 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 988} 989 990void 991ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 992{ 993 struct ieee80211com *ic = &sc->sc_ic; 994 struct ipw_soft_hdr *shdr; 995 struct ipw_soft_buf *sbuf; 996 997 switch (sbd->type) { 998 case IPW_SBD_TYPE_COMMAND: 999 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 1000 break; 1001 1002 case IPW_SBD_TYPE_HEADER: 1003 shdr = sbd->priv; 1004 bus_dmamap_unload(sc->sc_dmat, shdr->map); 1005 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 1006 break; 1007 1008 case IPW_SBD_TYPE_DATA: 1009 sbuf = sbd->priv; 1010 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1011 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1012 1013 m_freem(sbuf->m); 1014 1015 if (sbuf->ni != NULL) 1016 ieee80211_release_node(ic, sbuf->ni); 1017 1018 /* kill watchdog timer */ 1019 sc->sc_tx_timer = 0; 1020 break; 1021 } 1022 sbd->type = IPW_SBD_TYPE_NOASSOC; 1023} 1024 1025void 1026ipw_tx_intr(struct ipw_softc *sc) 1027{ 1028 struct ifnet *ifp = &sc->sc_ic.ic_if; 1029 struct ipw_soft_bd *sbd; 1030 uint32_t r, i; 1031 1032 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 1033 1034 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1035 sbd = &sc->stbd_list[i]; 1036 1037 if (sbd->type == IPW_SBD_TYPE_DATA) 1038 ifp->if_opackets++; 1039 1040 ipw_release_sbd(sc, sbd); 1041 sc->txfree++; 1042 } 1043 1044 /* remember what the firmware has processed */ 1045 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1046 1047 /* call start() since some buffer descriptors have been released */ 1048 ifp->if_flags &= ~IFF_OACTIVE; 1049 (*ifp->if_start)(ifp); 1050} 1051 1052int 1053ipw_intr(void *arg) 1054{ 1055 struct ipw_softc *sc = arg; 1056 struct ifnet *ifp = &sc->sc_ic.ic_if; 1057 uint32_t r; 1058 1059 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) 1060 return 0; 1061 1062 /* disable interrupts */ 1063 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1064 1065 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1066 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 1067 ifp->if_flags &= ~IFF_UP; 1068 ipw_stop(ifp, 1); 1069 return 1; 1070 } 1071 1072 if (r & IPW_INTR_FW_INIT_DONE) 1073 wakeup(sc); 1074 1075 if (r & IPW_INTR_RX_TRANSFER) 1076 ipw_rx_intr(sc); 1077 1078 if (r & IPW_INTR_TX_TRANSFER) 1079 ipw_tx_intr(sc); 1080 1081 /* acknowledge interrupts */ 1082 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1083 1084 /* re-enable interrupts */ 1085 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1086 1087 return 1; 1088} 1089 1090int 1091ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1092{ 1093 struct ipw_soft_bd *sbd; 1094 int s, error; 1095 1096 s = splnet(); 1097 1098 sc->cmd.type = htole32(type); 1099 sc->cmd.subtype = htole32(0); 1100 sc->cmd.len = htole32(len); 1101 sc->cmd.seq = htole32(0); 1102 if (data != NULL) 1103 bcopy(data, sc->cmd.data, len); 1104 1105 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 1106 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 1107 if (error != 0) { 1108 printf("%s: can't map command DMA memory\n", 1109 sc->sc_dev.dv_xname); 1110 splx(s); 1111 return error; 1112 } 1113 1114 sbd = &sc->stbd_list[sc->txcur]; 1115 sbd->type = IPW_SBD_TYPE_COMMAND; 1116 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1117 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1118 sbd->bd->nfrag = 1; 1119 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1120 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1121 1122 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1123 BUS_DMASYNC_PREWRITE); 1124 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1125 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1126 BUS_DMASYNC_PREWRITE); 1127 1128 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1129 sc->txfree--; 1130 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1131 1132 DPRINTFN(2, ("sending command type=%u,len=%u\n", type, len)); 1133 1134 /* wait at most one second for command to complete */ 1135 error = tsleep(&sc->cmd, 0, "ipwcmd", hz); 1136 splx(s); 1137 1138 return error; 1139} 1140 1141/* ARGSUSED */ 1142int 1143ipw_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type, 1144 int arg1, int arg2) 1145{ 1146 return EOPNOTSUPP; 1147} 1148 1149int 1150ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 1151{ 1152 struct ipw_softc *sc = ifp->if_softc; 1153 struct ieee80211com *ic = &sc->sc_ic; 1154 struct ieee80211_frame *wh; 1155 struct ieee80211_key *k; 1156 struct mbuf *m1; 1157 struct ipw_soft_bd *sbd; 1158 struct ipw_soft_hdr *shdr; 1159 struct ipw_soft_buf *sbuf; 1160 int error, i; 1161 1162 wh = mtod(m, struct ieee80211_frame *); 1163 1164 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1165 k = ieee80211_get_txkey(ic, wh, ni); 1166 1167 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1168 return ENOBUFS; 1169 1170 /* packet header may have moved, reset our local pointer */ 1171 wh = mtod(m, struct ieee80211_frame *); 1172 } 1173 1174#if NBPFILTER > 0 1175 if (sc->sc_drvbpf != NULL) { 1176 struct mbuf mb; 1177 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1178 1179 tap->wt_flags = 0; 1180 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1181 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1182 1183 mb.m_data = (caddr_t)tap; 1184 mb.m_len = sc->sc_txtap_len; 1185 mb.m_next = m; 1186 mb.m_nextpkt = NULL; 1187 mb.m_type = 0; 1188 mb.m_flags = 0; 1189 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1190 } 1191#endif 1192 1193 shdr = SLIST_FIRST(&sc->free_shdr); 1194 sbuf = SLIST_FIRST(&sc->free_sbuf); 1195 1196 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1197 shdr->hdr.subtype = htole32(0); 1198 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) ? 1 : 0; 1199 shdr->hdr.encrypt = 0; 1200 shdr->hdr.keyidx = 0; 1201 shdr->hdr.keysz = 0; 1202 shdr->hdr.fragmentsz = htole16(0); 1203 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1204 if (ic->ic_opmode == IEEE80211_M_STA) 1205 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1206 else 1207 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1208 1209 /* trim IEEE802.11 header */ 1210 m_adj(m, sizeof (struct ieee80211_frame)); 1211 1212 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 1213 if (error != 0 && error != EFBIG) { 1214 printf("%s: can't map mbuf (error %d)\n", 1215 sc->sc_dev.dv_xname, error); 1216 m_freem(m); 1217 return error; 1218 } 1219 if (error != 0) { 1220 /* too many fragments, linearize */ 1221 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1222 if (m1 == NULL) { 1223 m_freem(m); 1224 return ENOBUFS; 1225 } 1226 if (m->m_pkthdr.len > MHLEN) { 1227 MCLGET(m1, M_DONTWAIT); 1228 if (!(m1->m_flags & M_EXT)) { 1229 m_freem(m); 1230 m_freem(m1); 1231 return ENOBUFS; 1232 } 1233 } 1234 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, caddr_t)); 1235 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 1236 m_freem(m); 1237 m = m1; 1238 1239 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, 1240 BUS_DMA_NOWAIT); 1241 if (error != 0) { 1242 printf("%s: can't map mbuf (error %d)\n", 1243 sc->sc_dev.dv_xname, error); 1244 m_freem(m); 1245 return error; 1246 } 1247 } 1248 1249 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 1250 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 1251 if (error != 0) { 1252 printf("%s: can't map header DMA memory (error %d)\n", 1253 sc->sc_dev.dv_xname, error); 1254 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1255 m_freem(m); 1256 return error; 1257 } 1258 1259 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1260 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1261 1262 sbd = &sc->stbd_list[sc->txcur]; 1263 sbd->type = IPW_SBD_TYPE_HEADER; 1264 sbd->priv = shdr; 1265 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 1266 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1267 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1268 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1269 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1270 1271 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1272 sc->txcur * sizeof (struct ipw_bd), 1273 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1274 1275 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1276 sc->txfree--; 1277 1278 sbuf->m = m; 1279 sbuf->ni = ni; 1280 1281 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1282 sbd = &sc->stbd_list[sc->txcur]; 1283 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1284 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1285 sbd->bd->nfrag = 0; /* used only in first bd */ 1286 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1287 if (i == sbuf->map->dm_nsegs - 1) { 1288 sbd->type = IPW_SBD_TYPE_DATA; 1289 sbd->priv = sbuf; 1290 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1291 } else { 1292 sbd->type = IPW_SBD_TYPE_NOASSOC; 1293 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1294 } 1295 1296 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1297 sc->txcur * sizeof (struct ipw_bd), 1298 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1299 1300 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1301 sc->txfree--; 1302 } 1303 1304 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1305 BUS_DMASYNC_PREWRITE); 1306 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 1307 BUS_DMASYNC_PREWRITE); 1308 1309 /* inform firmware about this new packet */ 1310 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1311 1312 return 0; 1313} 1314 1315void 1316ipw_start(struct ifnet *ifp) 1317{ 1318 struct ipw_softc *sc = ifp->if_softc; 1319 struct ieee80211com *ic = &sc->sc_ic; 1320 struct ieee80211_node *ni; 1321 struct mbuf *m; 1322 1323 if (ic->ic_state != IEEE80211_S_RUN) 1324 return; 1325 1326 for (;;) { 1327 IFQ_POLL(&ifp->if_snd, m); 1328 if (m == NULL) 1329 break; 1330 1331 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1332 ifp->if_flags |= IFF_OACTIVE; 1333 break; 1334 } 1335 IFQ_DEQUEUE(&ifp->if_snd, m); 1336#if NBPFILTER > 0 1337 if (ifp->if_bpf != NULL) 1338 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1339#endif 1340 m = ieee80211_encap(ifp, m, &ni); 1341 if (m == NULL) 1342 continue; 1343#if NBPFILTER > 0 1344 if (ic->ic_rawbpf != NULL) 1345 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1346#endif 1347 if (ipw_tx_start(ifp, m, ni) != 0) { 1348 if (ni != NULL) 1349 ieee80211_release_node(ic, ni); 1350 ifp->if_oerrors++; 1351 break; 1352 } 1353 1354 /* start watchdog timer */ 1355 sc->sc_tx_timer = 5; 1356 ifp->if_timer = 1; 1357 } 1358} 1359 1360void 1361ipw_watchdog(struct ifnet *ifp) 1362{ 1363 struct ipw_softc *sc = ifp->if_softc; 1364 1365 ifp->if_timer = 0; 1366 1367 if (sc->sc_tx_timer > 0) { 1368 if (--sc->sc_tx_timer == 0) { 1369 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1370 ifp->if_flags &= ~IFF_UP; 1371 ipw_stop(ifp, 1); 1372 ifp->if_oerrors++; 1373 return; 1374 } 1375 ifp->if_timer = 1; 1376 } 1377 1378 ieee80211_watchdog(ifp); 1379} 1380 1381int 1382ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1383{ 1384 struct ipw_softc *sc = ifp->if_softc; 1385 struct ieee80211com *ic = &sc->sc_ic; 1386 struct ifaddr *ifa; 1387 struct ifreq *ifr; 1388 int s, error = 0; 1389 1390 s = splnet(); 1391 1392 switch (cmd) { 1393 case SIOCSIFADDR: 1394 ifa = (struct ifaddr *)data; 1395 ifp->if_flags |= IFF_UP; 1396#ifdef INET 1397 if (ifa->ifa_addr->sa_family == AF_INET) 1398 arp_ifinit(&ic->ic_ac, ifa); 1399#endif 1400 /* FALLTHROUGH */ 1401 case SIOCSIFFLAGS: 1402 if (ifp->if_flags & IFF_UP) { 1403 if (!(ifp->if_flags & IFF_RUNNING)) 1404 ipw_init(ifp); 1405 } else { 1406 if (ifp->if_flags & IFF_RUNNING) 1407 ipw_stop(ifp, 1); 1408 } 1409 break; 1410 1411 case SIOCADDMULTI: 1412 case SIOCDELMULTI: 1413 ifr = (struct ifreq *)data; 1414 error = (cmd == SIOCADDMULTI) ? 1415 ether_addmulti(ifr, &ic->ic_ac) : 1416 ether_delmulti(ifr, &ic->ic_ac); 1417 1418 if (error == ENETRESET) 1419 error = 0; 1420 break; 1421 1422 case SIOCG80211TXPOWER: 1423 /* 1424 * If the hardware radio transmitter switch is off, report a 1425 * tx power of IEEE80211_TXPOWER_MIN to indicate that radio 1426 * transmitter is killed. 1427 */ 1428 ((struct ieee80211_txpower *)data)->i_val = 1429 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 1430 IEEE80211_TXPOWER_MIN : sc->sc_ic.ic_txpower; 1431 break; 1432 1433 default: 1434 error = ieee80211_ioctl(ifp, cmd, data); 1435 } 1436 1437 if (error == ENETRESET) { 1438 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1439 (IFF_UP | IFF_RUNNING)) 1440 ipw_init(ifp); 1441 error = 0; 1442 } 1443 1444 splx(s); 1445 return error; 1446} 1447 1448uint32_t 1449ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1450{ 1451 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1452} 1453 1454void 1455ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1456{ 1457 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1458} 1459 1460int 1461ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1462{ 1463 uint32_t addr, info; 1464 uint16_t count, size; 1465 uint32_t total; 1466 1467 /* addr[4] + count[2] + size[2] */ 1468 addr = MEM_READ_4(sc, sc->table2_base + off); 1469 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1470 1471 count = info >> 16; 1472 size = info & 0xffff; 1473 total = count * size; 1474 1475 if (total > *len) { 1476 *len = total; 1477 return EINVAL; 1478 } 1479 *len = total; 1480 ipw_read_mem_1(sc, addr, buf, total); 1481 1482 return 0; 1483} 1484 1485void 1486ipw_stop_master(struct ipw_softc *sc) 1487{ 1488 uint32_t tmp; 1489 int ntries; 1490 1491 /* disable interrupts */ 1492 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1493 1494 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1495 for (ntries = 0; ntries < 50; ntries++) { 1496 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1497 break; 1498 DELAY(10); 1499 } 1500 if (ntries == 50) 1501 printf("%s: timeout waiting for master\n", 1502 sc->sc_dev.dv_xname); 1503 1504 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1505 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1506 1507 sc->flags &= ~IPW_FLAG_FW_INITED; 1508} 1509 1510int 1511ipw_reset(struct ipw_softc *sc) 1512{ 1513 uint32_t tmp; 1514 int ntries; 1515 1516 ipw_stop_master(sc); 1517 1518 /* move adapter to D0 state */ 1519 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1520 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1521 1522 /* wait for clock stabilization */ 1523 for (ntries = 0; ntries < 1000; ntries++) { 1524 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1525 break; 1526 DELAY(200); 1527 } 1528 if (ntries == 1000) 1529 return EIO; 1530 1531 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1532 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1533 1534 DELAY(10); 1535 1536 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1537 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1538 1539 return 0; 1540} 1541 1542int 1543ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1544{ 1545 int ntries; 1546 1547 /* voodoo from the Intel Linux driver */ 1548 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1549 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1550 1551 MEM_WRITE_2(sc, 0x220000, 0x0703); 1552 MEM_WRITE_2(sc, 0x220000, 0x0707); 1553 1554 MEM_WRITE_1(sc, 0x210014, 0x72); 1555 MEM_WRITE_1(sc, 0x210014, 0x72); 1556 1557 MEM_WRITE_1(sc, 0x210000, 0x40); 1558 MEM_WRITE_1(sc, 0x210000, 0x00); 1559 MEM_WRITE_1(sc, 0x210000, 0x40); 1560 1561 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1562 1563 MEM_WRITE_1(sc, 0x210000, 0x00); 1564 MEM_WRITE_1(sc, 0x210000, 0x00); 1565 MEM_WRITE_1(sc, 0x210000, 0x80); 1566 1567 MEM_WRITE_2(sc, 0x220000, 0x0703); 1568 MEM_WRITE_2(sc, 0x220000, 0x0707); 1569 1570 MEM_WRITE_1(sc, 0x210014, 0x72); 1571 MEM_WRITE_1(sc, 0x210014, 0x72); 1572 1573 MEM_WRITE_1(sc, 0x210000, 0x00); 1574 MEM_WRITE_1(sc, 0x210000, 0x80); 1575 1576 for (ntries = 0; ntries < 100; ntries++) { 1577 if (MEM_READ_1(sc, 0x210000) & 1) 1578 break; 1579 DELAY(1000); 1580 } 1581 if (ntries == 100) { 1582 printf("%s: timeout waiting for ucode to initialize\n", 1583 sc->sc_dev.dv_xname); 1584 return EIO; 1585 } 1586 1587 MEM_WRITE_4(sc, 0x3000e0, 0); 1588 1589 return 0; 1590} 1591 1592/* set of macros to handle unaligned little endian data in firmware image */ 1593#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1594#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1595int 1596ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1597{ 1598 u_char *p, *end; 1599 uint32_t tmp, dst; 1600 uint16_t len; 1601 int error; 1602 1603 p = fw; 1604 end = fw + size; 1605 while (p < end) { 1606 if (p + 6 > end) 1607 return EINVAL; 1608 1609 dst = GETLE32(p); p += 4; 1610 len = GETLE16(p); p += 2; 1611 1612 if (p + len > end) 1613 return EINVAL; 1614 1615 ipw_write_mem_1(sc, dst, p, len); 1616 p += len; 1617 } 1618 1619 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1620 IPW_IO_LED_OFF); 1621 1622 /* allow interrupts so we know when the firmware is inited */ 1623 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1624 1625 /* tell the adapter to initialize the firmware */ 1626 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1627 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1628 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1629 1630 /* wait at most one second for firmware initialization to complete */ 1631 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1632 printf("%s: timeout waiting for firmware initialization to " 1633 "complete\n", sc->sc_dev.dv_xname); 1634 return error; 1635 } 1636 1637 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1638 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1639 IPW_IO_GPIO3_MASK); 1640 1641 return 0; 1642} 1643 1644int 1645ipw_read_firmware(struct ipw_softc *sc, struct ipw_firmware *fw) 1646{ 1647 const struct ipw_firmware_hdr *hdr; 1648 const char *name; 1649 size_t size; 1650 int error; 1651 1652 switch (sc->sc_ic.ic_opmode) { 1653 case IEEE80211_M_STA: 1654 name = "ipw-bss"; 1655 break; 1656#ifndef IEEE80211_STA_ONLY 1657 case IEEE80211_M_IBSS: 1658 name = "ipw-ibss"; 1659 break; 1660#endif 1661 case IEEE80211_M_MONITOR: 1662 name = "ipw-monitor"; 1663 break; 1664 default: 1665 /* should not get there */ 1666 return ENODEV; 1667 } 1668 if ((error = loadfirmware(name, &fw->data, &size)) != 0) 1669 return error; 1670 1671 if (size < sizeof (*hdr)) { 1672 error = EINVAL; 1673 goto fail; 1674 } 1675 hdr = (const struct ipw_firmware_hdr *)fw->data; 1676 fw->main_size = letoh32(hdr->main_size); 1677 fw->ucode_size = letoh32(hdr->ucode_size); 1678 1679 if (size < sizeof (*hdr) + fw->main_size + fw->ucode_size) { 1680 error = EINVAL; 1681 goto fail; 1682 } 1683 fw->main = fw->data + sizeof (*hdr); 1684 fw->ucode = fw->main + fw->main_size; 1685 1686 return 0; 1687 1688fail: free(fw->data, M_DEVBUF); 1689 return error; 1690} 1691 1692void 1693ipw_scan(void *arg1, void *arg2) 1694{ 1695 struct ipw_softc *sc = arg1; 1696 struct ifnet *ifp = &sc->sc_ic.ic_if; 1697 struct ipw_scan_options scan; 1698 uint8_t ssid[IEEE80211_NWID_LEN]; 1699 int error; 1700 1701 /* 1702 * Firmware has a bug and does not honour the ``do not associate 1703 * after scan'' bit in the scan command. To prevent the firmware 1704 * from associating after the scan, we set the ESSID to something 1705 * unlikely to be used by a real AP. 1706 * XXX would setting the desired BSSID to a multicast address work? 1707 */ 1708 memset(ssid, '\r', sizeof ssid); 1709 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ssid, sizeof ssid); 1710 if (error != 0) 1711 goto fail; 1712 1713 /* no mandatory BSSID */ 1714 DPRINTF(("Setting mandatory BSSID to null\n")); 1715 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1716 if (error != 0) 1717 goto fail; 1718 1719 scan.flags = htole32(IPW_SCAN_DO_NOT_ASSOCIATE | IPW_SCAN_MIXED_CELL); 1720 scan.channels = htole32(0x3fff); /* scan channels 1-14 */ 1721 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1722 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1723 if (error != 0) 1724 goto fail; 1725 1726 /* start scanning */ 1727 DPRINTF(("Enabling adapter\n")); 1728 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1729 if (error != 0) 1730 goto fail; 1731 1732 return; 1733fail: 1734 printf("%s: scan request failed (error=%d)\n", sc->sc_dev.dv_xname, 1735 error); 1736 ieee80211_end_scan(ifp); 1737} 1738 1739void 1740ipw_auth_and_assoc(void *arg1, void *arg2) 1741{ 1742 struct ipw_softc *sc = arg1; 1743 struct ieee80211com *ic = &sc->sc_ic; 1744 struct ieee80211_node *ni = ic->ic_bss; 1745 struct ipw_scan_options scan; 1746 struct ipw_security security; 1747 struct ipw_assoc_req assoc; 1748 uint32_t data; 1749 uint8_t chan; 1750 int s, error; 1751 1752 DPRINTF(("Disabling adapter\n")); 1753 error = ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1754 if (error != 0) 1755 goto fail; 1756#if 1 1757 /* wait at most one second for card to be disabled */ 1758 s = splnet(); 1759 error = tsleep(sc, 0, "ipwdis", hz); 1760 splx(s); 1761 if (error != 0) { 1762 printf("%s: timeout waiting for disabled state\n", 1763 sc->sc_dev.dv_xname); 1764 goto fail; 1765 } 1766#else 1767 /* Intel's Linux driver polls for the DISABLED state instead.. */ 1768 for (ntries = 0; ntries < 1000; ntries++) { 1769 if (ipw_read_table1(sc, IPW_INFO_CARD_DISABLED) == 1) 1770 break; 1771 DELAY(10); 1772 } 1773 if (ntries == 1000) { 1774 printf("%s: timeout waiting for disabled state\n", 1775 sc->sc_dev.dv_xname); 1776 goto fail; 1777 } 1778#endif 1779 1780 bzero(&security, sizeof security); 1781 security.authmode = IPW_AUTH_OPEN; 1782 security.ciphers = htole32(IPW_CIPHER_NONE); 1783 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1784 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1785 sizeof security); 1786 if (error != 0) 1787 goto fail; 1788 1789#ifdef IPW_DEBUG 1790 if (ipw_debug > 0) { 1791 printf("Setting ESSID to "); 1792 ieee80211_print_essid(ni->ni_essid, ni->ni_esslen); 1793 printf("\n"); 1794 } 1795#endif 1796 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ni->ni_essid, ni->ni_esslen); 1797 if (error != 0) 1798 goto fail; 1799 1800 DPRINTF(("Setting BSSID to %s\n", ether_sprintf(ni->ni_bssid))); 1801 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, ni->ni_bssid, 1802 IEEE80211_ADDR_LEN); 1803 if (error != 0) 1804 goto fail; 1805 1806 data = htole32((ic->ic_flags & (IEEE80211_F_WEPON | 1807 IEEE80211_F_RSNON)) ? IPW_PRIVACYON : 0); 1808 DPRINTF(("Setting privacy flags to 0x%x\n", letoh32(data))); 1809 error = ipw_cmd(sc, IPW_CMD_SET_PRIVACY_FLAGS, &data, sizeof data); 1810 if (error != 0) 1811 goto fail; 1812 1813 /* let firmware set the capinfo, lintval, and bssid fixed fields */ 1814 bzero(&assoc, sizeof assoc); 1815 if (ic->ic_flags & IEEE80211_F_RSNON) { 1816 uint8_t *frm = assoc.optie; 1817 1818 /* tell firmware to add a WPA or RSN IE in (Re)Assoc req */ 1819 if (ni->ni_rsnprotos & IEEE80211_PROTO_RSN) 1820 frm = ieee80211_add_rsn(frm, ic, ni); 1821 else if (ni->ni_rsnprotos & IEEE80211_PROTO_WPA) 1822 frm = ieee80211_add_wpa(frm, ic, ni); 1823 assoc.optie_len = htole32(frm - assoc.optie); 1824 } 1825 DPRINTF(("Preparing assocation request (optional IE length=%d)\n", 1826 letoh32(assoc.optie_len))); 1827 error = ipw_cmd(sc, IPW_CMD_SET_ASSOC_REQ, &assoc, sizeof assoc); 1828 if (error != 0) 1829 goto fail; 1830 1831 scan.flags = htole32(IPW_SCAN_MIXED_CELL); 1832 chan = ieee80211_chan2ieee(ic, ni->ni_chan); 1833 scan.channels = htole32(1 << (chan - 1)); 1834 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1835 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1836 if (error != 0) 1837 goto fail; 1838 1839 /* trigger scan+association */ 1840 DPRINTF(("Enabling adapter\n")); 1841 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1842 if (error != 0) 1843 goto fail; 1844 1845 return; 1846fail: 1847 printf("%s: association failed (error=%d)\n", sc->sc_dev.dv_xname, 1848 error); 1849 ieee80211_begin_scan(&ic->ic_if); 1850} 1851 1852int 1853ipw_config(struct ipw_softc *sc) 1854{ 1855 struct ieee80211com *ic = &sc->sc_ic; 1856 struct ifnet *ifp = &ic->ic_if; 1857 struct ipw_configuration config; 1858 uint32_t data; 1859 int error; 1860 1861 switch (ic->ic_opmode) { 1862 case IEEE80211_M_STA: 1863 data = htole32(IPW_MODE_BSS); 1864 break; 1865#ifndef IEEE80211_STA_ONLY 1866 case IEEE80211_M_IBSS: 1867 data = htole32(IPW_MODE_IBSS); 1868 break; 1869#endif 1870 case IEEE80211_M_MONITOR: 1871 data = htole32(IPW_MODE_MONITOR); 1872 break; 1873 default: 1874 /* should not get there */ 1875 return ENODEV; 1876 } 1877 DPRINTF(("Setting mode to %u\n", letoh32(data))); 1878 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1879 if (error != 0) 1880 return error; 1881 1882 if ( 1883#ifndef IEEE80211_STA_ONLY 1884 ic->ic_opmode == IEEE80211_M_IBSS || 1885#endif 1886 ic->ic_opmode == IEEE80211_M_MONITOR) { 1887 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1888 DPRINTF(("Setting channel to %u\n", letoh32(data))); 1889 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1890 if (error != 0) 1891 return error; 1892 } 1893 1894 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1895 DPRINTF(("Enabling adapter\n")); 1896 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1897 } 1898 1899 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 1900 DPRINTF(("Setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 1901 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1902 IEEE80211_ADDR_LEN); 1903 if (error != 0) 1904 return error; 1905 1906 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1907 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1X_ENABLE); 1908#ifndef IEEE80211_STA_ONLY 1909 if (ic->ic_opmode == IEEE80211_M_IBSS) 1910 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1911#endif 1912 if (ifp->if_flags & IFF_PROMISC) 1913 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1914 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1915 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1916 DPRINTF(("Setting configuration 0x%x\n", config.flags)); 1917 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1918 if (error != 0) 1919 return error; 1920 1921 data = htole32(ic->ic_rtsthreshold); 1922 DPRINTF(("Setting RTS threshold to %u\n", letoh32(data))); 1923 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1924 if (error != 0) 1925 return error; 1926 1927 data = htole32(ic->ic_fragthreshold); 1928 DPRINTF(("Setting frag threshold to %u\n", letoh32(data))); 1929 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1930 if (error != 0) 1931 return error; 1932 1933 data = htole32(0x3); /* 1, 2 */ 1934 DPRINTF(("Setting basic tx rates to 0x%x\n", letoh32(data))); 1935 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1936 if (error != 0) 1937 return error; 1938 1939 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1940 DPRINTF(("Setting tx rates to 0x%x\n", letoh32(data))); 1941 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1942 if (error != 0) 1943 return error; 1944 1945 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1946 DPRINTF(("Setting MSDU tx rates to 0x%x\n", letoh32(data))); 1947 error = ipw_cmd(sc, IPW_CMD_SET_MSDU_TX_RATES, &data, sizeof data); 1948 if (error != 0) 1949 return error; 1950 1951 data = htole32(IPW_POWER_MODE_CAM); 1952 DPRINTF(("Setting power mode to %u\n", letoh32(data))); 1953 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1954 if (error != 0) 1955 return error; 1956 1957#ifndef IEEE80211_STA_ONLY 1958 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1959 data = htole32(32); /* default value */ 1960 DPRINTF(("Setting tx power index to %u\n", letoh32(data))); 1961 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1962 sizeof data); 1963 if (error != 0) 1964 return error; 1965 1966 data = htole32(ic->ic_lintval); 1967 DPRINTF(("Setting beacon interval to %u\n", letoh32(data))); 1968 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1969 sizeof data); 1970 if (error != 0) 1971 return error; 1972 } 1973#endif 1974 return 0; 1975} 1976 1977int 1978ipw_init(struct ifnet *ifp) 1979{ 1980 struct ipw_softc *sc = ifp->if_softc; 1981 struct ieee80211com *ic = &sc->sc_ic; 1982 struct ipw_firmware fw; 1983 int error; 1984 1985 ipw_stop(ifp, 0); 1986 1987 if ((error = ipw_reset(sc)) != 0) { 1988 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 1989 goto fail1; 1990 } 1991 1992 if ((error = ipw_read_firmware(sc, &fw)) != NULL) { 1993 printf("%s: error %d, could not read firmware\n", 1994 sc->sc_dev.dv_xname, error); 1995 goto fail1; 1996 } 1997 if ((error = ipw_load_ucode(sc, fw.ucode, fw.ucode_size)) != 0) { 1998 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 1999 goto fail2; 2000 } 2001 2002 ipw_stop_master(sc); 2003 2004 /* 2005 * Setup tx, rx and status rings. 2006 */ 2007 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2008 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 2009 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 2010 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 2011 sc->txold = IPW_NTBD - 1; /* latest bd index ack by firmware */ 2012 sc->txcur = 0; /* bd index to write to */ 2013 sc->txfree = IPW_NTBD - 2; 2014 2015 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2016 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 2017 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 2018 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 2019 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 2020 2021 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 2022 sc->status_map->dm_segs[0].ds_addr); 2023 2024 if ((error = ipw_load_firmware(sc, fw.main, fw.main_size)) != 0) { 2025 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 2026 goto fail2; 2027 } 2028 sc->flags |= IPW_FLAG_FW_INITED; 2029 free(fw.data, M_DEVBUF); 2030 2031 /* retrieve information tables base addresses */ 2032 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2033 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2034 2035 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2036 2037 if ((error = ipw_config(sc)) != 0) { 2038 printf("%s: device configuration failed\n", 2039 sc->sc_dev.dv_xname); 2040 goto fail2; 2041 } 2042 2043 ifp->if_flags &= ~IFF_OACTIVE; 2044 ifp->if_flags |= IFF_RUNNING; 2045 2046 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2047 ieee80211_begin_scan(ifp); 2048 else 2049 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2050 2051 return 0; 2052 2053fail2: free(fw.data, M_DEVBUF); 2054fail1: ipw_stop(ifp, 0); 2055 return error; 2056} 2057 2058void 2059ipw_stop(struct ifnet *ifp, int disable) 2060{ 2061 struct ipw_softc *sc = ifp->if_softc; 2062 struct ieee80211com *ic = &sc->sc_ic; 2063 int i; 2064 2065 ipw_stop_master(sc); 2066 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2067 2068 ifp->if_timer = 0; 2069 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2070 2071 /* 2072 * Release tx buffers. 2073 */ 2074 for (i = 0; i < IPW_NTBD; i++) 2075 ipw_release_sbd(sc, &sc->stbd_list[i]); 2076 2077 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2078} 2079 2080void 2081ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2082 bus_size_t count) 2083{ 2084 for (; count > 0; offset++, datap++, count--) { 2085 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2086 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2087 } 2088} 2089 2090void 2091ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2092 bus_size_t count) 2093{ 2094 for (; count > 0; offset++, datap++, count--) { 2095 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2096 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2097 } 2098} 2099 2100struct cfdriver ipw_cd = { 2101 NULL, "ipw", DV_IFNET 2102}; 2103