if_ipw.c revision 1.69
1/* $OpenBSD: if_ipw.c,v 1.69 2007/09/07 19:05:05 damien Exp $ */ 2 3/*- 4 * Copyright (c) 2004-2006 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* 31 * Driver for Intel PRO/Wireless 2100 802.11 network adapters. 32 */ 33 34#include "bpfilter.h" 35 36#include <sys/param.h> 37#include <sys/sockio.h> 38#include <sys/sysctl.h> 39#include <sys/mbuf.h> 40#include <sys/kernel.h> 41#include <sys/socket.h> 42#include <sys/systm.h> 43#include <sys/conf.h> 44#include <sys/device.h> 45 46#include <machine/bus.h> 47#include <machine/endian.h> 48#include <machine/intr.h> 49 50#include <dev/pci/pcireg.h> 51#include <dev/pci/pcivar.h> 52#include <dev/pci/pcidevs.h> 53 54#if NBPFILTER > 0 55#include <net/bpf.h> 56#endif 57#include <net/if.h> 58#include <net/if_arp.h> 59#include <net/if_dl.h> 60#include <net/if_media.h> 61#include <net/if_types.h> 62 63#include <netinet/in.h> 64#include <netinet/in_systm.h> 65#include <netinet/in_var.h> 66#include <netinet/if_ether.h> 67#include <netinet/ip.h> 68 69#include <net80211/ieee80211_var.h> 70#include <net80211/ieee80211_radiotap.h> 71 72#include <dev/pci/if_ipwreg.h> 73#include <dev/pci/if_ipwvar.h> 74 75int ipw_match(struct device *, void *, void *); 76void ipw_attach(struct device *, struct device *, void *); 77void ipw_power(int, void *); 78int ipw_dma_alloc(struct ipw_softc *); 79void ipw_release(struct ipw_softc *); 80int ipw_media_change(struct ifnet *); 81void ipw_media_status(struct ifnet *, struct ifmediareq *); 82int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 83uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 84void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 85void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 86void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 87 struct ipw_soft_bd *, struct ipw_soft_buf *); 88void ipw_notification_intr(struct ipw_softc *, 89 struct ipw_soft_buf *); 90void ipw_rx_intr(struct ipw_softc *); 91void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 92void ipw_tx_intr(struct ipw_softc *); 93int ipw_intr(void *); 94int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 95int ipw_tx_start(struct ifnet *, struct mbuf *, 96 struct ieee80211_node *); 97void ipw_start(struct ifnet *); 98void ipw_watchdog(struct ifnet *); 99int ipw_ioctl(struct ifnet *, u_long, caddr_t); 100uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 101void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 102int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 103 uint32_t *); 104void ipw_stop_master(struct ipw_softc *); 105int ipw_reset(struct ipw_softc *); 106int ipw_load_ucode(struct ipw_softc *, u_char *, int); 107int ipw_load_firmware(struct ipw_softc *, u_char *, int); 108int ipw_read_firmware(struct ipw_softc *, struct ipw_firmware *); 109int ipw_config(struct ipw_softc *); 110int ipw_init(struct ifnet *); 111void ipw_stop(struct ifnet *, int); 112void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 113 bus_size_t); 114void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 115 bus_size_t); 116 117static __inline uint8_t 118MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 119{ 120 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 121 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 122} 123 124static __inline uint32_t 125MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 126{ 127 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 128 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 129} 130 131#ifdef IPW_DEBUG 132#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 133#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 134int ipw_debug = 0; 135#else 136#define DPRINTF(x) 137#define DPRINTFN(n, x) 138#endif 139 140struct cfattach ipw_ca = { 141 sizeof (struct ipw_softc), ipw_match, ipw_attach 142}; 143 144int 145ipw_match(struct device *parent, void *match, void *aux) 146{ 147 struct pci_attach_args *pa = aux; 148 149 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 150 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 151 return 1; 152 153 return 0; 154} 155 156/* Base Address Register */ 157#define IPW_PCI_BAR0 0x10 158 159void 160ipw_attach(struct device *parent, struct device *self, void *aux) 161{ 162 struct ipw_softc *sc = (struct ipw_softc *)self; 163 struct ieee80211com *ic = &sc->sc_ic; 164 struct ifnet *ifp = &ic->ic_if; 165 struct pci_attach_args *pa = aux; 166 const char *intrstr; 167 bus_space_tag_t memt; 168 bus_space_handle_t memh; 169 bus_addr_t base; 170 pci_intr_handle_t ih; 171 pcireg_t data; 172 uint16_t val; 173 int error, i; 174 175 sc->sc_pct = pa->pa_pc; 176 sc->sc_pcitag = pa->pa_tag, 177 178 /* clear device specific PCI configuration register 0x41 */ 179 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 180 data &= ~0x0000ff00; 181 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 182 183 /* map the register window */ 184 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 185 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 186 if (error != 0) { 187 printf(": could not map memory space\n"); 188 return; 189 } 190 191 sc->sc_st = memt; 192 sc->sc_sh = memh; 193 sc->sc_dmat = pa->pa_dmat; 194 195 /* disable interrupts */ 196 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 197 198 if (pci_intr_map(pa, &ih) != 0) { 199 printf(": could not map interrupt\n"); 200 return; 201 } 202 203 intrstr = pci_intr_string(sc->sc_pct, ih); 204 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 205 sc->sc_dev.dv_xname); 206 if (sc->sc_ih == NULL) { 207 printf(": could not establish interrupt"); 208 if (intrstr != NULL) 209 printf(" at %s", intrstr); 210 printf("\n"); 211 return; 212 } 213 printf(": %s", intrstr); 214 215 if (ipw_reset(sc) != 0) { 216 printf(": could not reset adapter\n"); 217 return; 218 } 219 220 if (ipw_dma_alloc(sc) != 0) { 221 printf(": failed to allocate DMA resources\n"); 222 return; 223 } 224 225 ic->ic_phytype = IEEE80211_T_DS; 226 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 227 ic->ic_state = IEEE80211_S_INIT; 228 229 /* set device capabilities */ 230 ic->ic_caps = 231 IEEE80211_C_IBSS | /* IBSS mode supported */ 232 IEEE80211_C_MONITOR | /* monitor mode supported */ 233 IEEE80211_C_TXPMGT | /* tx power management */ 234 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 235 IEEE80211_C_WEP | /* s/w WEP */ 236 IEEE80211_C_SCANALL; /* h/w scanning */ 237 238 /* read MAC address from EEPROM */ 239 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 240 ic->ic_myaddr[0] = val >> 8; 241 ic->ic_myaddr[1] = val & 0xff; 242 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 243 ic->ic_myaddr[2] = val >> 8; 244 ic->ic_myaddr[3] = val & 0xff; 245 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 246 ic->ic_myaddr[4] = val >> 8; 247 ic->ic_myaddr[5] = val & 0xff; 248 249 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 250 251 /* set supported .11b rates */ 252 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 253 254 /* set supported .11b channels (1 through 14) */ 255 for (i = 1; i <= 14; i++) { 256 ic->ic_channels[i].ic_freq = 257 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 258 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 259 } 260 261 /* IBSS channel undefined for now */ 262 ic->ic_ibss_chan = &ic->ic_channels[0]; 263 264 ifp->if_softc = sc; 265 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 266 ifp->if_init = ipw_init; 267 ifp->if_ioctl = ipw_ioctl; 268 ifp->if_start = ipw_start; 269 ifp->if_watchdog = ipw_watchdog; 270 IFQ_SET_READY(&ifp->if_snd); 271 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 272 273 if_attach(ifp); 274 ieee80211_ifattach(ifp); 275 /* override state transition machine */ 276 sc->sc_newstate = ic->ic_newstate; 277 ic->ic_newstate = ipw_newstate; 278 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 279 280 sc->powerhook = powerhook_establish(ipw_power, sc); 281 282#if NBPFILTER > 0 283 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 284 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 285 286 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 287 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 288 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 289 290 sc->sc_txtap_len = sizeof sc->sc_txtapu; 291 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 292 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 293#endif 294} 295 296void 297ipw_power(int why, void *arg) 298{ 299 struct ipw_softc *sc = arg; 300 struct ifnet *ifp; 301 pcireg_t data; 302 303 if (why != PWR_RESUME) 304 return; 305 306 /* clear device specific PCI configuration register 0x41 */ 307 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 308 data &= ~0x0000ff00; 309 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 310 311 ifp = &sc->sc_ic.ic_if; 312 if (ifp->if_flags & IFF_UP) { 313 ifp->if_init(ifp); 314 if (ifp->if_flags & IFF_RUNNING) 315 ifp->if_start(ifp); 316 } 317} 318 319int 320ipw_dma_alloc(struct ipw_softc *sc) 321{ 322 struct ipw_soft_bd *sbd; 323 struct ipw_soft_hdr *shdr; 324 struct ipw_soft_buf *sbuf; 325 int i, nsegs, error; 326 327 /* 328 * Allocate and map tx ring. 329 */ 330 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 331 BUS_DMA_NOWAIT, &sc->tbd_map); 332 if (error != 0) { 333 printf("%s: could not create tx ring DMA map\n", 334 sc->sc_dev.dv_xname); 335 goto fail; 336 } 337 338 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 339 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 340 if (error != 0) { 341 printf("%s: could not allocate tx ring DMA memory\n", 342 sc->sc_dev.dv_xname); 343 goto fail; 344 } 345 346 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 347 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 348 if (error != 0) { 349 printf("%s: could not map tx ring DMA memory\n", 350 sc->sc_dev.dv_xname); 351 goto fail; 352 } 353 354 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 355 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 356 if (error != 0) { 357 printf("%s: could not load tx ring DMA map\n", 358 sc->sc_dev.dv_xname); 359 goto fail; 360 } 361 362 /* 363 * Allocate and map rx ring. 364 */ 365 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 366 BUS_DMA_NOWAIT, &sc->rbd_map); 367 if (error != 0) { 368 printf("%s: could not create rx ring DMA map\n", 369 sc->sc_dev.dv_xname); 370 goto fail; 371 } 372 373 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 374 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 375 if (error != 0) { 376 printf("%s: could not allocate rx ring DMA memory\n", 377 sc->sc_dev.dv_xname); 378 goto fail; 379 } 380 381 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 382 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 383 if (error != 0) { 384 printf("%s: could not map rx ring DMA memory\n", 385 sc->sc_dev.dv_xname); 386 goto fail; 387 } 388 389 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 390 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 391 if (error != 0) { 392 printf("%s: could not load tx ring DMA map\n", 393 sc->sc_dev.dv_xname); 394 goto fail; 395 } 396 397 /* 398 * Allocate and map status ring. 399 */ 400 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 401 0, BUS_DMA_NOWAIT, &sc->status_map); 402 if (error != 0) { 403 printf("%s: could not create status ring DMA map\n", 404 sc->sc_dev.dv_xname); 405 goto fail; 406 } 407 408 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 409 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 410 if (error != 0) { 411 printf("%s: could not allocate status ring DMA memory\n", 412 sc->sc_dev.dv_xname); 413 goto fail; 414 } 415 416 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 417 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 418 if (error != 0) { 419 printf("%s: could not map status ring DMA memory\n", 420 sc->sc_dev.dv_xname); 421 goto fail; 422 } 423 424 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 425 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 426 if (error != 0) { 427 printf("%s: could not load status ring DMA map\n", 428 sc->sc_dev.dv_xname); 429 goto fail; 430 } 431 432 /* 433 * Allocate command DMA map. 434 */ 435 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 436 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 437 if (error != 0) { 438 printf("%s: could not create command DMA map\n", 439 sc->sc_dev.dv_xname); 440 goto fail; 441 } 442 443 /* 444 * Allocate headers DMA maps. 445 */ 446 SLIST_INIT(&sc->free_shdr); 447 for (i = 0; i < IPW_NDATA; i++) { 448 shdr = &sc->shdr_list[i]; 449 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_hdr), 450 1, sizeof (struct ipw_hdr), 0, BUS_DMA_NOWAIT, &shdr->map); 451 if (error != 0) { 452 printf("%s: could not create header DMA map\n", 453 sc->sc_dev.dv_xname); 454 goto fail; 455 } 456 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 457 } 458 459 /* 460 * Allocate tx buffers DMA maps. 461 */ 462 SLIST_INIT(&sc->free_sbuf); 463 for (i = 0; i < IPW_NDATA; i++) { 464 sbuf = &sc->tx_sbuf_list[i]; 465 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, IPW_MAX_NSEG, 466 MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 467 if (error != 0) { 468 printf("%s: could not create tx DMA map\n", 469 sc->sc_dev.dv_xname); 470 goto fail; 471 } 472 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 473 } 474 475 /* 476 * Initialize tx ring. 477 */ 478 for (i = 0; i < IPW_NTBD; i++) { 479 sbd = &sc->stbd_list[i]; 480 sbd->bd = &sc->tbd_list[i]; 481 sbd->type = IPW_SBD_TYPE_NOASSOC; 482 } 483 484 /* 485 * Pre-allocate rx buffers and DMA maps. 486 */ 487 for (i = 0; i < IPW_NRBD; i++) { 488 sbd = &sc->srbd_list[i]; 489 sbuf = &sc->rx_sbuf_list[i]; 490 sbd->bd = &sc->rbd_list[i]; 491 492 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 493 if (sbuf->m == NULL) { 494 printf("%s: could not allocate rx mbuf\n", 495 sc->sc_dev.dv_xname); 496 error = ENOMEM; 497 goto fail; 498 } 499 500 MCLGET(sbuf->m, M_DONTWAIT); 501 if (!(sbuf->m->m_flags & M_EXT)) { 502 m_freem(sbuf->m); 503 printf("%s: could not allocate rx mbuf cluster\n", 504 sc->sc_dev.dv_xname); 505 error = ENOMEM; 506 goto fail; 507 } 508 509 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 510 0, BUS_DMA_NOWAIT, &sbuf->map); 511 if (error != 0) { 512 printf("%s: could not create rx DMA map\n", 513 sc->sc_dev.dv_xname); 514 goto fail; 515 } 516 517 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 518 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 519 if (error != 0) { 520 printf("%s: could not map rx DMA memory\n", 521 sc->sc_dev.dv_xname); 522 goto fail; 523 } 524 525 sbd->type = IPW_SBD_TYPE_DATA; 526 sbd->priv = sbuf; 527 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 528 sbd->bd->len = htole32(MCLBYTES); 529 } 530 531 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 532 BUS_DMASYNC_PREWRITE); 533 534 return 0; 535 536fail: ipw_release(sc); 537 return error; 538} 539 540void 541ipw_release(struct ipw_softc *sc) 542{ 543 struct ipw_soft_buf *sbuf; 544 int i; 545 546 if (sc->tbd_map != NULL) { 547 if (sc->tbd_list != NULL) { 548 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 549 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 550 IPW_TBD_SZ); 551 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 552 } 553 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 554 } 555 556 if (sc->rbd_map != NULL) { 557 if (sc->rbd_list != NULL) { 558 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 559 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 560 IPW_RBD_SZ); 561 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 562 } 563 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 564 } 565 566 if (sc->status_map != NULL) { 567 if (sc->status_list != NULL) { 568 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 569 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 570 IPW_RBD_SZ); 571 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 572 } 573 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 574 } 575 576 if (sc->cmd_map != NULL) 577 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 578 579 for (i = 0; i < IPW_NDATA; i++) 580 bus_dmamap_destroy(sc->sc_dmat, sc->shdr_list[i].map); 581 582 for (i = 0; i < IPW_NDATA; i++) 583 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 584 585 for (i = 0; i < IPW_NRBD; i++) { 586 sbuf = &sc->rx_sbuf_list[i]; 587 if (sbuf->map != NULL) { 588 if (sbuf->m != NULL) { 589 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 590 m_freem(sbuf->m); 591 } 592 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 593 } 594 } 595} 596 597int 598ipw_media_change(struct ifnet *ifp) 599{ 600 int error; 601 602 error = ieee80211_media_change(ifp); 603 if (error != ENETRESET) 604 return error; 605 606 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 607 ipw_init(ifp); 608 609 return 0; 610} 611 612void 613ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 614{ 615#define N(a) (sizeof (a) / sizeof (a[0])) 616 struct ipw_softc *sc = ifp->if_softc; 617 struct ieee80211com *ic = &sc->sc_ic; 618 static const struct { 619 uint32_t val; 620 int rate; 621 } rates[] = { 622 { IPW_RATE_DS1, 2 }, 623 { IPW_RATE_DS2, 4 }, 624 { IPW_RATE_DS5, 11 }, 625 { IPW_RATE_DS11, 22 }, 626 }; 627 uint32_t val; 628 int rate, i; 629 630 imr->ifm_status = IFM_AVALID; 631 imr->ifm_active = IFM_IEEE80211; 632 if (ic->ic_state == IEEE80211_S_RUN) 633 imr->ifm_status |= IFM_ACTIVE; 634 635 /* read current transmission rate from adapter */ 636 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 637 val &= 0xf; 638 639 /* convert rate to 802.11 rate */ 640 for (i = 0; i < N(rates) && rates[i].val != val; i++); 641 rate = (i < N(rates)) ? rates[i].rate : 0; 642 643 imr->ifm_active |= IFM_IEEE80211_11B; 644 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 645 switch (ic->ic_opmode) { 646 case IEEE80211_M_STA: 647 break; 648 649 case IEEE80211_M_IBSS: 650 imr->ifm_active |= IFM_IEEE80211_IBSS; 651 break; 652 653 case IEEE80211_M_MONITOR: 654 imr->ifm_active |= IFM_IEEE80211_MONITOR; 655 break; 656 657 case IEEE80211_M_AHDEMO: 658 case IEEE80211_M_HOSTAP: 659 /* should not get there */ 660 break; 661 } 662#undef N 663} 664 665int 666ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 667{ 668 struct ipw_softc *sc = ic->ic_softc; 669 struct ieee80211_node *ni; 670 uint8_t macaddr[IEEE80211_ADDR_LEN]; 671 uint32_t len; 672 673 switch (nstate) { 674 case IEEE80211_S_RUN: 675 DELAY(100); /* firmware needs a short delay here */ 676 677 len = IEEE80211_ADDR_LEN; 678 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 679 680 ni = ieee80211_find_node(ic, macaddr); 681 if (ni == NULL) 682 break; 683 684 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 685 ieee80211_node_newstate(ni, IEEE80211_STA_BSS); 686 break; 687 688 case IEEE80211_S_INIT: 689 case IEEE80211_S_SCAN: 690 case IEEE80211_S_AUTH: 691 case IEEE80211_S_ASSOC: 692 break; 693 } 694 695 ic->ic_state = nstate; 696 return 0; 697} 698 699/* 700 * Read 16 bits at address 'addr' from the Microwire EEPROM. 701 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 702 */ 703uint16_t 704ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 705{ 706 uint32_t tmp; 707 uint16_t val; 708 int n; 709 710 /* clock C once before the first command */ 711 IPW_EEPROM_CTL(sc, 0); 712 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 713 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 714 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 715 716 /* write start bit (1) */ 717 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 718 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 719 720 /* write READ opcode (10) */ 721 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 722 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 723 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 724 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 725 726 /* write address A7-A0 */ 727 for (n = 7; n >= 0; n--) { 728 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 729 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 730 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 731 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 732 } 733 734 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 735 736 /* read data Q15-Q0 */ 737 val = 0; 738 for (n = 15; n >= 0; n--) { 739 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 740 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 741 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 742 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 743 } 744 745 IPW_EEPROM_CTL(sc, 0); 746 747 /* clear Chip Select and clock C */ 748 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 749 IPW_EEPROM_CTL(sc, 0); 750 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 751 752 return val; 753} 754 755void 756ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 757{ 758 struct ipw_cmd *cmd; 759 760 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 761 BUS_DMASYNC_POSTREAD); 762 763 cmd = mtod(sbuf->m, struct ipw_cmd *); 764 765 DPRINTFN(2, ("RX!CMD!%u!%u!%u!%u!%u\n", 766 letoh32(cmd->type), letoh32(cmd->subtype), letoh32(cmd->seq), 767 letoh32(cmd->len), letoh32(cmd->status))); 768 769 wakeup(sc); 770} 771 772void 773ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 774{ 775 struct ieee80211com *ic = &sc->sc_ic; 776 struct ifnet *ifp = &ic->ic_if; 777 uint32_t state; 778 779 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 780 BUS_DMASYNC_POSTREAD); 781 782 state = letoh32(*mtod(sbuf->m, uint32_t *)); 783 784 DPRINTFN(2, ("RX!NEWSTATE!%u\n", state)); 785 786 switch (state) { 787 case IPW_STATE_ASSOCIATED: 788 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 789 break; 790 791 case IPW_STATE_SCANNING: 792 /* don't leave run state on background scan */ 793 if (ic->ic_state != IEEE80211_S_RUN) 794 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 795 796 ic->ic_flags |= IEEE80211_F_ASCAN; 797 break; 798 799 case IPW_STATE_SCAN_COMPLETE: 800 ic->ic_flags &= ~IEEE80211_F_ASCAN; 801 break; 802 803 case IPW_STATE_ASSOCIATION_LOST: 804 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 805 break; 806 807 case IPW_STATE_RADIO_DISABLED: 808 ifp->if_flags &= ~IFF_UP; 809 ipw_stop(&ic->ic_if, 1); 810 break; 811 } 812} 813 814void 815ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 816 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 817{ 818 struct ieee80211com *ic = &sc->sc_ic; 819 struct ifnet *ifp = &ic->ic_if; 820 struct mbuf *mnew, *m; 821 struct ieee80211_frame *wh; 822 struct ieee80211_node *ni; 823 int error; 824 825 DPRINTFN(5, ("RX!DATA!%u!%u\n", letoh32(status->len), status->rssi)); 826 827 /* 828 * Try to allocate a new mbuf for this ring element and load it before 829 * processing the current mbuf. If the ring element cannot be loaded, 830 * drop the received packet and reuse the old mbuf. In the unlikely 831 * case that the old mbuf can't be reloaded either, explicitly panic. 832 */ 833 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 834 if (mnew == NULL) { 835 ifp->if_ierrors++; 836 return; 837 } 838 839 MCLGET(mnew, M_DONTWAIT); 840 if (!(mnew->m_flags & M_EXT)) { 841 m_freem(mnew); 842 ifp->if_ierrors++; 843 return; 844 } 845 846 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 847 BUS_DMASYNC_POSTREAD); 848 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 849 850 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(mnew, void *), 851 MCLBYTES, NULL, BUS_DMA_NOWAIT); 852 if (error != 0) { 853 m_freem(mnew); 854 855 /* try to reload the old mbuf */ 856 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 857 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 858 if (error != 0) { 859 /* very unlikely that it will fail... */ 860 panic("%s: could not load old rx mbuf", 861 sc->sc_dev.dv_xname); 862 } 863 ifp->if_ierrors++; 864 return; 865 } 866 867 m = sbuf->m; 868 sbuf->m = mnew; 869 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 870 871 /* finalize mbuf */ 872 m->m_pkthdr.rcvif = ifp; 873 m->m_pkthdr.len = m->m_len = letoh32(status->len); 874 875#if NBPFILTER > 0 876 if (sc->sc_drvbpf != NULL) { 877 struct mbuf mb; 878 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 879 880 tap->wr_flags = 0; 881 tap->wr_antsignal = status->rssi; 882 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 883 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 884 885 mb.m_data = (caddr_t)tap; 886 mb.m_len = sc->sc_rxtap_len; 887 mb.m_next = m; 888 mb.m_nextpkt = NULL; 889 mb.m_type = 0; 890 mb.m_flags = 0; 891 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 892 } 893#endif 894 895 wh = mtod(m, struct ieee80211_frame *); 896 897 ni = ieee80211_find_rxnode(ic, wh); 898 899 /* send the frame to the upper layer */ 900 ieee80211_input(ifp, m, ni, status->rssi, 0); 901 902 ieee80211_release_node(ic, ni); 903} 904 905void 906ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 907{ 908 DPRINTFN(2, ("RX!NOTIFICATION\n")); 909} 910 911void 912ipw_rx_intr(struct ipw_softc *sc) 913{ 914 struct ipw_status *status; 915 struct ipw_soft_bd *sbd; 916 struct ipw_soft_buf *sbuf; 917 uint32_t r, i; 918 919 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 920 921 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 922 923 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 924 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 925 BUS_DMASYNC_POSTREAD); 926 927 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 928 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 929 BUS_DMASYNC_POSTREAD); 930 931 status = &sc->status_list[i]; 932 sbd = &sc->srbd_list[i]; 933 sbuf = sbd->priv; 934 935 switch (letoh16(status->code) & 0xf) { 936 case IPW_STATUS_CODE_COMMAND: 937 ipw_command_intr(sc, sbuf); 938 break; 939 940 case IPW_STATUS_CODE_NEWSTATE: 941 ipw_newstate_intr(sc, sbuf); 942 break; 943 944 case IPW_STATUS_CODE_DATA_802_3: 945 case IPW_STATUS_CODE_DATA_802_11: 946 ipw_data_intr(sc, status, sbd, sbuf); 947 break; 948 949 case IPW_STATUS_CODE_NOTIFICATION: 950 ipw_notification_intr(sc, sbuf); 951 break; 952 953 default: 954 printf("%s: unknown status code %u\n", 955 sc->sc_dev.dv_xname, letoh16(status->code)); 956 } 957 sbd->bd->flags = 0; 958 959 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 960 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 961 BUS_DMASYNC_PREWRITE); 962 } 963 964 /* tell the firmware what we have processed */ 965 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 966 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 967} 968 969void 970ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 971{ 972 struct ieee80211com *ic = &sc->sc_ic; 973 struct ipw_soft_hdr *shdr; 974 struct ipw_soft_buf *sbuf; 975 976 switch (sbd->type) { 977 case IPW_SBD_TYPE_COMMAND: 978 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 979 break; 980 981 case IPW_SBD_TYPE_HEADER: 982 shdr = sbd->priv; 983 bus_dmamap_unload(sc->sc_dmat, shdr->map); 984 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 985 break; 986 987 case IPW_SBD_TYPE_DATA: 988 sbuf = sbd->priv; 989 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 990 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 991 992 m_freem(sbuf->m); 993 994 if (sbuf->ni != NULL) 995 ieee80211_release_node(ic, sbuf->ni); 996 997 /* kill watchdog timer */ 998 sc->sc_tx_timer = 0; 999 break; 1000 } 1001 sbd->type = IPW_SBD_TYPE_NOASSOC; 1002} 1003 1004void 1005ipw_tx_intr(struct ipw_softc *sc) 1006{ 1007 struct ifnet *ifp = &sc->sc_ic.ic_if; 1008 struct ipw_soft_bd *sbd; 1009 uint32_t r, i; 1010 1011 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 1012 1013 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1014 sbd = &sc->stbd_list[i]; 1015 1016 if (sbd->type == IPW_SBD_TYPE_DATA) 1017 ifp->if_opackets++; 1018 1019 ipw_release_sbd(sc, sbd); 1020 sc->txfree++; 1021 } 1022 1023 /* remember what the firmware has processed */ 1024 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1025 1026 /* call start() since some buffer descriptors have been released */ 1027 ifp->if_flags &= ~IFF_OACTIVE; 1028 (*ifp->if_start)(ifp); 1029} 1030 1031int 1032ipw_intr(void *arg) 1033{ 1034 struct ipw_softc *sc = arg; 1035 struct ifnet *ifp = &sc->sc_ic.ic_if; 1036 uint32_t r; 1037 1038 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) 1039 return 0; 1040 1041 /* disable interrupts */ 1042 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1043 1044 DPRINTFN(8, ("INTR!0x%08x\n", r)); 1045 1046 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1047 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 1048 ifp->if_flags &= ~IFF_UP; 1049 ipw_stop(ifp, 1); 1050 return 1; 1051 } 1052 1053 if (r & IPW_INTR_FW_INIT_DONE) 1054 wakeup(sc); 1055 1056 if (r & IPW_INTR_RX_TRANSFER) 1057 ipw_rx_intr(sc); 1058 1059 if (r & IPW_INTR_TX_TRANSFER) 1060 ipw_tx_intr(sc); 1061 1062 /* acknowledge interrupts */ 1063 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1064 1065 /* re-enable interrupts */ 1066 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1067 1068 return 1; 1069} 1070 1071int 1072ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1073{ 1074 struct ipw_soft_bd *sbd; 1075 int error; 1076 1077 sbd = &sc->stbd_list[sc->txcur]; 1078 1079 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 1080 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 1081 if (error != 0) { 1082 printf("%s: could not map command DMA memory\n", 1083 sc->sc_dev.dv_xname); 1084 return error; 1085 } 1086 1087 sc->cmd.type = htole32(type); 1088 sc->cmd.subtype = htole32(0); 1089 sc->cmd.len = htole32(len); 1090 sc->cmd.seq = htole32(0); 1091 if (data != NULL) 1092 bcopy(data, sc->cmd.data, len); 1093 1094 sbd->type = IPW_SBD_TYPE_COMMAND; 1095 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1096 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1097 sbd->bd->nfrag = 1; 1098 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1099 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1100 1101 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1102 BUS_DMASYNC_PREWRITE); 1103 1104 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1105 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1106 BUS_DMASYNC_PREWRITE); 1107 1108 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1109 sc->txfree--; 1110 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1111 1112 DPRINTFN(2, ("TX!CMD!%u!%u!%u!%u\n", type, 0, 0, len)); 1113 1114 /* wait at most one second for command to complete */ 1115 return tsleep(sc, 0, "ipwcmd", hz); 1116} 1117 1118int 1119ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 1120{ 1121 struct ipw_softc *sc = ifp->if_softc; 1122 struct ieee80211com *ic = &sc->sc_ic; 1123 struct ieee80211_frame *wh; 1124 struct ipw_soft_bd *sbd; 1125 struct ipw_soft_hdr *shdr; 1126 struct ipw_soft_buf *sbuf; 1127 struct mbuf *mnew; 1128 int error, i; 1129 1130 wh = mtod(m, struct ieee80211_frame *); 1131 1132 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1133 m = ieee80211_wep_crypt(ifp, m, 1); 1134 if (m == NULL) 1135 return ENOBUFS; 1136 1137 /* packet header may have moved, reset our local pointer */ 1138 wh = mtod(m, struct ieee80211_frame *); 1139 } 1140 1141#if NBPFILTER > 0 1142 if (sc->sc_drvbpf != NULL) { 1143 struct mbuf mb; 1144 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1145 1146 tap->wt_flags = 0; 1147 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1148 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1149 1150 mb.m_data = (caddr_t)tap; 1151 mb.m_len = sc->sc_txtap_len; 1152 mb.m_next = m; 1153 mb.m_nextpkt = NULL; 1154 mb.m_type = 0; 1155 mb.m_flags = 0; 1156 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1157 } 1158#endif 1159 1160 shdr = SLIST_FIRST(&sc->free_shdr); 1161 sbuf = SLIST_FIRST(&sc->free_sbuf); 1162 1163 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1164 shdr->hdr.subtype = htole32(0); 1165 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1166 shdr->hdr.encrypt = 0; 1167 shdr->hdr.keyidx = 0; 1168 shdr->hdr.keysz = 0; 1169 shdr->hdr.fragmentsz = htole16(0); 1170 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1171 if (ic->ic_opmode == IEEE80211_M_STA) 1172 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1173 else 1174 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1175 1176 /* trim IEEE802.11 header */ 1177 m_adj(m, sizeof (struct ieee80211_frame)); 1178 1179 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 1180 if (error != 0 && error != EFBIG) { 1181 printf("%s: could not map mbuf (error %d)\n", 1182 sc->sc_dev.dv_xname, error); 1183 m_freem(m); 1184 return error; 1185 } 1186 if (error != 0) { 1187 /* too many fragments, linearize */ 1188 1189 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1190 if (mnew == NULL) { 1191 m_freem(m); 1192 return ENOMEM; 1193 } 1194 1195 M_DUP_PKTHDR(mnew, m); 1196 if (m->m_pkthdr.len > MHLEN) { 1197 MCLGET(mnew, M_DONTWAIT); 1198 if (!(mnew->m_flags & M_EXT)) { 1199 m_freem(m); 1200 m_freem(mnew); 1201 return ENOMEM; 1202 } 1203 } 1204 1205 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 1206 m_freem(m); 1207 mnew->m_len = mnew->m_pkthdr.len; 1208 m = mnew; 1209 1210 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, 1211 BUS_DMA_NOWAIT); 1212 if (error != 0) { 1213 printf("%s: could not map mbuf (error %d)\n", 1214 sc->sc_dev.dv_xname, error); 1215 m_freem(m); 1216 return error; 1217 } 1218 } 1219 1220 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 1221 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 1222 if (error != 0) { 1223 printf("%s: could not map header DMA memory (error %d)\n", 1224 sc->sc_dev.dv_xname, error); 1225 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1226 m_freem(m); 1227 return error; 1228 } 1229 1230 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1231 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1232 1233 sbd = &sc->stbd_list[sc->txcur]; 1234 sbd->type = IPW_SBD_TYPE_HEADER; 1235 sbd->priv = shdr; 1236 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 1237 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1238 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1239 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1240 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1241 1242 DPRINTFN(5, ("TX!HDR!%u!%u!%u!%u", shdr->hdr.type, shdr->hdr.subtype, 1243 shdr->hdr.encrypted, shdr->hdr.encrypt)); 1244 DPRINTFN(5, ("!%s", ether_sprintf(shdr->hdr.src_addr))); 1245 DPRINTFN(5, ("!%s\n", ether_sprintf(shdr->hdr.dst_addr))); 1246 1247 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1248 sc->txcur * sizeof (struct ipw_bd), 1249 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1250 1251 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1252 sc->txfree--; 1253 1254 sbuf->m = m; 1255 sbuf->ni = ni; 1256 1257 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1258 sbd = &sc->stbd_list[sc->txcur]; 1259 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1260 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1261 sbd->bd->nfrag = 0; /* used only in first bd */ 1262 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1263 if (i == sbuf->map->dm_nsegs - 1) { 1264 sbd->type = IPW_SBD_TYPE_DATA; 1265 sbd->priv = sbuf; 1266 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1267 } else { 1268 sbd->type = IPW_SBD_TYPE_NOASSOC; 1269 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1270 } 1271 1272 DPRINTFN(5, ("TX!FRAG!%d!%d\n", i, 1273 sbuf->map->dm_segs[i].ds_len)); 1274 1275 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1276 sc->txcur * sizeof (struct ipw_bd), 1277 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1278 1279 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1280 sc->txfree--; 1281 } 1282 1283 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1284 BUS_DMASYNC_PREWRITE); 1285 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 1286 BUS_DMASYNC_PREWRITE); 1287 1288 /* inform firmware about this new packet */ 1289 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1290 1291 return 0; 1292} 1293 1294void 1295ipw_start(struct ifnet *ifp) 1296{ 1297 struct ipw_softc *sc = ifp->if_softc; 1298 struct ieee80211com *ic = &sc->sc_ic; 1299 struct mbuf *m; 1300 struct ieee80211_node *ni; 1301 1302 if (ic->ic_state != IEEE80211_S_RUN) 1303 return; 1304 1305 for (;;) { 1306 IFQ_POLL(&ifp->if_snd, m); 1307 if (m == NULL) 1308 break; 1309 1310 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1311 ifp->if_flags |= IFF_OACTIVE; 1312 break; 1313 } 1314 IFQ_DEQUEUE(&ifp->if_snd, m); 1315#if NBPFILTER > 0 1316 if (ifp->if_bpf != NULL) 1317 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1318#endif 1319 1320 m = ieee80211_encap(ifp, m, &ni); 1321 if (m == NULL) 1322 continue; 1323 1324#if NBPFILTER > 0 1325 if (ic->ic_rawbpf != NULL) 1326 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1327#endif 1328 1329 if (ipw_tx_start(ifp, m, ni) != 0) { 1330 if (ni != NULL) 1331 ieee80211_release_node(ic, ni); 1332 ifp->if_oerrors++; 1333 break; 1334 } 1335 1336 /* start watchdog timer */ 1337 sc->sc_tx_timer = 5; 1338 ifp->if_timer = 1; 1339 } 1340} 1341 1342void 1343ipw_watchdog(struct ifnet *ifp) 1344{ 1345 struct ipw_softc *sc = ifp->if_softc; 1346 1347 ifp->if_timer = 0; 1348 1349 if (sc->sc_tx_timer > 0) { 1350 if (--sc->sc_tx_timer == 0) { 1351 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1352 ifp->if_flags &= ~IFF_UP; 1353 ipw_stop(ifp, 1); 1354 ifp->if_oerrors++; 1355 return; 1356 } 1357 ifp->if_timer = 1; 1358 } 1359 1360 ieee80211_watchdog(ifp); 1361} 1362 1363int 1364ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1365{ 1366 struct ipw_softc *sc = ifp->if_softc; 1367 struct ieee80211com *ic = &sc->sc_ic; 1368 struct ifaddr *ifa; 1369 struct ifreq *ifr; 1370 int s, error = 0; 1371 1372 s = splnet(); 1373 1374 switch (cmd) { 1375 case SIOCSIFADDR: 1376 ifa = (struct ifaddr *)data; 1377 ifp->if_flags |= IFF_UP; 1378#ifdef INET 1379 if (ifa->ifa_addr->sa_family == AF_INET) 1380 arp_ifinit(&ic->ic_ac, ifa); 1381#endif 1382 /* FALLTHROUGH */ 1383 case SIOCSIFFLAGS: 1384 if (ifp->if_flags & IFF_UP) { 1385 if (!(ifp->if_flags & IFF_RUNNING)) 1386 ipw_init(ifp); 1387 } else { 1388 if (ifp->if_flags & IFF_RUNNING) 1389 ipw_stop(ifp, 1); 1390 } 1391 break; 1392 1393 case SIOCADDMULTI: 1394 case SIOCDELMULTI: 1395 ifr = (struct ifreq *)data; 1396 error = (cmd == SIOCADDMULTI) ? 1397 ether_addmulti(ifr, &ic->ic_ac) : 1398 ether_delmulti(ifr, &ic->ic_ac); 1399 1400 if (error == ENETRESET) 1401 error = 0; 1402 break; 1403 1404 case SIOCG80211TXPOWER: 1405 /* 1406 * If the hardware radio transmitter switch is off, report a 1407 * tx power of IEEE80211_TXPOWER_MIN to indicate that radio 1408 * transmitter is killed. 1409 */ 1410 ((struct ieee80211_txpower *)data)->i_val = 1411 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 1412 IEEE80211_TXPOWER_MIN : sc->sc_ic.ic_txpower; 1413 break; 1414 1415 default: 1416 error = ieee80211_ioctl(ifp, cmd, data); 1417 } 1418 1419 if (error == ENETRESET) { 1420 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1421 (IFF_UP | IFF_RUNNING)) 1422 ipw_init(ifp); 1423 error = 0; 1424 } 1425 1426 splx(s); 1427 return error; 1428} 1429 1430uint32_t 1431ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1432{ 1433 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1434} 1435 1436void 1437ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1438{ 1439 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1440} 1441 1442int 1443ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1444{ 1445 uint32_t addr, info; 1446 uint16_t count, size; 1447 uint32_t total; 1448 1449 /* addr[4] + count[2] + size[2] */ 1450 addr = MEM_READ_4(sc, sc->table2_base + off); 1451 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1452 1453 count = info >> 16; 1454 size = info & 0xffff; 1455 total = count * size; 1456 1457 if (total > *len) { 1458 *len = total; 1459 return EINVAL; 1460 } 1461 1462 *len = total; 1463 ipw_read_mem_1(sc, addr, buf, total); 1464 1465 return 0; 1466} 1467 1468void 1469ipw_stop_master(struct ipw_softc *sc) 1470{ 1471 int ntries; 1472 1473 /* disable interrupts */ 1474 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1475 1476 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1477 for (ntries = 0; ntries < 50; ntries++) { 1478 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1479 break; 1480 DELAY(10); 1481 } 1482 if (ntries == 50) 1483 printf("%s: timeout waiting for master\n", 1484 sc->sc_dev.dv_xname); 1485 1486 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1487 IPW_RST_PRINCETON_RESET); 1488 1489 sc->flags &= ~IPW_FLAG_FW_INITED; 1490} 1491 1492int 1493ipw_reset(struct ipw_softc *sc) 1494{ 1495 int ntries; 1496 1497 ipw_stop_master(sc); 1498 1499 /* move adapter to D0 state */ 1500 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1501 IPW_CTL_INIT); 1502 1503 /* wait for clock stabilization */ 1504 for (ntries = 0; ntries < 1000; ntries++) { 1505 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1506 break; 1507 DELAY(200); 1508 } 1509 if (ntries == 1000) 1510 return EIO; 1511 1512 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1513 IPW_RST_SW_RESET); 1514 1515 DELAY(10); 1516 1517 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1518 IPW_CTL_INIT); 1519 1520 return 0; 1521} 1522 1523int 1524ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1525{ 1526 int ntries; 1527 1528 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1529 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1530 1531 MEM_WRITE_2(sc, 0x220000, 0x0703); 1532 MEM_WRITE_2(sc, 0x220000, 0x0707); 1533 1534 MEM_WRITE_1(sc, 0x210014, 0x72); 1535 MEM_WRITE_1(sc, 0x210014, 0x72); 1536 1537 MEM_WRITE_1(sc, 0x210000, 0x40); 1538 MEM_WRITE_1(sc, 0x210000, 0x00); 1539 MEM_WRITE_1(sc, 0x210000, 0x40); 1540 1541 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1542 1543 MEM_WRITE_1(sc, 0x210000, 0x00); 1544 MEM_WRITE_1(sc, 0x210000, 0x00); 1545 MEM_WRITE_1(sc, 0x210000, 0x80); 1546 1547 MEM_WRITE_2(sc, 0x220000, 0x0703); 1548 MEM_WRITE_2(sc, 0x220000, 0x0707); 1549 1550 MEM_WRITE_1(sc, 0x210014, 0x72); 1551 MEM_WRITE_1(sc, 0x210014, 0x72); 1552 1553 MEM_WRITE_1(sc, 0x210000, 0x00); 1554 MEM_WRITE_1(sc, 0x210000, 0x80); 1555 1556 for (ntries = 0; ntries < 100; ntries++) { 1557 if (MEM_READ_1(sc, 0x210000) & 1) 1558 break; 1559 DELAY(1000); 1560 } 1561 if (ntries == 100) { 1562 printf("%s: timeout waiting for ucode to initialize\n", 1563 sc->sc_dev.dv_xname); 1564 return EIO; 1565 } 1566 1567 MEM_WRITE_4(sc, 0x3000e0, 0); 1568 1569 return 0; 1570} 1571 1572/* set of macros to handle unaligned little endian data in firmware image */ 1573#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1574#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1575int 1576ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1577{ 1578 u_char *p, *end; 1579 uint32_t dst; 1580 uint16_t len; 1581 int error; 1582 1583 p = fw; 1584 end = fw + size; 1585 while (p < end) { 1586 if (p + 6 > end) 1587 return EINVAL; 1588 1589 dst = GETLE32(p); p += 4; 1590 len = GETLE16(p); p += 2; 1591 1592 if (p + len > end) 1593 return EINVAL; 1594 1595 ipw_write_mem_1(sc, dst, p, len); 1596 p += len; 1597 } 1598 1599 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1600 IPW_IO_LED_OFF); 1601 1602 /* allow interrupts so we know when the firmware is inited */ 1603 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1604 1605 /* tell the adapter to initialize the firmware */ 1606 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1607 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1608 IPW_CTL_ALLOW_STANDBY); 1609 1610 /* wait at most one second for firmware initialization to complete */ 1611 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1612 printf("%s: timeout waiting for firmware initialization to " 1613 "complete\n", sc->sc_dev.dv_xname); 1614 return error; 1615 } 1616 1617 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1618 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1619 1620 return 0; 1621} 1622 1623int 1624ipw_read_firmware(struct ipw_softc *sc, struct ipw_firmware *fw) 1625{ 1626 struct ipw_firmware_hdr *hdr; 1627 const char *name; 1628 u_char *p; 1629 size_t size; 1630 int error; 1631 1632 switch (sc->sc_ic.ic_opmode) { 1633 case IEEE80211_M_STA: 1634 case IEEE80211_M_HOSTAP: 1635 name = "ipw-bss"; 1636 break; 1637 1638 case IEEE80211_M_IBSS: 1639 case IEEE80211_M_AHDEMO: 1640 name = "ipw-ibss"; 1641 break; 1642 1643 case IEEE80211_M_MONITOR: 1644 name = "ipw-monitor"; 1645 break; 1646 } 1647 1648 if ((error = loadfirmware(name, &fw->data, &size)) != 0) 1649 return error; 1650 1651 if (size < sizeof (struct ipw_firmware_hdr)) { 1652 error = EINVAL; 1653 goto fail; 1654 } 1655 1656 p = fw->data; 1657 hdr = (struct ipw_firmware_hdr *)p; 1658 fw->main_size = letoh32(hdr->main_size); 1659 fw->ucode_size = letoh32(hdr->ucode_size); 1660 1661 p += sizeof (struct ipw_firmware_hdr); 1662 size -= sizeof (struct ipw_firmware_hdr); 1663 1664 if (size < fw->main_size + fw->ucode_size) { 1665 error = EINVAL; 1666 goto fail; 1667 } 1668 1669 fw->main = p; 1670 fw->ucode = p + fw->main_size; 1671 1672 return 0; 1673 1674fail: free(fw->data, M_DEVBUF); 1675 return error; 1676} 1677 1678int 1679ipw_config(struct ipw_softc *sc) 1680{ 1681 struct ieee80211com *ic = &sc->sc_ic; 1682 struct ifnet *ifp = &ic->ic_if; 1683 struct ipw_security security; 1684 struct ieee80211_key *k; 1685 struct ipw_wep_key wepkey; 1686 struct ipw_scan_options options; 1687 struct ipw_configuration config; 1688 uint32_t data; 1689 int error, i; 1690 1691 switch (ic->ic_opmode) { 1692 case IEEE80211_M_STA: 1693 case IEEE80211_M_HOSTAP: 1694 data = htole32(IPW_MODE_BSS); 1695 break; 1696 1697 case IEEE80211_M_IBSS: 1698 case IEEE80211_M_AHDEMO: 1699 data = htole32(IPW_MODE_IBSS); 1700 break; 1701 1702 case IEEE80211_M_MONITOR: 1703 data = htole32(IPW_MODE_MONITOR); 1704 break; 1705 } 1706 DPRINTF(("Setting mode to %u\n", letoh32(data))); 1707 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1708 if (error != 0) 1709 return error; 1710 1711 if (ic->ic_opmode == IEEE80211_M_IBSS || 1712 ic->ic_opmode == IEEE80211_M_MONITOR) { 1713 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1714 DPRINTF(("Setting channel to %u\n", letoh32(data))); 1715 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1716 if (error != 0) 1717 return error; 1718 } 1719 1720 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1721 DPRINTF(("Enabling adapter\n")); 1722 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1723 } 1724 1725 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 1726 DPRINTF(("Setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 1727 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1728 IEEE80211_ADDR_LEN); 1729 if (error != 0) 1730 return error; 1731 1732 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1733 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1734 if (ic->ic_opmode == IEEE80211_M_IBSS) 1735 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1736 if (ifp->if_flags & IFF_PROMISC) 1737 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1738 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1739 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1740 DPRINTF(("Setting configuration 0x%x\n", config.flags)); 1741 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1742 if (error != 0) 1743 return error; 1744 1745 data = htole32(0x3); /* 1, 2 */ 1746 DPRINTF(("Setting basic tx rates to 0x%x\n", letoh32(data))); 1747 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1748 if (error != 0) 1749 return error; 1750 1751 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1752 DPRINTF(("Setting tx rates to 0x%x\n", letoh32(data))); 1753 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1754 if (error != 0) 1755 return error; 1756 1757 data = htole32(IPW_POWER_MODE_CAM); 1758 DPRINTF(("Setting power mode to %u\n", letoh32(data))); 1759 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1760 if (error != 0) 1761 return error; 1762 1763 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1764 data = htole32(32); /* default value */ 1765 DPRINTF(("Setting tx power index to %u\n", letoh32(data))); 1766 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1767 sizeof data); 1768 if (error != 0) 1769 return error; 1770 } 1771 1772 data = htole32(ic->ic_rtsthreshold); 1773 DPRINTF(("Setting RTS threshold to %u\n", letoh32(data))); 1774 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1775 if (error != 0) 1776 return error; 1777 1778 data = htole32(ic->ic_fragthreshold); 1779 DPRINTF(("Setting frag threshold to %u\n", letoh32(data))); 1780 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1781 if (error != 0) 1782 return error; 1783 1784#ifdef IPW_DEBUG 1785 if (ipw_debug > 0) { 1786 printf("Setting ESSID to "); 1787 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1788 printf("\n"); 1789 } 1790#endif 1791 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1792 ic->ic_des_esslen); 1793 if (error != 0) 1794 return error; 1795 1796 /* no mandatory BSSID */ 1797 DPRINTF(("Setting mandatory BSSID to null\n")); 1798 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1799 if (error != 0) 1800 return error; 1801 1802 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1803 DPRINTF(("Setting adapter BSSID to %s\n", 1804 ether_sprintf(ic->ic_des_bssid))); 1805 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1806 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1807 if (error != 0) 1808 return error; 1809 } 1810 1811 bzero(&security, sizeof security); 1812 security.authmode = IPW_AUTH_OPEN; /* XXX shared mode */ 1813 security.ciphers = htole32(IPW_CIPHER_NONE); 1814 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1815 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1816 sizeof security); 1817 if (error != 0) 1818 return error; 1819 1820 if (ic->ic_flags & IEEE80211_F_WEPON) { 1821 k = ic->ic_nw_keys; 1822 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1823 if (k->k_len == 0) 1824 continue; 1825 1826 wepkey.idx = i; 1827 wepkey.len = k->k_len; 1828 bzero(wepkey.key, sizeof wepkey.key); 1829 bcopy(k->k_key, wepkey.key, k->k_len); 1830 DPRINTF(("Setting wep key index %u len %u\n", 1831 wepkey.idx, wepkey.len)); 1832 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1833 sizeof wepkey); 1834 if (error != 0) 1835 return error; 1836 } 1837 1838 data = htole32(ic->ic_wep_txkey); 1839 DPRINTF(("Setting wep tx key index to %u\n", letoh32(data))); 1840 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1841 sizeof data); 1842 if (error != 0) 1843 return error; 1844 } 1845 1846 data = htole32((ic->ic_flags & IEEE80211_F_WEPON) ? IPW_WEPON : 0); 1847 DPRINTF(("Setting wep flags to 0x%x\n", letoh32(data))); 1848 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1849 if (error != 0) 1850 return error; 1851 1852 if (ic->ic_opmode == IEEE80211_M_IBSS || 1853 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1854 data = htole32(ic->ic_lintval); 1855 DPRINTF(("Setting beacon interval to %u\n", letoh32(data))); 1856 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1857 sizeof data); 1858 if (error != 0) 1859 return error; 1860 } 1861 1862 options.flags = htole32(0); 1863 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1864 DPRINTF(("Setting scan options to 0x%x\n", letoh32(options.flags))); 1865 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1866 if (error != 0) 1867 return error; 1868 1869 /* finally, enable adapter (start scanning for an access point) */ 1870 DPRINTF(("Enabling adapter\n")); 1871 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1872} 1873 1874int 1875ipw_init(struct ifnet *ifp) 1876{ 1877 struct ipw_softc *sc = ifp->if_softc; 1878 struct ipw_firmware fw; 1879 int error; 1880 1881 ipw_stop(ifp, 0); 1882 1883 if ((error = ipw_reset(sc)) != 0) { 1884 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 1885 goto fail1; 1886 } 1887 1888 if ((error = ipw_read_firmware(sc, &fw)) != NULL) { 1889 printf("%s: error %d, could not read firmware\n", 1890 sc->sc_dev.dv_xname, error); 1891 goto fail1; 1892 } 1893 1894 if ((error = ipw_load_ucode(sc, fw.ucode, fw.ucode_size)) != 0) { 1895 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 1896 goto fail2; 1897 } 1898 1899 ipw_stop_master(sc); 1900 1901 /* 1902 * Setup tx, rx and status rings. 1903 */ 1904 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1905 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1906 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1907 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1908 sc->txold = IPW_NTBD - 1; /* latest bd index ack by firmware */ 1909 sc->txcur = 0; /* bd index to write to */ 1910 sc->txfree = IPW_NTBD - 2; 1911 1912 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1913 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1914 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1915 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1916 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1917 1918 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1919 sc->status_map->dm_segs[0].ds_addr); 1920 1921 if ((error = ipw_load_firmware(sc, fw.main, fw.main_size)) != 0) { 1922 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 1923 goto fail2; 1924 } 1925 1926 sc->flags |= IPW_FLAG_FW_INITED; 1927 1928 /* retrieve information tables base addresses */ 1929 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 1930 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 1931 1932 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 1933 1934 if ((error = ipw_config(sc)) != 0) { 1935 printf("%s: device configuration failed\n", 1936 sc->sc_dev.dv_xname); 1937 goto fail2; 1938 } 1939 1940 ifp->if_flags &= ~IFF_OACTIVE; 1941 ifp->if_flags |= IFF_RUNNING; 1942 1943 return 0; 1944 1945fail2: free(fw.data, M_DEVBUF); 1946fail1: ipw_stop(ifp, 0); 1947 1948 return error; 1949} 1950 1951void 1952ipw_stop(struct ifnet *ifp, int disable) 1953{ 1954 struct ipw_softc *sc = ifp->if_softc; 1955 struct ieee80211com *ic = &sc->sc_ic; 1956 int i; 1957 1958 ipw_stop_master(sc); 1959 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1960 1961 ifp->if_timer = 0; 1962 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1963 1964 /* 1965 * Release tx buffers. 1966 */ 1967 for (i = 0; i < IPW_NTBD; i++) 1968 ipw_release_sbd(sc, &sc->stbd_list[i]); 1969 1970 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1971} 1972 1973void 1974ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 1975 bus_size_t count) 1976{ 1977 for (; count > 0; offset++, datap++, count--) { 1978 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1979 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 1980 } 1981} 1982 1983void 1984ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 1985 bus_size_t count) 1986{ 1987 for (; count > 0; offset++, datap++, count--) { 1988 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1989 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 1990 } 1991} 1992 1993struct cfdriver ipw_cd = { 1994 NULL, "ipw", DV_IFNET 1995}; 1996