if_ipw.c revision 1.56
1/* $OpenBSD: if_ipw.c,v 1.56 2006/03/25 22:41:45 djm Exp $ */ 2 3/*- 4 * Copyright (c) 2004-2006 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/*- 31 * Intel(R) PRO/Wireless 2100 MiniPCI driver 32 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 33 */ 34 35#include "bpfilter.h" 36 37#include <sys/param.h> 38#include <sys/sockio.h> 39#include <sys/sysctl.h> 40#include <sys/mbuf.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43#include <sys/systm.h> 44#include <sys/malloc.h> 45#include <sys/conf.h> 46#include <sys/device.h> 47 48#include <machine/bus.h> 49#include <machine/endian.h> 50#include <machine/intr.h> 51 52#include <dev/pci/pcireg.h> 53#include <dev/pci/pcivar.h> 54#include <dev/pci/pcidevs.h> 55 56#if NBPFILTER > 0 57#include <net/bpf.h> 58#endif 59#include <net/if.h> 60#include <net/if_arp.h> 61#include <net/if_dl.h> 62#include <net/if_media.h> 63#include <net/if_types.h> 64 65#include <netinet/in.h> 66#include <netinet/in_systm.h> 67#include <netinet/in_var.h> 68#include <netinet/if_ether.h> 69#include <netinet/ip.h> 70 71#include <net80211/ieee80211_var.h> 72#include <net80211/ieee80211_radiotap.h> 73 74#include <dev/pci/if_ipwreg.h> 75#include <dev/pci/if_ipwvar.h> 76 77static const struct ieee80211_rateset ipw_rateset_11b = 78 { 4, { 2, 4, 11, 22 } }; 79 80int ipw_match(struct device *, void *, void *); 81void ipw_attach(struct device *, struct device *, void *); 82int ipw_detach(struct device *, int); 83void ipw_power(int, void *); 84int ipw_dma_alloc(struct ipw_softc *); 85void ipw_release(struct ipw_softc *); 86int ipw_media_change(struct ifnet *); 87void ipw_media_status(struct ifnet *, struct ifmediareq *); 88int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 89uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 90void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 91void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 92void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 93 struct ipw_soft_bd *, struct ipw_soft_buf *); 94void ipw_notification_intr(struct ipw_softc *, 95 struct ipw_soft_buf *); 96void ipw_rx_intr(struct ipw_softc *); 97void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 98void ipw_tx_intr(struct ipw_softc *); 99int ipw_intr(void *); 100int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 101int ipw_tx_start(struct ifnet *, struct mbuf *, 102 struct ieee80211_node *); 103void ipw_start(struct ifnet *); 104void ipw_watchdog(struct ifnet *); 105int ipw_get_table1(struct ipw_softc *, uint32_t *); 106int ipw_get_radio(struct ipw_softc *, int *); 107int ipw_ioctl(struct ifnet *, u_long, caddr_t); 108uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 109void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 110int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 111 uint32_t *); 112void ipw_stop_master(struct ipw_softc *); 113int ipw_reset(struct ipw_softc *); 114int ipw_load_ucode(struct ipw_softc *, u_char *, int); 115int ipw_load_firmware(struct ipw_softc *, u_char *, int); 116int ipw_read_firmware(struct ipw_softc *, struct ipw_firmware *); 117int ipw_config(struct ipw_softc *); 118int ipw_init(struct ifnet *); 119void ipw_stop(struct ifnet *, int); 120void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 121 bus_size_t); 122void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 123 bus_size_t); 124 125static __inline uint8_t 126MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 127{ 128 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 129 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 130} 131 132static __inline uint32_t 133MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 134{ 135 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 136 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 137} 138 139#ifdef IPW_DEBUG 140#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 141#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 142int ipw_debug = 0; 143#else 144#define DPRINTF(x) 145#define DPRINTFN(n, x) 146#endif 147 148struct cfattach ipw_ca = { 149 sizeof (struct ipw_softc), ipw_match, ipw_attach, ipw_detach 150}; 151 152int 153ipw_match(struct device *parent, void *match, void *aux) 154{ 155 struct pci_attach_args *pa = aux; 156 157 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 158 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 159 return 1; 160 161 return 0; 162} 163 164/* Base Address Register */ 165#define IPW_PCI_BAR0 0x10 166 167void 168ipw_attach(struct device *parent, struct device *self, void *aux) 169{ 170 struct ipw_softc *sc = (struct ipw_softc *)self; 171 struct ieee80211com *ic = &sc->sc_ic; 172 struct ifnet *ifp = &ic->ic_if; 173 struct pci_attach_args *pa = aux; 174 const char *intrstr; 175 bus_space_tag_t memt; 176 bus_space_handle_t memh; 177 bus_addr_t base; 178 pci_intr_handle_t ih; 179 pcireg_t data; 180 uint16_t val; 181 int error, i; 182 183 sc->sc_pct = pa->pa_pc; 184 sc->sc_pcitag = pa->pa_tag, 185 186 /* clear device specific PCI configuration register 0x41 */ 187 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 188 data &= ~0x0000ff00; 189 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 190 191 /* map the register window */ 192 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 193 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 194 if (error != 0) { 195 printf(": could not map memory space\n"); 196 return; 197 } 198 199 sc->sc_st = memt; 200 sc->sc_sh = memh; 201 sc->sc_dmat = pa->pa_dmat; 202 203 /* disable interrupts */ 204 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 205 206 if (pci_intr_map(pa, &ih) != 0) { 207 printf(": could not map interrupt\n"); 208 return; 209 } 210 211 intrstr = pci_intr_string(sc->sc_pct, ih); 212 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 213 sc->sc_dev.dv_xname); 214 if (sc->sc_ih == NULL) { 215 printf(": could not establish interrupt"); 216 if (intrstr != NULL) 217 printf(" at %s", intrstr); 218 printf("\n"); 219 return; 220 } 221 printf(": %s", intrstr); 222 223 if (ipw_reset(sc) != 0) { 224 printf(": could not reset adapter\n"); 225 return; 226 } 227 228 if (ipw_dma_alloc(sc) != 0) { 229 printf(": failed to allocate DMA resources\n"); 230 return; 231 } 232 233 ic->ic_phytype = IEEE80211_T_DS; 234 ic->ic_opmode = IEEE80211_M_STA; 235 ic->ic_state = IEEE80211_S_INIT; 236 237 /* set device capabilities */ 238 ic->ic_caps = IEEE80211_C_IBSS | IEEE80211_C_MONITOR | 239 IEEE80211_C_PMGT | IEEE80211_C_TXPMGT | IEEE80211_C_WEP | 240 IEEE80211_C_SHPREAMBLE | IEEE80211_C_SCANALL; 241 242 /* read MAC address from EEPROM */ 243 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 244 ic->ic_myaddr[0] = val >> 8; 245 ic->ic_myaddr[1] = val & 0xff; 246 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 247 ic->ic_myaddr[2] = val >> 8; 248 ic->ic_myaddr[3] = val & 0xff; 249 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 250 ic->ic_myaddr[4] = val >> 8; 251 ic->ic_myaddr[5] = val & 0xff; 252 253 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 254 255 /* set supported .11b rates */ 256 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 257 258 /* set supported .11b channels (1 through 14) */ 259 for (i = 1; i <= 14; i++) { 260 ic->ic_channels[i].ic_freq = 261 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 262 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 263 } 264 265 /* default to authmode OPEN */ 266 sc->authmode = IEEE80211_AUTH_OPEN; 267 268 /* IBSS channel undefined for now */ 269 ic->ic_ibss_chan = &ic->ic_channels[0]; 270 271 ifp->if_softc = sc; 272 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 273 ifp->if_init = ipw_init; 274 ifp->if_ioctl = ipw_ioctl; 275 ifp->if_start = ipw_start; 276 ifp->if_watchdog = ipw_watchdog; 277 IFQ_SET_READY(&ifp->if_snd); 278 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 279 280 if_attach(ifp); 281 ieee80211_ifattach(ifp); 282 /* override state transition machine */ 283 sc->sc_newstate = ic->ic_newstate; 284 ic->ic_newstate = ipw_newstate; 285 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 286 287 sc->powerhook = powerhook_establish(ipw_power, sc); 288 289#if NBPFILTER > 0 290 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 291 sizeof (struct ieee80211_frame) + 64); 292 293 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 294 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 295 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 296 297 sc->sc_txtap_len = sizeof sc->sc_txtapu; 298 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 299 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 300#endif 301} 302 303int 304ipw_detach(struct device* self, int flags) 305{ 306 struct ipw_softc *sc = (struct ipw_softc *)self; 307 struct ifnet *ifp = &sc->sc_ic.ic_if; 308 309 ipw_stop(ifp, 1); 310 311 ieee80211_ifdetach(ifp); 312 if_detach(ifp); 313 314 ipw_release(sc); 315 316 if (sc->sc_ih != NULL) { 317 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 318 sc->sc_ih = NULL; 319 } 320 321 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 322 323 return 0; 324} 325 326void 327ipw_power(int why, void *arg) 328{ 329 struct ipw_softc *sc = arg; 330 struct ifnet *ifp; 331 pcireg_t data; 332 333 if (why != PWR_RESUME) 334 return; 335 336 /* clear device specific PCI configuration register 0x41 */ 337 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 338 data &= ~0x0000ff00; 339 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 340 341 ifp = &sc->sc_ic.ic_if; 342 if (ifp->if_flags & IFF_UP) { 343 ifp->if_init(ifp); 344 if (ifp->if_flags & IFF_RUNNING) 345 ifp->if_start(ifp); 346 } 347} 348 349int 350ipw_dma_alloc(struct ipw_softc *sc) 351{ 352 struct ipw_soft_bd *sbd; 353 struct ipw_soft_hdr *shdr; 354 struct ipw_soft_buf *sbuf; 355 int i, nsegs, error; 356 357 /* 358 * Allocate and map tx ring. 359 */ 360 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 361 BUS_DMA_NOWAIT, &sc->tbd_map); 362 if (error != 0) { 363 printf("%s: could not create tx ring DMA map\n", 364 sc->sc_dev.dv_xname); 365 goto fail; 366 } 367 368 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 369 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 370 if (error != 0) { 371 printf("%s: could not allocate tx ring DMA memory\n", 372 sc->sc_dev.dv_xname); 373 goto fail; 374 } 375 376 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 377 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 378 if (error != 0) { 379 printf("%s: could not map tx ring DMA memory\n", 380 sc->sc_dev.dv_xname); 381 goto fail; 382 } 383 384 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 385 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 386 if (error != 0) { 387 printf("%s: could not load tx ring DMA map\n", 388 sc->sc_dev.dv_xname); 389 goto fail; 390 } 391 392 /* 393 * Allocate and map rx ring. 394 */ 395 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 396 BUS_DMA_NOWAIT, &sc->rbd_map); 397 if (error != 0) { 398 printf("%s: could not create rx ring DMA map\n", 399 sc->sc_dev.dv_xname); 400 goto fail; 401 } 402 403 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 404 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 405 if (error != 0) { 406 printf("%s: could not allocate rx ring DMA memory\n", 407 sc->sc_dev.dv_xname); 408 goto fail; 409 } 410 411 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 412 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 413 if (error != 0) { 414 printf("%s: could not map rx ring DMA memory\n", 415 sc->sc_dev.dv_xname); 416 goto fail; 417 } 418 419 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 420 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 421 if (error != 0) { 422 printf("%s: could not load tx ring DMA map\n", 423 sc->sc_dev.dv_xname); 424 goto fail; 425 } 426 427 /* 428 * Allocate and map status ring. 429 */ 430 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 431 0, BUS_DMA_NOWAIT, &sc->status_map); 432 if (error != 0) { 433 printf("%s: could not create status ring DMA map\n", 434 sc->sc_dev.dv_xname); 435 goto fail; 436 } 437 438 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 439 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 440 if (error != 0) { 441 printf("%s: could not allocate status ring DMA memory\n", 442 sc->sc_dev.dv_xname); 443 goto fail; 444 } 445 446 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 447 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 448 if (error != 0) { 449 printf("%s: could not map status ring DMA memory\n", 450 sc->sc_dev.dv_xname); 451 goto fail; 452 } 453 454 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 455 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 456 if (error != 0) { 457 printf("%s: could not load status ring DMA map\n", 458 sc->sc_dev.dv_xname); 459 goto fail; 460 } 461 462 /* 463 * Allocate command DMA map. 464 */ 465 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 466 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 467 if (error != 0) { 468 printf("%s: could not create command DMA map\n", 469 sc->sc_dev.dv_xname); 470 goto fail; 471 } 472 473 /* 474 * Allocate headers DMA maps. 475 */ 476 SLIST_INIT(&sc->free_shdr); 477 for (i = 0; i < IPW_NDATA; i++) { 478 shdr = &sc->shdr_list[i]; 479 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_hdr), 480 1, sizeof (struct ipw_hdr), 0, BUS_DMA_NOWAIT, &shdr->map); 481 if (error != 0) { 482 printf("%s: could not create header DMA map\n", 483 sc->sc_dev.dv_xname); 484 goto fail; 485 } 486 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 487 } 488 489 /* 490 * Allocate tx buffers DMA maps. 491 */ 492 SLIST_INIT(&sc->free_sbuf); 493 for (i = 0; i < IPW_NDATA; i++) { 494 sbuf = &sc->tx_sbuf_list[i]; 495 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, IPW_MAX_NSEG, 496 MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 497 if (error != 0) { 498 printf("%s: could not create tx DMA map\n", 499 sc->sc_dev.dv_xname); 500 goto fail; 501 } 502 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 503 } 504 505 /* 506 * Initialize tx ring. 507 */ 508 for (i = 0; i < IPW_NTBD; i++) { 509 sbd = &sc->stbd_list[i]; 510 sbd->bd = &sc->tbd_list[i]; 511 sbd->type = IPW_SBD_TYPE_NOASSOC; 512 } 513 514 /* 515 * Pre-allocate rx buffers and DMA maps. 516 */ 517 for (i = 0; i < IPW_NRBD; i++) { 518 sbd = &sc->srbd_list[i]; 519 sbuf = &sc->rx_sbuf_list[i]; 520 sbd->bd = &sc->rbd_list[i]; 521 522 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 523 if (sbuf->m == NULL) { 524 printf("%s: could not allocate rx mbuf\n", 525 sc->sc_dev.dv_xname); 526 error = ENOMEM; 527 goto fail; 528 } 529 530 MCLGET(sbuf->m, M_DONTWAIT); 531 if (!(sbuf->m->m_flags & M_EXT)) { 532 m_freem(sbuf->m); 533 printf("%s: could not allocate rx mbuf cluster\n", 534 sc->sc_dev.dv_xname); 535 error = ENOMEM; 536 goto fail; 537 } 538 539 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 540 0, BUS_DMA_NOWAIT, &sbuf->map); 541 if (error != 0) { 542 printf("%s: could not create rx DMA map\n", 543 sc->sc_dev.dv_xname); 544 goto fail; 545 } 546 547 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 548 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 549 if (error != 0) { 550 printf("%s: could not map rx DMA memory\n", 551 sc->sc_dev.dv_xname); 552 goto fail; 553 } 554 555 sbd->type = IPW_SBD_TYPE_DATA; 556 sbd->priv = sbuf; 557 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 558 sbd->bd->len = htole32(MCLBYTES); 559 } 560 561 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 562 BUS_DMASYNC_PREWRITE); 563 564 return 0; 565 566fail: ipw_release(sc); 567 return error; 568} 569 570void 571ipw_release(struct ipw_softc *sc) 572{ 573 struct ipw_soft_buf *sbuf; 574 int i; 575 576 if (sc->tbd_map != NULL) { 577 if (sc->tbd_list != NULL) { 578 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 579 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 580 IPW_TBD_SZ); 581 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 582 } 583 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 584 } 585 586 if (sc->rbd_map != NULL) { 587 if (sc->rbd_list != NULL) { 588 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 589 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 590 IPW_RBD_SZ); 591 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 592 } 593 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 594 } 595 596 if (sc->status_map != NULL) { 597 if (sc->status_list != NULL) { 598 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 599 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 600 IPW_RBD_SZ); 601 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 602 } 603 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 604 } 605 606 if (sc->cmd_map != NULL) 607 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 608 609 for (i = 0; i < IPW_NDATA; i++) 610 bus_dmamap_destroy(sc->sc_dmat, sc->shdr_list[i].map); 611 612 for (i = 0; i < IPW_NDATA; i++) 613 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 614 615 for (i = 0; i < IPW_NRBD; i++) { 616 sbuf = &sc->rx_sbuf_list[i]; 617 if (sbuf->map != NULL) { 618 if (sbuf->m != NULL) { 619 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 620 m_freem(sbuf->m); 621 } 622 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 623 } 624 } 625} 626 627int 628ipw_media_change(struct ifnet *ifp) 629{ 630 int error; 631 632 error = ieee80211_media_change(ifp); 633 if (error != ENETRESET) 634 return error; 635 636 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 637 ipw_init(ifp); 638 639 return 0; 640} 641 642void 643ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 644{ 645#define N(a) (sizeof (a) / sizeof (a[0])) 646 struct ipw_softc *sc = ifp->if_softc; 647 struct ieee80211com *ic = &sc->sc_ic; 648 static const struct { 649 uint32_t val; 650 int rate; 651 } rates[] = { 652 { IPW_RATE_DS1, 2 }, 653 { IPW_RATE_DS2, 4 }, 654 { IPW_RATE_DS5, 11 }, 655 { IPW_RATE_DS11, 22 }, 656 }; 657 uint32_t val; 658 int rate, i; 659 660 imr->ifm_status = IFM_AVALID; 661 imr->ifm_active = IFM_IEEE80211; 662 if (ic->ic_state == IEEE80211_S_RUN) 663 imr->ifm_status |= IFM_ACTIVE; 664 665 /* read current transmission rate from adapter */ 666 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 667 val &= 0xf; 668 669 /* convert rate to 802.11 rate */ 670 for (i = 0; i < N(rates) && rates[i].val != val; i++); 671 rate = (i < N(rates)) ? rates[i].rate : 0; 672 673 imr->ifm_active |= IFM_IEEE80211_11B; 674 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 675 switch (ic->ic_opmode) { 676 case IEEE80211_M_STA: 677 break; 678 679 case IEEE80211_M_IBSS: 680 imr->ifm_active |= IFM_IEEE80211_IBSS; 681 break; 682 683 case IEEE80211_M_MONITOR: 684 imr->ifm_active |= IFM_IEEE80211_MONITOR; 685 break; 686 687 case IEEE80211_M_AHDEMO: 688 case IEEE80211_M_HOSTAP: 689 /* should not get there */ 690 break; 691 } 692#undef N 693} 694 695int 696ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 697{ 698 struct ipw_softc *sc = ic->ic_softc; 699 struct ieee80211_node *ni; 700 uint8_t macaddr[IEEE80211_ADDR_LEN]; 701 uint32_t len; 702 703 switch (nstate) { 704 case IEEE80211_S_RUN: 705 DELAY(100); /* firmware needs a short delay here */ 706 707 len = IEEE80211_ADDR_LEN; 708 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 709 710 ni = ieee80211_find_node(ic, macaddr); 711 if (ni == NULL) 712 break; 713 714 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 715 ieee80211_node_newstate(ni, IEEE80211_STA_BSS); 716 break; 717 718 case IEEE80211_S_INIT: 719 case IEEE80211_S_SCAN: 720 case IEEE80211_S_AUTH: 721 case IEEE80211_S_ASSOC: 722 break; 723 } 724 725 ic->ic_state = nstate; 726 return 0; 727} 728 729/* 730 * Read 16 bits at address 'addr' from the Microwire EEPROM. 731 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 732 */ 733uint16_t 734ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 735{ 736 uint32_t tmp; 737 uint16_t val; 738 int n; 739 740 /* clock C once before the first command */ 741 IPW_EEPROM_CTL(sc, 0); 742 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 743 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 744 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 745 746 /* write start bit (1) */ 747 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 748 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 749 750 /* write READ opcode (10) */ 751 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 752 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 753 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 754 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 755 756 /* write address A7-A0 */ 757 for (n = 7; n >= 0; n--) { 758 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 759 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 760 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 761 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 762 } 763 764 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 765 766 /* read data Q15-Q0 */ 767 val = 0; 768 for (n = 15; n >= 0; n--) { 769 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 770 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 771 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 772 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 773 } 774 775 IPW_EEPROM_CTL(sc, 0); 776 777 /* clear Chip Select and clock C */ 778 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 779 IPW_EEPROM_CTL(sc, 0); 780 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 781 782 return val; 783} 784 785void 786ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 787{ 788 struct ipw_cmd *cmd; 789 790 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 791 BUS_DMASYNC_POSTREAD); 792 793 cmd = mtod(sbuf->m, struct ipw_cmd *); 794 795 DPRINTFN(2, ("RX!CMD!%u!%u!%u!%u!%u\n", 796 letoh32(cmd->type), letoh32(cmd->subtype), letoh32(cmd->seq), 797 letoh32(cmd->len), letoh32(cmd->status))); 798 799 wakeup(sc); 800} 801 802void 803ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 804{ 805 struct ieee80211com *ic = &sc->sc_ic; 806 uint32_t state; 807 808 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 809 BUS_DMASYNC_POSTREAD); 810 811 state = letoh32(*mtod(sbuf->m, uint32_t *)); 812 813 DPRINTFN(2, ("RX!NEWSTATE!%u\n", state)); 814 815 switch (state) { 816 case IPW_STATE_ASSOCIATED: 817 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 818 break; 819 820 case IPW_STATE_SCANNING: 821 /* don't leave run state on background scan */ 822 if (ic->ic_state != IEEE80211_S_RUN) 823 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 824 825 ic->ic_flags |= IEEE80211_F_ASCAN; 826 break; 827 828 case IPW_STATE_SCAN_COMPLETE: 829 ic->ic_flags &= ~IEEE80211_F_ASCAN; 830 break; 831 832 case IPW_STATE_ASSOCIATION_LOST: 833 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 834 break; 835 836 case IPW_STATE_RADIO_DISABLED: 837 ipw_stop(&ic->ic_if, 1); 838 break; 839 } 840} 841 842void 843ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 844 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 845{ 846 struct ieee80211com *ic = &sc->sc_ic; 847 struct ifnet *ifp = &ic->ic_if; 848 struct mbuf *mnew, *m; 849 struct ieee80211_frame *wh; 850 struct ieee80211_node *ni; 851 int error; 852 853 DPRINTFN(5, ("RX!DATA!%u!%u\n", letoh32(status->len), status->rssi)); 854 855 /* 856 * Try to allocate a new mbuf for this ring element and load it before 857 * processing the current mbuf. If the ring element cannot be loaded, 858 * drop the received packet and reuse the old mbuf. In the unlikely 859 * case that the old mbuf can't be reloaded either, explicitly panic. 860 */ 861 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 862 if (mnew == NULL) { 863 ifp->if_ierrors++; 864 return; 865 } 866 867 MCLGET(mnew, M_DONTWAIT); 868 if (!(mnew->m_flags & M_EXT)) { 869 m_freem(mnew); 870 ifp->if_ierrors++; 871 return; 872 } 873 874 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 875 BUS_DMASYNC_POSTREAD); 876 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 877 878 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(mnew, void *), 879 MCLBYTES, NULL, BUS_DMA_NOWAIT); 880 if (error != 0) { 881 m_freem(mnew); 882 883 /* try to reload the old mbuf */ 884 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 885 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 886 if (error != 0) { 887 /* very unlikely that it will fail... */ 888 panic("%s: could not load old rx mbuf", 889 sc->sc_dev.dv_xname); 890 } 891 ifp->if_ierrors++; 892 return; 893 } 894 895 m = sbuf->m; 896 sbuf->m = mnew; 897 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 898 899 /* finalize mbuf */ 900 m->m_pkthdr.rcvif = ifp; 901 m->m_pkthdr.len = m->m_len = letoh32(status->len); 902 903#if NBPFILTER > 0 904 if (sc->sc_drvbpf != NULL) { 905 struct mbuf mb; 906 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 907 908 tap->wr_flags = 0; 909 tap->wr_antsignal = status->rssi; 910 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 911 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 912 913 M_DUP_PKTHDR(&mb, m); 914 mb.m_data = (caddr_t)tap; 915 mb.m_len = sc->sc_rxtap_len; 916 mb.m_next = m; 917 mb.m_pkthdr.len += mb.m_len; 918 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 919 } 920#endif 921 922 wh = mtod(m, struct ieee80211_frame *); 923 924 ni = ieee80211_find_rxnode(ic, wh); 925 926 /* send the frame to the upper layer */ 927 ieee80211_input(ifp, m, ni, status->rssi, 0); 928 929 ieee80211_release_node(ic, ni); 930} 931 932void 933ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 934{ 935 DPRINTFN(2, ("RX!NOTIFICATION\n")); 936} 937 938void 939ipw_rx_intr(struct ipw_softc *sc) 940{ 941 struct ipw_status *status; 942 struct ipw_soft_bd *sbd; 943 struct ipw_soft_buf *sbuf; 944 uint32_t r, i; 945 946 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 947 948 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 949 950 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 951 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 952 BUS_DMASYNC_POSTREAD); 953 954 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 955 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 956 BUS_DMASYNC_POSTREAD); 957 958 status = &sc->status_list[i]; 959 sbd = &sc->srbd_list[i]; 960 sbuf = sbd->priv; 961 962 switch (letoh16(status->code) & 0xf) { 963 case IPW_STATUS_CODE_COMMAND: 964 ipw_command_intr(sc, sbuf); 965 break; 966 967 case IPW_STATUS_CODE_NEWSTATE: 968 ipw_newstate_intr(sc, sbuf); 969 break; 970 971 case IPW_STATUS_CODE_DATA_802_3: 972 case IPW_STATUS_CODE_DATA_802_11: 973 ipw_data_intr(sc, status, sbd, sbuf); 974 break; 975 976 case IPW_STATUS_CODE_NOTIFICATION: 977 ipw_notification_intr(sc, sbuf); 978 break; 979 980 default: 981 printf("%s: unknown status code %u\n", 982 sc->sc_dev.dv_xname, letoh16(status->code)); 983 } 984 sbd->bd->flags = 0; 985 986 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 987 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 988 BUS_DMASYNC_PREWRITE); 989 } 990 991 /* tell the firmware what we have processed */ 992 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 993 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 994} 995 996void 997ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 998{ 999 struct ieee80211com *ic = &sc->sc_ic; 1000 struct ipw_soft_hdr *shdr; 1001 struct ipw_soft_buf *sbuf; 1002 1003 switch (sbd->type) { 1004 case IPW_SBD_TYPE_COMMAND: 1005 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 1006 break; 1007 1008 case IPW_SBD_TYPE_HEADER: 1009 shdr = sbd->priv; 1010 bus_dmamap_unload(sc->sc_dmat, shdr->map); 1011 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 1012 break; 1013 1014 case IPW_SBD_TYPE_DATA: 1015 sbuf = sbd->priv; 1016 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1017 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1018 1019 m_freem(sbuf->m); 1020 1021 if (sbuf->ni != NULL) 1022 ieee80211_release_node(ic, sbuf->ni); 1023 1024 /* kill watchdog timer */ 1025 sc->sc_tx_timer = 0; 1026 break; 1027 } 1028 sbd->type = IPW_SBD_TYPE_NOASSOC; 1029} 1030 1031void 1032ipw_tx_intr(struct ipw_softc *sc) 1033{ 1034 struct ifnet *ifp = &sc->sc_ic.ic_if; 1035 struct ipw_soft_bd *sbd; 1036 uint32_t r, i; 1037 1038 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 1039 1040 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1041 sbd = &sc->stbd_list[i]; 1042 1043 if (sbd->type == IPW_SBD_TYPE_DATA) 1044 ifp->if_opackets++; 1045 1046 ipw_release_sbd(sc, sbd); 1047 sc->txfree++; 1048 } 1049 1050 /* remember what the firmware has processed */ 1051 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1052 1053 /* call start() since some buffer descriptors have been released */ 1054 ifp->if_flags &= ~IFF_OACTIVE; 1055 (*ifp->if_start)(ifp); 1056} 1057 1058int 1059ipw_intr(void *arg) 1060{ 1061 struct ipw_softc *sc = arg; 1062 uint32_t r; 1063 1064 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) 1065 return 0; 1066 1067 /* disable interrupts */ 1068 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1069 1070 DPRINTFN(8, ("INTR!0x%08x\n", r)); 1071 1072 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1073 printf("%s: fatal error\n", sc->sc_dev.dv_xname); 1074 ipw_stop(&sc->sc_ic.ic_if, 1); 1075 } 1076 1077 if (r & IPW_INTR_FW_INIT_DONE) { 1078 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1079 wakeup(sc); 1080 } 1081 1082 if (r & IPW_INTR_RX_TRANSFER) 1083 ipw_rx_intr(sc); 1084 1085 if (r & IPW_INTR_TX_TRANSFER) 1086 ipw_tx_intr(sc); 1087 1088 /* acknowledge interrupts */ 1089 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1090 1091 /* re-enable interrupts */ 1092 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1093 1094 return 1; 1095} 1096 1097int 1098ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1099{ 1100 struct ipw_soft_bd *sbd; 1101 int error; 1102 1103 sbd = &sc->stbd_list[sc->txcur]; 1104 1105 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 1106 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 1107 if (error != 0) { 1108 printf("%s: could not map command DMA memory\n", 1109 sc->sc_dev.dv_xname); 1110 return error; 1111 } 1112 1113 sc->cmd.type = htole32(type); 1114 sc->cmd.subtype = htole32(0); 1115 sc->cmd.len = htole32(len); 1116 sc->cmd.seq = htole32(0); 1117 if (data != NULL) 1118 bcopy(data, sc->cmd.data, len); 1119 1120 sbd->type = IPW_SBD_TYPE_COMMAND; 1121 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1122 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1123 sbd->bd->nfrag = 1; 1124 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1125 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1126 1127 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1128 BUS_DMASYNC_PREWRITE); 1129 1130 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1131 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1132 BUS_DMASYNC_PREWRITE); 1133 1134 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1135 sc->txfree--; 1136 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1137 1138 DPRINTFN(2, ("TX!CMD!%u!%u!%u!%u\n", type, 0, 0, len)); 1139 1140 /* wait at most one second for command to complete */ 1141 return tsleep(sc, 0, "ipwcmd", hz); 1142} 1143 1144int 1145ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 1146{ 1147 struct ipw_softc *sc = ifp->if_softc; 1148 struct ieee80211com *ic = &sc->sc_ic; 1149 struct ieee80211_frame *wh; 1150 struct ipw_soft_bd *sbd; 1151 struct ipw_soft_hdr *shdr; 1152 struct ipw_soft_buf *sbuf; 1153 struct mbuf *mnew; 1154 int error, i; 1155 1156 if (ic->ic_flags & IEEE80211_F_WEPON) { 1157 m = ieee80211_wep_crypt(ifp, m, 1); 1158 if (m == NULL) 1159 return ENOBUFS; 1160 } 1161 1162#if NBPFILTER > 0 1163 if (sc->sc_drvbpf != NULL) { 1164 struct mbuf mb; 1165 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1166 1167 tap->wt_flags = 0; 1168 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1169 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1170 1171 M_DUP_PKTHDR(&mb, m); 1172 mb.m_data = (caddr_t)tap; 1173 mb.m_len = sc->sc_txtap_len; 1174 mb.m_next = m; 1175 mb.m_pkthdr.len += mb.m_len; 1176 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1177 } 1178#endif 1179 1180 wh = mtod(m, struct ieee80211_frame *); 1181 1182 shdr = SLIST_FIRST(&sc->free_shdr); 1183 sbuf = SLIST_FIRST(&sc->free_sbuf); 1184 1185 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1186 shdr->hdr.subtype = htole32(0); 1187 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1188 shdr->hdr.encrypt = 0; 1189 shdr->hdr.keyidx = 0; 1190 shdr->hdr.keysz = 0; 1191 shdr->hdr.fragmentsz = htole16(0); 1192 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1193 if (ic->ic_opmode == IEEE80211_M_STA) 1194 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1195 else 1196 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1197 1198 /* trim IEEE802.11 header */ 1199 m_adj(m, sizeof (struct ieee80211_frame)); 1200 1201 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 1202 if (error != 0 && error != EFBIG) { 1203 printf("%s: could not map mbuf (error %d)\n", 1204 sc->sc_dev.dv_xname, error); 1205 m_freem(m); 1206 return error; 1207 } 1208 if (error != 0) { 1209 /* too many fragments, linearize */ 1210 1211 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1212 if (mnew == NULL) { 1213 m_freem(m); 1214 return ENOMEM; 1215 } 1216 1217 M_DUP_PKTHDR(mnew, m); 1218 if (m->m_pkthdr.len > MHLEN) { 1219 MCLGET(mnew, M_DONTWAIT); 1220 if (!(mnew->m_flags & M_EXT)) { 1221 m_freem(m); 1222 m_freem(mnew); 1223 return ENOMEM; 1224 } 1225 } 1226 1227 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 1228 m_freem(m); 1229 mnew->m_len = mnew->m_pkthdr.len; 1230 m = mnew; 1231 1232 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, 1233 BUS_DMA_NOWAIT); 1234 if (error != 0) { 1235 printf("%s: could not map mbuf (error %d)\n", 1236 sc->sc_dev.dv_xname, error); 1237 m_freem(m); 1238 return error; 1239 } 1240 } 1241 1242 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 1243 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 1244 if (error != 0) { 1245 printf("%s: could not map header DMA memory (error %d)\n", 1246 sc->sc_dev.dv_xname, error); 1247 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1248 m_freem(m); 1249 return error; 1250 } 1251 1252 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1253 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1254 1255 sbd = &sc->stbd_list[sc->txcur]; 1256 sbd->type = IPW_SBD_TYPE_HEADER; 1257 sbd->priv = shdr; 1258 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 1259 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1260 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1261 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1262 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1263 1264 DPRINTFN(5, ("TX!HDR!%u!%u!%u!%u", shdr->hdr.type, shdr->hdr.subtype, 1265 shdr->hdr.encrypted, shdr->hdr.encrypt)); 1266 DPRINTFN(5, ("!%s", ether_sprintf(shdr->hdr.src_addr))); 1267 DPRINTFN(5, ("!%s\n", ether_sprintf(shdr->hdr.dst_addr))); 1268 1269 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1270 sc->txcur * sizeof (struct ipw_bd), 1271 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1272 1273 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1274 sc->txfree--; 1275 1276 sbuf->m = m; 1277 sbuf->ni = ni; 1278 1279 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1280 sbd = &sc->stbd_list[sc->txcur]; 1281 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1282 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1283 sbd->bd->nfrag = 0; /* used only in first bd */ 1284 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1285 if (i == sbuf->map->dm_nsegs - 1) { 1286 sbd->type = IPW_SBD_TYPE_DATA; 1287 sbd->priv = sbuf; 1288 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1289 } else { 1290 sbd->type = IPW_SBD_TYPE_NOASSOC; 1291 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1292 } 1293 1294 DPRINTFN(5, ("TX!FRAG!%d!%d\n", i, 1295 sbuf->map->dm_segs[i].ds_len)); 1296 1297 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1298 sc->txcur * sizeof (struct ipw_bd), 1299 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1300 1301 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1302 sc->txfree--; 1303 } 1304 1305 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 1306 BUS_DMASYNC_PREWRITE); 1307 1308 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1309 BUS_DMASYNC_PREWRITE); 1310 1311 /* inform firmware about this new packet */ 1312 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1313 1314 return 0; 1315} 1316 1317void 1318ipw_start(struct ifnet *ifp) 1319{ 1320 struct ipw_softc *sc = ifp->if_softc; 1321 struct ieee80211com *ic = &sc->sc_ic; 1322 struct mbuf *m; 1323 struct ieee80211_node *ni; 1324 1325 if (ic->ic_state != IEEE80211_S_RUN) 1326 return; 1327 1328 for (;;) { 1329 IF_DEQUEUE(&ifp->if_snd, m); 1330 if (m == NULL) 1331 break; 1332 1333 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1334 IF_PREPEND(&ifp->if_snd, m); 1335 ifp->if_flags |= IFF_OACTIVE; 1336 break; 1337 } 1338 1339#if NBPFILTER > 0 1340 if (ifp->if_bpf != NULL) 1341 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1342#endif 1343 1344 m = ieee80211_encap(ifp, m, &ni); 1345 if (m == NULL) 1346 continue; 1347 1348#if NBPFILTER > 0 1349 if (ic->ic_rawbpf != NULL) 1350 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1351#endif 1352 1353 if (ipw_tx_start(ifp, m, ni) != 0) { 1354 if (ni != NULL) 1355 ieee80211_release_node(ic, ni); 1356 ifp->if_oerrors++; 1357 break; 1358 } 1359 1360 /* start watchdog timer */ 1361 sc->sc_tx_timer = 5; 1362 ifp->if_timer = 1; 1363 } 1364} 1365 1366void 1367ipw_watchdog(struct ifnet *ifp) 1368{ 1369 struct ipw_softc *sc = ifp->if_softc; 1370 1371 ifp->if_timer = 0; 1372 1373 if (sc->sc_tx_timer > 0) { 1374 if (--sc->sc_tx_timer == 0) { 1375 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1376 ipw_stop(ifp, 1); 1377 ifp->if_oerrors++; 1378 return; 1379 } 1380 ifp->if_timer = 1; 1381 } 1382 1383 ieee80211_watchdog(ifp); 1384} 1385 1386int 1387ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1388{ 1389 struct ipw_softc *sc = ifp->if_softc; 1390 struct ieee80211com *ic = &sc->sc_ic; 1391 struct ifaddr *ifa; 1392 struct ifreq *ifr; 1393 int s, error = 0; 1394 1395 s = splnet(); 1396 1397 switch (cmd) { 1398 case SIOCSIFADDR: 1399 ifa = (struct ifaddr *)data; 1400 ifp->if_flags |= IFF_UP; 1401#ifdef INET 1402 if (ifa->ifa_addr->sa_family == AF_INET) 1403 arp_ifinit(&ic->ic_ac, ifa); 1404#endif 1405 /* FALLTHROUGH */ 1406 case SIOCSIFFLAGS: 1407 if (ifp->if_flags & IFF_UP) { 1408 if (!(ifp->if_flags & IFF_RUNNING)) 1409 ipw_init(ifp); 1410 } else { 1411 if (ifp->if_flags & IFF_RUNNING) 1412 ipw_stop(ifp, 1); 1413 } 1414 break; 1415 1416 case SIOCADDMULTI: 1417 case SIOCDELMULTI: 1418 ifr = (struct ifreq *)data; 1419 error = (cmd == SIOCADDMULTI) ? 1420 ether_addmulti(ifr, &ic->ic_ac) : 1421 ether_delmulti(ifr, &ic->ic_ac); 1422 1423 if (error == ENETRESET) 1424 error = 0; 1425 break; 1426 1427 case SIOCG80211TXPOWER: 1428 /* 1429 * If the hardware radio transmitter switch is off, report a 1430 * tx power of IEEE80211_TXPOWER_MIN to indicate that radio 1431 * transmitter is killed. 1432 */ 1433 ((struct ieee80211_txpower *)data)->i_val = 1434 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 1435 IEEE80211_TXPOWER_MIN : sc->sc_ic.ic_txpower; 1436 break; 1437 1438 case SIOCG80211AUTH: 1439 ((struct ieee80211_auth *)data)->i_authtype = sc->authmode; 1440 break; 1441 1442 case SIOCS80211AUTH: 1443 /* only super-user can do that! */ 1444 if ((error = suser(curproc, 0)) != 0) 1445 break; 1446 1447 sc->authmode = ((struct ieee80211_auth *)data)->i_authtype; 1448 break; 1449 1450 default: 1451 error = ieee80211_ioctl(ifp, cmd, data); 1452 } 1453 1454 if (error == ENETRESET) { 1455 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1456 (IFF_UP | IFF_RUNNING)) 1457 ipw_init(ifp); 1458 error = 0; 1459 } 1460 1461 splx(s); 1462 return error; 1463} 1464 1465uint32_t 1466ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1467{ 1468 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1469} 1470 1471void 1472ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1473{ 1474 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1475} 1476 1477int 1478ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1479{ 1480 uint32_t addr, info; 1481 uint16_t count, size; 1482 uint32_t total; 1483 1484 /* addr[4] + count[2] + size[2] */ 1485 addr = MEM_READ_4(sc, sc->table2_base + off); 1486 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1487 1488 count = info >> 16; 1489 size = info & 0xffff; 1490 total = count * size; 1491 1492 if (total > *len) { 1493 *len = total; 1494 return EINVAL; 1495 } 1496 1497 *len = total; 1498 ipw_read_mem_1(sc, addr, buf, total); 1499 1500 return 0; 1501} 1502 1503void 1504ipw_stop_master(struct ipw_softc *sc) 1505{ 1506 int ntries; 1507 1508 /* disable interrupts */ 1509 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1510 1511 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1512 for (ntries = 0; ntries < 50; ntries++) { 1513 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1514 break; 1515 DELAY(10); 1516 } 1517 if (ntries == 50) 1518 printf("%s: timeout waiting for master\n", 1519 sc->sc_dev.dv_xname); 1520 1521 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1522 IPW_RST_PRINCETON_RESET); 1523 1524 sc->flags &= ~IPW_FLAG_FW_INITED; 1525} 1526 1527int 1528ipw_reset(struct ipw_softc *sc) 1529{ 1530 int ntries; 1531 1532 ipw_stop_master(sc); 1533 1534 /* move adapter to D0 state */ 1535 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1536 IPW_CTL_INIT); 1537 1538 /* wait for clock stabilization */ 1539 for (ntries = 0; ntries < 1000; ntries++) { 1540 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1541 break; 1542 DELAY(200); 1543 } 1544 if (ntries == 1000) 1545 return EIO; 1546 1547 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1548 IPW_RST_SW_RESET); 1549 1550 DELAY(10); 1551 1552 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1553 IPW_CTL_INIT); 1554 1555 return 0; 1556} 1557 1558int 1559ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1560{ 1561 int ntries; 1562 1563 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1564 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1565 1566 MEM_WRITE_2(sc, 0x220000, 0x0703); 1567 MEM_WRITE_2(sc, 0x220000, 0x0707); 1568 1569 MEM_WRITE_1(sc, 0x210014, 0x72); 1570 MEM_WRITE_1(sc, 0x210014, 0x72); 1571 1572 MEM_WRITE_1(sc, 0x210000, 0x40); 1573 MEM_WRITE_1(sc, 0x210000, 0x00); 1574 MEM_WRITE_1(sc, 0x210000, 0x40); 1575 1576 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1577 1578 MEM_WRITE_1(sc, 0x210000, 0x00); 1579 MEM_WRITE_1(sc, 0x210000, 0x00); 1580 MEM_WRITE_1(sc, 0x210000, 0x80); 1581 1582 MEM_WRITE_2(sc, 0x220000, 0x0703); 1583 MEM_WRITE_2(sc, 0x220000, 0x0707); 1584 1585 MEM_WRITE_1(sc, 0x210014, 0x72); 1586 MEM_WRITE_1(sc, 0x210014, 0x72); 1587 1588 MEM_WRITE_1(sc, 0x210000, 0x00); 1589 MEM_WRITE_1(sc, 0x210000, 0x80); 1590 1591 for (ntries = 0; ntries < 100; ntries++) { 1592 if (MEM_READ_1(sc, 0x210000) & 1) 1593 break; 1594 DELAY(1000); 1595 } 1596 if (ntries == 100) { 1597 printf("%s: timeout waiting for ucode to initialize\n", 1598 sc->sc_dev.dv_xname); 1599 return EIO; 1600 } 1601 1602 MEM_WRITE_4(sc, 0x3000e0, 0); 1603 1604 return 0; 1605} 1606 1607/* set of macros to handle unaligned little endian data in firmware image */ 1608#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1609#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1610int 1611ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1612{ 1613 u_char *p, *end; 1614 uint32_t dst; 1615 uint16_t len; 1616 int error; 1617 1618 p = fw; 1619 end = fw + size; 1620 while (p < end) { 1621 if (p + 6 > end) 1622 return EINVAL; 1623 1624 dst = GETLE32(p); p += 4; 1625 len = GETLE16(p); p += 2; 1626 1627 if (p + len > end) 1628 return EINVAL; 1629 1630 ipw_write_mem_1(sc, dst, p, len); 1631 p += len; 1632 } 1633 1634 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1635 IPW_IO_LED_OFF); 1636 1637 /* allow interrupts so we know when the firmware is inited */ 1638 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1639 1640 /* tell the adapter to initialize the firmware */ 1641 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1642 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1643 IPW_CTL_ALLOW_STANDBY); 1644 1645 /* wait at most one second for firmware initialization to complete */ 1646 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1647 printf("%s: timeout waiting for firmware initialization to " 1648 "complete\n", sc->sc_dev.dv_xname); 1649 return error; 1650 } 1651 1652 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1653 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1654 1655 return 0; 1656} 1657 1658int 1659ipw_read_firmware(struct ipw_softc *sc, struct ipw_firmware *fw) 1660{ 1661 struct ipw_firmware_hdr *hdr; 1662 const char *name; 1663 u_char *p; 1664 size_t size; 1665 int error; 1666 1667 switch (sc->sc_ic.ic_opmode) { 1668 case IEEE80211_M_STA: 1669 case IEEE80211_M_HOSTAP: 1670 name = "ipw-bss"; 1671 break; 1672 1673 case IEEE80211_M_IBSS: 1674 case IEEE80211_M_AHDEMO: 1675 name = "ipw-ibss"; 1676 break; 1677 1678 case IEEE80211_M_MONITOR: 1679 name = "ipw-monitor"; 1680 break; 1681 } 1682 1683 if ((error = loadfirmware(name, &fw->data, &size)) != 0) 1684 return error; 1685 1686 if (size < sizeof (struct ipw_firmware_hdr)) { 1687 error = EINVAL; 1688 goto fail; 1689 } 1690 1691 p = fw->data; 1692 hdr = (struct ipw_firmware_hdr *)p; 1693 fw->main_size = letoh32(hdr->main_size); 1694 fw->ucode_size = letoh32(hdr->ucode_size); 1695 1696 p += sizeof (struct ipw_firmware_hdr); 1697 size -= sizeof (struct ipw_firmware_hdr); 1698 1699 if (size < fw->main_size + fw->ucode_size) { 1700 error = EINVAL; 1701 goto fail; 1702 } 1703 1704 fw->main = p; 1705 fw->ucode = p + fw->main_size; 1706 1707 return 0; 1708 1709fail: free(fw->data, M_DEVBUF); 1710 return error; 1711} 1712 1713int 1714ipw_config(struct ipw_softc *sc) 1715{ 1716 struct ieee80211com *ic = &sc->sc_ic; 1717 struct ifnet *ifp = &ic->ic_if; 1718 struct ipw_security security; 1719 struct ieee80211_wepkey *k; 1720 struct ipw_wep_key wepkey; 1721 struct ipw_scan_options options; 1722 struct ipw_configuration config; 1723 uint32_t data; 1724 int error, i; 1725 1726 switch (ic->ic_opmode) { 1727 case IEEE80211_M_STA: 1728 case IEEE80211_M_HOSTAP: 1729 data = htole32(IPW_MODE_BSS); 1730 break; 1731 1732 case IEEE80211_M_IBSS: 1733 case IEEE80211_M_AHDEMO: 1734 data = htole32(IPW_MODE_IBSS); 1735 break; 1736 1737 case IEEE80211_M_MONITOR: 1738 data = htole32(IPW_MODE_MONITOR); 1739 break; 1740 } 1741 DPRINTF(("Setting mode to %u\n", letoh32(data))); 1742 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1743 if (error != 0) 1744 return error; 1745 1746 if (ic->ic_opmode == IEEE80211_M_IBSS || 1747 ic->ic_opmode == IEEE80211_M_MONITOR) { 1748 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1749 DPRINTF(("Setting channel to %u\n", letoh32(data))); 1750 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1751 if (error != 0) 1752 return error; 1753 } 1754 1755 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1756 DPRINTF(("Enabling adapter\n")); 1757 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1758 } 1759 1760 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 1761 DPRINTF(("Setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 1762 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1763 IEEE80211_ADDR_LEN); 1764 if (error != 0) 1765 return error; 1766 1767 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1768 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1769 if (ic->ic_opmode == IEEE80211_M_IBSS) 1770 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1771 if (ifp->if_flags & IFF_PROMISC) 1772 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1773 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1774 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1775 DPRINTF(("Setting configuration 0x%x\n", config.flags)); 1776 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1777 if (error != 0) 1778 return error; 1779 1780 data = htole32(0x3); /* 1, 2 */ 1781 DPRINTF(("Setting basic tx rates to 0x%x\n", letoh32(data))); 1782 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1783 if (error != 0) 1784 return error; 1785 1786 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1787 DPRINTF(("Setting tx rates to 0x%x\n", letoh32(data))); 1788 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1789 if (error != 0) 1790 return error; 1791 1792 data = htole32(IPW_POWER_MODE_CAM); 1793 DPRINTF(("Setting power mode to %u\n", letoh32(data))); 1794 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1795 if (error != 0) 1796 return error; 1797 1798 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1799 data = htole32(32); /* default value */ 1800 DPRINTF(("Setting tx power index to %u\n", letoh32(data))); 1801 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1802 sizeof data); 1803 if (error != 0) 1804 return error; 1805 } 1806 1807 data = htole32(ic->ic_rtsthreshold); 1808 DPRINTF(("Setting RTS threshold to %u\n", letoh32(data))); 1809 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1810 if (error != 0) 1811 return error; 1812 1813 data = htole32(ic->ic_fragthreshold); 1814 DPRINTF(("Setting frag threshold to %u\n", letoh32(data))); 1815 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1816 if (error != 0) 1817 return error; 1818 1819#ifdef IPW_DEBUG 1820 if (ipw_debug > 0) { 1821 printf("Setting ESSID to "); 1822 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1823 printf("\n"); 1824 } 1825#endif 1826 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1827 ic->ic_des_esslen); 1828 if (error != 0) 1829 return error; 1830 1831 /* no mandatory BSSID */ 1832 DPRINTF(("Setting mandatory BSSID to null\n")); 1833 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1834 if (error != 0) 1835 return error; 1836 1837 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1838 DPRINTF(("Setting adapter BSSID to %s\n", 1839 ether_sprintf(ic->ic_des_bssid))); 1840 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1841 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1842 if (error != 0) 1843 return error; 1844 } 1845 1846 bzero(&security, sizeof security); 1847 security.authmode = (sc->authmode == IEEE80211_AUTH_SHARED) ? 1848 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 1849 security.ciphers = htole32(IPW_CIPHER_NONE); 1850 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1851 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1852 sizeof security); 1853 if (error != 0) 1854 return error; 1855 1856 if (ic->ic_flags & IEEE80211_F_WEPON) { 1857 k = ic->ic_nw_keys; 1858 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1859 if (k->wk_len == 0) 1860 continue; 1861 1862 wepkey.idx = i; 1863 wepkey.len = k->wk_len; 1864 bzero(wepkey.key, sizeof wepkey.key); 1865 bcopy(k->wk_key, wepkey.key, k->wk_len); 1866 DPRINTF(("Setting wep key index %u len %u\n", 1867 wepkey.idx, wepkey.len)); 1868 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1869 sizeof wepkey); 1870 if (error != 0) 1871 return error; 1872 } 1873 1874 data = htole32(ic->ic_wep_txkey); 1875 DPRINTF(("Setting wep tx key index to %u\n", letoh32(data))); 1876 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1877 sizeof data); 1878 if (error != 0) 1879 return error; 1880 } 1881 1882 data = htole32((ic->ic_flags & IEEE80211_F_WEPON) ? IPW_WEPON : 0); 1883 DPRINTF(("Setting wep flags to 0x%x\n", letoh32(data))); 1884 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1885 if (error != 0) 1886 return error; 1887 1888 if (ic->ic_opmode == IEEE80211_M_IBSS || 1889 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1890 data = htole32(ic->ic_lintval); 1891 DPRINTF(("Setting beacon interval to %u\n", letoh32(data))); 1892 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1893 sizeof data); 1894 if (error != 0) 1895 return error; 1896 } 1897 1898 options.flags = htole32(0); 1899 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1900 DPRINTF(("Setting scan options to 0x%x\n", letoh32(options.flags))); 1901 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1902 if (error != 0) 1903 return error; 1904 1905 /* finally, enable adapter (start scanning for an access point) */ 1906 DPRINTF(("Enabling adapter\n")); 1907 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1908} 1909 1910int 1911ipw_init(struct ifnet *ifp) 1912{ 1913 struct ipw_softc *sc = ifp->if_softc; 1914 struct ipw_firmware fw; 1915 int error; 1916 1917 ipw_stop(ifp, 0); 1918 1919 if ((error = ipw_reset(sc)) != 0) { 1920 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 1921 goto fail1; 1922 } 1923 1924 if ((error = ipw_read_firmware(sc, &fw)) != NULL) { 1925 printf("%s: could not read firmware\n", sc->sc_dev.dv_xname); 1926 goto fail1; 1927 } 1928 1929 if ((error = ipw_load_ucode(sc, fw.ucode, fw.ucode_size)) != 0) { 1930 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 1931 goto fail2; 1932 } 1933 1934 ipw_stop_master(sc); 1935 1936 /* 1937 * Setup tx, rx and status rings. 1938 */ 1939 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1940 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1941 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1942 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1943 sc->txold = IPW_NTBD - 1; /* latest bd index ack by firmware */ 1944 sc->txcur = 0; /* bd index to write to */ 1945 sc->txfree = IPW_NTBD - 2; 1946 1947 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1948 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1949 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1950 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1951 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1952 1953 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1954 sc->status_map->dm_segs[0].ds_addr); 1955 1956 if ((error = ipw_load_firmware(sc, fw.main, fw.main_size)) != 0) { 1957 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 1958 goto fail2; 1959 } 1960 1961 sc->flags |= IPW_FLAG_FW_INITED; 1962 1963 /* retrieve information tables base addresses */ 1964 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 1965 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 1966 1967 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 1968 1969 if ((error = ipw_config(sc)) != 0) { 1970 printf("%s: device configuration failed\n", 1971 sc->sc_dev.dv_xname); 1972 goto fail2; 1973 } 1974 1975 ifp->if_flags &= ~IFF_OACTIVE; 1976 ifp->if_flags |= IFF_RUNNING; 1977 1978 return 0; 1979 1980fail2: free(fw.data, M_DEVBUF); 1981fail1: ipw_stop(ifp, 0); 1982 1983 return error; 1984} 1985 1986void 1987ipw_stop(struct ifnet *ifp, int disable) 1988{ 1989 struct ipw_softc *sc = ifp->if_softc; 1990 struct ieee80211com *ic = &sc->sc_ic; 1991 int i; 1992 1993 ipw_stop_master(sc); 1994 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1995 1996 ifp->if_timer = 0; 1997 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1998 1999 /* 2000 * Release tx buffers. 2001 */ 2002 for (i = 0; i < IPW_NTBD; i++) 2003 ipw_release_sbd(sc, &sc->stbd_list[i]); 2004 2005 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2006} 2007 2008void 2009ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2010 bus_size_t count) 2011{ 2012 for (; count > 0; offset++, datap++, count--) { 2013 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2014 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2015 } 2016} 2017 2018void 2019ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2020 bus_size_t count) 2021{ 2022 for (; count > 0; offset++, datap++, count--) { 2023 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2024 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2025 } 2026} 2027 2028struct cfdriver ipw_cd = { 2029 0, "ipw", DV_IFNET 2030}; 2031