if_ipw.c revision 1.47
1/* $OpenBSD: if_ipw.c,v 1.47 2005/04/17 13:41:46 damien Exp $ */ 2 3/*- 4 * Copyright (c) 2004, 2005 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/*- 31 * Intel(R) PRO/Wireless 2100 MiniPCI driver 32 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 33 */ 34 35#include "bpfilter.h" 36 37#include <sys/param.h> 38#include <sys/sockio.h> 39#include <sys/sysctl.h> 40#include <sys/mbuf.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43#include <sys/systm.h> 44#include <sys/malloc.h> 45#include <sys/conf.h> 46#include <sys/device.h> 47 48#include <machine/bus.h> 49#include <machine/endian.h> 50#include <machine/intr.h> 51 52#include <dev/pci/pcireg.h> 53#include <dev/pci/pcivar.h> 54#include <dev/pci/pcidevs.h> 55 56#if NBPFILTER > 0 57#include <net/bpf.h> 58#endif 59#include <net/if.h> 60#include <net/if_arp.h> 61#include <net/if_dl.h> 62#include <net/if_media.h> 63#include <net/if_types.h> 64 65#include <netinet/in.h> 66#include <netinet/in_systm.h> 67#include <netinet/in_var.h> 68#include <netinet/if_ether.h> 69#include <netinet/ip.h> 70 71#include <net80211/ieee80211_var.h> 72#include <net80211/ieee80211_radiotap.h> 73 74#include <dev/pci/if_ipwreg.h> 75#include <dev/pci/if_ipwvar.h> 76 77static const struct ieee80211_rateset ipw_rateset_11b = 78 { 4, { 2, 4, 11, 22 } }; 79 80int ipw_match(struct device *, void *, void *); 81void ipw_attach(struct device *, struct device *, void *); 82int ipw_detach(struct device *, int); 83void ipw_power(int, void *); 84int ipw_dma_alloc(struct ipw_softc *); 85void ipw_release(struct ipw_softc *); 86int ipw_media_change(struct ifnet *); 87void ipw_media_status(struct ifnet *, struct ifmediareq *); 88int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 89u_int16_t ipw_read_prom_word(struct ipw_softc *, u_int8_t); 90void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 91void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 92void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 93 struct ipw_soft_bd *, struct ipw_soft_buf *); 94void ipw_notification_intr(struct ipw_softc *, struct ipw_soft_buf *); 95void ipw_rx_intr(struct ipw_softc *); 96void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 97void ipw_tx_intr(struct ipw_softc *); 98int ipw_intr(void *); 99int ipw_cmd(struct ipw_softc *, u_int32_t, void *, u_int32_t); 100int ipw_tx_start(struct ifnet *, struct mbuf *, struct ieee80211_node *); 101void ipw_start(struct ifnet *); 102void ipw_watchdog(struct ifnet *); 103int ipw_get_table1(struct ipw_softc *, u_int32_t *); 104int ipw_get_radio(struct ipw_softc *, int *); 105int ipw_ioctl(struct ifnet *, u_long, caddr_t); 106u_int32_t ipw_read_table1(struct ipw_softc *, u_int32_t); 107void ipw_write_table1(struct ipw_softc *, u_int32_t, u_int32_t); 108int ipw_read_table2(struct ipw_softc *, u_int32_t, void *, u_int32_t *); 109void ipw_stop_master(struct ipw_softc *); 110int ipw_reset(struct ipw_softc *); 111int ipw_load_ucode(struct ipw_softc *, u_char *, int); 112int ipw_load_firmware(struct ipw_softc *, u_char *, int); 113int ipw_read_firmware(struct ipw_softc *, struct ipw_firmware *); 114int ipw_config(struct ipw_softc *); 115int ipw_init(struct ifnet *); 116void ipw_stop(struct ifnet *, int); 117void ipw_read_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, bus_size_t); 118void ipw_write_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, bus_size_t); 119 120static __inline u_int8_t MEM_READ_1(struct ipw_softc *sc, u_int32_t addr) 121{ 122 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 123 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 124} 125 126static __inline u_int32_t MEM_READ_4(struct ipw_softc *sc, u_int32_t addr) 127{ 128 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 129 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 130} 131 132#ifdef IPW_DEBUG 133#define DPRINTF(x) if (ipw_debug > 0) printf x 134#define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 135int ipw_debug = 0; 136#else 137#define DPRINTF(x) 138#define DPRINTFN(n, x) 139#endif 140 141struct cfattach ipw_ca = { 142 sizeof (struct ipw_softc), ipw_match, ipw_attach, ipw_detach 143}; 144 145int 146ipw_match(struct device *parent, void *match, void *aux) 147{ 148 struct pci_attach_args *pa = aux; 149 150 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 151 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 152 return 1; 153 154 return 0; 155} 156 157/* Base Address Register */ 158#define IPW_PCI_BAR0 0x10 159 160void 161ipw_attach(struct device *parent, struct device *self, void *aux) 162{ 163 struct ipw_softc *sc = (struct ipw_softc *)self; 164 struct ieee80211com *ic = &sc->sc_ic; 165 struct ifnet *ifp = &ic->ic_if; 166 struct pci_attach_args *pa = aux; 167 const char *intrstr; 168 bus_space_tag_t memt; 169 bus_space_handle_t memh; 170 bus_addr_t base; 171 pci_intr_handle_t ih; 172 pcireg_t data; 173 u_int16_t val; 174 int error, i; 175 176 sc->sc_pct = pa->pa_pc; 177 sc->sc_pcitag = pa->pa_tag, 178 179 /* clear device specific PCI configuration register 0x41 */ 180 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 181 data &= ~0x0000ff00; 182 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 183 184 /* enable bus-mastering */ 185 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 186 data |= PCI_COMMAND_MASTER_ENABLE; 187 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, data); 188 189 /* map the register window */ 190 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 191 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 192 if (error != 0) { 193 printf(": could not map memory space\n"); 194 return; 195 } 196 197 sc->sc_st = memt; 198 sc->sc_sh = memh; 199 sc->sc_dmat = pa->pa_dmat; 200 201 /* disable interrupts */ 202 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 203 204 if (pci_intr_map(pa, &ih) != 0) { 205 printf(": could not map interrupt\n"); 206 return; 207 } 208 209 intrstr = pci_intr_string(sc->sc_pct, ih); 210 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 211 sc->sc_dev.dv_xname); 212 if (sc->sc_ih == NULL) { 213 printf(": could not establish interrupt"); 214 if (intrstr != NULL) 215 printf(" at %s", intrstr); 216 printf("\n"); 217 return; 218 } 219 printf(": %s", intrstr); 220 221 if (ipw_reset(sc) != 0) { 222 printf(": could not reset adapter\n"); 223 return; 224 } 225 226 if (ipw_dma_alloc(sc) != 0) { 227 printf(": failed to allocate DMA resources\n"); 228 return; 229 } 230 231 ic->ic_phytype = IEEE80211_T_DS; 232 ic->ic_opmode = IEEE80211_M_STA; 233 ic->ic_state = IEEE80211_S_INIT; 234 235 /* set device capabilities */ 236 ic->ic_caps = IEEE80211_C_IBSS | IEEE80211_C_MONITOR | 237 IEEE80211_C_PMGT | IEEE80211_C_TXPMGT | IEEE80211_C_WEP | 238 IEEE80211_C_SHPREAMBLE | IEEE80211_C_SCANALL; 239 240 /* read MAC address from EEPROM */ 241 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 242 ic->ic_myaddr[0] = val >> 8; 243 ic->ic_myaddr[1] = val & 0xff; 244 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 245 ic->ic_myaddr[2] = val >> 8; 246 ic->ic_myaddr[3] = val & 0xff; 247 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 248 ic->ic_myaddr[4] = val >> 8; 249 ic->ic_myaddr[5] = val & 0xff; 250 251 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 252 253 /* set supported .11b rates */ 254 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 255 256 /* set supported .11b channels (1 through 14) */ 257 for (i = 1; i <= 14; i++) { 258 ic->ic_channels[i].ic_freq = 259 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 260 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 261 } 262 263 /* default to authmode OPEN */ 264 sc->authmode = IEEE80211_AUTH_OPEN; 265 266 /* IBSS channel undefined for now */ 267 ic->ic_ibss_chan = &ic->ic_channels[0]; 268 269 ifp->if_softc = sc; 270 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 271 ifp->if_init = ipw_init; 272 ifp->if_ioctl = ipw_ioctl; 273 ifp->if_start = ipw_start; 274 ifp->if_watchdog = ipw_watchdog; 275 IFQ_SET_READY(&ifp->if_snd); 276 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 277 278 if_attach(ifp); 279 ieee80211_ifattach(ifp); 280 /* override state transition machine */ 281 sc->sc_newstate = ic->ic_newstate; 282 ic->ic_newstate = ipw_newstate; 283 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 284 285 sc->powerhook = powerhook_establish(ipw_power, sc); 286 287#if NBPFILTER > 0 288 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 289 sizeof (struct ieee80211_frame) + 64); 290 291 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 292 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 293 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 294 295 sc->sc_txtap_len = sizeof sc->sc_txtapu; 296 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 297 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 298#endif 299} 300 301int 302ipw_detach(struct device* self, int flags) 303{ 304 struct ipw_softc *sc = (struct ipw_softc *)self; 305 struct ifnet *ifp = &sc->sc_ic.ic_if; 306 307 ipw_stop(ifp, 1); 308 309#if NBPFILTER > 0 310 bpfdetach(ifp); 311#endif 312 ieee80211_ifdetach(ifp); 313 if_detach(ifp); 314 315 ipw_release(sc); 316 317 if (sc->sc_ih != NULL) { 318 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 319 sc->sc_ih = NULL; 320 } 321 322 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 323 324 return 0; 325} 326 327void 328ipw_power(int why, void *arg) 329{ 330 struct ipw_softc *sc = arg; 331 struct ifnet *ifp; 332 pcireg_t data; 333 334 if (why != PWR_RESUME) 335 return; 336 337 /* clear device specific PCI configuration register 0x41 */ 338 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 339 data &= ~0x0000ff00; 340 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 341 342 ifp = &sc->sc_ic.ic_if; 343 if (ifp->if_flags & IFF_UP) { 344 ifp->if_init(ifp); 345 if (ifp->if_flags & IFF_RUNNING) 346 ifp->if_start(ifp); 347 } 348} 349 350int 351ipw_dma_alloc(struct ipw_softc *sc) 352{ 353 struct ipw_soft_bd *sbd; 354 struct ipw_soft_hdr *shdr; 355 struct ipw_soft_buf *sbuf; 356 int i, nsegs, error; 357 358 /* 359 * Allocate and map tx ring 360 */ 361 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 362 BUS_DMA_NOWAIT, &sc->tbd_map); 363 if (error != 0) { 364 printf("%s: could not create tx ring DMA map\n", 365 sc->sc_dev.dv_xname); 366 goto fail; 367 } 368 369 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 370 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 371 if (error != 0) { 372 printf("%s: could not allocate tx ring DMA memory\n", 373 sc->sc_dev.dv_xname); 374 goto fail; 375 } 376 377 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 378 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 379 if (error != 0) { 380 printf("%s: could not map tx ring DMA memory\n", 381 sc->sc_dev.dv_xname); 382 goto fail; 383 } 384 385 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 386 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 387 if (error != 0) { 388 printf("%s: could not load tx ring DMA map\n", 389 sc->sc_dev.dv_xname); 390 goto fail; 391 } 392 393 /* 394 * Allocate and map rx ring 395 */ 396 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 397 BUS_DMA_NOWAIT, &sc->rbd_map); 398 if (error != 0) { 399 printf("%s: could not create rx ring DMA map\n", 400 sc->sc_dev.dv_xname); 401 goto fail; 402 } 403 404 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 405 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 406 if (error != 0) { 407 printf("%s: could not allocate rx ring DMA memory\n", 408 sc->sc_dev.dv_xname); 409 goto fail; 410 } 411 412 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 413 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 414 if (error != 0) { 415 printf("%s: could not map rx ring DMA memory\n", 416 sc->sc_dev.dv_xname); 417 goto fail; 418 } 419 420 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 421 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 422 if (error != 0) { 423 printf("%s: could not load tx ring DMA map\n", 424 sc->sc_dev.dv_xname); 425 goto fail; 426 } 427 428 /* 429 * Allocate and map status ring 430 */ 431 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 432 0, BUS_DMA_NOWAIT, &sc->status_map); 433 if (error != 0) { 434 printf("%s: could not create status ring DMA map\n", 435 sc->sc_dev.dv_xname); 436 goto fail; 437 } 438 439 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 440 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 441 if (error != 0) { 442 printf("%s: could not allocate status ring DMA memory\n", 443 sc->sc_dev.dv_xname); 444 goto fail; 445 } 446 447 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 448 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 449 if (error != 0) { 450 printf("%s: could not map status ring DMA memory\n", 451 sc->sc_dev.dv_xname); 452 goto fail; 453 } 454 455 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 456 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 457 if (error != 0) { 458 printf("%s: could not load status ring DMA map\n", 459 sc->sc_dev.dv_xname); 460 goto fail; 461 } 462 463 /* 464 * Allocate command DMA map 465 */ 466 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 467 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 468 if (error != 0) { 469 printf("%s: could not create command DMA map\n", 470 sc->sc_dev.dv_xname); 471 goto fail; 472 } 473 474 /* 475 * Allocate headers DMA maps 476 */ 477 SLIST_INIT(&sc->free_shdr); 478 for (i = 0; i < IPW_NDATA; i++) { 479 shdr = &sc->shdr_list[i]; 480 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_hdr), 481 1, sizeof (struct ipw_hdr), 0, BUS_DMA_NOWAIT, &shdr->map); 482 if (error != 0) { 483 printf("%s: could not create header DMA map\n", 484 sc->sc_dev.dv_xname); 485 goto fail; 486 } 487 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 488 } 489 490 /* 491 * Allocate tx buffers DMA maps 492 */ 493 SLIST_INIT(&sc->free_sbuf); 494 for (i = 0; i < IPW_NDATA; i++) { 495 sbuf = &sc->tx_sbuf_list[i]; 496 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, IPW_MAX_NSEG, 497 MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 498 if (error != 0) { 499 printf("%s: could not create tx DMA map\n", 500 sc->sc_dev.dv_xname); 501 goto fail; 502 } 503 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 504 } 505 506 /* 507 * Initialize tx ring 508 */ 509 for (i = 0; i < IPW_NTBD; i++) { 510 sbd = &sc->stbd_list[i]; 511 sbd->bd = &sc->tbd_list[i]; 512 sbd->type = IPW_SBD_TYPE_NOASSOC; 513 } 514 515 /* 516 * Pre-allocate rx buffers and DMA maps 517 */ 518 for (i = 0; i < IPW_NRBD; i++) { 519 sbd = &sc->srbd_list[i]; 520 sbuf = &sc->rx_sbuf_list[i]; 521 sbd->bd = &sc->rbd_list[i]; 522 523 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 524 if (sbuf->m == NULL) { 525 printf("%s: could not allocate rx mbuf\n", 526 sc->sc_dev.dv_xname); 527 error = ENOMEM; 528 goto fail; 529 } 530 531 MCLGET(sbuf->m, M_DONTWAIT); 532 if (!(sbuf->m->m_flags & M_EXT)) { 533 m_freem(sbuf->m); 534 printf("%s: could not allocate rx mbuf cluster\n", 535 sc->sc_dev.dv_xname); 536 error = ENOMEM; 537 goto fail; 538 } 539 540 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 541 0, BUS_DMA_NOWAIT, &sbuf->map); 542 if (error != 0) { 543 printf("%s: could not create rx DMA map\n", 544 sc->sc_dev.dv_xname); 545 goto fail; 546 } 547 548 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 549 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 550 if (error != 0) { 551 printf("%s: could not map rx DMA memory\n", 552 sc->sc_dev.dv_xname); 553 goto fail; 554 } 555 556 sbd->type = IPW_SBD_TYPE_DATA; 557 sbd->priv = sbuf; 558 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 559 sbd->bd->len = htole32(MCLBYTES); 560 } 561 562 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 563 BUS_DMASYNC_PREWRITE); 564 565 return 0; 566 567fail: ipw_release(sc); 568 return error; 569} 570 571void 572ipw_release(struct ipw_softc *sc) 573{ 574 struct ipw_soft_buf *sbuf; 575 int i; 576 577 if (sc->tbd_map != NULL) { 578 if (sc->tbd_list != NULL) { 579 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 580 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 581 IPW_TBD_SZ); 582 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 583 } 584 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 585 } 586 587 if (sc->rbd_map != NULL) { 588 if (sc->rbd_list != NULL) { 589 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 590 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 591 IPW_RBD_SZ); 592 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 593 } 594 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 595 } 596 597 if (sc->status_map != NULL) { 598 if (sc->status_list != NULL) { 599 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 600 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 601 IPW_RBD_SZ); 602 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 603 } 604 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 605 } 606 607 if (sc->cmd_map != NULL) 608 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 609 610 for (i = 0; i < IPW_NDATA; i++) 611 bus_dmamap_destroy(sc->sc_dmat, sc->shdr_list[i].map); 612 613 for (i = 0; i < IPW_NDATA; i++) 614 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 615 616 for (i = 0; i < IPW_NRBD; i++) { 617 sbuf = &sc->rx_sbuf_list[i]; 618 if (sbuf->map != NULL) { 619 if (sbuf->m != NULL) { 620 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 621 m_freem(sbuf->m); 622 } 623 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 624 } 625 } 626} 627 628int 629ipw_media_change(struct ifnet *ifp) 630{ 631 int error; 632 633 error = ieee80211_media_change(ifp); 634 if (error != ENETRESET) 635 return error; 636 637 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 638 ipw_init(ifp); 639 640 return 0; 641} 642 643void 644ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 645{ 646 struct ipw_softc *sc = ifp->if_softc; 647 struct ieee80211com *ic = &sc->sc_ic; 648#define N(a) (sizeof (a) / sizeof (a[0])) 649 static const struct { 650 u_int32_t val; 651 int rate; 652 } rates[] = { 653 { IPW_RATE_DS1, 2 }, 654 { IPW_RATE_DS2, 4 }, 655 { IPW_RATE_DS5, 11 }, 656 { IPW_RATE_DS11, 22 }, 657 }; 658 u_int32_t val; 659 int rate, i; 660 661 imr->ifm_status = IFM_AVALID; 662 imr->ifm_active = IFM_IEEE80211; 663 if (ic->ic_state == IEEE80211_S_RUN) 664 imr->ifm_status |= IFM_ACTIVE; 665 666 /* read current transmission rate from adapter */ 667 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 668 val &= 0xf; 669 670 /* convert rate to 802.11 rate */ 671 for (i = 0; i < N(rates) && rates[i].val != val; i++); 672 rate = (i < N(rates)) ? rates[i].rate : 0; 673 674 imr->ifm_active |= IFM_IEEE80211_11B; 675 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 676 switch (ic->ic_opmode) { 677 case IEEE80211_M_STA: 678 break; 679 680 case IEEE80211_M_IBSS: 681 imr->ifm_active |= IFM_IEEE80211_IBSS; 682 break; 683 684 case IEEE80211_M_MONITOR: 685 imr->ifm_active |= IFM_IEEE80211_MONITOR; 686 break; 687 688 case IEEE80211_M_AHDEMO: 689 case IEEE80211_M_HOSTAP: 690 /* should not get there */ 691 break; 692 } 693#undef N 694} 695 696int 697ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 698{ 699 struct ipw_softc *sc = ic->ic_softc; 700 struct ieee80211_node *ni; 701 u_int8_t macaddr[IEEE80211_ADDR_LEN]; 702 u_int32_t len; 703 704 switch (nstate) { 705 case IEEE80211_S_RUN: 706 DELAY(100); /* firmware needs a short delay here */ 707 708 len = IEEE80211_ADDR_LEN; 709 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 710 711 ni = ieee80211_find_node(ic, macaddr); 712 if (ni == NULL) 713 break; 714 715 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 716 ieee80211_node_newstate(ni, IEEE80211_STA_BSS); 717 break; 718 719 case IEEE80211_S_INIT: 720 case IEEE80211_S_SCAN: 721 case IEEE80211_S_AUTH: 722 case IEEE80211_S_ASSOC: 723 break; 724 } 725 726 ic->ic_state = nstate; 727 return 0; 728} 729 730/* 731 * Read 16 bits at address 'addr' from the Microwire EEPROM. 732 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 733 */ 734u_int16_t 735ipw_read_prom_word(struct ipw_softc *sc, u_int8_t addr) 736{ 737 u_int32_t tmp; 738 u_int16_t val; 739 int n; 740 741 /* Clock C once before the first command */ 742 IPW_EEPROM_CTL(sc, 0); 743 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 744 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 745 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 746 747 /* Write start bit (1) */ 748 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 749 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 750 751 /* Write READ opcode (10) */ 752 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 753 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 754 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 755 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 756 757 /* Write address A7-A0 */ 758 for (n = 7; n >= 0; n--) { 759 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 760 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 761 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 762 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 763 } 764 765 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 766 767 /* Read data Q15-Q0 */ 768 val = 0; 769 for (n = 15; n >= 0; n--) { 770 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 771 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 772 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 773 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 774 } 775 776 IPW_EEPROM_CTL(sc, 0); 777 778 /* Clear Chip Select and clock C */ 779 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 780 IPW_EEPROM_CTL(sc, 0); 781 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 782 783 return letoh16(val); 784} 785 786void 787ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 788{ 789 struct ipw_cmd *cmd; 790 791 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 792 BUS_DMASYNC_POSTREAD); 793 794 cmd = mtod(sbuf->m, struct ipw_cmd *); 795 796 DPRINTFN(2, ("RX!CMD!%u!%u!%u!%u!%u\n", 797 letoh32(cmd->type), letoh32(cmd->subtype), letoh32(cmd->seq), 798 letoh32(cmd->len), letoh32(cmd->status))); 799 800 wakeup(sc); 801} 802 803void 804ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 805{ 806 struct ieee80211com *ic = &sc->sc_ic; 807 u_int32_t state; 808 809 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 810 BUS_DMASYNC_POSTREAD); 811 812 state = letoh32(*mtod(sbuf->m, u_int32_t *)); 813 814 DPRINTFN(2, ("RX!NEWSTATE!%u\n", state)); 815 816 switch (state) { 817 case IPW_STATE_ASSOCIATED: 818 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 819 break; 820 821 case IPW_STATE_SCANNING: 822 /* don't leave run state on background scan */ 823 if (ic->ic_state != IEEE80211_S_RUN) 824 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 825 826 ic->ic_flags |= IEEE80211_F_ASCAN; 827 break; 828 829 case IPW_STATE_SCAN_COMPLETE: 830 ic->ic_flags &= ~IEEE80211_F_ASCAN; 831 break; 832 833 case IPW_STATE_ASSOCIATION_LOST: 834 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 835 break; 836 837 case IPW_STATE_RADIO_DISABLED: 838 ipw_stop(&ic->ic_if, 1); 839 break; 840 } 841} 842 843void 844ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 845 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 846{ 847 struct ieee80211com *ic = &sc->sc_ic; 848 struct ifnet *ifp = &ic->ic_if; 849 struct mbuf *m; 850 struct ieee80211_frame *wh; 851 struct ieee80211_node *ni; 852 int error; 853 854 DPRINTFN(5, ("RX!DATA!%u!%u\n", letoh32(status->len), status->rssi)); 855 856 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 857 BUS_DMASYNC_POSTREAD); 858 859 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 860 861 /* Finalize mbuf */ 862 m = sbuf->m; 863 m->m_pkthdr.rcvif = ifp; 864 m->m_pkthdr.len = m->m_len = letoh32(status->len); 865 866#if NBPFILTER > 0 867 if (sc->sc_drvbpf != NULL) { 868 struct mbuf mb; 869 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 870 871 tap->wr_flags = 0; 872 tap->wr_antsignal = status->rssi; 873 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 874 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 875 876 M_DUP_PKTHDR(&mb, m); 877 mb.m_data = (caddr_t)tap; 878 mb.m_len = sc->sc_rxtap_len; 879 mb.m_next = m; 880 mb.m_pkthdr.len += mb.m_len; 881 bpf_mtap(sc->sc_drvbpf, &mb); 882 } 883#endif 884 885 wh = mtod(m, struct ieee80211_frame *); 886 887 ni = ieee80211_find_rxnode(ic, wh); 888 889 /* Send the frame to the upper layer */ 890 ieee80211_input(ifp, m, ni, status->rssi, 0); 891 892 ieee80211_release_node(ic, ni); 893 894 MGETHDR(m, M_DONTWAIT, MT_DATA); 895 if (m == NULL) { 896 printf("%s: could not allocate rx mbuf\n", 897 sc->sc_dev.dv_xname); 898 return; 899 } 900 MCLGET(m, M_DONTWAIT); 901 if (!(m->m_flags & M_EXT)) { 902 m_freem(m); 903 printf("%s: could not allocate rx mbuf cluster\n", 904 sc->sc_dev.dv_xname); 905 return; 906 } 907 908 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(m, void *), 909 MCLBYTES, NULL, BUS_DMA_NOWAIT); 910 if (error != 0) { 911 printf("%s: could not map rx DMA memory\n", 912 sc->sc_dev.dv_xname); 913 m_freem(m); 914 return; 915 } 916 917 sbuf->m = m; 918 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 919} 920 921void 922ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 923{ 924 DPRINTFN(2, ("RX!NOTIFICATION\n")); 925} 926 927void 928ipw_rx_intr(struct ipw_softc *sc) 929{ 930 struct ipw_status *status; 931 struct ipw_soft_bd *sbd; 932 struct ipw_soft_buf *sbuf; 933 u_int32_t r, i; 934 935 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 936 937 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 938 939 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 940 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 941 BUS_DMASYNC_POSTREAD); 942 943 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 944 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 945 BUS_DMASYNC_POSTREAD); 946 947 status = &sc->status_list[i]; 948 sbd = &sc->srbd_list[i]; 949 sbuf = sbd->priv; 950 951 switch (letoh16(status->code) & 0xf) { 952 case IPW_STATUS_CODE_COMMAND: 953 ipw_command_intr(sc, sbuf); 954 break; 955 956 case IPW_STATUS_CODE_NEWSTATE: 957 ipw_newstate_intr(sc, sbuf); 958 break; 959 960 case IPW_STATUS_CODE_DATA_802_3: 961 case IPW_STATUS_CODE_DATA_802_11: 962 ipw_data_intr(sc, status, sbd, sbuf); 963 break; 964 965 case IPW_STATUS_CODE_NOTIFICATION: 966 ipw_notification_intr(sc, sbuf); 967 break; 968 969 default: 970 printf("%s: unknown status code %u\n", 971 sc->sc_dev.dv_xname, letoh16(status->code)); 972 } 973 sbd->bd->flags = 0; 974 975 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 976 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 977 BUS_DMASYNC_PREWRITE); 978 } 979 980 /* Tell the firmware what we have processed */ 981 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 982 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 983} 984 985void 986ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 987{ 988 struct ieee80211com *ic = &sc->sc_ic; 989 struct ipw_soft_hdr *shdr; 990 struct ipw_soft_buf *sbuf; 991 992 switch (sbd->type) { 993 case IPW_SBD_TYPE_COMMAND: 994 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 995 break; 996 997 case IPW_SBD_TYPE_HEADER: 998 shdr = sbd->priv; 999 bus_dmamap_unload(sc->sc_dmat, shdr->map); 1000 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 1001 break; 1002 1003 case IPW_SBD_TYPE_DATA: 1004 sbuf = sbd->priv; 1005 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1006 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1007 1008 m_freem(sbuf->m); 1009 1010 if (sbuf->ni != NULL) 1011 ieee80211_release_node(ic, sbuf->ni); 1012 1013 /* kill watchdog timer */ 1014 sc->sc_tx_timer = 0; 1015 break; 1016 } 1017 sbd->type = IPW_SBD_TYPE_NOASSOC; 1018} 1019 1020void 1021ipw_tx_intr(struct ipw_softc *sc) 1022{ 1023 struct ifnet *ifp = &sc->sc_ic.ic_if; 1024 struct ipw_soft_bd *sbd; 1025 u_int32_t r, i; 1026 1027 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 1028 1029 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1030 sbd = &sc->stbd_list[i]; 1031 1032 if (sbd->type == IPW_SBD_TYPE_DATA) 1033 ifp->if_opackets++; 1034 1035 ipw_release_sbd(sc, sbd); 1036 sc->txfree++; 1037 } 1038 1039 /* Remember what the firmware has processed */ 1040 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1041 1042 /* Call start() since some buffer descriptors have been released */ 1043 ifp->if_flags &= ~IFF_OACTIVE; 1044 (*ifp->if_start)(ifp); 1045} 1046 1047int 1048ipw_intr(void *arg) 1049{ 1050 struct ipw_softc *sc = arg; 1051 u_int32_t r; 1052 1053 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) 1054 return 0; 1055 1056 /* Disable interrupts */ 1057 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1058 1059 DPRINTFN(8, ("INTR!0x%08x\n", r)); 1060 1061 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1062 printf("%s: fatal error\n", sc->sc_dev.dv_xname); 1063 ipw_stop(&sc->sc_ic.ic_if, 1); 1064 } 1065 1066 if (r & IPW_INTR_FW_INIT_DONE) { 1067 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1068 wakeup(sc); 1069 } 1070 1071 if (r & IPW_INTR_RX_TRANSFER) 1072 ipw_rx_intr(sc); 1073 1074 if (r & IPW_INTR_TX_TRANSFER) 1075 ipw_tx_intr(sc); 1076 1077 /* Acknowledge interrupts */ 1078 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1079 1080 /* Re-enable interrupts */ 1081 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1082 1083 return 1; 1084} 1085 1086int 1087ipw_cmd(struct ipw_softc *sc, u_int32_t type, void *data, u_int32_t len) 1088{ 1089 struct ipw_soft_bd *sbd; 1090 int error; 1091 1092 sbd = &sc->stbd_list[sc->txcur]; 1093 1094 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 1095 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 1096 if (error != 0) { 1097 printf("%s: could not map command DMA memory\n", 1098 sc->sc_dev.dv_xname); 1099 return error; 1100 } 1101 1102 sc->cmd.type = htole32(type); 1103 sc->cmd.subtype = htole32(0); 1104 sc->cmd.len = htole32(len); 1105 sc->cmd.seq = htole32(0); 1106 if (data != NULL) 1107 bcopy(data, sc->cmd.data, len); 1108 1109 sbd->type = IPW_SBD_TYPE_COMMAND; 1110 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1111 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1112 sbd->bd->nfrag = 1; 1113 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1114 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1115 1116 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1117 BUS_DMASYNC_PREWRITE); 1118 1119 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1120 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1121 BUS_DMASYNC_PREWRITE); 1122 1123 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1124 sc->txfree--; 1125 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1126 1127 DPRINTFN(2, ("TX!CMD!%u!%u!%u!%u\n", type, 0, 0, len)); 1128 1129 /* Wait at most one second for command to complete */ 1130 return tsleep(sc, 0, "ipwcmd", hz); 1131} 1132 1133int 1134ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 1135{ 1136 struct ipw_softc *sc = ifp->if_softc; 1137 struct ieee80211com *ic = &sc->sc_ic; 1138 struct ieee80211_frame *wh; 1139 struct ipw_soft_bd *sbd; 1140 struct ipw_soft_hdr *shdr; 1141 struct ipw_soft_buf *sbuf; 1142 struct mbuf *mnew; 1143 int error, i; 1144 1145 if (ic->ic_flags & IEEE80211_F_WEPON) { 1146 m = ieee80211_wep_crypt(ifp, m, 1); 1147 if (m == NULL) 1148 return ENOBUFS; 1149 } 1150 1151#if NBPFILTER > 0 1152 if (sc->sc_drvbpf != NULL) { 1153 struct mbuf mb; 1154 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1155 1156 tap->wt_flags = 0; 1157 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1158 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1159 1160 M_DUP_PKTHDR(&mb, m); 1161 mb.m_data = (caddr_t)tap; 1162 mb.m_len = sc->sc_txtap_len; 1163 mb.m_next = m; 1164 mb.m_pkthdr.len += mb.m_len; 1165 bpf_mtap(sc->sc_drvbpf, &mb); 1166 } 1167#endif 1168 1169 wh = mtod(m, struct ieee80211_frame *); 1170 1171 shdr = SLIST_FIRST(&sc->free_shdr); 1172 sbuf = SLIST_FIRST(&sc->free_sbuf); 1173 1174 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1175 shdr->hdr.subtype = htole32(0); 1176 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1177 shdr->hdr.encrypt = 0; 1178 shdr->hdr.keyidx = 0; 1179 shdr->hdr.keysz = 0; 1180 shdr->hdr.fragmentsz = htole16(0); 1181 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1182 if (ic->ic_opmode == IEEE80211_M_STA) 1183 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1184 else 1185 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1186 1187 /* trim IEEE802.11 header */ 1188 m_adj(m, sizeof (struct ieee80211_frame)); 1189 1190 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 1191 if (error != 0 && error != EFBIG) { 1192 printf("%s: could not map mbuf (error %d)\n", 1193 sc->sc_dev.dv_xname, error); 1194 m_freem(m); 1195 return error; 1196 } 1197 if (error != 0) { 1198 /* too many fragments, linearize */ 1199 1200 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1201 if (mnew == NULL) { 1202 m_freem(m); 1203 return ENOMEM; 1204 } 1205 1206 M_DUP_PKTHDR(mnew, m); 1207 MCLGET(mnew, M_DONTWAIT); 1208 if (!(mnew->m_flags & M_EXT)) { 1209 m_freem(m); 1210 m_freem(mnew); 1211 return ENOMEM; 1212 } 1213 1214 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 1215 m_freem(m); 1216 mnew->m_len = mnew->m_pkthdr.len; 1217 m = mnew; 1218 1219 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, 1220 BUS_DMA_NOWAIT); 1221 if (error != 0) { 1222 printf("%s: could not map mbuf (error %d)\n", 1223 sc->sc_dev.dv_xname, error); 1224 m_freem(m); 1225 return error; 1226 } 1227 } 1228 1229 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 1230 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 1231 if (error != 0) { 1232 printf("%s: could not map header DMA memory (error %d)\n", 1233 sc->sc_dev.dv_xname, error); 1234 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1235 m_freem(m); 1236 return error; 1237 } 1238 1239 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1240 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1241 1242 sbd = &sc->stbd_list[sc->txcur]; 1243 sbd->type = IPW_SBD_TYPE_HEADER; 1244 sbd->priv = shdr; 1245 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 1246 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1247 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1248 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1249 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1250 1251 DPRINTFN(5, ("TX!HDR!%u!%u!%u!%u", shdr->hdr.type, shdr->hdr.subtype, 1252 shdr->hdr.encrypted, shdr->hdr.encrypt)); 1253 DPRINTFN(5, ("!%s", ether_sprintf(shdr->hdr.src_addr))); 1254 DPRINTFN(5, ("!%s\n", ether_sprintf(shdr->hdr.dst_addr))); 1255 1256 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1257 sc->txcur * sizeof (struct ipw_bd), 1258 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1259 1260 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1261 sc->txfree--; 1262 1263 sbuf->m = m; 1264 sbuf->ni = ni; 1265 1266 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1267 sbd = &sc->stbd_list[sc->txcur]; 1268 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1269 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1270 sbd->bd->nfrag = 0; /* used only in first bd */ 1271 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1272 if (i == sbuf->map->dm_nsegs - 1) { 1273 sbd->type = IPW_SBD_TYPE_DATA; 1274 sbd->priv = sbuf; 1275 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1276 } else { 1277 sbd->type = IPW_SBD_TYPE_NOASSOC; 1278 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1279 } 1280 1281 DPRINTFN(5, ("TX!FRAG!%d!%d\n", i, 1282 sbuf->map->dm_segs[i].ds_len)); 1283 1284 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1285 sc->txcur * sizeof (struct ipw_bd), 1286 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1287 1288 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1289 sc->txfree--; 1290 } 1291 1292 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 1293 BUS_DMASYNC_PREWRITE); 1294 1295 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1296 BUS_DMASYNC_PREWRITE); 1297 1298 /* Inform firmware about this new packet */ 1299 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1300 1301 return 0; 1302} 1303 1304void 1305ipw_start(struct ifnet *ifp) 1306{ 1307 struct ipw_softc *sc = ifp->if_softc; 1308 struct ieee80211com *ic = &sc->sc_ic; 1309 struct mbuf *m; 1310 struct ieee80211_node *ni; 1311 1312 if (ic->ic_state != IEEE80211_S_RUN) 1313 return; 1314 1315 for (;;) { 1316 IF_DEQUEUE(&ifp->if_snd, m); 1317 if (m == NULL) 1318 break; 1319 1320 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1321 IF_PREPEND(&ifp->if_snd, m); 1322 ifp->if_flags |= IFF_OACTIVE; 1323 break; 1324 } 1325 1326#if NBPFILTER > 0 1327 if (ifp->if_bpf != NULL) 1328 bpf_mtap(ifp->if_bpf, m); 1329#endif 1330 1331 m = ieee80211_encap(ifp, m, &ni); 1332 if (m == NULL) 1333 continue; 1334 1335#if NBPFILTER > 0 1336 if (ic->ic_rawbpf != NULL) 1337 bpf_mtap(ic->ic_rawbpf, m); 1338#endif 1339 1340 if (ipw_tx_start(ifp, m, ni) != 0) { 1341 if (ni != NULL) 1342 ieee80211_release_node(ic, ni); 1343 ifp->if_oerrors++; 1344 break; 1345 } 1346 1347 /* start watchdog timer */ 1348 sc->sc_tx_timer = 5; 1349 ifp->if_timer = 1; 1350 } 1351} 1352 1353void 1354ipw_watchdog(struct ifnet *ifp) 1355{ 1356 struct ipw_softc *sc = ifp->if_softc; 1357 1358 ifp->if_timer = 0; 1359 1360 if (sc->sc_tx_timer > 0) { 1361 if (--sc->sc_tx_timer == 0) { 1362 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1363 ipw_stop(ifp, 1); 1364 ifp->if_oerrors++; 1365 return; 1366 } 1367 ifp->if_timer = 1; 1368 } 1369 1370 ieee80211_watchdog(ifp); 1371} 1372 1373int 1374ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1375{ 1376 struct ipw_softc *sc = ifp->if_softc; 1377 struct ieee80211com *ic = &sc->sc_ic; 1378 struct ifaddr *ifa; 1379 struct ifreq *ifr; 1380 int s, error = 0; 1381 1382 s = splnet(); 1383 1384 switch (cmd) { 1385 case SIOCSIFADDR: 1386 ifa = (struct ifaddr *)data; 1387 ifp->if_flags |= IFF_UP; 1388#ifdef INET 1389 if (ifa->ifa_addr->sa_family == AF_INET) 1390 arp_ifinit(&ic->ic_ac, ifa); 1391#endif 1392 /* FALLTHROUGH */ 1393 case SIOCSIFFLAGS: 1394 if (ifp->if_flags & IFF_UP) { 1395 if (!(ifp->if_flags & IFF_RUNNING)) 1396 ipw_init(ifp); 1397 } else { 1398 if (ifp->if_flags & IFF_RUNNING) 1399 ipw_stop(ifp, 1); 1400 } 1401 break; 1402 1403 case SIOCADDMULTI: 1404 case SIOCDELMULTI: 1405 ifr = (struct ifreq *)data; 1406 error = (cmd == SIOCADDMULTI) ? 1407 ether_addmulti(ifr, &ic->ic_ac) : 1408 ether_delmulti(ifr, &ic->ic_ac); 1409 1410 if (error == ENETRESET) 1411 error = 0; 1412 break; 1413 1414 case SIOCG80211TXPOWER: 1415 /* 1416 * If the hardware radio transmitter switch is off, report a 1417 * tx power of IEEE80211_TXPOWER_MIN to indicate that radio 1418 * transmitter is killed. 1419 */ 1420 ((struct ieee80211_txpower *)data)->i_val = 1421 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 1422 IEEE80211_TXPOWER_MIN : sc->sc_ic.ic_txpower; 1423 break; 1424 1425 case SIOCG80211AUTH: 1426 ((struct ieee80211_auth *)data)->i_authtype = sc->authmode; 1427 break; 1428 1429 case SIOCS80211AUTH: 1430 /* only super-user can do that! */ 1431 if ((error = suser(curproc, 0)) != 0) 1432 break; 1433 1434 sc->authmode = ((struct ieee80211_auth *)data)->i_authtype; 1435 break; 1436 1437 default: 1438 error = ieee80211_ioctl(ifp, cmd, data); 1439 } 1440 1441 if (error == ENETRESET) { 1442 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1443 (IFF_UP | IFF_RUNNING)) 1444 ipw_init(ifp); 1445 error = 0; 1446 } 1447 1448 splx(s); 1449 return error; 1450} 1451 1452u_int32_t 1453ipw_read_table1(struct ipw_softc *sc, u_int32_t off) 1454{ 1455 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1456} 1457 1458void 1459ipw_write_table1(struct ipw_softc *sc, u_int32_t off, u_int32_t info) 1460{ 1461 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1462} 1463 1464int 1465ipw_read_table2(struct ipw_softc *sc, u_int32_t off, void *buf, u_int32_t *len) 1466{ 1467 u_int32_t addr, info; 1468 u_int16_t count, size; 1469 u_int32_t total; 1470 1471 /* addr[4] + count[2] + size[2] */ 1472 addr = MEM_READ_4(sc, sc->table2_base + off); 1473 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1474 1475 count = info >> 16; 1476 size = info & 0xffff; 1477 total = count * size; 1478 1479 if (total > *len) { 1480 *len = total; 1481 return EINVAL; 1482 } 1483 1484 *len = total; 1485 ipw_read_mem_1(sc, addr, buf, total); 1486 1487 return 0; 1488} 1489 1490void 1491ipw_stop_master(struct ipw_softc *sc) 1492{ 1493 int ntries; 1494 1495 /* Disable interrupts */ 1496 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1497 1498 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1499 for (ntries = 0; ntries < 50; ntries++) { 1500 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1501 break; 1502 DELAY(10); 1503 } 1504 if (ntries == 50) 1505 printf("%s: timeout waiting for master\n", 1506 sc->sc_dev.dv_xname); 1507 1508 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1509 IPW_RST_PRINCETON_RESET); 1510 1511 sc->flags &= ~IPW_FLAG_FW_INITED; 1512} 1513 1514int 1515ipw_reset(struct ipw_softc *sc) 1516{ 1517 int ntries; 1518 1519 ipw_stop_master(sc); 1520 1521 /* Move adapter to D0 state */ 1522 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1523 IPW_CTL_INIT); 1524 1525 /* Wait for clock stabilization */ 1526 for (ntries = 0; ntries < 1000; ntries++) { 1527 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1528 break; 1529 DELAY(200); 1530 } 1531 if (ntries == 1000) 1532 return EIO; 1533 1534 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1535 IPW_RST_SW_RESET); 1536 1537 DELAY(10); 1538 1539 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1540 IPW_CTL_INIT); 1541 1542 return 0; 1543} 1544 1545int 1546ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1547{ 1548 int ntries; 1549 1550 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1551 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1552 1553 MEM_WRITE_2(sc, 0x220000, 0x0703); 1554 MEM_WRITE_2(sc, 0x220000, 0x0707); 1555 1556 MEM_WRITE_1(sc, 0x210014, 0x72); 1557 MEM_WRITE_1(sc, 0x210014, 0x72); 1558 1559 MEM_WRITE_1(sc, 0x210000, 0x40); 1560 MEM_WRITE_1(sc, 0x210000, 0x00); 1561 MEM_WRITE_1(sc, 0x210000, 0x40); 1562 1563 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1564 1565 MEM_WRITE_1(sc, 0x210000, 0x00); 1566 MEM_WRITE_1(sc, 0x210000, 0x00); 1567 MEM_WRITE_1(sc, 0x210000, 0x80); 1568 1569 MEM_WRITE_2(sc, 0x220000, 0x0703); 1570 MEM_WRITE_2(sc, 0x220000, 0x0707); 1571 1572 MEM_WRITE_1(sc, 0x210014, 0x72); 1573 MEM_WRITE_1(sc, 0x210014, 0x72); 1574 1575 MEM_WRITE_1(sc, 0x210000, 0x00); 1576 MEM_WRITE_1(sc, 0x210000, 0x80); 1577 1578 for (ntries = 0; ntries < 100; ntries++) { 1579 if (MEM_READ_1(sc, 0x210000) & 1) 1580 break; 1581 DELAY(1000); 1582 } 1583 if (ntries == 100) { 1584 printf("%s: timeout waiting for ucode to initialize\n", 1585 sc->sc_dev.dv_xname); 1586 return EIO; 1587 } 1588 1589 MEM_WRITE_4(sc, 0x3000e0, 0); 1590 1591 return 0; 1592} 1593 1594/* set of macros to handle unaligned little endian data in firmware image */ 1595#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1596#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1597int 1598ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1599{ 1600 u_char *p, *end; 1601 u_int32_t dst; 1602 u_int16_t len; 1603 int error; 1604 1605 p = fw; 1606 end = fw + size; 1607 while (p < end) { 1608 if (p + 6 > end) 1609 return EINVAL; 1610 1611 dst = GETLE32(p); p += 4; 1612 len = GETLE16(p); p += 2; 1613 1614 if (p + len > end) 1615 return EINVAL; 1616 1617 ipw_write_mem_1(sc, dst, p, len); 1618 p += len; 1619 } 1620 1621 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1622 IPW_IO_LED_OFF); 1623 1624 /* Allow interrupts so we know when the firmware is inited */ 1625 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1626 1627 /* Tell the adapter to initialize the firmware */ 1628 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1629 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1630 IPW_CTL_ALLOW_STANDBY); 1631 1632 /* Wait at most one second for firmware initialization to complete */ 1633 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1634 printf("%s: timeout waiting for firmware initialization to " 1635 "complete\n", sc->sc_dev.dv_xname); 1636 return error; 1637 } 1638 1639 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1640 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1641 1642 return 0; 1643} 1644 1645int 1646ipw_read_firmware(struct ipw_softc *sc, struct ipw_firmware *fw) 1647{ 1648 struct ipw_firmware_hdr *hdr; 1649 const char *name; 1650 u_char *p; 1651 size_t size; 1652 int error; 1653 1654 switch (sc->sc_ic.ic_opmode) { 1655 case IEEE80211_M_STA: 1656 case IEEE80211_M_HOSTAP: 1657 name = "ipw-bss"; 1658 break; 1659 1660 case IEEE80211_M_IBSS: 1661 case IEEE80211_M_AHDEMO: 1662 name = "ipw-ibss"; 1663 break; 1664 1665 case IEEE80211_M_MONITOR: 1666 name = "ipw-monitor"; 1667 break; 1668 } 1669 1670 if ((error = loadfirmware(name, &fw->data, &size)) != 0) 1671 return error; 1672 1673 if (size < sizeof (struct ipw_firmware_hdr)) { 1674 error = EINVAL; 1675 goto fail; 1676 } 1677 1678 p = fw->data; 1679 hdr = (struct ipw_firmware_hdr *)p; 1680 fw->main_size = letoh32(hdr->main_size); 1681 fw->ucode_size = letoh32(hdr->ucode_size); 1682 1683 p += sizeof (struct ipw_firmware_hdr); 1684 size -= sizeof (struct ipw_firmware_hdr); 1685 1686 if (size < fw->main_size + fw->ucode_size) { 1687 error = EINVAL; 1688 goto fail; 1689 } 1690 1691 fw->main = p; 1692 fw->ucode = p + fw->main_size; 1693 1694 return 0; 1695 1696fail: free(fw->data, M_DEVBUF); 1697 return error; 1698} 1699 1700int 1701ipw_config(struct ipw_softc *sc) 1702{ 1703 struct ieee80211com *ic = &sc->sc_ic; 1704 struct ifnet *ifp = &ic->ic_if; 1705 struct ipw_security security; 1706 struct ieee80211_wepkey *k; 1707 struct ipw_wep_key wepkey; 1708 struct ipw_scan_options options; 1709 struct ipw_configuration config; 1710 u_int32_t data; 1711 int error, i; 1712 1713 switch (ic->ic_opmode) { 1714 case IEEE80211_M_STA: 1715 case IEEE80211_M_HOSTAP: 1716 data = htole32(IPW_MODE_BSS); 1717 break; 1718 1719 case IEEE80211_M_IBSS: 1720 case IEEE80211_M_AHDEMO: 1721 data = htole32(IPW_MODE_IBSS); 1722 break; 1723 1724 case IEEE80211_M_MONITOR: 1725 data = htole32(IPW_MODE_MONITOR); 1726 break; 1727 } 1728 DPRINTF(("Setting mode to %u\n", letoh32(data))); 1729 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1730 if (error != 0) 1731 return error; 1732 1733 if (ic->ic_opmode == IEEE80211_M_IBSS || 1734 ic->ic_opmode == IEEE80211_M_MONITOR) { 1735 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1736 DPRINTF(("Setting channel to %u\n", letoh32(data))); 1737 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1738 if (error != 0) 1739 return error; 1740 } 1741 1742 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1743 DPRINTF(("Enabling adapter\n")); 1744 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1745 } 1746 1747 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 1748 DPRINTF(("Setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 1749 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1750 IEEE80211_ADDR_LEN); 1751 if (error != 0) 1752 return error; 1753 1754 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1755 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1756 if (ic->ic_opmode == IEEE80211_M_IBSS) 1757 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1758 if (ifp->if_flags & IFF_PROMISC) 1759 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1760 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1761 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1762 DPRINTF(("Setting configuration 0x%x\n", config.flags)); 1763 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1764 if (error != 0) 1765 return error; 1766 1767 data = htole32(0x3); /* 1, 2 */ 1768 DPRINTF(("Setting basic tx rates to 0x%x\n", letoh32(data))); 1769 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1770 if (error != 0) 1771 return error; 1772 1773 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1774 DPRINTF(("Setting tx rates to 0x%x\n", letoh32(data))); 1775 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1776 if (error != 0) 1777 return error; 1778 1779 data = htole32(IPW_POWER_MODE_CAM); 1780 DPRINTF(("Setting power mode to %u\n", letoh32(data))); 1781 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1782 if (error != 0) 1783 return error; 1784 1785 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1786 data = htole32(32); /* default value */ 1787 DPRINTF(("Setting tx power index to %u\n", letoh32(data))); 1788 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1789 sizeof data); 1790 if (error != 0) 1791 return error; 1792 } 1793 1794 data = htole32(ic->ic_rtsthreshold); 1795 DPRINTF(("Setting RTS threshold to %u\n", letoh32(data))); 1796 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1797 if (error != 0) 1798 return error; 1799 1800 data = htole32(ic->ic_fragthreshold); 1801 DPRINTF(("Setting frag threshold to %u\n", letoh32(data))); 1802 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1803 if (error != 0) 1804 return error; 1805 1806#ifdef IPW_DEBUG 1807 if (ipw_debug > 0) { 1808 printf("Setting ESSID to "); 1809 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1810 printf("\n"); 1811 } 1812#endif 1813 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1814 ic->ic_des_esslen); 1815 if (error != 0) 1816 return error; 1817 1818 /* no mandatory BSSID */ 1819 DPRINTF(("Setting mandatory BSSID to null\n")); 1820 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1821 if (error != 0) 1822 return error; 1823 1824 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1825 DPRINTF(("Setting adapter BSSID to %s\n", 1826 ether_sprintf(ic->ic_des_bssid))); 1827 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1828 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1829 if (error != 0) 1830 return error; 1831 } 1832 1833 bzero(&security, sizeof security); 1834 security.authmode = (sc->authmode == IEEE80211_AUTH_SHARED) ? 1835 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 1836 security.ciphers = htole32(IPW_CIPHER_NONE); 1837 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1838 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1839 sizeof security); 1840 if (error != 0) 1841 return error; 1842 1843 if (ic->ic_flags & IEEE80211_F_WEPON) { 1844 k = ic->ic_nw_keys; 1845 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1846 if (k->wk_len == 0) 1847 continue; 1848 1849 wepkey.idx = i; 1850 wepkey.len = k->wk_len; 1851 bzero(wepkey.key, sizeof wepkey.key); 1852 bcopy(k->wk_key, wepkey.key, k->wk_len); 1853 DPRINTF(("Setting wep key index %u len %u\n", 1854 wepkey.idx, wepkey.len)); 1855 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1856 sizeof wepkey); 1857 if (error != 0) 1858 return error; 1859 } 1860 1861 data = htole32(ic->ic_wep_txkey); 1862 DPRINTF(("Setting wep tx key index to %u\n", letoh32(data))); 1863 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1864 sizeof data); 1865 if (error != 0) 1866 return error; 1867 } 1868 1869 data = htole32((ic->ic_flags & IEEE80211_F_WEPON) ? IPW_WEPON : 0); 1870 DPRINTF(("Setting wep flags to 0x%x\n", letoh32(data))); 1871 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1872 if (error != 0) 1873 return error; 1874 1875 if (ic->ic_opmode == IEEE80211_M_IBSS || 1876 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1877 data = htole32(ic->ic_lintval); 1878 DPRINTF(("Setting beacon interval to %u\n", letoh32(data))); 1879 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1880 sizeof data); 1881 if (error != 0) 1882 return error; 1883 } 1884 1885 options.flags = htole32(0); 1886 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1887 DPRINTF(("Setting scan options to 0x%x\n", letoh32(options.flags))); 1888 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1889 if (error != 0) 1890 return error; 1891 1892 /* finally, enable adapter (start scanning for an access point) */ 1893 DPRINTF(("Enabling adapter\n")); 1894 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1895} 1896 1897int 1898ipw_init(struct ifnet *ifp) 1899{ 1900 struct ipw_softc *sc = ifp->if_softc; 1901 struct ipw_firmware fw; 1902 int error; 1903 1904 ipw_stop(ifp, 0); 1905 1906 if ((error = ipw_reset(sc)) != 0) { 1907 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 1908 goto fail1; 1909 } 1910 1911 if ((error = ipw_read_firmware(sc, &fw)) != NULL) { 1912 printf("%s: could not read firmware\n", sc->sc_dev.dv_xname); 1913 goto fail1; 1914 } 1915 1916 if ((error = ipw_load_ucode(sc, fw.ucode, fw.ucode_size)) != 0) { 1917 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 1918 goto fail2; 1919 } 1920 1921 ipw_stop_master(sc); 1922 1923 /* 1924 * Setup tx, rx and status rings 1925 */ 1926 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1927 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1928 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1929 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1930 sc->txold = IPW_NTBD - 1; /* latest bd index ack'ed by firmware */ 1931 sc->txcur = 0; /* bd index to write to */ 1932 sc->txfree = IPW_NTBD - 2; 1933 1934 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1935 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1936 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1937 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1938 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1939 1940 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1941 sc->status_map->dm_segs[0].ds_addr); 1942 1943 if ((error = ipw_load_firmware(sc, fw.main, fw.main_size)) != 0) { 1944 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 1945 goto fail2; 1946 } 1947 1948 sc->flags |= IPW_FLAG_FW_INITED; 1949 1950 /* Retrieve information tables base addresses */ 1951 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 1952 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 1953 1954 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 1955 1956 if ((error = ipw_config(sc)) != 0) { 1957 printf("%s: device configuration failed\n", 1958 sc->sc_dev.dv_xname); 1959 goto fail2; 1960 } 1961 1962 ifp->if_flags &= ~IFF_OACTIVE; 1963 ifp->if_flags |= IFF_RUNNING; 1964 1965 return 0; 1966 1967fail2: free(fw.data, M_DEVBUF); 1968fail1: ipw_stop(ifp, 0); 1969 1970 return error; 1971} 1972 1973void 1974ipw_stop(struct ifnet *ifp, int disable) 1975{ 1976 struct ipw_softc *sc = ifp->if_softc; 1977 struct ieee80211com *ic = &sc->sc_ic; 1978 int i; 1979 1980 ipw_stop_master(sc); 1981 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1982 1983 /* 1984 * Release tx buffers 1985 */ 1986 for (i = 0; i < IPW_NTBD; i++) 1987 ipw_release_sbd(sc, &sc->stbd_list[i]); 1988 1989 ifp->if_timer = 0; 1990 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1991 1992 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1993} 1994 1995void 1996ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1997 bus_size_t count) 1998{ 1999 for (; count > 0; offset++, datap++, count--) { 2000 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2001 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2002 } 2003} 2004 2005void 2006ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 2007 bus_size_t count) 2008{ 2009 for (; count > 0; offset++, datap++, count--) { 2010 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2011 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2012 } 2013} 2014 2015struct cfdriver ipw_cd = { 2016 0, "ipw", DV_IFNET 2017}; 2018