if_ipw.c revision 1.15
1/* $Id: if_ipw.c,v 1.15 2004/10/27 21:23:45 damien Exp $ */ 2 3/*- 4 * Copyright (c) 2004 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/*- 31 * Intel(R) PRO/Wireless 2100 MiniPCI driver 32 * www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 33 */ 34 35#include "bpfilter.h" 36 37#include <sys/param.h> 38#include <sys/sockio.h> 39#include <sys/sysctl.h> 40#include <sys/mbuf.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43#include <sys/systm.h> 44#include <sys/malloc.h> 45#include <sys/conf.h> 46 47#include <machine/bus.h> 48#include <machine/endian.h> 49#include <machine/intr.h> 50 51#include <dev/pci/pcireg.h> 52#include <dev/pci/pcivar.h> 53#include <dev/pci/pcidevs.h> 54 55#if NBPFILTER > 0 56#include <net/bpf.h> 57#endif 58#include <net/if.h> 59#include <net/if_arp.h> 60#include <net/if_dl.h> 61#include <net/if_media.h> 62#include <net/if_types.h> 63 64#include <netinet/in.h> 65#include <netinet/in_systm.h> 66#include <netinet/in_var.h> 67#include <netinet/if_ether.h> 68#include <netinet/ip.h> 69 70#include <net80211/ieee80211_var.h> 71#include <net80211/ieee80211_radiotap.h> 72 73#include <dev/pci/if_ipwreg.h> 74#include <dev/pci/if_ipwvar.h> 75 76static const struct ieee80211_rateset ipw_rateset_11b = 77 { 4, { 2, 4, 11, 22 } }; 78 79int ipw_match(struct device *, void *, void *); 80void ipw_attach(struct device *, struct device *, void *); 81int ipw_detach(struct device *, int); 82int ipw_media_change(struct ifnet *); 83void ipw_media_status(struct ifnet *, struct ifmediareq *); 84int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 85u_int16_t ipw_read_prom_word(struct ipw_softc *, u_int8_t); 86void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 87void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 88void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 89 struct ipw_soft_bd *, struct ipw_soft_buf *); 90void ipw_notification_intr(struct ipw_softc *, struct ipw_soft_buf *); 91void ipw_rx_intr(struct ipw_softc *); 92void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 93void ipw_tx_intr(struct ipw_softc *); 94int ipw_intr(void *); 95int ipw_cmd(struct ipw_softc *, u_int32_t, void *, u_int32_t); 96int ipw_tx_start(struct ifnet *, struct mbuf *, struct ieee80211_node *); 97void ipw_start(struct ifnet *); 98void ipw_watchdog(struct ifnet *); 99int ipw_get_table1(struct ipw_softc *, u_int32_t *); 100int ipw_get_radio(struct ipw_softc *, int *); 101int ipw_ioctl(struct ifnet *, u_long, caddr_t); 102u_int32_t ipw_read_table1(struct ipw_softc *, u_int32_t); 103void ipw_write_table1(struct ipw_softc *, u_int32_t, u_int32_t); 104int ipw_read_table2(struct ipw_softc *, u_int32_t, void *, u_int32_t *); 105int ipw_tx_init(struct ipw_softc *); 106void ipw_tx_stop(struct ipw_softc *); 107int ipw_rx_init(struct ipw_softc *); 108void ipw_rx_stop(struct ipw_softc *); 109void ipw_stop_master(struct ipw_softc *); 110int ipw_reset(struct ipw_softc *); 111int ipw_load_ucode(struct ipw_softc *, u_char *, int); 112int ipw_load_firmware(struct ipw_softc *, u_char *, int); 113int ipw_cache_firmware(struct ipw_softc *, void *); 114void ipw_free_firmware(struct ipw_softc *); 115int ipw_config(struct ipw_softc *); 116int ipw_init(struct ifnet *); 117void ipw_stop(struct ifnet *, int); 118void ipw_read_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, bus_size_t); 119void ipw_write_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, bus_size_t); 120 121static __inline u_int8_t MEM_READ_1(struct ipw_softc *sc, u_int32_t addr) 122{ 123 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 124 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 125} 126 127static __inline u_int32_t MEM_READ_4(struct ipw_softc *sc, u_int32_t addr) 128{ 129 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 130 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 131} 132 133#ifdef IPW_DEBUG 134#define DPRINTF(x) if (ipw_debug > 0) printf x 135#define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 136int ipw_debug = 0; 137#else 138#define DPRINTF(x) 139#define DPRINTFN(n, x) 140#endif 141 142struct cfattach ipw_ca = { 143 sizeof (struct ipw_softc), ipw_match, ipw_attach, ipw_detach 144}; 145 146int 147ipw_match(struct device *parent, void *match, void *aux) 148{ 149 struct pci_attach_args *pa = aux; 150 151 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 152 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_2100_3B) 153 return 1; 154 155 return 0; 156} 157 158/* Base Address Register */ 159#define IPW_PCI_BAR0 0x10 160 161void 162ipw_attach(struct device *parent, struct device *self, void *aux) 163{ 164 struct ipw_softc *sc = (struct ipw_softc *)self; 165 struct ieee80211com *ic = &sc->sc_ic; 166 struct ifnet *ifp = &ic->ic_if; 167 struct pci_attach_args *pa = aux; 168 const char *intrstr; 169 bus_space_tag_t memt; 170 bus_space_handle_t memh; 171 bus_addr_t base; 172 pci_intr_handle_t ih; 173 pcireg_t data; 174 u_int16_t val; 175 int error, i; 176 177 sc->sc_pct = pa->pa_pc; 178 179 data = pci_conf_read(sc->sc_pct, pa->pa_tag, 0x40); 180 data &= ~0x00ff0000; 181 pci_conf_write(sc->sc_pct, pa->pa_tag, 0x40, data); 182 183 /* enable bus-mastering */ 184 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 185 data |= PCI_COMMAND_MASTER_ENABLE; 186 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 187 188 /* map the register window */ 189 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 190 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 191 if (error != 0) { 192 printf(": could not map memory space\n"); 193 return; 194 } 195 196 sc->sc_st = memt; 197 sc->sc_sh = memh; 198 sc->sc_dmat = pa->pa_dmat; 199 200 /* disable interrupts */ 201 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 202 203 if (pci_intr_map(pa, &ih) != 0) { 204 printf(": could not map interrupt\n"); 205 return; 206 } 207 208 intrstr = pci_intr_string(sc->sc_pct, ih); 209 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 210 sc->sc_dev.dv_xname); 211 if (sc->sc_ih == NULL) { 212 printf(": could not establish interrupt"); 213 if (intrstr != NULL) 214 printf(" at %s", intrstr); 215 printf("\n"); 216 return; 217 } 218 printf(": %s\n", intrstr); 219 220 if (ipw_reset(sc) != 0) { 221 printf(": could not reset adapter\n"); 222 return; 223 } 224 225 ic->ic_phytype = IEEE80211_T_DS; 226 ic->ic_opmode = IEEE80211_M_STA; 227 ic->ic_state = IEEE80211_S_INIT; 228 229 /* set device capabilities */ 230 ic->ic_caps = IEEE80211_C_IBSS | IEEE80211_C_MONITOR | 231 IEEE80211_C_PMGT | IEEE80211_C_TXPMGT | IEEE80211_C_WEP; 232 233 /* read MAC address from EEPROM */ 234 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 235 ic->ic_myaddr[0] = val >> 8; 236 ic->ic_myaddr[1] = val & 0xff; 237 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 238 ic->ic_myaddr[2] = val >> 8; 239 ic->ic_myaddr[3] = val & 0xff; 240 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 241 ic->ic_myaddr[4] = val >> 8; 242 ic->ic_myaddr[5] = val & 0xff; 243 244 /* set supported .11b rates */ 245 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 246 247 /* set supported .11b channels (1 through 14) */ 248 for (i = 1; i <= 14; i++) { 249 ic->ic_channels[i].ic_freq = 250 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 251 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 252 } 253 254 /* default to authmode OPEN */ 255 sc->authmode = IEEE80211_AUTH_OPEN; 256 257 /* IBSS channel undefined for now */ 258 ic->ic_ibss_chan = &ic->ic_channels[0]; 259 260 ifp->if_softc = sc; 261 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 262 ifp->if_init = ipw_init; 263 ifp->if_ioctl = ipw_ioctl; 264 ifp->if_start = ipw_start; 265 ifp->if_watchdog = ipw_watchdog; 266 IFQ_SET_READY(&ifp->if_snd); 267 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 268 269 if_attach(ifp); 270 ieee80211_ifattach(ifp); 271 /* override state transition machine */ 272 sc->sc_newstate = ic->ic_newstate; 273 ic->ic_newstate = ipw_newstate; 274 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 275 276#if NBPFILTER > 0 277 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 278 sizeof (struct ieee80211_frame) + 64); 279 280 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 281 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 282 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 283 284 sc->sc_txtap_len = sizeof sc->sc_txtapu; 285 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 286 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 287#endif 288} 289 290int 291ipw_detach(struct device* self, int flags) 292{ 293 struct ipw_softc *sc = (struct ipw_softc *)self; 294 struct ifnet *ifp = &sc->sc_ic.ic_if; 295 296 ipw_stop(ifp, 1); 297 298 if (sc->flags & IPW_FLAG_FW_CACHED) 299 ipw_free_firmware(sc); 300 301#if NBPFILTER > 0 302 bpfdetach(ifp); 303#endif 304 ieee80211_ifdetach(ifp); 305 if_detach(ifp); 306 307 if (sc->sc_ih != NULL) { 308 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 309 sc->sc_ih = NULL; 310 } 311 312 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 313 314 return 0; 315} 316 317int 318ipw_media_change(struct ifnet *ifp) 319{ 320 int error; 321 322 error = ieee80211_media_change(ifp); 323 if (error != ENETRESET) 324 return error; 325 326 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 327 ipw_init(ifp); 328 329 return 0; 330} 331 332void 333ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 334{ 335 struct ipw_softc *sc = ifp->if_softc; 336 struct ieee80211com *ic = &sc->sc_ic; 337#define N(a) (sizeof (a) / sizeof (a[0])) 338 static const struct { 339 u_int32_t val; 340 int rate; 341 } rates[] = { 342 { IPW_RATE_DS1, 2 }, 343 { IPW_RATE_DS2, 4 }, 344 { IPW_RATE_DS5, 11 }, 345 { IPW_RATE_DS11, 22 }, 346 }; 347 u_int32_t val; 348 int rate, i; 349 350 imr->ifm_status = IFM_AVALID; 351 imr->ifm_active = IFM_IEEE80211; 352 if (ic->ic_state == IEEE80211_S_RUN) 353 imr->ifm_status |= IFM_ACTIVE; 354 355 /* read current transmission rate from adapter */ 356 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 357 val &= 0xf; 358 359 /* convert rate to 802.11 rate */ 360 for (i = 0; i < N(rates) && rates[i].val != val; i++); 361 rate = (i < N(rates)) ? rates[i].rate : 0; 362 363 imr->ifm_active |= IFM_IEEE80211_11B; 364 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 365 switch (ic->ic_opmode) { 366 case IEEE80211_M_STA: 367 break; 368 369 case IEEE80211_M_IBSS: 370 imr->ifm_active |= IFM_IEEE80211_ADHOC; 371 break; 372 373 case IEEE80211_M_MONITOR: 374 imr->ifm_active |= IFM_IEEE80211_MONITOR; 375 break; 376 377 case IEEE80211_M_AHDEMO: 378 case IEEE80211_M_HOSTAP: 379 /* should not get there */ 380 break; 381 } 382#undef N 383} 384 385int 386ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 387{ 388 struct ipw_softc *sc = ic->ic_softc; 389 struct ieee80211_node *ni = ic->ic_bss; 390 u_int32_t val, len; 391 392 switch (nstate) { 393 case IEEE80211_S_RUN: 394 len = IEEE80211_NWID_LEN; 395 ipw_read_table2(sc, IPW_INFO_CURRENT_SSID, ni->ni_essid, &len); 396 ni->ni_esslen = len; 397 398 val = ipw_read_table1(sc, IPW_INFO_CURRENT_CHANNEL); 399 ni->ni_chan = &ic->ic_channels[val]; 400 401 DELAY(100); /* firmware needs a short delay here */ 402 403 len = IEEE80211_ADDR_LEN; 404 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, ni->ni_bssid, &len); 405 break; 406 407 case IEEE80211_S_INIT: 408 case IEEE80211_S_SCAN: 409 case IEEE80211_S_AUTH: 410 case IEEE80211_S_ASSOC: 411 break; 412 } 413 414 ic->ic_state = nstate; 415 return 0; 416} 417 418/* 419 * Read 16 bits at address 'addr' from the Microwire EEPROM. 420 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 421 */ 422u_int16_t 423ipw_read_prom_word(struct ipw_softc *sc, u_int8_t addr) 424{ 425 u_int32_t tmp; 426 u_int16_t val; 427 int n; 428 429 /* Clock C once before the first command */ 430 IPW_EEPROM_CTL(sc, 0); 431 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 432 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 433 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 434 435 /* Write start bit (1) */ 436 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 437 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 438 439 /* Write READ opcode (10) */ 440 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 441 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 442 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 443 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 444 445 /* Write address A7-A0 */ 446 for (n = 7; n >= 0; n--) { 447 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 448 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 449 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 450 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 451 } 452 453 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 454 455 /* Read data Q15-Q0 */ 456 val = 0; 457 for (n = 15; n >= 0; n--) { 458 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 459 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 460 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 461 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 462 } 463 464 IPW_EEPROM_CTL(sc, 0); 465 466 /* Clear Chip Select and clock C */ 467 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 468 IPW_EEPROM_CTL(sc, 0); 469 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 470 471 return letoh16(val); 472} 473 474void 475ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 476{ 477 struct ipw_cmd *cmd; 478 479 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 480 BUS_DMASYNC_POSTREAD); 481 482 cmd = mtod(sbuf->m, struct ipw_cmd *); 483 484 DPRINTFN(2, ("RX!CMD!%u!%u!%u!%u!%u\n", 485 letoh32(cmd->type), letoh32(cmd->subtype), letoh32(cmd->seq), 486 letoh32(cmd->len), letoh32(cmd->status))); 487 488 wakeup(sc); 489} 490 491void 492ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 493{ 494 struct ieee80211com *ic = &sc->sc_ic; 495 u_int32_t state; 496 497 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 498 BUS_DMASYNC_POSTREAD); 499 500 state = letoh32(*mtod(sbuf->m, u_int32_t *)); 501 502 DPRINTFN(2, ("RX!NEWSTATE!%u\n", state)); 503 504 switch (state) { 505 case IPW_STATE_ASSOCIATED: 506 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 507 break; 508 509 case IPW_STATE_SCANNING: 510 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 511 break; 512 513 case IPW_STATE_ASSOCIATION_LOST: 514 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 515 break; 516 517 case IPW_STATE_RADIO_DISABLED: 518 /* XXX should turn the interface down */ 519 break; 520 } 521} 522 523void 524ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 525 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 526{ 527 struct ieee80211com *ic = &sc->sc_ic; 528 struct ifnet *ifp = &ic->ic_if; 529 struct mbuf *m; 530 struct ieee80211_frame *wh; 531 struct ieee80211_node *ni; 532 int error; 533 534 DPRINTFN(5, ("RX!DATA!%u!%u\n", letoh32(status->len), status->rssi)); 535 536 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 537 BUS_DMASYNC_POSTREAD); 538 539 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 540 541 /* Finalize mbuf */ 542 m = sbuf->m; 543 m->m_pkthdr.rcvif = ifp; 544 m->m_pkthdr.len = m->m_len = letoh32(status->len); 545 546#if NBPFILTER > 0 547 if (sc->sc_drvbpf != NULL) { 548 struct mbuf mb; 549 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 550 551 tap->wr_flags = 0; 552 tap->wr_antsignal = status->rssi; 553 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 554 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 555 556 M_DUP_PKTHDR(&mb, m); 557 mb.m_data = (caddr_t)tap; 558 mb.m_len = sc->sc_rxtap_len; 559 mb.m_next = m; 560 mb.m_pkthdr.len += mb.m_len; 561 bpf_mtap(sc->sc_drvbpf, &mb); 562 } 563#endif 564 565 wh = mtod(m, struct ieee80211_frame *); 566 567 ni = ieee80211_find_rxnode(ic, wh); 568 569 /* Send it up to the upper layer */ 570 ieee80211_input(ifp, m, ni, status->rssi, 0); 571 572 if (ni == ic->ic_bss) 573 ieee80211_unref_node(&ni); 574 else 575 ieee80211_free_node(ic, ni); 576 577 MGETHDR(m, M_DONTWAIT, MT_DATA); 578 if (m == NULL) { 579 printf("%s: could not allocate rx mbuf\n", 580 sc->sc_dev.dv_xname); 581 return; 582 } 583 MCLGET(m, M_DONTWAIT); 584 if (!(m->m_flags & M_EXT)) { 585 m_freem(m); 586 printf("%s: could not allocate rx mbuf cluster\n", 587 sc->sc_dev.dv_xname); 588 return; 589 } 590 591 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(m, void *), 592 MCLBYTES, NULL, BUS_DMA_NOWAIT); 593 if (error != 0) { 594 printf("%s: could not map rxbuf dma memory\n", 595 sc->sc_dev.dv_xname); 596 m_freem(m); 597 return; 598 } 599 600 sbuf->m = m; 601 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 602} 603 604void 605ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 606{ 607 DPRINTFN(2, ("RX!NOTIFICATION\n")); 608} 609 610void 611ipw_rx_intr(struct ipw_softc *sc) 612{ 613 struct ipw_status *status; 614 struct ipw_soft_bd *sbd; 615 struct ipw_soft_buf *sbuf; 616 u_int32_t r, i; 617 618 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 619 620 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 621 622 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 623 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 624 BUS_DMASYNC_POSTREAD); 625 626 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 627 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 628 BUS_DMASYNC_POSTREAD); 629 630 status = &sc->status_list[i]; 631 sbd = &sc->srbd_list[i]; 632 sbuf = sbd->priv; 633 634 switch (letoh16(status->code) & 0xf) { 635 case IPW_STATUS_CODE_COMMAND: 636 ipw_command_intr(sc, sbuf); 637 break; 638 639 case IPW_STATUS_CODE_NEWSTATE: 640 ipw_newstate_intr(sc, sbuf); 641 break; 642 643 case IPW_STATUS_CODE_DATA_802_3: 644 case IPW_STATUS_CODE_DATA_802_11: 645 ipw_data_intr(sc, status, sbd, sbuf); 646 break; 647 648 case IPW_STATUS_CODE_NOTIFICATION: 649 ipw_notification_intr(sc, sbuf); 650 break; 651 652 default: 653 printf("%s: unknown status code %u\n", 654 sc->sc_dev.dv_xname, letoh16(status->code)); 655 } 656 sbd->bd->flags = 0; 657 658 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 659 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 660 BUS_DMASYNC_PREWRITE); 661 } 662 663 /* Tell the firmware what we have processed */ 664 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 665 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 666} 667 668void 669ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 670{ 671 struct ieee80211com *ic; 672 struct ipw_soft_hdr *shdr; 673 struct ipw_soft_buf *sbuf; 674 675 switch (sbd->type) { 676 case IPW_SBD_TYPE_COMMAND: 677 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 678 break; 679 680 case IPW_SBD_TYPE_HEADER: 681 shdr = sbd->priv; 682 bus_dmamap_unload(sc->sc_dmat, shdr->map); 683 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 684 break; 685 686 case IPW_SBD_TYPE_DATA: 687 ic = &sc->sc_ic; 688 sbuf = sbd->priv; 689 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 690 m_freem(sbuf->m); 691 if (sbuf->ni != NULL && sbuf->ni != ic->ic_bss) 692 ieee80211_free_node(ic, sbuf->ni); 693 /* kill watchdog timer */ 694 sc->sc_tx_timer = 0; 695 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 696 break; 697 } 698 sbd->type = IPW_SBD_TYPE_NOASSOC; 699} 700 701void 702ipw_tx_intr(struct ipw_softc *sc) 703{ 704 struct ifnet *ifp = &sc->sc_ic.ic_if; 705 u_int32_t r, i; 706 707 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 708 709 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) 710 ipw_release_sbd(sc, &sc->stbd_list[i]); 711 712 /* Remember what the firmware has processed */ 713 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 714 715 /* Call start() since some buffer descriptors have been released */ 716 ifp->if_flags &= ~IFF_OACTIVE; 717 (*ifp->if_start)(ifp); 718} 719 720int 721ipw_intr(void *arg) 722{ 723 struct ipw_softc *sc = arg; 724 u_int32_t r; 725 726 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0) 727 return 0; 728 729 /* Disable interrupts */ 730 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 731 732 DPRINTFN(8, ("INTR!0x%08x\n", r)); 733 734 if (r & IPW_INTR_RX_TRANSFER) 735 ipw_rx_intr(sc); 736 737 if (r & IPW_INTR_TX_TRANSFER) 738 ipw_tx_intr(sc); 739 740 if (r & IPW_INTR_FW_INIT_DONE) { 741 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 742 wakeup(sc); 743 } 744 745 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 746 printf("%s: fatal error\n", sc->sc_dev.dv_xname); 747 ipw_stop(&sc->sc_ic.ic_if, 1); 748 } 749 750 /* Acknowledge interrupts */ 751 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 752 753 /* Re-enable interrupts */ 754 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 755 756 return 0; 757} 758 759int 760ipw_cmd(struct ipw_softc *sc, u_int32_t type, void *data, u_int32_t len) 761{ 762 struct ipw_soft_bd *sbd; 763 int error; 764 765 sbd = &sc->stbd_list[sc->txcur]; 766 767 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, sc->cmd, 768 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 769 if (error != 0) { 770 printf("%s: could not map cmd dma memory\n", 771 sc->sc_dev.dv_xname); 772 return error; 773 } 774 775 sc->cmd->type = htole32(type); 776 sc->cmd->subtype = htole32(0); 777 sc->cmd->len = htole32(len); 778 sc->cmd->seq = htole32(0); 779 if (data != NULL) 780 bcopy(data, sc->cmd->data, len); 781 782 sbd->type = IPW_SBD_TYPE_COMMAND; 783 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 784 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 785 sbd->bd->nfrag = 1; 786 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 787 IPW_BD_FLAG_TX_LAST_FRAGMENT; 788 789 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 790 BUS_DMASYNC_PREWRITE); 791 792 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 793 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 794 BUS_DMASYNC_PREWRITE); 795 796 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 797 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 798 799 DPRINTFN(2, ("TX!CMD!%u!%u!%u!%u\n", type, 0, 0, len)); 800 801 /* Wait at most one second for command to complete */ 802 return tsleep(sc, 0, "ipwcmd", hz); 803} 804 805int 806ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 807{ 808 struct ipw_softc *sc = ifp->if_softc; 809 struct ieee80211com *ic = &sc->sc_ic; 810 struct ieee80211_frame *wh; 811 struct ipw_soft_bd *sbd; 812 struct ipw_soft_hdr *shdr; 813 struct ipw_soft_buf *sbuf; 814 int error, i; 815 816 if (ic->ic_flags & IEEE80211_F_WEPON) { 817 m = ieee80211_wep_crypt(ifp, m, 1); 818 if (m == NULL) 819 return ENOBUFS; 820 } 821 822#if NBPFILTER > 0 823 if (sc->sc_drvbpf != NULL) { 824 struct mbuf mb; 825 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 826 827 tap->wt_flags = 0; 828 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 829 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 830 831 M_DUP_PKTHDR(&mb, m); 832 mb.m_data = (caddr_t)tap; 833 mb.m_len = sc->sc_txtap_len; 834 mb.m_next = m; 835 mb.m_pkthdr.len += mb.m_len; 836 bpf_mtap(sc->sc_drvbpf, &mb); 837 } 838#endif 839 840 wh = mtod(m, struct ieee80211_frame *); 841 842 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 843 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 844 845 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 846 shdr->hdr.subtype = htole32(0); 847 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 848 shdr->hdr.encrypt = 0; 849 shdr->hdr.keyidx = 0; 850 shdr->hdr.keysz = 0; 851 shdr->hdr.fragmentsz = htole16(0); 852 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 853 if (ic->ic_opmode == IEEE80211_M_STA) 854 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 855 else 856 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 857 858 /* trim IEEE802.11 header */ 859 m_adj(m, sizeof (struct ieee80211_frame)); 860 861 /* 862 * We need to map the mbuf first to know how many buffer descriptors 863 * are needed for this transfer. 864 */ 865 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 866 if (error != 0) { 867 printf("%s: could not map mbuf (error %d)\n", 868 sc->sc_dev.dv_xname, error); 869 m_freem(m); 870 return error; 871 } 872 873 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 874 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 875 if (error != 0) { 876 printf("%s: could not map header (error %d)\n", 877 sc->sc_dev.dv_xname, error); 878 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 879 m_freem(m); 880 return error; 881 } 882 883 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 884 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 885 886 sbd = &sc->stbd_list[sc->txcur]; 887 sbd->type = IPW_SBD_TYPE_HEADER; 888 sbd->priv = shdr; 889 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 890 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 891 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 892 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 893 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 894 895 DPRINTFN(5, ("TX!HDR!%u!%u!%u!%u", shdr->hdr.type, shdr->hdr.subtype, 896 shdr->hdr.encrypted, shdr->hdr.encrypt)); 897 DPRINTFN(5, ("!%s", ether_sprintf(shdr->hdr.src_addr))); 898 DPRINTFN(5, ("!%s\n", ether_sprintf(shdr->hdr.dst_addr))); 899 900 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 901 sc->txcur * sizeof (struct ipw_bd), 902 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 903 904 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 905 906 sbuf->m = m; 907 sbuf->ni = ni; 908 909 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 910 sbd = &sc->stbd_list[sc->txcur]; 911 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 912 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 913 sbd->bd->nfrag = 0; /* used only in first bd */ 914 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 915 if (i == sbuf->map->dm_nsegs - 1) { 916 sbd->type = IPW_SBD_TYPE_DATA; 917 sbd->priv = sbuf; 918 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 919 } else { 920 sbd->type = IPW_SBD_TYPE_NOASSOC; 921 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 922 } 923 924 DPRINTFN(5, ("TX!FRAG!%d!%d\n", i, 925 sbuf->map->dm_segs[i].ds_len)); 926 927 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 928 sc->txcur * sizeof (struct ipw_bd), 929 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 930 931 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 932 } 933 934 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 935 BUS_DMASYNC_PREWRITE); 936 937 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 938 BUS_DMASYNC_PREWRITE); 939 940 /* Inform firmware about this new packet */ 941 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 942 943 return 0; 944} 945 946void 947ipw_start(struct ifnet *ifp) 948{ 949 struct ipw_softc *sc = ifp->if_softc; 950 struct ieee80211com *ic = &sc->sc_ic; 951 struct mbuf *m; 952 struct ieee80211_node *ni; 953 954 if (ic->ic_state != IEEE80211_S_RUN) 955 return; 956 957 for (;;) { 958 IF_DEQUEUE(&ifp->if_snd, m); 959 if (m == NULL) 960 break; 961 962#if NBPFILTER > 0 963 if (ifp->if_bpf != NULL) 964 bpf_mtap(ifp->if_bpf, m); 965#endif 966 967 m = ieee80211_encap(ifp, m, &ni); 968 if (m == NULL) 969 continue; 970 971#if NBPFILTER > 0 972 if (ic->ic_rawbpf != NULL) 973 bpf_mtap(ic->ic_rawbpf, m); 974#endif 975 976 if (ipw_tx_start(ifp, m, ni) != 0) { 977 if (ni != NULL && ni != ic->ic_bss) 978 ieee80211_free_node(ic, ni); 979 break; 980 } 981 982 /* start watchdog timer */ 983 sc->sc_tx_timer = 5; 984 ifp->if_timer = 1; 985 } 986} 987 988void 989ipw_watchdog(struct ifnet *ifp) 990{ 991 struct ipw_softc *sc = ifp->if_softc; 992 993 ifp->if_timer = 0; 994 995 if (sc->sc_tx_timer > 0) { 996 if (--sc->sc_tx_timer == 0) { 997 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 998 ipw_stop(ifp, 1); 999 return; 1000 } 1001 ifp->if_timer = 1; 1002 } 1003 1004 ieee80211_watchdog(ifp); 1005} 1006 1007int 1008ipw_get_table1(struct ipw_softc *sc, u_int32_t *tbl) 1009{ 1010 u_int32_t i, size, buf[256]; 1011 1012 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 1013 bzero(buf, sizeof buf); 1014 return copyout(buf, tbl, sizeof buf); 1015 } 1016 1017 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1018 1019 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1020 for (i = 1; i < size; i++) 1021 buf[i] = MEM_READ_4(sc, CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA)); 1022 1023 return copyout(buf, tbl, size * sizeof (u_int32_t)); 1024} 1025 1026int 1027ipw_get_radio(struct ipw_softc *sc, int *ret) 1028{ 1029 int val; 1030 1031 val = (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 0 : 1; 1032 return copyout(&val, ret, sizeof val); 1033} 1034 1035int 1036ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1037{ 1038 struct ipw_softc *sc = ifp->if_softc; 1039 struct ifreq *ifr; 1040 struct ifaddr *ifa; 1041 int s, error = 0; 1042 1043 s = splnet(); 1044 1045 switch (cmd) { 1046 case SIOCSIFADDR: 1047 ifa = (struct ifaddr *) data; 1048 ifp->if_flags |= IFF_UP; 1049 switch (ifa->ifa_addr->sa_family) { 1050#ifdef INET 1051 case AF_INET: 1052 arp_ifinit(&sc->sc_ic.ic_ac, ifa); 1053 ipw_init(ifp); 1054 break; 1055#endif 1056 default: 1057 ipw_init(ifp); 1058 } 1059 break; 1060 1061 case SIOCSIFFLAGS: 1062 if (ifp->if_flags & IFF_UP) { 1063 if (!(ifp->if_flags & IFF_RUNNING)) 1064 ipw_init(ifp); 1065 } else { 1066 if (ifp->if_flags & IFF_RUNNING) 1067 ipw_stop(ifp, 1); 1068 } 1069 break; 1070 1071 case SIOCGTABLE1: 1072 ifr = (struct ifreq *)data; 1073 error = ipw_get_table1(sc, (u_int32_t *)ifr->ifr_data); 1074 break; 1075 1076 case SIOCGRADIO: 1077 ifr = (struct ifreq *)data; 1078 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1079 break; 1080 1081 case SIOCSLOADFW: 1082 /* only super-user can do that! */ 1083 if ((error = suser(curproc, 0)) != 0) 1084 break; 1085 1086 ifr = (struct ifreq *)data; 1087 error = ipw_cache_firmware(sc, ifr->ifr_data); 1088 break; 1089 1090 case SIOCSKILLFW: 1091 /* only super-user can do that! */ 1092 if ((error = suser(curproc, 0)) != 0) 1093 break; 1094 1095 ipw_stop(ifp, 1); 1096 ipw_free_firmware(sc); 1097 break; 1098 1099 case SIOCG80211AUTH: 1100 ((struct ieee80211_auth *)data)->i_authtype = sc->authmode; 1101 break; 1102 1103 case SIOCS80211AUTH: 1104 /* only super-user can do that! */ 1105 if ((error = suser(curproc, 0)) != 0) 1106 break; 1107 1108 sc->authmode = ((struct ieee80211_auth *)data)->i_authtype; 1109 break; 1110 1111 default: 1112 error = ieee80211_ioctl(ifp, cmd, data); 1113 } 1114 1115 if (error == ENETRESET && cmd != SIOCADDMULTI) { 1116 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1117 (IFF_UP | IFF_RUNNING)) 1118 ipw_init(ifp); 1119 error = 0; 1120 } 1121 1122 splx(s); 1123 return error; 1124} 1125 1126u_int32_t 1127ipw_read_table1(struct ipw_softc *sc, u_int32_t off) 1128{ 1129 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1130} 1131 1132void 1133ipw_write_table1(struct ipw_softc *sc, u_int32_t off, u_int32_t info) 1134{ 1135 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1136} 1137 1138int 1139ipw_read_table2(struct ipw_softc *sc, u_int32_t off, void *buf, u_int32_t *len) 1140{ 1141 u_int32_t addr, info; 1142 u_int16_t count, size; 1143 u_int32_t total; 1144 1145 /* addr[4] + count[2] + size[2] */ 1146 addr = MEM_READ_4(sc, sc->table2_base + off); 1147 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1148 1149 count = info >> 16; 1150 size = info & 0xffff; 1151 total = count * size; 1152 1153 if (total > *len) { 1154 *len = total; 1155 return EINVAL; 1156 } 1157 1158 *len = total; 1159 ipw_read_mem_1(sc, addr, buf, total); 1160 1161 return 0; 1162} 1163 1164int 1165ipw_tx_init(struct ipw_softc *sc) 1166{ 1167 char *errmsg; 1168 struct ipw_bd *bd; 1169 struct ipw_soft_bd *sbd; 1170 struct ipw_soft_hdr *shdr; 1171 struct ipw_soft_buf *sbuf; 1172 int error, i, nsegs; 1173 1174 /* Allocate transmission buffer descriptors */ 1175 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 1176 BUS_DMA_NOWAIT, &sc->tbd_map); 1177 if (error != 0) { 1178 errmsg = "could not create tbd dma map"; 1179 goto fail; 1180 } 1181 1182 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 1183 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1184 if (error != 0) { 1185 errmsg = "could not allocate tbd dma memory"; 1186 goto fail; 1187 } 1188 1189 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 1190 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 1191 if (error != 0) { 1192 errmsg = "could not map tbd dma memory"; 1193 goto fail; 1194 } 1195 1196 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 1197 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 1198 if (error != 0) { 1199 errmsg = "could not load tbd dma memory"; 1200 goto fail; 1201 } 1202 1203 sc->stbd_list = malloc(IPW_NTBD * sizeof (struct ipw_soft_bd), 1204 M_DEVBUF, M_NOWAIT); 1205 if (sc->stbd_list == NULL) { 1206 errmsg = "could not allocate soft tbd"; 1207 error = ENOMEM; 1208 goto fail; 1209 } 1210 sbd = sc->stbd_list; 1211 bd = sc->tbd_list; 1212 for (i = 0; i < IPW_NTBD; i++, sbd++, bd++) { 1213 sbd->type = IPW_SBD_TYPE_NOASSOC; 1214 sbd->bd = bd; 1215 } 1216 1217 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1218 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1219 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1220 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1221 sc->txold = IPW_NTBD - 1; /* latest bd index ack'ed by firmware */ 1222 sc->txcur = 0; /* bd index to write to */ 1223 1224 /* Allocate a DMA-able command */ 1225 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 1226 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 1227 if (error != 0) { 1228 errmsg = "could not create cmd dma map"; 1229 goto fail; 1230 } 1231 1232 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 1233 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1234 if (error != 0) { 1235 errmsg = "could not allocate cmd dma memory"; 1236 goto fail; 1237 } 1238 1239 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 1240 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 1241 if (error != 0) { 1242 errmsg = "could not map cmd dma memory"; 1243 goto fail; 1244 } 1245 1246 /* Allocate a pool of DMA-able headers */ 1247 sc->shdr_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_hdr), 1248 M_DEVBUF, M_NOWAIT); 1249 if (sc->shdr_list == NULL) { 1250 errmsg = "could not allocate soft hdr"; 1251 error = ENOMEM; 1252 goto fail; 1253 } 1254 TAILQ_INIT(&sc->sc_free_shdr); 1255 for (i = 0, shdr = sc->shdr_list; i < IPW_NDATA; i++, shdr++) { 1256 error = bus_dmamap_create(sc->sc_dmat, 1257 sizeof (struct ipw_soft_hdr), 1, 1258 sizeof (struct ipw_soft_hdr), 0, BUS_DMA_NOWAIT, 1259 &shdr->map); 1260 if (error != 0) { 1261 errmsg = "could not create hdr dma map"; 1262 goto fail; 1263 } 1264 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1265 } 1266 1267 /* Allocate a pool of DMA-able buffers */ 1268 sc->tx_sbuf_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_buf), 1269 M_DEVBUF, M_NOWAIT); 1270 if (sc->tx_sbuf_list == NULL) { 1271 errmsg = "could not allocate soft txbuf"; 1272 error = ENOMEM; 1273 goto fail; 1274 } 1275 TAILQ_INIT(&sc->sc_free_sbuf); 1276 for (i = 0, sbuf = sc->tx_sbuf_list; i < IPW_NDATA; i++, sbuf++) { 1277 error = bus_dmamap_create(sc->sc_dmat, IPW_NDATA * MCLBYTES, 1278 IPW_NDATA, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1279 if (error != 0) { 1280 errmsg = "could not create txbuf dma map"; 1281 goto fail; 1282 } 1283 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1284 } 1285 1286 return 0; 1287 1288fail: printf("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1289 ipw_tx_stop(sc); 1290 1291 return error; 1292} 1293 1294void 1295ipw_tx_stop(struct ipw_softc *sc) 1296{ 1297 struct ipw_soft_hdr *shdr; 1298 struct ipw_soft_buf *sbuf; 1299 int i; 1300 1301 if (sc->tbd_map != NULL) { 1302 if (sc->tbd_list != NULL) { 1303 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 1304 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 1305 IPW_TBD_SZ); 1306 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 1307 sc->tbd_list = NULL; 1308 } 1309 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 1310 sc->tbd_map = NULL; 1311 } 1312 1313 if (sc->stbd_list != NULL) { 1314 for (i = 0; i < IPW_NTBD; i++) 1315 ipw_release_sbd(sc, &sc->stbd_list[i]); 1316 free(sc->stbd_list, M_DEVBUF); 1317 sc->stbd_list = NULL; 1318 } 1319 1320 if (sc->cmd_map != NULL) { 1321 if (sc->cmd != NULL) { 1322 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->cmd, 1323 sizeof (struct ipw_cmd)); 1324 bus_dmamem_free(sc->sc_dmat, &sc->cmd_seg, 1); 1325 sc->cmd = NULL; 1326 } 1327 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 1328 sc->cmd_map = NULL; 1329 } 1330 1331 if (sc->shdr_list != NULL) { 1332 TAILQ_FOREACH(shdr, &sc->sc_free_shdr, next) 1333 bus_dmamap_destroy(sc->sc_dmat, shdr->map); 1334 free(sc->shdr_list, M_DEVBUF); 1335 sc->shdr_list = NULL; 1336 } 1337 1338 1339 if (sc->tx_sbuf_list != NULL) { 1340 TAILQ_FOREACH(sbuf, &sc->sc_free_sbuf, next) 1341 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1342 free(sc->tx_sbuf_list, M_DEVBUF); 1343 sc->tx_sbuf_list = NULL; 1344 } 1345} 1346 1347int 1348ipw_rx_init(struct ipw_softc *sc) 1349{ 1350 char *errmsg; 1351 struct ipw_bd *bd; 1352 struct ipw_soft_bd *sbd; 1353 struct ipw_soft_buf *sbuf; 1354 int error, i, nsegs; 1355 1356 /* Allocate reception buffer descriptors */ 1357 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 1358 BUS_DMA_NOWAIT, &sc->rbd_map); 1359 if (error != 0) { 1360 errmsg = "could not create rbd dma map"; 1361 goto fail; 1362 } 1363 1364 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 1365 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1366 if (error != 0) { 1367 errmsg = "could not allocate rbd dma memory"; 1368 goto fail; 1369 } 1370 1371 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 1372 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 1373 if (error != 0) { 1374 errmsg = "could not map rbd dma memory"; 1375 goto fail; 1376 } 1377 1378 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 1379 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 1380 if (error != 0) { 1381 errmsg = "could not load rbd dma memory"; 1382 goto fail; 1383 } 1384 1385 sc->srbd_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_bd), 1386 M_DEVBUF, M_NOWAIT); 1387 if (sc->srbd_list == NULL) { 1388 errmsg = "could not allocate soft rbd"; 1389 error = ENOMEM; 1390 goto fail; 1391 } 1392 sbd = sc->srbd_list; 1393 bd = sc->rbd_list; 1394 for (i = 0; i < IPW_NRBD; i++, sbd++, bd++) { 1395 sbd->type = IPW_SBD_TYPE_NOASSOC; 1396 sbd->bd = bd; 1397 } 1398 1399 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1400 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1401 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1402 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1403 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1404 1405 /* Allocate status descriptors */ 1406 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 1407 0, BUS_DMA_NOWAIT, &sc->status_map); 1408 if (error != 0) { 1409 errmsg = "could not create status dma map"; 1410 goto fail; 1411 } 1412 1413 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 1414 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1415 if (error != 0) { 1416 errmsg = "could not allocate status dma memory"; 1417 goto fail; 1418 } 1419 1420 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 1421 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 1422 if (error != 0) { 1423 errmsg = "could not map status dma memory"; 1424 goto fail; 1425 } 1426 1427 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 1428 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 1429 if (error != 0) { 1430 errmsg = "could not load status dma memory"; 1431 goto fail; 1432 } 1433 1434 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1435 sc->status_map->dm_segs[0].ds_addr); 1436 1437 sc->rx_sbuf_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_buf), 1438 M_DEVBUF, M_NOWAIT); 1439 if (sc->rx_sbuf_list == NULL) { 1440 errmsg = "could not allocate soft rxbuf"; 1441 error = ENOMEM; 1442 goto fail; 1443 } 1444 1445 sbuf = sc->rx_sbuf_list; 1446 sbd = sc->srbd_list; 1447 for (i = 0; i < IPW_NRBD; i++, sbuf++, sbd++) { 1448 1449 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 1450 if (sbuf->m == NULL) { 1451 errmsg = "could not allocate rx mbuf"; 1452 error = ENOMEM; 1453 goto fail; 1454 } 1455 MCLGET(sbuf->m, M_DONTWAIT); 1456 if (!(sbuf->m->m_flags & M_EXT)) { 1457 m_freem(sbuf->m); 1458 errmsg = "could not allocate rx mbuf cluster"; 1459 error = ENOMEM; 1460 goto fail; 1461 } 1462 1463 error = bus_dmamap_create(sc->sc_dmat, IPW_NRBD * MCLBYTES, 1464 IPW_NRBD, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1465 if (error != 0) { 1466 m_freem(sbuf->m); 1467 errmsg = "could not create rxbuf dma map"; 1468 goto fail; 1469 } 1470 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 1471 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1472 if (error != 0) { 1473 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1474 m_freem(sbuf->m); 1475 errmsg = "could not map rxbuf dma memory"; 1476 goto fail; 1477 } 1478 sbd->type = IPW_SBD_TYPE_DATA; 1479 sbd->priv = sbuf; 1480 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1481 sbd->bd->len = htole32(MCLBYTES); 1482 } 1483 1484 return 0; 1485 1486fail: printf("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1487 ipw_rx_stop(sc); 1488 1489 return error; 1490} 1491 1492void 1493ipw_rx_stop(struct ipw_softc *sc) 1494{ 1495 struct ipw_soft_bd *sbd; 1496 struct ipw_soft_buf *sbuf; 1497 int i; 1498 1499 if (sc->rbd_map != NULL) { 1500 if (sc->rbd_list != NULL) { 1501 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 1502 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 1503 IPW_RBD_SZ); 1504 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 1505 sc->rbd_list = NULL; 1506 } 1507 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 1508 sc->rbd_map = NULL; 1509 } 1510 1511 if (sc->status_map != NULL) { 1512 if (sc->status_list != NULL) { 1513 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 1514 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 1515 IPW_STATUS_SZ); 1516 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 1517 sc->status_list = NULL; 1518 } 1519 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 1520 sc->status_map = NULL; 1521 } 1522 1523 if (sc->srbd_list != NULL) { 1524 for (i = 0, sbd = sc->srbd_list; i < IPW_NRBD; i++, sbd++) { 1525 if (sbd->type == IPW_SBD_TYPE_NOASSOC) 1526 continue; 1527 1528 sbuf = sbd->priv; 1529 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1530 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1531 m_freem(sbuf->m); 1532 } 1533 free(sc->srbd_list, M_DEVBUF); 1534 sc->srbd_list = NULL; 1535 } 1536 1537 if (sc->rx_sbuf_list != NULL) { 1538 free(sc->rx_sbuf_list, M_DEVBUF); 1539 sc->rx_sbuf_list = NULL; 1540 } 1541} 1542 1543void 1544ipw_stop_master(struct ipw_softc *sc) 1545{ 1546 int ntries; 1547 1548 /* Disable interrupts */ 1549 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1550 1551 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1552 for (ntries = 0; ntries < 5; ntries++) { 1553 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1554 break; 1555 DELAY(10); 1556 } 1557 if (ntries == 5) 1558 printf("%s: timeout waiting for master\n", 1559 sc->sc_dev.dv_xname); 1560 1561 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1562 IPW_RST_PRINCETON_RESET); 1563 1564 sc->flags &= ~IPW_FLAG_FW_INITED; 1565} 1566 1567int 1568ipw_reset(struct ipw_softc *sc) 1569{ 1570 int ntries; 1571 1572 ipw_stop_master(sc); 1573 1574 /* Move adapter to D0 state */ 1575 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1576 IPW_CTL_INIT); 1577 1578 /* Wait for clock stabilization */ 1579 for (ntries = 0; ntries < 1000; ntries++) { 1580 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1581 break; 1582 DELAY(200); 1583 } 1584 if (ntries == 1000) 1585 return EIO; 1586 1587 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1588 IPW_RST_SW_RESET); 1589 1590 DELAY(10); 1591 1592 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1593 IPW_CTL_INIT); 1594 1595 return 0; 1596} 1597 1598int 1599ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1600{ 1601 int ntries; 1602 1603 MEM_WRITE_4(sc, 0x003000e0, 0x80000000); 1604 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1605 1606 MEM_WRITE_2(sc, 0x220000, 0x0703); 1607 MEM_WRITE_2(sc, 0x220000, 0x0707); 1608 1609 MEM_WRITE_1(sc, 0x210014, 0x72); 1610 MEM_WRITE_1(sc, 0x210014, 0x72); 1611 1612 MEM_WRITE_1(sc, 0x210000, 0x40); 1613 MEM_WRITE_1(sc, 0x210000, 0x00); 1614 MEM_WRITE_1(sc, 0x210000, 0x40); 1615 1616 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1617 1618 MEM_WRITE_1(sc, 0x210000, 0x00); 1619 MEM_WRITE_1(sc, 0x210000, 0x00); 1620 MEM_WRITE_1(sc, 0x210000, 0x80); 1621 1622 MEM_WRITE_2(sc, 0x220000, 0x0703); 1623 MEM_WRITE_2(sc, 0x220000, 0x0707); 1624 1625 MEM_WRITE_1(sc, 0x210014, 0x72); 1626 MEM_WRITE_1(sc, 0x210014, 0x72); 1627 1628 MEM_WRITE_1(sc, 0x210000, 0x00); 1629 MEM_WRITE_1(sc, 0x210000, 0x80); 1630 1631 for (ntries = 0; ntries < 10; ntries++) { 1632 if (MEM_READ_1(sc, 0x210000) & 1) 1633 break; 1634 DELAY(10); 1635 } 1636 if (ntries == 10) 1637 return EIO; 1638 1639 MEM_WRITE_4(sc, 0x003000e0, 0); 1640 1641 return 0; 1642} 1643 1644/* set of macros to handle unaligned little endian data in firmware image */ 1645#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1646#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1647int 1648ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1649{ 1650 u_char *p, *end; 1651 u_int32_t dst; 1652 u_int16_t len; 1653 int error; 1654 1655 p = fw; 1656 end = fw + size; 1657 while (p < end) { 1658 if (p + 6 > end) 1659 return EINVAL; 1660 1661 dst = GETLE32(p); p += 4; 1662 len = GETLE16(p); p += 2; 1663 1664 if (p + len > end) 1665 return EINVAL; 1666 1667 ipw_write_mem_1(sc, dst, p, len); 1668 p += len; 1669 } 1670 1671 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1672 IPW_IO_LED_OFF); 1673 1674 /* Allow interrupts so we know when the firmware is inited */ 1675 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1676 1677 /* Tell the adapter to initialize the firmware */ 1678 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1679 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1680 IPW_CTL_ALLOW_STANDBY); 1681 1682 /* Wait at most one second for firmware initialization to complete */ 1683 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1684 printf("%s: timeout waiting for firmware initialization to " 1685 "complete\n", sc->sc_dev.dv_xname); 1686 return error; 1687 } 1688 1689 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1690 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1691 1692 return 0; 1693} 1694 1695/* 1696 * Store firmware into kernel memory so we can download it when we need to, 1697 * e.g when the adapter wakes up from suspend mode. 1698 */ 1699int 1700ipw_cache_firmware(struct ipw_softc *sc, void *data) 1701{ 1702 struct ipw_firmware *fw = &sc->fw; 1703 struct ipw_firmware_hdr hdr; 1704 u_char *p = data; 1705 int error; 1706 1707 if (sc->flags & IPW_FLAG_FW_CACHED) 1708 ipw_free_firmware(sc); 1709 1710 if ((error = copyin(data, &hdr, sizeof hdr)) != 0) 1711 goto fail1; 1712 1713 fw->main_size = letoh32(hdr.main_size); 1714 fw->ucode_size = letoh32(hdr.ucode_size); 1715 p += sizeof hdr; 1716 1717 fw->main = malloc(fw->main_size, M_DEVBUF, M_NOWAIT); 1718 if (fw->main == NULL) { 1719 error = ENOMEM; 1720 goto fail1; 1721 } 1722 1723 fw->ucode = malloc(fw->ucode_size, M_DEVBUF, M_NOWAIT); 1724 if (fw->ucode == NULL) { 1725 error = ENOMEM; 1726 goto fail2; 1727 } 1728 1729 if ((error = copyin(p, fw->main, fw->main_size)) != 0) 1730 goto fail3; 1731 1732 p += fw->main_size; 1733 if ((error = copyin(p, fw->ucode, fw->ucode_size)) != 0) 1734 goto fail3; 1735 1736 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1737 fw->ucode_size)); 1738 1739 sc->flags |= IPW_FLAG_FW_CACHED; 1740 1741 return 0; 1742 1743fail3: free(fw->ucode, M_DEVBUF); 1744fail2: free(fw->main, M_DEVBUF); 1745fail1: return error; 1746} 1747 1748void 1749ipw_free_firmware(struct ipw_softc *sc) 1750{ 1751 free(sc->fw.main, M_DEVBUF); 1752 free(sc->fw.ucode, M_DEVBUF); 1753 1754 sc->flags &= ~IPW_FLAG_FW_CACHED; 1755} 1756 1757int 1758ipw_config(struct ipw_softc *sc) 1759{ 1760 struct ieee80211com *ic = &sc->sc_ic; 1761 struct ifnet *ifp = &ic->ic_if; 1762 struct ipw_security security; 1763 struct ieee80211_wepkey *k; 1764 struct ipw_wep_key wepkey; 1765 struct ipw_scan_options options; 1766 struct ipw_configuration config; 1767 u_int32_t data; 1768 int error, i; 1769 1770 switch (ic->ic_opmode) { 1771 case IEEE80211_M_STA: 1772 case IEEE80211_M_HOSTAP: 1773 data = htole32(IPW_MODE_BSS); 1774 break; 1775 1776 case IEEE80211_M_IBSS: 1777 case IEEE80211_M_AHDEMO: 1778 data = htole32(IPW_MODE_IBSS); 1779 break; 1780 1781 case IEEE80211_M_MONITOR: 1782 data = htole32(IPW_MODE_MONITOR); 1783 break; 1784 } 1785 DPRINTF(("Setting adapter mode to %u\n", data)); 1786 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1787 if (error != 0) 1788 return error; 1789 1790 if (ic->ic_opmode == IEEE80211_M_IBSS || 1791 ic->ic_opmode == IEEE80211_M_MONITOR) { 1792 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1793 DPRINTF(("Setting adapter channel to %u\n", data)); 1794 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1795 if (error != 0) 1796 return error; 1797 } 1798 1799 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1800 DPRINTF(("Enabling adapter\n")); 1801 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1802 } 1803 1804 DPRINTF(("Setting adapter MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1805 IEEE80211_ADDR_COPY(((struct arpcom *)ifp)->ac_enaddr, ic->ic_myaddr); 1806 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1807 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1808 IEEE80211_ADDR_LEN); 1809 if (error != 0) 1810 return error; 1811 1812 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1813 IPW_CFG_PREAMBLE_LEN | IPW_CFG_802_1x_ENABLE); 1814 if (ic->ic_opmode == IEEE80211_M_IBSS) 1815 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1816 if (ifp->if_flags & IFF_PROMISC) 1817 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1818 config.channels = htole32(0x3fff); /* channels 1-14 */ 1819 config.ibss_chan = htole32(0x7ff); 1820 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1821 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1822 if (error != 0) 1823 return error; 1824 1825 data = htole32(0x3); /* 1, 2 */ 1826 DPRINTF(("Setting adapter basic tx rates to 0x%x\n", data)); 1827 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1828 if (error != 0) 1829 return error; 1830 1831 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1832 DPRINTF(("Setting adapter tx rates to 0x%x\n", data)); 1833 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1834 if (error != 0) 1835 return error; 1836 1837 data = htole32(IPW_POWER_MODE_CAM); 1838 DPRINTF(("Setting adapter power mode to %u\n", data)); 1839 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1840 if (error != 0) 1841 return error; 1842 1843 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1844 data = htole32(ic->ic_txpower); 1845 DPRINTF(("Setting adapter tx power index to %u\n", data)); 1846 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1847 sizeof data); 1848 if (error != 0) 1849 return error; 1850 } 1851 1852 data = htole32(ic->ic_rtsthreshold); 1853 DPRINTF(("Setting adapter RTS threshold to %u\n", data)); 1854 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1855 if (error != 0) 1856 return error; 1857 1858 data = htole32(ic->ic_fragthreshold); 1859 DPRINTF(("Setting adapter frag threshold to %u\n", data)); 1860 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1861 if (error != 0) 1862 return error; 1863 1864#ifdef IPW_DEBUG 1865 if (ipw_debug > 0) { 1866 printf("Setting adapter ESSID to "); 1867 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1868 printf("\n"); 1869 } 1870#endif 1871 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1872 ic->ic_des_esslen); 1873 if (error != 0) 1874 return error; 1875 1876 /* no mandatory BSSID */ 1877 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1878 if (error != 0) 1879 return error; 1880 1881 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1882 DPRINTF(("Setting adapter desired BSSID to %s\n", 1883 ether_sprintf(ic->ic_des_bssid))); 1884 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1885 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1886 if (error != 0) 1887 return error; 1888 } 1889 1890 security.authmode = (sc->authmode == IEEE80211_AUTH_SHARED) ? 1891 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 1892 security.ciphers = htole32(IPW_CIPHER_NONE); 1893 security.version = htole16(0); 1894 security.replay_counters_number = 0; 1895 security.unicast_using_group = 0; 1896 DPRINTF(("Setting adapter authmode to %u\n", security.authmode)); 1897 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1898 sizeof security); 1899 if (error != 0) 1900 return error; 1901 1902 if (ic->ic_flags & IEEE80211_F_WEPON) { 1903 k = ic->ic_nw_keys; 1904 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1905 if (k->wk_len == 0) 1906 continue; 1907 1908 wepkey.idx = i; 1909 wepkey.len = k->wk_len; 1910 bzero(wepkey.key, sizeof wepkey.key); 1911 bcopy(k->wk_key, wepkey.key, k->wk_len); 1912 DPRINTF(("Setting wep key index %d len %d\n", 1913 wepkey.idx, wepkey.len)); 1914 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1915 sizeof wepkey); 1916 if (error != 0) 1917 return error; 1918 } 1919 1920 data = htole32(ic->ic_wep_txkey); 1921 DPRINTF(("Setting adapter tx key index to %u\n", data)); 1922 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1923 sizeof data); 1924 if (error != 0) 1925 return error; 1926 } 1927 1928 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_WEPON) ? 0x8 : 0); 1929 DPRINTF(("Setting adapter wep flags to 0x%x\n", data)); 1930 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1931 if (error != 0) 1932 return error; 1933 1934 if (ic->ic_opmode == IEEE80211_M_IBSS || 1935 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1936 data = htole32(ic->ic_lintval); 1937 DPRINTF(("Setting adapter beacon interval to %u\n", data)); 1938 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1939 sizeof data); 1940 if (error != 0) 1941 return error; 1942 } 1943 1944 options.flags = htole32(0); 1945 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1946 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1947 if (error != 0) 1948 return error; 1949 1950 /* finally, enable adapter (start scanning for an access point) */ 1951 DPRINTF(("Enabling adapter\n")); 1952 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1953} 1954 1955int 1956ipw_init(struct ifnet *ifp) 1957{ 1958 struct ipw_softc *sc = ifp->if_softc; 1959 struct ipw_firmware *fw = &sc->fw; 1960 int error; 1961 1962 /* exit immediately if firmware has not been ioctl'd */ 1963 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 1964 ifp->if_flags &= ~IFF_UP; 1965 return EIO; 1966 } 1967 1968 if ((error = ipw_reset(sc)) != 0) { 1969 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 1970 goto fail; 1971 } 1972 1973 if ((error = ipw_load_ucode(sc, fw->ucode, fw->ucode_size)) != 0) { 1974 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 1975 goto fail; 1976 } 1977 1978 ipw_stop_master(sc); 1979 1980 if ((error = ipw_rx_init(sc)) != 0) { 1981 printf("%s: could not initialize rx queue\n", 1982 sc->sc_dev.dv_xname); 1983 goto fail; 1984 } 1985 1986 if ((error = ipw_tx_init(sc)) != 0) { 1987 printf("%s: could not initialize tx queue\n", 1988 sc->sc_dev.dv_xname); 1989 goto fail; 1990 } 1991 1992 if ((error = ipw_load_firmware(sc, fw->main, fw->main_size)) != 0) { 1993 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 1994 goto fail; 1995 } 1996 1997 sc->flags |= IPW_FLAG_FW_INITED; 1998 1999 /* Retrieve information tables base addresses */ 2000 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2001 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2002 2003 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2004 2005 if ((error = ipw_config(sc)) != 0) { 2006 printf("%s: device configuration failed\n", 2007 sc->sc_dev.dv_xname); 2008 goto fail; 2009 } 2010 2011 ifp->if_flags &= ~IFF_OACTIVE; 2012 ifp->if_flags |= IFF_RUNNING; 2013 2014 return 0; 2015 2016fail: ipw_stop(ifp, 0); 2017 2018 return error; 2019} 2020 2021void 2022ipw_stop(struct ifnet *ifp, int disable) 2023{ 2024 struct ipw_softc *sc = ifp->if_softc; 2025 struct ieee80211com *ic = &sc->sc_ic; 2026 2027 ipw_stop_master(sc); 2028 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2029 2030 ipw_tx_stop(sc); 2031 ipw_rx_stop(sc); 2032 2033 ifp->if_timer = 0; 2034 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2035 2036 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2037} 2038 2039void 2040ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 2041 bus_size_t count) 2042{ 2043 for (; count > 0; offset++, datap++, count--) { 2044 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2045 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2046 } 2047} 2048 2049void 2050ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 2051 bus_size_t count) 2052{ 2053 for (; count > 0; offset++, datap++, count--) { 2054 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2055 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2056 } 2057} 2058 2059struct cfdriver ipw_cd = { 2060 0, "ipw", DV_IFNET 2061}; 2062