if_ipw.c revision 1.14
1/* $Id: if_ipw.c,v 1.14 2004/10/27 21:23:01 damien Exp $ */ 2 3/*- 4 * Copyright (c) 2004 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/*- 31 * Intel(R) PRO/Wireless 2100 MiniPCI driver 32 * www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 33 */ 34 35#include "bpfilter.h" 36 37#include <sys/param.h> 38#include <sys/sockio.h> 39#include <sys/sysctl.h> 40#include <sys/mbuf.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43#include <sys/systm.h> 44#include <sys/malloc.h> 45#include <sys/conf.h> 46 47#include <machine/bus.h> 48#include <machine/endian.h> 49#include <machine/intr.h> 50 51#include <dev/pci/pcireg.h> 52#include <dev/pci/pcivar.h> 53#include <dev/pci/pcidevs.h> 54 55#if NBPFILTER > 0 56#include <net/bpf.h> 57#endif 58#include <net/if.h> 59#include <net/if_arp.h> 60#include <net/if_dl.h> 61#include <net/if_media.h> 62#include <net/if_types.h> 63 64#include <netinet/in.h> 65#include <netinet/in_systm.h> 66#include <netinet/in_var.h> 67#include <netinet/if_ether.h> 68#include <netinet/ip.h> 69 70#include <net80211/ieee80211_var.h> 71#include <net80211/ieee80211_radiotap.h> 72 73#include <dev/pci/if_ipwreg.h> 74#include <dev/pci/if_ipwvar.h> 75 76static const struct ieee80211_rateset ipw_rateset_11b = 77 { 4, { 2, 4, 11, 22 } }; 78 79int ipw_match(struct device *, void *, void *); 80void ipw_attach(struct device *, struct device *, void *); 81int ipw_detach(struct device *, int); 82int ipw_media_change(struct ifnet *); 83void ipw_media_status(struct ifnet *, struct ifmediareq *); 84int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 85u_int16_t ipw_read_prom_word(struct ipw_softc *, u_int8_t); 86void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 87void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 88void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 89 struct ipw_soft_bd *, struct ipw_soft_buf *); 90void ipw_notification_intr(struct ipw_softc *, struct ipw_soft_buf *); 91void ipw_rx_intr(struct ipw_softc *); 92void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 93void ipw_tx_intr(struct ipw_softc *); 94int ipw_intr(void *); 95int ipw_cmd(struct ipw_softc *, u_int32_t, void *, u_int32_t); 96int ipw_tx_start(struct ifnet *, struct mbuf *, struct ieee80211_node *); 97void ipw_start(struct ifnet *); 98void ipw_watchdog(struct ifnet *); 99int ipw_get_table1(struct ipw_softc *, u_int32_t *); 100int ipw_get_radio(struct ipw_softc *, int *); 101int ipw_ioctl(struct ifnet *, u_long, caddr_t); 102u_int32_t ipw_read_table1(struct ipw_softc *, u_int32_t); 103void ipw_write_table1(struct ipw_softc *, u_int32_t, u_int32_t); 104int ipw_read_table2(struct ipw_softc *, u_int32_t, void *, u_int32_t *); 105int ipw_tx_init(struct ipw_softc *); 106void ipw_tx_stop(struct ipw_softc *); 107int ipw_rx_init(struct ipw_softc *); 108void ipw_rx_stop(struct ipw_softc *); 109void ipw_stop_master(struct ipw_softc *); 110int ipw_reset(struct ipw_softc *); 111int ipw_load_ucode(struct ipw_softc *, u_char *, int); 112int ipw_load_firmware(struct ipw_softc *, u_char *, int); 113int ipw_cache_firmware(struct ipw_softc *, void *); 114void ipw_free_firmware(struct ipw_softc *); 115int ipw_config(struct ipw_softc *); 116int ipw_init(struct ifnet *); 117void ipw_stop(struct ifnet *, int); 118void ipw_read_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, bus_size_t); 119void ipw_write_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, bus_size_t); 120 121static __inline u_int8_t MEM_READ_1(struct ipw_softc *sc, u_int32_t addr) 122{ 123 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 124 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 125} 126 127static __inline u_int32_t MEM_READ_4(struct ipw_softc *sc, u_int32_t addr) 128{ 129 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 130 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 131} 132 133#ifdef IPW_DEBUG 134#define DPRINTF(x) if (ipw_debug > 0) printf x 135#define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 136int ipw_debug = 0; 137#else 138#define DPRINTF(x) 139#define DPRINTFN(n, x) 140#endif 141 142struct cfattach ipw_ca = { 143 sizeof (struct ipw_softc), ipw_match, ipw_attach, ipw_detach 144}; 145 146int 147ipw_match(struct device *parent, void *match, void *aux) 148{ 149 struct pci_attach_args *pa = aux; 150 151 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 152 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_2100_3B) 153 return 1; 154 155 return 0; 156} 157 158/* Base Address Register */ 159#define IPW_PCI_BAR0 0x10 160 161void 162ipw_attach(struct device *parent, struct device *self, void *aux) 163{ 164 struct ipw_softc *sc = (struct ipw_softc *)self; 165 struct ieee80211com *ic = &sc->sc_ic; 166 struct ifnet *ifp = &ic->ic_if; 167 struct pci_attach_args *pa = aux; 168 const char *intrstr; 169 bus_space_tag_t memt; 170 bus_space_handle_t memh; 171 bus_addr_t base; 172 pci_intr_handle_t ih; 173 pcireg_t data; 174 u_int16_t val; 175 int error, i; 176 177 sc->sc_pct = pa->pa_pc; 178 179 data = pci_conf_read(sc->sc_pct, pa->pa_tag, 0x40); 180 data &= ~0x00ff0000; 181 pci_conf_write(sc->sc_pct, pa->pa_tag, 0x40, data); 182 183 /* enable bus-mastering */ 184 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 185 data |= PCI_COMMAND_MASTER_ENABLE; 186 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 187 188 /* map the register window */ 189 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 190 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 191 if (error != 0) { 192 printf(": could not map memory space\n"); 193 return; 194 } 195 196 sc->sc_st = memt; 197 sc->sc_sh = memh; 198 sc->sc_dmat = pa->pa_dmat; 199 200 /* disable interrupts */ 201 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 202 203 if (pci_intr_map(pa, &ih) != 0) { 204 printf(": could not map interrupt\n"); 205 return; 206 } 207 208 intrstr = pci_intr_string(sc->sc_pct, ih); 209 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 210 sc->sc_dev.dv_xname); 211 if (sc->sc_ih == NULL) { 212 printf(": could not establish interrupt"); 213 if (intrstr != NULL) 214 printf(" at %s", intrstr); 215 printf("\n"); 216 return; 217 } 218 printf(": %s\n", intrstr); 219 220 if (ipw_reset(sc) != 0) { 221 printf(": could not reset adapter\n"); 222 return; 223 } 224 225 ic->ic_phytype = IEEE80211_T_DS; 226 ic->ic_opmode = IEEE80211_M_STA; 227 ic->ic_state = IEEE80211_S_INIT; 228 229 /* set device capabilities */ 230 ic->ic_caps = IEEE80211_C_IBSS | IEEE80211_C_MONITOR | 231 IEEE80211_C_PMGT | IEEE80211_C_TXPMGT | IEEE80211_C_WEP; 232 233 /* read MAC address from EEPROM */ 234 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 235 ic->ic_myaddr[0] = val >> 8; 236 ic->ic_myaddr[1] = val & 0xff; 237 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 238 ic->ic_myaddr[2] = val >> 8; 239 ic->ic_myaddr[3] = val & 0xff; 240 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 241 ic->ic_myaddr[4] = val >> 8; 242 ic->ic_myaddr[5] = val & 0xff; 243 244 /* set supported .11b rates */ 245 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 246 247 /* set supported .11b channels (1 through 14) */ 248 for (i = 1; i <= 14; i++) { 249 ic->ic_channels[i].ic_freq = 250 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 251 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 252 } 253 254 /* default to authmode OPEN */ 255 sc->authmode = IEEE80211_AUTH_OPEN; 256 257 /* IBSS channel undefined for now */ 258 ic->ic_ibss_chan = &ic->ic_channels[0]; 259 260 ifp->if_softc = sc; 261 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 262 ifp->if_init = ipw_init; 263 ifp->if_ioctl = ipw_ioctl; 264 ifp->if_start = ipw_start; 265 ifp->if_watchdog = ipw_watchdog; 266 IFQ_SET_READY(&ifp->if_snd); 267 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 268 269 if_attach(ifp); 270 ieee80211_ifattach(ifp); 271 /* override state transition machine */ 272 sc->sc_newstate = ic->ic_newstate; 273 ic->ic_newstate = ipw_newstate; 274 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 275 276#if NBPFILTER > 0 277 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 278 sizeof (struct ieee80211_frame) + 64); 279 280 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 281 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 282 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 283 284 sc->sc_txtap_len = sizeof sc->sc_txtapu; 285 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 286 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 287#endif 288} 289 290int 291ipw_detach(struct device* self, int flags) 292{ 293 struct ipw_softc *sc = (struct ipw_softc *)self; 294 struct ifnet *ifp = &sc->sc_ic.ic_if; 295 296 ipw_stop(ifp, 1); 297 298 if (sc->flags & IPW_FLAG_FW_CACHED) 299 ipw_free_firmware(sc); 300 301#if NBPFILTER > 0 302 bpfdetach(ifp); 303#endif 304 ieee80211_ifdetach(ifp); 305 if_detach(ifp); 306 307 if (sc->sc_ih != NULL) { 308 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 309 sc->sc_ih = NULL; 310 } 311 312 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 313 314 return 0; 315} 316 317int 318ipw_media_change(struct ifnet *ifp) 319{ 320 int error; 321 322 error = ieee80211_media_change(ifp); 323 if (error != ENETRESET) 324 return error; 325 326 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 327 ipw_init(ifp); 328 329 return 0; 330} 331 332void 333ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 334{ 335 struct ipw_softc *sc = ifp->if_softc; 336 struct ieee80211com *ic = &sc->sc_ic; 337#define N(a) (sizeof (a) / sizeof (a[0])) 338 static const struct { 339 u_int32_t val; 340 int rate; 341 } rates[] = { 342 { IPW_RATE_DS1, 2 }, 343 { IPW_RATE_DS2, 4 }, 344 { IPW_RATE_DS5, 11 }, 345 { IPW_RATE_DS11, 22 }, 346 }; 347 u_int32_t val; 348 int rate, i; 349 350 imr->ifm_status = IFM_AVALID; 351 imr->ifm_active = IFM_IEEE80211; 352 if (ic->ic_state == IEEE80211_S_RUN) 353 imr->ifm_status |= IFM_ACTIVE; 354 355 /* read current transmission rate from adapter */ 356 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 357 val &= 0xf; 358 359 /* convert rate to 802.11 rate */ 360 for (i = 0; i < N(rates) && rates[i].val != val; i++); 361 rate = (i < N(rates)) ? rates[i].rate : 0; 362 363 imr->ifm_active |= IFM_IEEE80211_11B; 364 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 365 switch (ic->ic_opmode) { 366 case IEEE80211_M_STA: 367 break; 368 369 case IEEE80211_M_IBSS: 370 imr->ifm_active |= IFM_IEEE80211_ADHOC; 371 break; 372 373 case IEEE80211_M_MONITOR: 374 imr->ifm_active |= IFM_IEEE80211_MONITOR; 375 break; 376 377 case IEEE80211_M_AHDEMO: 378 case IEEE80211_M_HOSTAP: 379 /* should not get there */ 380 break; 381 } 382#undef N 383} 384 385int 386ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 387{ 388 struct ipw_softc *sc = ic->ic_softc; 389 struct ieee80211_node *ni = ic->ic_bss; 390 u_int32_t val, len; 391 392 switch (nstate) { 393 case IEEE80211_S_RUN: 394 len = IEEE80211_NWID_LEN; 395 ipw_read_table2(sc, IPW_INFO_CURRENT_SSID, ni->ni_essid, &len); 396 ni->ni_esslen = len; 397 398 val = ipw_read_table1(sc, IPW_INFO_CURRENT_CHANNEL); 399 ni->ni_chan = &ic->ic_channels[val]; 400 401 DELAY(100); /* firmware needs a short delay here */ 402 403 len = IEEE80211_ADDR_LEN; 404 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, ni->ni_bssid, &len); 405 break; 406 407 case IEEE80211_S_INIT: 408 case IEEE80211_S_SCAN: 409 case IEEE80211_S_AUTH: 410 case IEEE80211_S_ASSOC: 411 break; 412 } 413 414 ic->ic_state = nstate; 415 return 0; 416} 417 418/* 419 * Read 16 bits at address 'addr' from the Microwire EEPROM. 420 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 421 */ 422u_int16_t 423ipw_read_prom_word(struct ipw_softc *sc, u_int8_t addr) 424{ 425 u_int32_t tmp; 426 u_int16_t val; 427 int n; 428 429 /* Clock C once before the first command */ 430 IPW_EEPROM_CTL(sc, 0); 431 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 432 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 433 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 434 435 /* Write start bit (1) */ 436 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 437 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 438 439 /* Write READ opcode (10) */ 440 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 441 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 442 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 443 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 444 445 /* Write address A7-A0 */ 446 for (n = 7; n >= 0; n--) { 447 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 448 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 449 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 450 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 451 } 452 453 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 454 455 /* Read data Q15-Q0 */ 456 val = 0; 457 for (n = 15; n >= 0; n--) { 458 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 459 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 460 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 461 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 462 } 463 464 IPW_EEPROM_CTL(sc, 0); 465 466 /* Clear Chip Select and clock C */ 467 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 468 IPW_EEPROM_CTL(sc, 0); 469 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 470 471 return letoh16(val); 472} 473 474void 475ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 476{ 477 struct ipw_cmd *cmd; 478 479 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 480 BUS_DMASYNC_POSTREAD); 481 482 cmd = mtod(sbuf->m, struct ipw_cmd *); 483 484 DPRINTFN(2, ("RX!CMD!%u!%u!%u!%u!%u\n", 485 letoh32(cmd->type), letoh32(cmd->subtype), letoh32(cmd->seq), 486 letoh32(cmd->len), letoh32(cmd->status))); 487 488 wakeup(sc); 489} 490 491void 492ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 493{ 494 struct ieee80211com *ic = &sc->sc_ic; 495 u_int32_t state; 496 497 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 498 BUS_DMASYNC_POSTREAD); 499 500 state = letoh32(*mtod(sbuf->m, u_int32_t *)); 501 502 DPRINTFN(2, ("RX!NEWSTATE!%u\n", state)); 503 504 switch (state) { 505 case IPW_STATE_ASSOCIATED: 506 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 507 break; 508 509 case IPW_STATE_SCANNING: 510 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 511 break; 512 513 case IPW_STATE_ASSOCIATION_LOST: 514 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 515 break; 516 517 case IPW_STATE_RADIO_DISABLED: 518 /* XXX should turn the interface down */ 519 break; 520 } 521} 522 523void 524ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 525 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 526{ 527 struct ieee80211com *ic = &sc->sc_ic; 528 struct ifnet *ifp = &ic->ic_if; 529 struct mbuf *m; 530 struct ieee80211_frame *wh; 531 struct ieee80211_node *ni; 532 int error; 533 534 DPRINTFN(5, ("RX!DATA!%u!%u\n", letoh32(status->len), status->rssi)); 535 536 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 537 BUS_DMASYNC_POSTREAD); 538 539 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 540 541 /* Finalize mbuf */ 542 m = sbuf->m; 543 m->m_pkthdr.rcvif = ifp; 544 m->m_pkthdr.len = m->m_len = letoh32(status->len); 545 546#if NBPFILTER > 0 547 if (sc->sc_drvbpf != NULL) { 548 struct mbuf mb; 549 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 550 551 tap->wr_flags = 0; 552 tap->wr_antsignal = status->rssi; 553 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 554 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 555 556 M_DUP_PKTHDR(&mb, m); 557 mb.m_data = (caddr_t)tap; 558 mb.m_len = sc->sc_rxtap_len; 559 mb.m_next = m; 560 mb.m_pkthdr.len += mb.m_len; 561 bpf_mtap(sc->sc_drvbpf, &mb); 562 } 563#endif 564 565 wh = mtod(m, struct ieee80211_frame *); 566 567 ni = ieee80211_find_rxnode(ic, wh); 568 569 /* Send it up to the upper layer */ 570 ieee80211_input(ifp, m, ni, status->rssi, 0); 571 572 if (ni == ic->ic_bss) 573 ieee80211_unref_node(&ni); 574 else 575 ieee80211_free_node(ic, ni); 576 577 MGETHDR(m, M_DONTWAIT, MT_DATA); 578 if (m == NULL) { 579 printf("%s: could not allocate rx mbuf\n", 580 sc->sc_dev.dv_xname); 581 return; 582 } 583 MCLGET(m, M_DONTWAIT); 584 if (!(m->m_flags & M_EXT)) { 585 m_freem(m); 586 printf("%s: could not allocate rx mbuf cluster\n", 587 sc->sc_dev.dv_xname); 588 return; 589 } 590 591 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(m, void *), 592 MCLBYTES, NULL, BUS_DMA_NOWAIT); 593 if (error != 0) { 594 printf("%s: could not map rxbuf dma memory\n", 595 sc->sc_dev.dv_xname); 596 m_freem(m); 597 return; 598 } 599 600 sbuf->m = m; 601 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 602} 603 604void 605ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 606{ 607 DPRINTFN(2, ("RX!NOTIFICATION\n")); 608} 609 610void 611ipw_rx_intr(struct ipw_softc *sc) 612{ 613 struct ipw_status *status; 614 struct ipw_soft_bd *sbd; 615 struct ipw_soft_buf *sbuf; 616 u_int32_t r, i; 617 618 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 619 620 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 621 622 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 623 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 624 BUS_DMASYNC_POSTREAD); 625 626 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 627 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 628 BUS_DMASYNC_POSTREAD); 629 630 status = &sc->status_list[i]; 631 sbd = &sc->srbd_list[i]; 632 sbuf = sbd->priv; 633 634 switch (letoh16(status->code) & 0xf) { 635 case IPW_STATUS_CODE_COMMAND: 636 ipw_command_intr(sc, sbuf); 637 break; 638 639 case IPW_STATUS_CODE_NEWSTATE: 640 ipw_newstate_intr(sc, sbuf); 641 break; 642 643 case IPW_STATUS_CODE_DATA_802_3: 644 case IPW_STATUS_CODE_DATA_802_11: 645 ipw_data_intr(sc, status, sbd, sbuf); 646 break; 647 648 case IPW_STATUS_CODE_NOTIFICATION: 649 ipw_notification_intr(sc, sbuf); 650 break; 651 652 default: 653 printf("%s: unknown status code %u\n", 654 sc->sc_dev.dv_xname, letoh16(status->code)); 655 } 656 sbd->bd->flags = 0; 657 658 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 659 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 660 BUS_DMASYNC_PREWRITE); 661 } 662 663 /* Tell the firmware what we have processed */ 664 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 665 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 666} 667 668void 669ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 670{ 671 struct ieee80211com *ic; 672 struct ipw_soft_hdr *shdr; 673 struct ipw_soft_buf *sbuf; 674 675 switch (sbd->type) { 676 case IPW_SBD_TYPE_COMMAND: 677 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 678 break; 679 680 case IPW_SBD_TYPE_HEADER: 681 shdr = sbd->priv; 682 bus_dmamap_unload(sc->sc_dmat, shdr->map); 683 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 684 break; 685 686 case IPW_SBD_TYPE_DATA: 687 ic = &sc->sc_ic; 688 sbuf = sbd->priv; 689 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 690 m_freem(sbuf->m); 691 if (sbuf->ni != NULL && sbuf->ni != ic->ic_bss) 692 ieee80211_free_node(ic, sbuf->ni); 693 /* kill watchdog timer */ 694 sc->sc_tx_timer = 0; 695 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 696 break; 697 } 698 sbd->type = IPW_SBD_TYPE_NOASSOC; 699} 700 701void 702ipw_tx_intr(struct ipw_softc *sc) 703{ 704 struct ifnet *ifp = &sc->sc_ic.ic_if; 705 u_int32_t r, i; 706 707 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 708 709 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) 710 ipw_release_sbd(sc, &sc->stbd_list[i]); 711 712 /* Remember what the firmware has processed */ 713 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 714 715 /* Call start() since some buffer descriptors have been released */ 716 ifp->if_flags &= ~IFF_OACTIVE; 717 (*ifp->if_start)(ifp); 718} 719 720int 721ipw_intr(void *arg) 722{ 723 struct ipw_softc *sc = arg; 724 u_int32_t r; 725 726 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0) 727 return 0; 728 729 /* Disable interrupts */ 730 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 731 732 DPRINTFN(8, ("INTR!0x%08x\n", r)); 733 734 if (r & IPW_INTR_RX_TRANSFER) 735 ipw_rx_intr(sc); 736 737 if (r & IPW_INTR_TX_TRANSFER) 738 ipw_tx_intr(sc); 739 740 if (r & IPW_INTR_FW_INIT_DONE) { 741 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 742 wakeup(sc); 743 } 744 745 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 746 printf("%s: fatal error\n", sc->sc_dev.dv_xname); 747 ipw_stop(&sc->sc_ic.ic_if, 1); 748 } 749 750 /* Acknowledge interrupts */ 751 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 752 753 /* Re-enable interrupts */ 754 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 755 756 return 0; 757} 758 759int 760ipw_cmd(struct ipw_softc *sc, u_int32_t type, void *data, u_int32_t len) 761{ 762 struct ipw_soft_bd *sbd; 763 int error; 764 765 sbd = &sc->stbd_list[sc->txcur]; 766 767 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, sc->cmd, 768 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 769 if (error != 0) { 770 printf("%s: could not map cmd dma memory\n", 771 sc->sc_dev.dv_xname); 772 return error; 773 } 774 775 sc->cmd->type = htole32(type); 776 sc->cmd->subtype = htole32(0); 777 sc->cmd->len = htole32(len); 778 sc->cmd->seq = htole32(0); 779 if (data != NULL) 780 bcopy(data, sc->cmd->data, len); 781 782 sbd->type = IPW_SBD_TYPE_COMMAND; 783 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 784 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 785 sbd->bd->nfrag = 1; 786 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 787 IPW_BD_FLAG_TX_LAST_FRAGMENT; 788 789 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 790 BUS_DMASYNC_PREWRITE); 791 792 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 793 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 794 BUS_DMASYNC_PREWRITE); 795 796 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 797 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 798 799 DPRINTFN(2, ("TX!CMD!%u!%u!%u!%u\n", type, 0, 0, len)); 800 801 /* Wait at most one second for command to complete */ 802 return tsleep(sc, 0, "ipwcmd", hz); 803} 804 805int 806ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 807{ 808 struct ipw_softc *sc = ifp->if_softc; 809 struct ieee80211com *ic = &sc->sc_ic; 810 struct ieee80211_frame *wh; 811 struct ipw_soft_bd *sbd; 812 struct ipw_soft_hdr *shdr; 813 struct ipw_soft_buf *sbuf; 814 int error, i; 815 816 if (ic->ic_flags & IEEE80211_F_WEPON) { 817 m = ieee80211_wep_crypt(ifp, m, 1); 818 if (m == NULL) 819 return ENOBUFS; 820 } 821 822#if NBPFILTER > 0 823 if (sc->sc_drvbpf != NULL) { 824 struct mbuf mb; 825 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 826 827 tap->wt_flags = 0; 828 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 829 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 830 831 M_DUP_PKTHDR(&mb, m); 832 mb.m_data = (caddr_t)tap; 833 mb.m_len = sc->sc_txtap_len; 834 mb.m_next = m; 835 mb.m_pkthdr.len += mb.m_len; 836 bpf_mtap(sc->sc_drvbpf, &mb); 837 } 838#endif 839 840 wh = mtod(m, struct ieee80211_frame *); 841 842 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 843 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 844 845 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 846 shdr->hdr.subtype = htole32(0); 847 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 848 shdr->hdr.encrypt = 0; 849 shdr->hdr.keyidx = 0; 850 shdr->hdr.keysz = 0; 851 shdr->hdr.fragmentsz = htole16(0); 852 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 853 if (ic->ic_opmode == IEEE80211_M_STA) 854 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 855 else 856 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 857 858 /* trim IEEE802.11 header */ 859 m_adj(m, sizeof (struct ieee80211_frame)); 860 861 /* 862 * We need to map the mbuf first to know how many buffer descriptors 863 * are needed for this transfer. 864 */ 865 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 866 if (error != 0) { 867 printf("%s: could not map mbuf (error %d)\n", 868 sc->sc_dev.dv_xname, error); 869 m_freem(m); 870 return error; 871 } 872 873 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 874 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 875 if (error != 0) { 876 printf("%s: could not map header (error %d)\n", 877 sc->sc_dev.dv_xname, error); 878 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 879 m_freem(m); 880 return error; 881 } 882 883 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 884 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 885 886 sbd = &sc->stbd_list[sc->txcur]; 887 sbd->type = IPW_SBD_TYPE_HEADER; 888 sbd->priv = shdr; 889 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 890 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 891 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 892 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 893 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 894 895 DPRINTFN(5, ("TX!HDR!%u!%u!%u!%u", shdr->hdr.type, shdr->hdr.subtype, 896 shdr->hdr.encrypted, shdr->hdr.encrypt)); 897 DPRINTFN(5, ("!%s", ether_sprintf(shdr->hdr.src_addr))); 898 DPRINTFN(5, ("!%s\n", ether_sprintf(shdr->hdr.dst_addr))); 899 900 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 901 sc->txcur * sizeof (struct ipw_bd), 902 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 903 904 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 905 906 sbuf->m = m; 907 sbuf->ni = ni; 908 909 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 910 sbd = &sc->stbd_list[sc->txcur]; 911 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 912 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 913 sbd->bd->nfrag = 0; /* used only in first bd */ 914 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 915 if (i == sbuf->map->dm_nsegs - 1) { 916 sbd->type = IPW_SBD_TYPE_DATA; 917 sbd->priv = sbuf; 918 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 919 } else { 920 sbd->type = IPW_SBD_TYPE_NOASSOC; 921 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 922 } 923 924 DPRINTFN(5, ("TX!FRAG!%d!%d\n", i, 925 sbuf->map->dm_segs[i].ds_len)); 926 927 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 928 sc->txcur * sizeof (struct ipw_bd), 929 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 930 931 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 932 } 933 934 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 935 BUS_DMASYNC_PREWRITE); 936 937 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 938 BUS_DMASYNC_PREWRITE); 939 940 /* Inform firmware about this new packet */ 941 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 942 943 return 0; 944} 945 946void 947ipw_start(struct ifnet *ifp) 948{ 949 struct ipw_softc *sc = ifp->if_softc; 950 struct ieee80211com *ic = &sc->sc_ic; 951 struct mbuf *m; 952 struct ieee80211_node *ni; 953 954 for (;;) { 955 IF_DEQUEUE(&ifp->if_snd, m); 956 if (m == NULL) 957 break; 958 959#if NBPFILTER > 0 960 if (ifp->if_bpf != NULL) 961 bpf_mtap(ifp->if_bpf, m); 962#endif 963 964 m = ieee80211_encap(ifp, m, &ni); 965 if (m == NULL) 966 continue; 967 968#if NBPFILTER > 0 969 if (ic->ic_rawbpf != NULL) 970 bpf_mtap(ic->ic_rawbpf, m); 971#endif 972 973 if (ipw_tx_start(ifp, m, ni) != 0) { 974 if (ni != NULL && ni != ic->ic_bss) 975 ieee80211_free_node(ic, ni); 976 break; 977 } 978 979 /* start watchdog timer */ 980 sc->sc_tx_timer = 5; 981 ifp->if_timer = 1; 982 } 983} 984 985void 986ipw_watchdog(struct ifnet *ifp) 987{ 988 struct ipw_softc *sc = ifp->if_softc; 989 990 ifp->if_timer = 0; 991 992 if (sc->sc_tx_timer > 0) { 993 if (--sc->sc_tx_timer == 0) { 994 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 995#ifdef notyet 996 ipw_init(ifp); 997#endif 998 return; 999 } 1000 ifp->if_timer = 1; 1001 } 1002 1003 ieee80211_watchdog(ifp); 1004} 1005 1006int 1007ipw_get_table1(struct ipw_softc *sc, u_int32_t *tbl) 1008{ 1009 u_int32_t i, size, buf[256]; 1010 1011 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 1012 bzero(buf, sizeof buf); 1013 return copyout(buf, tbl, sizeof buf); 1014 } 1015 1016 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1017 1018 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1019 for (i = 1; i < size; i++) 1020 buf[i] = MEM_READ_4(sc, CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA)); 1021 1022 return copyout(buf, tbl, size * sizeof (u_int32_t)); 1023} 1024 1025int 1026ipw_get_radio(struct ipw_softc *sc, int *ret) 1027{ 1028 int val; 1029 1030 val = (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 0 : 1; 1031 return copyout(&val, ret, sizeof val); 1032} 1033 1034int 1035ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1036{ 1037 struct ipw_softc *sc = ifp->if_softc; 1038 struct ifreq *ifr; 1039 struct ifaddr *ifa; 1040 int s, error = 0; 1041 1042 s = splnet(); 1043 1044 switch (cmd) { 1045 case SIOCSIFADDR: 1046 ifa = (struct ifaddr *) data; 1047 ifp->if_flags |= IFF_UP; 1048 switch (ifa->ifa_addr->sa_family) { 1049#ifdef INET 1050 case AF_INET: 1051 arp_ifinit(&sc->sc_ic.ic_ac, ifa); 1052 ipw_init(ifp); 1053 break; 1054#endif 1055 default: 1056 ipw_init(ifp); 1057 } 1058 break; 1059 1060 case SIOCSIFFLAGS: 1061 if (ifp->if_flags & IFF_UP) { 1062 if (!(ifp->if_flags & IFF_RUNNING)) 1063 ipw_init(ifp); 1064 } else { 1065 if (ifp->if_flags & IFF_RUNNING) 1066 ipw_stop(ifp, 1); 1067 } 1068 break; 1069 1070 case SIOCGTABLE1: 1071 ifr = (struct ifreq *)data; 1072 error = ipw_get_table1(sc, (u_int32_t *)ifr->ifr_data); 1073 break; 1074 1075 case SIOCGRADIO: 1076 ifr = (struct ifreq *)data; 1077 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1078 break; 1079 1080 case SIOCSLOADFW: 1081 /* only super-user can do that! */ 1082 if ((error = suser(curproc, 0)) != 0) 1083 break; 1084 1085 ifr = (struct ifreq *)data; 1086 error = ipw_cache_firmware(sc, ifr->ifr_data); 1087 break; 1088 1089 case SIOCSKILLFW: 1090 /* only super-user can do that! */ 1091 if ((error = suser(curproc, 0)) != 0) 1092 break; 1093 1094 ipw_stop(ifp, 1); 1095 ipw_free_firmware(sc); 1096 break; 1097 1098 case SIOCG80211AUTH: 1099 ((struct ieee80211_auth *)data)->i_authtype = sc->authmode; 1100 break; 1101 1102 case SIOCS80211AUTH: 1103 /* only super-user can do that! */ 1104 if ((error = suser(curproc, 0)) != 0) 1105 break; 1106 1107 sc->authmode = ((struct ieee80211_auth *)data)->i_authtype; 1108 break; 1109 1110 default: 1111 error = ieee80211_ioctl(ifp, cmd, data); 1112 } 1113 1114 if (error == ENETRESET && cmd != SIOCADDMULTI) { 1115 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1116 (IFF_UP | IFF_RUNNING)) 1117 ipw_init(ifp); 1118 error = 0; 1119 } 1120 1121 splx(s); 1122 return error; 1123} 1124 1125u_int32_t 1126ipw_read_table1(struct ipw_softc *sc, u_int32_t off) 1127{ 1128 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1129} 1130 1131void 1132ipw_write_table1(struct ipw_softc *sc, u_int32_t off, u_int32_t info) 1133{ 1134 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1135} 1136 1137int 1138ipw_read_table2(struct ipw_softc *sc, u_int32_t off, void *buf, u_int32_t *len) 1139{ 1140 u_int32_t addr, info; 1141 u_int16_t count, size; 1142 u_int32_t total; 1143 1144 /* addr[4] + count[2] + size[2] */ 1145 addr = MEM_READ_4(sc, sc->table2_base + off); 1146 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1147 1148 count = info >> 16; 1149 size = info & 0xffff; 1150 total = count * size; 1151 1152 if (total > *len) { 1153 *len = total; 1154 return EINVAL; 1155 } 1156 1157 *len = total; 1158 ipw_read_mem_1(sc, addr, buf, total); 1159 1160 return 0; 1161} 1162 1163int 1164ipw_tx_init(struct ipw_softc *sc) 1165{ 1166 char *errmsg; 1167 struct ipw_bd *bd; 1168 struct ipw_soft_bd *sbd; 1169 struct ipw_soft_hdr *shdr; 1170 struct ipw_soft_buf *sbuf; 1171 int error, i, nsegs; 1172 1173 /* Allocate transmission buffer descriptors */ 1174 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 1175 BUS_DMA_NOWAIT, &sc->tbd_map); 1176 if (error != 0) { 1177 errmsg = "could not create tbd dma map"; 1178 goto fail; 1179 } 1180 1181 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 1182 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1183 if (error != 0) { 1184 errmsg = "could not allocate tbd dma memory"; 1185 goto fail; 1186 } 1187 1188 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 1189 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 1190 if (error != 0) { 1191 errmsg = "could not map tbd dma memory"; 1192 goto fail; 1193 } 1194 1195 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 1196 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 1197 if (error != 0) { 1198 errmsg = "could not load tbd dma memory"; 1199 goto fail; 1200 } 1201 1202 sc->stbd_list = malloc(IPW_NTBD * sizeof (struct ipw_soft_bd), 1203 M_DEVBUF, M_NOWAIT); 1204 if (sc->stbd_list == NULL) { 1205 errmsg = "could not allocate soft tbd"; 1206 error = ENOMEM; 1207 goto fail; 1208 } 1209 sbd = sc->stbd_list; 1210 bd = sc->tbd_list; 1211 for (i = 0; i < IPW_NTBD; i++, sbd++, bd++) { 1212 sbd->type = IPW_SBD_TYPE_NOASSOC; 1213 sbd->bd = bd; 1214 } 1215 1216 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1217 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1218 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1219 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1220 sc->txold = IPW_NTBD - 1; /* latest bd index ack'ed by firmware */ 1221 sc->txcur = 0; /* bd index to write to */ 1222 1223 /* Allocate a DMA-able command */ 1224 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 1225 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 1226 if (error != 0) { 1227 errmsg = "could not create cmd dma map"; 1228 goto fail; 1229 } 1230 1231 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 1232 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1233 if (error != 0) { 1234 errmsg = "could not allocate cmd dma memory"; 1235 goto fail; 1236 } 1237 1238 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 1239 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 1240 if (error != 0) { 1241 errmsg = "could not map cmd dma memory"; 1242 goto fail; 1243 } 1244 1245 /* Allocate a pool of DMA-able headers */ 1246 sc->shdr_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_hdr), 1247 M_DEVBUF, M_NOWAIT); 1248 if (sc->shdr_list == NULL) { 1249 errmsg = "could not allocate soft hdr"; 1250 error = ENOMEM; 1251 goto fail; 1252 } 1253 TAILQ_INIT(&sc->sc_free_shdr); 1254 for (i = 0, shdr = sc->shdr_list; i < IPW_NDATA; i++, shdr++) { 1255 error = bus_dmamap_create(sc->sc_dmat, 1256 sizeof (struct ipw_soft_hdr), 1, 1257 sizeof (struct ipw_soft_hdr), 0, BUS_DMA_NOWAIT, 1258 &shdr->map); 1259 if (error != 0) { 1260 errmsg = "could not create hdr dma map"; 1261 goto fail; 1262 } 1263 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1264 } 1265 1266 /* Allocate a pool of DMA-able buffers */ 1267 sc->tx_sbuf_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_buf), 1268 M_DEVBUF, M_NOWAIT); 1269 if (sc->tx_sbuf_list == NULL) { 1270 errmsg = "could not allocate soft txbuf"; 1271 error = ENOMEM; 1272 goto fail; 1273 } 1274 TAILQ_INIT(&sc->sc_free_sbuf); 1275 for (i = 0, sbuf = sc->tx_sbuf_list; i < IPW_NDATA; i++, sbuf++) { 1276 error = bus_dmamap_create(sc->sc_dmat, IPW_NDATA * MCLBYTES, 1277 IPW_NDATA, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1278 if (error != 0) { 1279 errmsg = "could not create txbuf dma map"; 1280 goto fail; 1281 } 1282 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1283 } 1284 1285 return 0; 1286 1287fail: printf("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1288 ipw_tx_stop(sc); 1289 1290 return error; 1291} 1292 1293void 1294ipw_tx_stop(struct ipw_softc *sc) 1295{ 1296 struct ipw_soft_hdr *shdr; 1297 struct ipw_soft_buf *sbuf; 1298 int i; 1299 1300 if (sc->tbd_map != NULL) { 1301 if (sc->tbd_list != NULL) { 1302 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 1303 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 1304 IPW_TBD_SZ); 1305 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 1306 sc->tbd_list = NULL; 1307 } 1308 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 1309 sc->tbd_map = NULL; 1310 } 1311 1312 if (sc->stbd_list != NULL) { 1313 for (i = 0; i < IPW_NTBD; i++) 1314 ipw_release_sbd(sc, &sc->stbd_list[i]); 1315 free(sc->stbd_list, M_DEVBUF); 1316 sc->stbd_list = NULL; 1317 } 1318 1319 if (sc->cmd_map != NULL) { 1320 if (sc->cmd != NULL) { 1321 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->cmd, 1322 sizeof (struct ipw_cmd)); 1323 bus_dmamem_free(sc->sc_dmat, &sc->cmd_seg, 1); 1324 sc->cmd = NULL; 1325 } 1326 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 1327 sc->cmd_map = NULL; 1328 } 1329 1330 if (sc->shdr_list != NULL) { 1331 TAILQ_FOREACH(shdr, &sc->sc_free_shdr, next) 1332 bus_dmamap_destroy(sc->sc_dmat, shdr->map); 1333 free(sc->shdr_list, M_DEVBUF); 1334 sc->shdr_list = NULL; 1335 } 1336 1337 1338 if (sc->tx_sbuf_list != NULL) { 1339 TAILQ_FOREACH(sbuf, &sc->sc_free_sbuf, next) 1340 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1341 free(sc->tx_sbuf_list, M_DEVBUF); 1342 sc->tx_sbuf_list = NULL; 1343 } 1344} 1345 1346int 1347ipw_rx_init(struct ipw_softc *sc) 1348{ 1349 char *errmsg; 1350 struct ipw_bd *bd; 1351 struct ipw_soft_bd *sbd; 1352 struct ipw_soft_buf *sbuf; 1353 int error, i, nsegs; 1354 1355 /* Allocate reception buffer descriptors */ 1356 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 1357 BUS_DMA_NOWAIT, &sc->rbd_map); 1358 if (error != 0) { 1359 errmsg = "could not create rbd dma map"; 1360 goto fail; 1361 } 1362 1363 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 1364 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1365 if (error != 0) { 1366 errmsg = "could not allocate rbd dma memory"; 1367 goto fail; 1368 } 1369 1370 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 1371 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 1372 if (error != 0) { 1373 errmsg = "could not map rbd dma memory"; 1374 goto fail; 1375 } 1376 1377 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 1378 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 1379 if (error != 0) { 1380 errmsg = "could not load rbd dma memory"; 1381 goto fail; 1382 } 1383 1384 sc->srbd_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_bd), 1385 M_DEVBUF, M_NOWAIT); 1386 if (sc->srbd_list == NULL) { 1387 errmsg = "could not allocate soft rbd"; 1388 error = ENOMEM; 1389 goto fail; 1390 } 1391 sbd = sc->srbd_list; 1392 bd = sc->rbd_list; 1393 for (i = 0; i < IPW_NRBD; i++, sbd++, bd++) { 1394 sbd->type = IPW_SBD_TYPE_NOASSOC; 1395 sbd->bd = bd; 1396 } 1397 1398 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1399 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1400 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1401 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1402 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1403 1404 /* Allocate status descriptors */ 1405 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 1406 0, BUS_DMA_NOWAIT, &sc->status_map); 1407 if (error != 0) { 1408 errmsg = "could not create status dma map"; 1409 goto fail; 1410 } 1411 1412 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 1413 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1414 if (error != 0) { 1415 errmsg = "could not allocate status dma memory"; 1416 goto fail; 1417 } 1418 1419 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 1420 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 1421 if (error != 0) { 1422 errmsg = "could not map status dma memory"; 1423 goto fail; 1424 } 1425 1426 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 1427 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 1428 if (error != 0) { 1429 errmsg = "could not load status dma memory"; 1430 goto fail; 1431 } 1432 1433 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1434 sc->status_map->dm_segs[0].ds_addr); 1435 1436 sc->rx_sbuf_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_buf), 1437 M_DEVBUF, M_NOWAIT); 1438 if (sc->rx_sbuf_list == NULL) { 1439 errmsg = "could not allocate soft rxbuf"; 1440 error = ENOMEM; 1441 goto fail; 1442 } 1443 1444 sbuf = sc->rx_sbuf_list; 1445 sbd = sc->srbd_list; 1446 for (i = 0; i < IPW_NRBD; i++, sbuf++, sbd++) { 1447 1448 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 1449 if (sbuf->m == NULL) { 1450 errmsg = "could not allocate rx mbuf"; 1451 error = ENOMEM; 1452 goto fail; 1453 } 1454 MCLGET(sbuf->m, M_DONTWAIT); 1455 if (!(sbuf->m->m_flags & M_EXT)) { 1456 m_freem(sbuf->m); 1457 errmsg = "could not allocate rx mbuf cluster"; 1458 error = ENOMEM; 1459 goto fail; 1460 } 1461 1462 error = bus_dmamap_create(sc->sc_dmat, IPW_NRBD * MCLBYTES, 1463 IPW_NRBD, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1464 if (error != 0) { 1465 m_freem(sbuf->m); 1466 errmsg = "could not create rxbuf dma map"; 1467 goto fail; 1468 } 1469 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 1470 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1471 if (error != 0) { 1472 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1473 m_freem(sbuf->m); 1474 errmsg = "could not map rxbuf dma memory"; 1475 goto fail; 1476 } 1477 sbd->type = IPW_SBD_TYPE_DATA; 1478 sbd->priv = sbuf; 1479 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1480 sbd->bd->len = htole32(MCLBYTES); 1481 } 1482 1483 return 0; 1484 1485fail: printf("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1486 ipw_rx_stop(sc); 1487 1488 return error; 1489} 1490 1491void 1492ipw_rx_stop(struct ipw_softc *sc) 1493{ 1494 struct ipw_soft_bd *sbd; 1495 struct ipw_soft_buf *sbuf; 1496 int i; 1497 1498 if (sc->rbd_map != NULL) { 1499 if (sc->rbd_list != NULL) { 1500 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 1501 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 1502 IPW_RBD_SZ); 1503 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 1504 sc->rbd_list = NULL; 1505 } 1506 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 1507 sc->rbd_map = NULL; 1508 } 1509 1510 if (sc->status_map != NULL) { 1511 if (sc->status_list != NULL) { 1512 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 1513 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 1514 IPW_STATUS_SZ); 1515 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 1516 sc->status_list = NULL; 1517 } 1518 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 1519 sc->status_map = NULL; 1520 } 1521 1522 if (sc->srbd_list != NULL) { 1523 for (i = 0, sbd = sc->srbd_list; i < IPW_NRBD; i++, sbd++) { 1524 if (sbd->type == IPW_SBD_TYPE_NOASSOC) 1525 continue; 1526 1527 sbuf = sbd->priv; 1528 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1529 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1530 m_freem(sbuf->m); 1531 } 1532 free(sc->srbd_list, M_DEVBUF); 1533 sc->srbd_list = NULL; 1534 } 1535 1536 if (sc->rx_sbuf_list != NULL) { 1537 free(sc->rx_sbuf_list, M_DEVBUF); 1538 sc->rx_sbuf_list = NULL; 1539 } 1540} 1541 1542void 1543ipw_stop_master(struct ipw_softc *sc) 1544{ 1545 int ntries; 1546 1547 /* Disable interrupts */ 1548 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1549 1550 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1551 for (ntries = 0; ntries < 5; ntries++) { 1552 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1553 break; 1554 DELAY(10); 1555 } 1556 if (ntries == 5) 1557 printf("%s: timeout waiting for master\n", 1558 sc->sc_dev.dv_xname); 1559 1560 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1561 IPW_RST_PRINCETON_RESET); 1562 1563 sc->flags &= ~IPW_FLAG_FW_INITED; 1564} 1565 1566int 1567ipw_reset(struct ipw_softc *sc) 1568{ 1569 int ntries; 1570 1571 ipw_stop_master(sc); 1572 1573 /* Move adapter to D0 state */ 1574 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1575 IPW_CTL_INIT); 1576 1577 /* Wait for clock stabilization */ 1578 for (ntries = 0; ntries < 1000; ntries++) { 1579 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1580 break; 1581 DELAY(200); 1582 } 1583 if (ntries == 1000) 1584 return EIO; 1585 1586 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1587 IPW_RST_SW_RESET); 1588 1589 DELAY(10); 1590 1591 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1592 IPW_CTL_INIT); 1593 1594 return 0; 1595} 1596 1597int 1598ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1599{ 1600 int ntries; 1601 1602 MEM_WRITE_4(sc, 0x003000e0, 0x80000000); 1603 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1604 1605 MEM_WRITE_2(sc, 0x220000, 0x0703); 1606 MEM_WRITE_2(sc, 0x220000, 0x0707); 1607 1608 MEM_WRITE_1(sc, 0x210014, 0x72); 1609 MEM_WRITE_1(sc, 0x210014, 0x72); 1610 1611 MEM_WRITE_1(sc, 0x210000, 0x40); 1612 MEM_WRITE_1(sc, 0x210000, 0x00); 1613 MEM_WRITE_1(sc, 0x210000, 0x40); 1614 1615 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1616 1617 MEM_WRITE_1(sc, 0x210000, 0x00); 1618 MEM_WRITE_1(sc, 0x210000, 0x00); 1619 MEM_WRITE_1(sc, 0x210000, 0x80); 1620 1621 MEM_WRITE_2(sc, 0x220000, 0x0703); 1622 MEM_WRITE_2(sc, 0x220000, 0x0707); 1623 1624 MEM_WRITE_1(sc, 0x210014, 0x72); 1625 MEM_WRITE_1(sc, 0x210014, 0x72); 1626 1627 MEM_WRITE_1(sc, 0x210000, 0x00); 1628 MEM_WRITE_1(sc, 0x210000, 0x80); 1629 1630 for (ntries = 0; ntries < 10; ntries++) { 1631 if (MEM_READ_1(sc, 0x210000) & 1) 1632 break; 1633 DELAY(10); 1634 } 1635 if (ntries == 10) 1636 return EIO; 1637 1638 MEM_WRITE_4(sc, 0x003000e0, 0); 1639 1640 return 0; 1641} 1642 1643/* set of macros to handle unaligned little endian data in firmware image */ 1644#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1645#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1646int 1647ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1648{ 1649 u_char *p, *end; 1650 u_int32_t dst; 1651 u_int16_t len; 1652 int error; 1653 1654 p = fw; 1655 end = fw + size; 1656 while (p < end) { 1657 if (p + 6 > end) 1658 return EINVAL; 1659 1660 dst = GETLE32(p); p += 4; 1661 len = GETLE16(p); p += 2; 1662 1663 if (p + len > end) 1664 return EINVAL; 1665 1666 ipw_write_mem_1(sc, dst, p, len); 1667 p += len; 1668 } 1669 1670 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1671 IPW_IO_LED_OFF); 1672 1673 /* Allow interrupts so we know when the firmware is inited */ 1674 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1675 1676 /* Tell the adapter to initialize the firmware */ 1677 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1678 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1679 IPW_CTL_ALLOW_STANDBY); 1680 1681 /* Wait at most one second for firmware initialization to complete */ 1682 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1683 printf("%s: timeout waiting for firmware initialization to " 1684 "complete\n", sc->sc_dev.dv_xname); 1685 return error; 1686 } 1687 1688 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1689 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1690 1691 return 0; 1692} 1693 1694/* 1695 * Store firmware into kernel memory so we can download it when we need to, 1696 * e.g when the adapter wakes up from suspend mode. 1697 */ 1698int 1699ipw_cache_firmware(struct ipw_softc *sc, void *data) 1700{ 1701 struct ipw_firmware *fw = &sc->fw; 1702 struct ipw_firmware_hdr hdr; 1703 u_char *p = data; 1704 int error; 1705 1706 if (sc->flags & IPW_FLAG_FW_CACHED) 1707 ipw_free_firmware(sc); 1708 1709 if ((error = copyin(data, &hdr, sizeof hdr)) != 0) 1710 goto fail1; 1711 1712 fw->main_size = letoh32(hdr.main_size); 1713 fw->ucode_size = letoh32(hdr.ucode_size); 1714 p += sizeof hdr; 1715 1716 fw->main = malloc(fw->main_size, M_DEVBUF, M_NOWAIT); 1717 if (fw->main == NULL) { 1718 error = ENOMEM; 1719 goto fail1; 1720 } 1721 1722 fw->ucode = malloc(fw->ucode_size, M_DEVBUF, M_NOWAIT); 1723 if (fw->ucode == NULL) { 1724 error = ENOMEM; 1725 goto fail2; 1726 } 1727 1728 if ((error = copyin(p, fw->main, fw->main_size)) != 0) 1729 goto fail3; 1730 1731 p += fw->main_size; 1732 if ((error = copyin(p, fw->ucode, fw->ucode_size)) != 0) 1733 goto fail3; 1734 1735 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1736 fw->ucode_size)); 1737 1738 sc->flags |= IPW_FLAG_FW_CACHED; 1739 1740 return 0; 1741 1742fail3: free(fw->ucode, M_DEVBUF); 1743fail2: free(fw->main, M_DEVBUF); 1744fail1: return error; 1745} 1746 1747void 1748ipw_free_firmware(struct ipw_softc *sc) 1749{ 1750 free(sc->fw.main, M_DEVBUF); 1751 free(sc->fw.ucode, M_DEVBUF); 1752 1753 sc->flags &= ~IPW_FLAG_FW_CACHED; 1754} 1755 1756int 1757ipw_config(struct ipw_softc *sc) 1758{ 1759 struct ieee80211com *ic = &sc->sc_ic; 1760 struct ifnet *ifp = &ic->ic_if; 1761 struct ipw_security security; 1762 struct ieee80211_wepkey *k; 1763 struct ipw_wep_key wepkey; 1764 struct ipw_scan_options options; 1765 struct ipw_configuration config; 1766 u_int32_t data; 1767 int error, i; 1768 1769 switch (ic->ic_opmode) { 1770 case IEEE80211_M_STA: 1771 case IEEE80211_M_HOSTAP: 1772 data = htole32(IPW_MODE_BSS); 1773 break; 1774 1775 case IEEE80211_M_IBSS: 1776 case IEEE80211_M_AHDEMO: 1777 data = htole32(IPW_MODE_IBSS); 1778 break; 1779 1780 case IEEE80211_M_MONITOR: 1781 data = htole32(IPW_MODE_MONITOR); 1782 break; 1783 } 1784 DPRINTF(("Setting adapter mode to %u\n", data)); 1785 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1786 if (error != 0) 1787 return error; 1788 1789 if (ic->ic_opmode == IEEE80211_M_IBSS || 1790 ic->ic_opmode == IEEE80211_M_MONITOR) { 1791 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1792 DPRINTF(("Setting adapter channel to %u\n", data)); 1793 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1794 if (error != 0) 1795 return error; 1796 } 1797 1798 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1799 DPRINTF(("Enabling adapter\n")); 1800 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1801 } 1802 1803 DPRINTF(("Setting adapter MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1804 IEEE80211_ADDR_COPY(((struct arpcom *)ifp)->ac_enaddr, ic->ic_myaddr); 1805 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1806 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1807 IEEE80211_ADDR_LEN); 1808 if (error != 0) 1809 return error; 1810 1811 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1812 IPW_CFG_PREAMBLE_LEN | IPW_CFG_802_1x_ENABLE); 1813 if (ic->ic_opmode == IEEE80211_M_IBSS) 1814 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1815 if (ifp->if_flags & IFF_PROMISC) 1816 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1817 config.channels = htole32(0x3fff); /* channels 1-14 */ 1818 config.ibss_chan = htole32(0x7ff); 1819 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1820 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1821 if (error != 0) 1822 return error; 1823 1824 data = htole32(0x3); /* 1, 2 */ 1825 DPRINTF(("Setting adapter basic tx rates to 0x%x\n", data)); 1826 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1827 if (error != 0) 1828 return error; 1829 1830 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1831 DPRINTF(("Setting adapter tx rates to 0x%x\n", data)); 1832 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1833 if (error != 0) 1834 return error; 1835 1836 data = htole32(IPW_POWER_MODE_CAM); 1837 DPRINTF(("Setting adapter power mode to %u\n", data)); 1838 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1839 if (error != 0) 1840 return error; 1841 1842 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1843 data = htole32(ic->ic_txpower); 1844 DPRINTF(("Setting adapter tx power index to %u\n", data)); 1845 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1846 sizeof data); 1847 if (error != 0) 1848 return error; 1849 } 1850 1851 data = htole32(ic->ic_rtsthreshold); 1852 DPRINTF(("Setting adapter RTS threshold to %u\n", data)); 1853 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1854 if (error != 0) 1855 return error; 1856 1857 data = htole32(ic->ic_fragthreshold); 1858 DPRINTF(("Setting adapter frag threshold to %u\n", data)); 1859 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1860 if (error != 0) 1861 return error; 1862 1863#ifdef IPW_DEBUG 1864 if (ipw_debug > 0) { 1865 printf("Setting adapter ESSID to "); 1866 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1867 printf("\n"); 1868 } 1869#endif 1870 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1871 ic->ic_des_esslen); 1872 if (error != 0) 1873 return error; 1874 1875 /* no mandatory BSSID */ 1876 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1877 if (error != 0) 1878 return error; 1879 1880 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1881 DPRINTF(("Setting adapter desired BSSID to %s\n", 1882 ether_sprintf(ic->ic_des_bssid))); 1883 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1884 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1885 if (error != 0) 1886 return error; 1887 } 1888 1889 security.authmode = (sc->authmode == IEEE80211_AUTH_SHARED) ? 1890 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 1891 security.ciphers = htole32(IPW_CIPHER_NONE); 1892 security.version = htole16(0); 1893 security.replay_counters_number = 0; 1894 security.unicast_using_group = 0; 1895 DPRINTF(("Setting adapter authmode to %u\n", security.authmode)); 1896 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1897 sizeof security); 1898 if (error != 0) 1899 return error; 1900 1901 if (ic->ic_flags & IEEE80211_F_WEPON) { 1902 k = ic->ic_nw_keys; 1903 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1904 if (k->wk_len == 0) 1905 continue; 1906 1907 wepkey.idx = i; 1908 wepkey.len = k->wk_len; 1909 bzero(wepkey.key, sizeof wepkey.key); 1910 bcopy(k->wk_key, wepkey.key, k->wk_len); 1911 DPRINTF(("Setting wep key index %d len %d\n", 1912 wepkey.idx, wepkey.len)); 1913 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1914 sizeof wepkey); 1915 if (error != 0) 1916 return error; 1917 } 1918 1919 data = htole32(ic->ic_wep_txkey); 1920 DPRINTF(("Setting adapter tx key index to %u\n", data)); 1921 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1922 sizeof data); 1923 if (error != 0) 1924 return error; 1925 } 1926 1927 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_WEPON) ? 0x8 : 0); 1928 DPRINTF(("Setting adapter wep flags to 0x%x\n", data)); 1929 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1930 if (error != 0) 1931 return error; 1932 1933 if (ic->ic_opmode == IEEE80211_M_IBSS || 1934 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1935 data = htole32(ic->ic_lintval); 1936 DPRINTF(("Setting adapter beacon interval to %u\n", data)); 1937 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1938 sizeof data); 1939 if (error != 0) 1940 return error; 1941 } 1942 1943 options.flags = htole32(0); 1944 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1945 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1946 if (error != 0) 1947 return error; 1948 1949 /* finally, enable adapter (start scanning for an access point) */ 1950 DPRINTF(("Enabling adapter\n")); 1951 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1952} 1953 1954int 1955ipw_init(struct ifnet *ifp) 1956{ 1957 struct ipw_softc *sc = ifp->if_softc; 1958 struct ipw_firmware *fw = &sc->fw; 1959 int error; 1960 1961 /* exit immediately if firmware has not been ioctl'd */ 1962 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 1963 ifp->if_flags &= ~IFF_UP; 1964 return EIO; 1965 } 1966 1967 if ((error = ipw_reset(sc)) != 0) { 1968 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 1969 goto fail; 1970 } 1971 1972 if ((error = ipw_load_ucode(sc, fw->ucode, fw->ucode_size)) != 0) { 1973 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 1974 goto fail; 1975 } 1976 1977 ipw_stop_master(sc); 1978 1979 if ((error = ipw_rx_init(sc)) != 0) { 1980 printf("%s: could not initialize rx queue\n", 1981 sc->sc_dev.dv_xname); 1982 goto fail; 1983 } 1984 1985 if ((error = ipw_tx_init(sc)) != 0) { 1986 printf("%s: could not initialize tx queue\n", 1987 sc->sc_dev.dv_xname); 1988 goto fail; 1989 } 1990 1991 if ((error = ipw_load_firmware(sc, fw->main, fw->main_size)) != 0) { 1992 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 1993 goto fail; 1994 } 1995 1996 sc->flags |= IPW_FLAG_FW_INITED; 1997 1998 /* Retrieve information tables base addresses */ 1999 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2000 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2001 2002 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2003 2004 if ((error = ipw_config(sc)) != 0) { 2005 printf("%s: device configuration failed\n", 2006 sc->sc_dev.dv_xname); 2007 goto fail; 2008 } 2009 2010 ifp->if_flags &= ~IFF_OACTIVE; 2011 ifp->if_flags |= IFF_RUNNING; 2012 2013 return 0; 2014 2015fail: ipw_stop(ifp, 0); 2016 2017 return error; 2018} 2019 2020void 2021ipw_stop(struct ifnet *ifp, int disable) 2022{ 2023 struct ipw_softc *sc = ifp->if_softc; 2024 struct ieee80211com *ic = &sc->sc_ic; 2025 2026 ipw_stop_master(sc); 2027 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2028 2029 ipw_tx_stop(sc); 2030 ipw_rx_stop(sc); 2031 2032 ifp->if_timer = 0; 2033 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2034 2035 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2036} 2037 2038void 2039ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 2040 bus_size_t count) 2041{ 2042 for (; count > 0; offset++, datap++, count--) { 2043 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2044 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2045 } 2046} 2047 2048void 2049ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 2050 bus_size_t count) 2051{ 2052 for (; count > 0; offset++, datap++, count--) { 2053 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2054 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2055 } 2056} 2057 2058struct cfdriver ipw_cd = { 2059 0, "ipw", DV_IFNET 2060}; 2061