if_ipw.c revision 1.134
1/* $OpenBSD: if_ipw.c,v 1.134 2024/04/14 03:26:25 jsg Exp $ */ 2 3/*- 4 * Copyright (c) 2004-2008 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/* 21 * Driver for Intel PRO/Wireless 2100 802.11 network adapters. 22 */ 23 24#include "bpfilter.h" 25 26#include <sys/param.h> 27#include <sys/sockio.h> 28#include <sys/task.h> 29#include <sys/mbuf.h> 30#include <sys/kernel.h> 31#include <sys/rwlock.h> 32#include <sys/socket.h> 33#include <sys/systm.h> 34#include <sys/conf.h> 35#include <sys/device.h> 36#include <sys/endian.h> 37 38#include <machine/bus.h> 39#include <machine/intr.h> 40 41#include <dev/pci/pcireg.h> 42#include <dev/pci/pcivar.h> 43#include <dev/pci/pcidevs.h> 44 45#if NBPFILTER > 0 46#include <net/bpf.h> 47#endif 48#include <net/if.h> 49#include <net/if_dl.h> 50#include <net/if_media.h> 51 52#include <netinet/in.h> 53#include <netinet/if_ether.h> 54 55#include <net80211/ieee80211_var.h> 56#include <net80211/ieee80211_radiotap.h> 57 58#include <dev/pci/if_ipwreg.h> 59#include <dev/pci/if_ipwvar.h> 60 61int ipw_match(struct device *, void *, void *); 62void ipw_attach(struct device *, struct device *, void *); 63int ipw_activate(struct device *, int); 64void ipw_wakeup(struct ipw_softc *); 65int ipw_dma_alloc(struct ipw_softc *); 66void ipw_release(struct ipw_softc *); 67int ipw_media_change(struct ifnet *); 68void ipw_media_status(struct ifnet *, struct ifmediareq *); 69int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 70uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 71void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 72void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 73void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 74 struct ipw_soft_bd *, struct ipw_soft_buf *, 75 struct mbuf_list *); 76void ipw_notification_intr(struct ipw_softc *, 77 struct ipw_soft_buf *); 78void ipw_rx_intr(struct ipw_softc *); 79void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 80void ipw_tx_intr(struct ipw_softc *); 81int ipw_intr(void *); 82int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 83int ipw_send_mgmt(struct ieee80211com *, struct ieee80211_node *, 84 int, int, int); 85int ipw_tx_start(struct ifnet *, struct mbuf *, 86 struct ieee80211_node *); 87void ipw_start(struct ifnet *); 88void ipw_watchdog(struct ifnet *); 89int ipw_ioctl(struct ifnet *, u_long, caddr_t); 90uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 91void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 92int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 93 uint32_t *); 94void ipw_stop_master(struct ipw_softc *); 95int ipw_reset(struct ipw_softc *); 96int ipw_load_ucode(struct ipw_softc *, u_char *, int); 97int ipw_load_firmware(struct ipw_softc *, u_char *, int); 98int ipw_read_firmware(struct ipw_softc *, struct ipw_firmware *); 99void ipw_scan(void *); 100void ipw_auth_and_assoc(void *); 101int ipw_config(struct ipw_softc *); 102int ipw_init(struct ifnet *); 103void ipw_stop(struct ifnet *, int); 104void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 105 bus_size_t); 106void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 107 bus_size_t); 108 109static __inline uint8_t 110MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 111{ 112 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 113 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 114} 115 116static __inline uint32_t 117MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 118{ 119 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 120 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 121} 122 123#ifdef IPW_DEBUG 124#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 125#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 126int ipw_debug = 0; 127#else 128#define DPRINTF(x) 129#define DPRINTFN(n, x) 130#endif 131 132const struct cfattach ipw_ca = { 133 sizeof (struct ipw_softc), ipw_match, ipw_attach, NULL, 134 ipw_activate 135}; 136 137int 138ipw_match(struct device *parent, void *match, void *aux) 139{ 140 struct pci_attach_args *pa = aux; 141 142 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 143 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 144 return 1; 145 146 return 0; 147} 148 149/* Base Address Register */ 150#define IPW_PCI_BAR0 0x10 151 152void 153ipw_attach(struct device *parent, struct device *self, void *aux) 154{ 155 struct ipw_softc *sc = (struct ipw_softc *)self; 156 struct ieee80211com *ic = &sc->sc_ic; 157 struct ifnet *ifp = &ic->ic_if; 158 struct pci_attach_args *pa = aux; 159 const char *intrstr; 160 bus_space_tag_t memt; 161 bus_space_handle_t memh; 162 bus_addr_t base; 163 pci_intr_handle_t ih; 164 pcireg_t data; 165 uint16_t val; 166 int error, i; 167 168 sc->sc_pct = pa->pa_pc; 169 sc->sc_pcitag = pa->pa_tag, 170 171 /* clear device specific PCI configuration register 0x41 */ 172 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 173 data &= ~0x0000ff00; 174 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 175 176 /* map the register window */ 177 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 178 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 179 if (error != 0) { 180 printf(": can't map mem space\n"); 181 return; 182 } 183 184 sc->sc_st = memt; 185 sc->sc_sh = memh; 186 sc->sc_dmat = pa->pa_dmat; 187 188 /* disable interrupts */ 189 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 190 191 if (pci_intr_map(pa, &ih) != 0) { 192 printf(": can't map interrupt\n"); 193 return; 194 } 195 196 intrstr = pci_intr_string(sc->sc_pct, ih); 197 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 198 sc->sc_dev.dv_xname); 199 if (sc->sc_ih == NULL) { 200 printf(": can't establish interrupt"); 201 if (intrstr != NULL) 202 printf(" at %s", intrstr); 203 printf("\n"); 204 return; 205 } 206 printf(": %s", intrstr); 207 208 rw_init(&sc->sc_rwlock, "ipwlock"); 209 task_set(&sc->sc_scantask, ipw_scan, sc); 210 task_set(&sc->sc_authandassoctask, ipw_auth_and_assoc, sc); 211 212 if (ipw_reset(sc) != 0) { 213 printf(": could not reset adapter\n"); 214 return; 215 } 216 217 if (ipw_dma_alloc(sc) != 0) { 218 printf(": failed to allocate DMA resources\n"); 219 return; 220 } 221 222 ic->ic_phytype = IEEE80211_T_DS; 223 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 224 ic->ic_state = IEEE80211_S_INIT; 225 226 /* set device capabilities */ 227 ic->ic_caps = 228#ifndef IEEE80211_STA_ONLY 229 IEEE80211_C_IBSS | /* IBSS mode supported */ 230#endif 231 IEEE80211_C_MONITOR | /* monitor mode supported */ 232 IEEE80211_C_TXPMGT | /* tx power management */ 233 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 234 IEEE80211_C_WEP | /* s/w WEP */ 235 IEEE80211_C_RSN | /* WPA/RSN */ 236 IEEE80211_C_SCANALL; /* h/w scanning */ 237 238 /* read MAC address from EEPROM */ 239 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 240 ic->ic_myaddr[0] = val >> 8; 241 ic->ic_myaddr[1] = val & 0xff; 242 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 243 ic->ic_myaddr[2] = val >> 8; 244 ic->ic_myaddr[3] = val & 0xff; 245 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 246 ic->ic_myaddr[4] = val >> 8; 247 ic->ic_myaddr[5] = val & 0xff; 248 249 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 250 251 /* set supported .11b rates */ 252 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 253 254 /* set supported .11b channels (1 through 14) */ 255 for (i = 1; i <= 14; i++) { 256 ic->ic_channels[i].ic_freq = 257 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 258 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 259 } 260 261 /* IBSS channel undefined for now */ 262 ic->ic_ibss_chan = &ic->ic_channels[0]; 263 264 ifp->if_softc = sc; 265 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 266 ifp->if_ioctl = ipw_ioctl; 267 ifp->if_start = ipw_start; 268 ifp->if_watchdog = ipw_watchdog; 269 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 270 271 if_attach(ifp); 272 ieee80211_ifattach(ifp); 273 /* override state transition machine */ 274 sc->sc_newstate = ic->ic_newstate; 275 ic->ic_newstate = ipw_newstate; 276 ic->ic_send_mgmt = ipw_send_mgmt; 277 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 278 279#if NBPFILTER > 0 280 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 281 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 282 283 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 284 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 285 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 286 287 sc->sc_txtap_len = sizeof sc->sc_txtapu; 288 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 289 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 290#endif 291} 292 293int 294ipw_activate(struct device *self, int act) 295{ 296 struct ipw_softc *sc = (struct ipw_softc *)self; 297 struct ifnet *ifp = &sc->sc_ic.ic_if; 298 299 switch (act) { 300 case DVACT_SUSPEND: 301 if (ifp->if_flags & IFF_RUNNING) 302 ipw_stop(ifp, 0); 303 break; 304 case DVACT_WAKEUP: 305 ipw_wakeup(sc); 306 break; 307 } 308 309 return 0; 310} 311 312void 313ipw_wakeup(struct ipw_softc *sc) 314{ 315 struct ifnet *ifp = &sc->sc_ic.ic_if; 316 pcireg_t data; 317 int s; 318 319 /* clear device specific PCI configuration register 0x41 */ 320 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 321 data &= ~0x0000ff00; 322 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 323 324 rw_enter_write(&sc->sc_rwlock); 325 s = splnet(); 326 327 if (ifp->if_flags & IFF_UP) 328 ipw_init(ifp); 329 330 splx(s); 331 rw_exit_write(&sc->sc_rwlock); 332} 333 334int 335ipw_dma_alloc(struct ipw_softc *sc) 336{ 337 struct ipw_soft_bd *sbd; 338 struct ipw_soft_hdr *shdr; 339 struct ipw_soft_buf *sbuf; 340 int i, nsegs, error; 341 342 /* 343 * Allocate and map tx ring. 344 */ 345 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 346 BUS_DMA_NOWAIT, &sc->tbd_map); 347 if (error != 0) { 348 printf("%s: could not create tx ring DMA map\n", 349 sc->sc_dev.dv_xname); 350 goto fail; 351 } 352 353 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 354 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 355 if (error != 0) { 356 printf("%s: could not allocate tx ring DMA memory\n", 357 sc->sc_dev.dv_xname); 358 goto fail; 359 } 360 361 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 362 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 363 if (error != 0) { 364 printf("%s: can't map tx ring DMA memory\n", 365 sc->sc_dev.dv_xname); 366 goto fail; 367 } 368 369 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 370 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 371 if (error != 0) { 372 printf("%s: could not load tx ring DMA map\n", 373 sc->sc_dev.dv_xname); 374 goto fail; 375 } 376 377 /* 378 * Allocate and map rx ring. 379 */ 380 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 381 BUS_DMA_NOWAIT, &sc->rbd_map); 382 if (error != 0) { 383 printf("%s: could not create rx ring DMA map\n", 384 sc->sc_dev.dv_xname); 385 goto fail; 386 } 387 388 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 389 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 390 if (error != 0) { 391 printf("%s: could not allocate rx ring DMA memory\n", 392 sc->sc_dev.dv_xname); 393 goto fail; 394 } 395 396 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 397 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 398 if (error != 0) { 399 printf("%s: can't map rx ring DMA memory\n", 400 sc->sc_dev.dv_xname); 401 goto fail; 402 } 403 404 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 405 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 406 if (error != 0) { 407 printf("%s: could not load tx ring DMA map\n", 408 sc->sc_dev.dv_xname); 409 goto fail; 410 } 411 412 /* 413 * Allocate and map status ring. 414 */ 415 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 416 0, BUS_DMA_NOWAIT, &sc->status_map); 417 if (error != 0) { 418 printf("%s: could not create status ring DMA map\n", 419 sc->sc_dev.dv_xname); 420 goto fail; 421 } 422 423 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 424 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 425 if (error != 0) { 426 printf("%s: could not allocate status ring DMA memory\n", 427 sc->sc_dev.dv_xname); 428 goto fail; 429 } 430 431 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 432 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 433 if (error != 0) { 434 printf("%s: can't map status ring DMA memory\n", 435 sc->sc_dev.dv_xname); 436 goto fail; 437 } 438 439 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 440 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 441 if (error != 0) { 442 printf("%s: could not load status ring DMA map\n", 443 sc->sc_dev.dv_xname); 444 goto fail; 445 } 446 447 /* 448 * Allocate command DMA map. 449 */ 450 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 451 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 452 if (error != 0) { 453 printf("%s: could not create command DMA map\n", 454 sc->sc_dev.dv_xname); 455 goto fail; 456 } 457 458 /* 459 * Allocate headers DMA maps. 460 */ 461 SLIST_INIT(&sc->free_shdr); 462 for (i = 0; i < IPW_NDATA; i++) { 463 shdr = &sc->shdr_list[i]; 464 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_hdr), 465 1, sizeof (struct ipw_hdr), 0, BUS_DMA_NOWAIT, &shdr->map); 466 if (error != 0) { 467 printf("%s: could not create header DMA map\n", 468 sc->sc_dev.dv_xname); 469 goto fail; 470 } 471 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 472 } 473 474 /* 475 * Allocate tx buffers DMA maps. 476 */ 477 SLIST_INIT(&sc->free_sbuf); 478 for (i = 0; i < IPW_NDATA; i++) { 479 sbuf = &sc->tx_sbuf_list[i]; 480 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, IPW_MAX_NSEG, 481 MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 482 if (error != 0) { 483 printf("%s: could not create tx DMA map\n", 484 sc->sc_dev.dv_xname); 485 goto fail; 486 } 487 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 488 } 489 490 /* 491 * Initialize tx ring. 492 */ 493 for (i = 0; i < IPW_NTBD; i++) { 494 sbd = &sc->stbd_list[i]; 495 sbd->bd = &sc->tbd_list[i]; 496 sbd->type = IPW_SBD_TYPE_NOASSOC; 497 } 498 499 /* 500 * Pre-allocate rx buffers and DMA maps. 501 */ 502 for (i = 0; i < IPW_NRBD; i++) { 503 sbd = &sc->srbd_list[i]; 504 sbuf = &sc->rx_sbuf_list[i]; 505 sbd->bd = &sc->rbd_list[i]; 506 507 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 508 if (sbuf->m == NULL) { 509 printf("%s: could not allocate rx mbuf\n", 510 sc->sc_dev.dv_xname); 511 error = ENOMEM; 512 goto fail; 513 } 514 MCLGET(sbuf->m, M_DONTWAIT); 515 if (!(sbuf->m->m_flags & M_EXT)) { 516 m_freem(sbuf->m); 517 printf("%s: could not allocate rx mbuf cluster\n", 518 sc->sc_dev.dv_xname); 519 error = ENOMEM; 520 goto fail; 521 } 522 523 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 524 0, BUS_DMA_NOWAIT, &sbuf->map); 525 if (error != 0) { 526 printf("%s: could not create rx DMA map\n", 527 sc->sc_dev.dv_xname); 528 goto fail; 529 } 530 531 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 532 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 533 if (error != 0) { 534 printf("%s: can't map rx DMA memory\n", 535 sc->sc_dev.dv_xname); 536 goto fail; 537 } 538 539 sbd->type = IPW_SBD_TYPE_DATA; 540 sbd->priv = sbuf; 541 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 542 sbd->bd->len = htole32(MCLBYTES); 543 } 544 545 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 546 BUS_DMASYNC_PREWRITE); 547 548 return 0; 549 550fail: ipw_release(sc); 551 return error; 552} 553 554void 555ipw_release(struct ipw_softc *sc) 556{ 557 struct ipw_soft_buf *sbuf; 558 int i; 559 560 if (sc->tbd_map != NULL) { 561 if (sc->tbd_list != NULL) { 562 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 563 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 564 IPW_TBD_SZ); 565 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 566 } 567 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 568 } 569 570 if (sc->rbd_map != NULL) { 571 if (sc->rbd_list != NULL) { 572 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 573 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 574 IPW_RBD_SZ); 575 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 576 } 577 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 578 } 579 580 if (sc->status_map != NULL) { 581 if (sc->status_list != NULL) { 582 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 583 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 584 IPW_RBD_SZ); 585 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 586 } 587 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 588 } 589 590 if (sc->cmd_map != NULL) 591 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 592 593 for (i = 0; i < IPW_NDATA; i++) 594 bus_dmamap_destroy(sc->sc_dmat, sc->shdr_list[i].map); 595 596 for (i = 0; i < IPW_NDATA; i++) 597 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 598 599 for (i = 0; i < IPW_NRBD; i++) { 600 sbuf = &sc->rx_sbuf_list[i]; 601 if (sbuf->map != NULL) { 602 if (sbuf->m != NULL) { 603 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 604 m_freem(sbuf->m); 605 } 606 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 607 } 608 } 609 610 task_del(systq, &sc->sc_scantask); 611 task_del(systq, &sc->sc_authandassoctask); 612} 613 614int 615ipw_media_change(struct ifnet *ifp) 616{ 617 int error; 618 619 error = ieee80211_media_change(ifp); 620 if (error != ENETRESET) 621 return error; 622 623 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 624 ipw_init(ifp); 625 626 return 0; 627} 628 629void 630ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 631{ 632 struct ipw_softc *sc = ifp->if_softc; 633 struct ieee80211com *ic = &sc->sc_ic; 634 static const struct { 635 uint32_t val; 636 int rate; 637 } rates[] = { 638 { IPW_RATE_DS1, 2 }, 639 { IPW_RATE_DS2, 4 }, 640 { IPW_RATE_DS5, 11 }, 641 { IPW_RATE_DS11, 22 }, 642 }; 643 uint32_t val; 644 int rate, i; 645 646 imr->ifm_status = IFM_AVALID; 647 imr->ifm_active = IFM_IEEE80211; 648 if (ic->ic_state == IEEE80211_S_RUN) 649 imr->ifm_status |= IFM_ACTIVE; 650 651 /* read current transmission rate from adapter */ 652 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 653 val &= 0xf; 654 655 /* convert rate to 802.11 rate */ 656 for (i = 0; i < nitems(rates) && rates[i].val != val; i++) 657 ; 658 rate = (i < nitems(rates)) ? rates[i].rate : 0; 659 660 imr->ifm_active |= IFM_IEEE80211_11B; 661 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 662 switch (ic->ic_opmode) { 663 case IEEE80211_M_STA: 664 break; 665#ifndef IEEE80211_STA_ONLY 666 case IEEE80211_M_IBSS: 667 imr->ifm_active |= IFM_IEEE80211_IBSS; 668 break; 669#endif 670 case IEEE80211_M_MONITOR: 671 imr->ifm_active |= IFM_IEEE80211_MONITOR; 672 break; 673 default: 674 /* should not get there */ 675 break; 676 } 677} 678 679int 680ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 681{ 682 struct ipw_softc *sc = ic->ic_softc; 683 struct ifnet *ifp = &ic->ic_if; 684 685 if (LINK_STATE_IS_UP(ifp->if_link_state)) 686 ieee80211_set_link_state(ic, LINK_STATE_DOWN); 687 688 switch (nstate) { 689 case IEEE80211_S_SCAN: 690 task_add(systq, &sc->sc_scantask); 691 break; 692 693 case IEEE80211_S_AUTH: 694 task_add(systq, &sc->sc_authandassoctask); 695 break; 696 697 case IEEE80211_S_RUN: 698 if (!(ic->ic_flags & IEEE80211_F_RSNON)) { 699 /* 700 * NB: When RSN is enabled, we defer setting 701 * the link up until the port is valid. 702 */ 703 ieee80211_set_link_state(ic, LINK_STATE_UP); 704 } 705 break; 706 case IEEE80211_S_INIT: 707 case IEEE80211_S_ASSOC: 708 /* nothing to do */ 709 break; 710 } 711 712 ic->ic_state = nstate; 713 return 0; 714} 715 716/* 717 * Read 16 bits at address 'addr' from the Microwire EEPROM. 718 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 719 */ 720uint16_t 721ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 722{ 723 uint32_t tmp; 724 uint16_t val; 725 int n; 726 727 /* clock C once before the first command */ 728 IPW_EEPROM_CTL(sc, 0); 729 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 730 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 731 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 732 733 /* write start bit (1) */ 734 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 735 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 736 737 /* write READ opcode (10) */ 738 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 739 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 740 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 741 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 742 743 /* write address A7-A0 */ 744 for (n = 7; n >= 0; n--) { 745 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 746 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 747 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 748 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 749 } 750 751 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 752 753 /* read data Q15-Q0 */ 754 val = 0; 755 for (n = 15; n >= 0; n--) { 756 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 757 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 758 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 759 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 760 } 761 762 IPW_EEPROM_CTL(sc, 0); 763 764 /* clear Chip Select and clock C */ 765 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 766 IPW_EEPROM_CTL(sc, 0); 767 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 768 769 return val; 770} 771 772void 773ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 774{ 775 struct ipw_cmd *cmd; 776 777 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 778 BUS_DMASYNC_POSTREAD); 779 780 cmd = mtod(sbuf->m, struct ipw_cmd *); 781 782 DPRINTFN(2, ("received command ack type=%u,status=%u\n", 783 letoh32(cmd->type), letoh32(cmd->status))); 784 785 wakeup(&sc->cmd); 786} 787 788void 789ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 790{ 791 struct ieee80211com *ic = &sc->sc_ic; 792 struct ifnet *ifp = &ic->ic_if; 793 uint32_t state; 794 795 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 796 BUS_DMASYNC_POSTREAD); 797 798 state = letoh32(*mtod(sbuf->m, uint32_t *)); 799 800 DPRINTFN(2, ("firmware state changed to 0x%x\n", state)); 801 802 switch (state) { 803 case IPW_STATE_ASSOCIATED: 804 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 805 break; 806 807 case IPW_STATE_SCANNING: 808 if (ic->ic_state == IEEE80211_S_RUN) 809 ieee80211_begin_scan(ifp); 810 break; 811 812 case IPW_STATE_SCAN_COMPLETE: 813 if (ic->ic_state == IEEE80211_S_SCAN) 814 ieee80211_end_scan(ifp); 815 break; 816 817 case IPW_STATE_ASSOCIATION_LOST: 818 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 819 break; 820 821 case IPW_STATE_DISABLED: 822 wakeup(sc); 823 break; 824 825 case IPW_STATE_RADIO_DISABLED: 826 ipw_stop(&ic->ic_if, 1); 827 break; 828 } 829} 830 831void 832ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 833 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf, struct mbuf_list *ml) 834{ 835 struct ieee80211com *ic = &sc->sc_ic; 836 struct ifnet *ifp = &ic->ic_if; 837 struct mbuf *mnew, *m; 838 struct ieee80211_frame *wh; 839 struct ieee80211_rxinfo rxi; 840 struct ieee80211_node *ni; 841 int error; 842 843 DPRINTFN(5, ("received data frame len=%u,rssi=%u\n", 844 letoh32(status->len), status->rssi)); 845 846 /* 847 * Try to allocate a new mbuf for this ring element and load it before 848 * processing the current mbuf. If the ring element cannot be loaded, 849 * drop the received packet and reuse the old mbuf. In the unlikely 850 * case that the old mbuf can't be reloaded either, explicitly panic. 851 */ 852 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 853 if (mnew == NULL) { 854 ifp->if_ierrors++; 855 return; 856 } 857 MCLGET(mnew, M_DONTWAIT); 858 if (!(mnew->m_flags & M_EXT)) { 859 m_freem(mnew); 860 ifp->if_ierrors++; 861 return; 862 } 863 864 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 865 BUS_DMASYNC_POSTREAD); 866 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 867 868 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(mnew, void *), 869 MCLBYTES, NULL, BUS_DMA_NOWAIT); 870 if (error != 0) { 871 m_freem(mnew); 872 873 /* try to reload the old mbuf */ 874 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 875 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 876 if (error != 0) { 877 /* very unlikely that it will fail... */ 878 panic("%s: could not load old rx mbuf", 879 sc->sc_dev.dv_xname); 880 } 881 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 882 ifp->if_ierrors++; 883 return; 884 } 885 886 m = sbuf->m; 887 sbuf->m = mnew; 888 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 889 890 /* finalize mbuf */ 891 m->m_pkthdr.len = m->m_len = letoh32(status->len); 892 893#if NBPFILTER > 0 894 if (sc->sc_drvbpf != NULL) { 895 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 896 897 tap->wr_flags = 0; 898 tap->wr_antsignal = status->rssi; 899 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 900 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 901 902 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_rxtap_len, 903 m, BPF_DIRECTION_IN); 904 } 905#endif 906 907 wh = mtod(m, struct ieee80211_frame *); 908 ni = ieee80211_find_rxnode(ic, wh); 909 910 /* send the frame to the upper layer */ 911 memset(&rxi, 0, sizeof(rxi)); 912 rxi.rxi_rssi = status->rssi; 913 ieee80211_inputm(ifp, m, ni, &rxi, ml); 914 915 ieee80211_release_node(ic, ni); 916} 917 918void 919ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 920{ 921 DPRINTFN(2, ("received notification\n")); 922} 923 924void 925ipw_rx_intr(struct ipw_softc *sc) 926{ 927 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 928 struct ipw_status *status; 929 struct ipw_soft_bd *sbd; 930 struct ipw_soft_buf *sbuf; 931 uint32_t r, i; 932 933 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 934 935 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 936 937 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 938 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 939 BUS_DMASYNC_POSTREAD); 940 941 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 942 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 943 BUS_DMASYNC_POSTREAD); 944 945 status = &sc->status_list[i]; 946 sbd = &sc->srbd_list[i]; 947 sbuf = sbd->priv; 948 949 switch (letoh16(status->code) & 0xf) { 950 case IPW_STATUS_CODE_COMMAND: 951 ipw_command_intr(sc, sbuf); 952 break; 953 954 case IPW_STATUS_CODE_NEWSTATE: 955 ipw_newstate_intr(sc, sbuf); 956 break; 957 958 case IPW_STATUS_CODE_DATA_802_3: 959 case IPW_STATUS_CODE_DATA_802_11: 960 ipw_data_intr(sc, status, sbd, sbuf, &ml); 961 break; 962 963 case IPW_STATUS_CODE_NOTIFICATION: 964 ipw_notification_intr(sc, sbuf); 965 break; 966 967 default: 968 printf("%s: unknown status code %u\n", 969 sc->sc_dev.dv_xname, letoh16(status->code)); 970 } 971 sbd->bd->flags = 0; 972 973 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 974 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 975 BUS_DMASYNC_PREWRITE); 976 } 977 if_input(&sc->sc_ic.ic_if, &ml); 978 979 /* tell the firmware what we have processed */ 980 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 981 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 982} 983 984void 985ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 986{ 987 struct ieee80211com *ic = &sc->sc_ic; 988 struct ipw_soft_hdr *shdr; 989 struct ipw_soft_buf *sbuf; 990 991 switch (sbd->type) { 992 case IPW_SBD_TYPE_COMMAND: 993 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 994 break; 995 996 case IPW_SBD_TYPE_HEADER: 997 shdr = sbd->priv; 998 bus_dmamap_unload(sc->sc_dmat, shdr->map); 999 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 1000 break; 1001 1002 case IPW_SBD_TYPE_DATA: 1003 sbuf = sbd->priv; 1004 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1005 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1006 1007 m_freem(sbuf->m); 1008 1009 if (sbuf->ni != NULL) 1010 ieee80211_release_node(ic, sbuf->ni); 1011 1012 /* kill watchdog timer */ 1013 sc->sc_tx_timer = 0; 1014 break; 1015 } 1016 sbd->type = IPW_SBD_TYPE_NOASSOC; 1017} 1018 1019void 1020ipw_tx_intr(struct ipw_softc *sc) 1021{ 1022 struct ifnet *ifp = &sc->sc_ic.ic_if; 1023 struct ipw_soft_bd *sbd; 1024 uint32_t r, i; 1025 1026 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 1027 1028 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1029 sbd = &sc->stbd_list[i]; 1030 1031 ipw_release_sbd(sc, sbd); 1032 sc->txfree++; 1033 } 1034 1035 /* remember what the firmware has processed */ 1036 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1037 1038 /* call start() since some buffer descriptors have been released */ 1039 ifq_clr_oactive(&ifp->if_snd); 1040 (*ifp->if_start)(ifp); 1041} 1042 1043int 1044ipw_intr(void *arg) 1045{ 1046 struct ipw_softc *sc = arg; 1047 struct ifnet *ifp = &sc->sc_ic.ic_if; 1048 uint32_t r; 1049 1050 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) 1051 return 0; 1052 1053 /* disable interrupts */ 1054 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1055 1056 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1057 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 1058 ipw_stop(ifp, 1); 1059 return 1; 1060 } 1061 1062 if (r & IPW_INTR_FW_INIT_DONE) 1063 wakeup(sc); 1064 1065 if (r & IPW_INTR_RX_TRANSFER) 1066 ipw_rx_intr(sc); 1067 1068 if (r & IPW_INTR_TX_TRANSFER) 1069 ipw_tx_intr(sc); 1070 1071 /* acknowledge interrupts */ 1072 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1073 1074 /* re-enable interrupts */ 1075 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1076 1077 return 1; 1078} 1079 1080int 1081ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1082{ 1083 struct ipw_soft_bd *sbd; 1084 int s, error; 1085 1086 s = splnet(); 1087 1088 sc->cmd.type = htole32(type); 1089 sc->cmd.subtype = htole32(0); 1090 sc->cmd.len = htole32(len); 1091 sc->cmd.seq = htole32(0); 1092 if (data != NULL) 1093 bcopy(data, sc->cmd.data, len); 1094 1095 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 1096 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 1097 if (error != 0) { 1098 printf("%s: can't map command DMA memory\n", 1099 sc->sc_dev.dv_xname); 1100 splx(s); 1101 return error; 1102 } 1103 1104 sbd = &sc->stbd_list[sc->txcur]; 1105 sbd->type = IPW_SBD_TYPE_COMMAND; 1106 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1107 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1108 sbd->bd->nfrag = 1; 1109 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1110 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1111 1112 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1113 BUS_DMASYNC_PREWRITE); 1114 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1115 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1116 BUS_DMASYNC_PREWRITE); 1117 1118 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1119 sc->txfree--; 1120 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1121 1122 DPRINTFN(2, ("sending command type=%u,len=%u\n", type, len)); 1123 1124 /* wait at most one second for command to complete */ 1125 error = tsleep_nsec(&sc->cmd, 0, "ipwcmd", SEC_TO_NSEC(1)); 1126 splx(s); 1127 1128 return error; 1129} 1130 1131int 1132ipw_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type, 1133 int arg1, int arg2) 1134{ 1135 return EOPNOTSUPP; 1136} 1137 1138int 1139ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 1140{ 1141 struct ipw_softc *sc = ifp->if_softc; 1142 struct ieee80211com *ic = &sc->sc_ic; 1143 struct ieee80211_frame *wh; 1144 struct ieee80211_key *k; 1145 struct ipw_soft_bd *sbd; 1146 struct ipw_soft_hdr *shdr; 1147 struct ipw_soft_buf *sbuf; 1148 int error, i; 1149 1150 wh = mtod(m, struct ieee80211_frame *); 1151 1152 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1153 k = ieee80211_get_txkey(ic, wh, ni); 1154 1155 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1156 return ENOBUFS; 1157 1158 /* packet header may have moved, reset our local pointer */ 1159 wh = mtod(m, struct ieee80211_frame *); 1160 } 1161 1162#if NBPFILTER > 0 1163 if (sc->sc_drvbpf != NULL) { 1164 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1165 1166 tap->wt_flags = 0; 1167 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1168 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1169 1170 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_txtap_len, 1171 m, BPF_DIRECTION_OUT); 1172 } 1173#endif 1174 1175 shdr = SLIST_FIRST(&sc->free_shdr); 1176 sbuf = SLIST_FIRST(&sc->free_sbuf); 1177 1178 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1179 shdr->hdr.subtype = htole32(0); 1180 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) ? 1 : 0; 1181 shdr->hdr.encrypt = 0; 1182 shdr->hdr.keyidx = 0; 1183 shdr->hdr.keysz = 0; 1184 shdr->hdr.fragmentsz = htole16(0); 1185 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1186 if (ic->ic_opmode == IEEE80211_M_STA) 1187 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1188 else 1189 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1190 1191 /* trim IEEE802.11 header */ 1192 m_adj(m, sizeof (struct ieee80211_frame)); 1193 1194 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 1195 if (error != 0 && error != EFBIG) { 1196 printf("%s: can't map mbuf (error %d)\n", 1197 sc->sc_dev.dv_xname, error); 1198 m_freem(m); 1199 return error; 1200 } 1201 if (error != 0) { 1202 /* too many fragments, linearize */ 1203 if (m_defrag(m, M_DONTWAIT)) { 1204 m_freem(m); 1205 return ENOBUFS; 1206 } 1207 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, 1208 BUS_DMA_NOWAIT); 1209 if (error != 0) { 1210 printf("%s: can't map mbuf (error %d)\n", 1211 sc->sc_dev.dv_xname, error); 1212 m_freem(m); 1213 return error; 1214 } 1215 } 1216 1217 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 1218 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 1219 if (error != 0) { 1220 printf("%s: can't map header DMA memory (error %d)\n", 1221 sc->sc_dev.dv_xname, error); 1222 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1223 m_freem(m); 1224 return error; 1225 } 1226 1227 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1228 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1229 1230 sbd = &sc->stbd_list[sc->txcur]; 1231 sbd->type = IPW_SBD_TYPE_HEADER; 1232 sbd->priv = shdr; 1233 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 1234 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1235 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1236 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1237 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1238 1239 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1240 sc->txcur * sizeof (struct ipw_bd), 1241 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1242 1243 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1244 sc->txfree--; 1245 1246 sbuf->m = m; 1247 sbuf->ni = ni; 1248 1249 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1250 sbd = &sc->stbd_list[sc->txcur]; 1251 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1252 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1253 sbd->bd->nfrag = 0; /* used only in first bd */ 1254 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1255 if (i == sbuf->map->dm_nsegs - 1) { 1256 sbd->type = IPW_SBD_TYPE_DATA; 1257 sbd->priv = sbuf; 1258 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1259 } else { 1260 sbd->type = IPW_SBD_TYPE_NOASSOC; 1261 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1262 } 1263 1264 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1265 sc->txcur * sizeof (struct ipw_bd), 1266 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1267 1268 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1269 sc->txfree--; 1270 } 1271 1272 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1273 BUS_DMASYNC_PREWRITE); 1274 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 1275 BUS_DMASYNC_PREWRITE); 1276 1277 /* inform firmware about this new packet */ 1278 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1279 1280 return 0; 1281} 1282 1283void 1284ipw_start(struct ifnet *ifp) 1285{ 1286 struct ipw_softc *sc = ifp->if_softc; 1287 struct ieee80211com *ic = &sc->sc_ic; 1288 struct ieee80211_node *ni; 1289 struct mbuf *m; 1290 1291 if (ic->ic_state != IEEE80211_S_RUN) 1292 return; 1293 1294 for (;;) { 1295 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1296 ifq_set_oactive(&ifp->if_snd); 1297 break; 1298 } 1299 1300 m = ifq_dequeue(&ifp->if_snd); 1301 if (m == NULL) 1302 break; 1303 1304#if NBPFILTER > 0 1305 if (ifp->if_bpf != NULL) 1306 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1307#endif 1308 1309 m = ieee80211_encap(ifp, m, &ni); 1310 if (m == NULL) 1311 continue; 1312#if NBPFILTER > 0 1313 if (ic->ic_rawbpf != NULL) 1314 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1315#endif 1316 if (ipw_tx_start(ifp, m, ni) != 0) { 1317 if (ni != NULL) 1318 ieee80211_release_node(ic, ni); 1319 ifp->if_oerrors++; 1320 break; 1321 } 1322 1323 /* start watchdog timer */ 1324 sc->sc_tx_timer = 5; 1325 ifp->if_timer = 1; 1326 } 1327} 1328 1329void 1330ipw_watchdog(struct ifnet *ifp) 1331{ 1332 struct ipw_softc *sc = ifp->if_softc; 1333 1334 ifp->if_timer = 0; 1335 1336 if (sc->sc_tx_timer > 0) { 1337 if (--sc->sc_tx_timer == 0) { 1338 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1339 ipw_stop(ifp, 1); 1340 ifp->if_oerrors++; 1341 return; 1342 } 1343 ifp->if_timer = 1; 1344 } 1345 1346 ieee80211_watchdog(ifp); 1347} 1348 1349int 1350ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1351{ 1352 struct ipw_softc *sc = ifp->if_softc; 1353 int s, error = 0; 1354 1355 error = rw_enter(&sc->sc_rwlock, RW_WRITE | RW_INTR); 1356 if (error) 1357 return error; 1358 s = splnet(); 1359 1360 switch (cmd) { 1361 case SIOCSIFADDR: 1362 ifp->if_flags |= IFF_UP; 1363 /* FALLTHROUGH */ 1364 case SIOCSIFFLAGS: 1365 if (ifp->if_flags & IFF_UP) { 1366 if (!(ifp->if_flags & IFF_RUNNING)) 1367 ipw_init(ifp); 1368 } else { 1369 if (ifp->if_flags & IFF_RUNNING) 1370 ipw_stop(ifp, 1); 1371 } 1372 break; 1373 1374 case SIOCG80211TXPOWER: 1375 /* 1376 * If the hardware radio transmitter switch is off, report a 1377 * tx power of IEEE80211_TXPOWER_MIN to indicate that radio 1378 * transmitter is killed. 1379 */ 1380 ((struct ieee80211_txpower *)data)->i_val = 1381 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 1382 IEEE80211_TXPOWER_MIN : sc->sc_ic.ic_txpower; 1383 break; 1384 1385 default: 1386 error = ieee80211_ioctl(ifp, cmd, data); 1387 } 1388 1389 if (error == ENETRESET) { 1390 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1391 (IFF_UP | IFF_RUNNING)) 1392 ipw_init(ifp); 1393 error = 0; 1394 } 1395 1396 splx(s); 1397 rw_exit_write(&sc->sc_rwlock); 1398 return error; 1399} 1400 1401uint32_t 1402ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1403{ 1404 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1405} 1406 1407void 1408ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1409{ 1410 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1411} 1412 1413int 1414ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1415{ 1416 uint32_t addr, info; 1417 uint16_t count, size; 1418 uint32_t total; 1419 1420 /* addr[4] + count[2] + size[2] */ 1421 addr = MEM_READ_4(sc, sc->table2_base + off); 1422 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1423 1424 count = info >> 16; 1425 size = info & 0xffff; 1426 total = count * size; 1427 1428 if (total > *len) { 1429 *len = total; 1430 return EINVAL; 1431 } 1432 *len = total; 1433 ipw_read_mem_1(sc, addr, buf, total); 1434 1435 return 0; 1436} 1437 1438void 1439ipw_stop_master(struct ipw_softc *sc) 1440{ 1441 uint32_t tmp; 1442 int ntries; 1443 1444 /* disable interrupts */ 1445 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1446 1447 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1448 for (ntries = 0; ntries < 50; ntries++) { 1449 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1450 break; 1451 DELAY(10); 1452 } 1453 if (ntries == 50) 1454 printf("%s: timeout waiting for master\n", 1455 sc->sc_dev.dv_xname); 1456 1457 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1458 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1459} 1460 1461int 1462ipw_reset(struct ipw_softc *sc) 1463{ 1464 uint32_t tmp; 1465 int ntries; 1466 1467 ipw_stop_master(sc); 1468 1469 /* move adapter to D0 state */ 1470 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1471 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1472 1473 /* wait for clock stabilization */ 1474 for (ntries = 0; ntries < 1000; ntries++) { 1475 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1476 break; 1477 DELAY(200); 1478 } 1479 if (ntries == 1000) 1480 return EIO; 1481 1482 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1483 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1484 1485 DELAY(10); 1486 1487 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1488 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1489 1490 return 0; 1491} 1492 1493int 1494ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1495{ 1496 int ntries; 1497 1498 /* voodoo from the Intel Linux driver */ 1499 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1500 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1501 1502 MEM_WRITE_2(sc, 0x220000, 0x0703); 1503 MEM_WRITE_2(sc, 0x220000, 0x0707); 1504 1505 MEM_WRITE_1(sc, 0x210014, 0x72); 1506 MEM_WRITE_1(sc, 0x210014, 0x72); 1507 1508 MEM_WRITE_1(sc, 0x210000, 0x40); 1509 MEM_WRITE_1(sc, 0x210000, 0x00); 1510 MEM_WRITE_1(sc, 0x210000, 0x40); 1511 1512 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1513 1514 MEM_WRITE_1(sc, 0x210000, 0x00); 1515 MEM_WRITE_1(sc, 0x210000, 0x00); 1516 MEM_WRITE_1(sc, 0x210000, 0x80); 1517 1518 MEM_WRITE_2(sc, 0x220000, 0x0703); 1519 MEM_WRITE_2(sc, 0x220000, 0x0707); 1520 1521 MEM_WRITE_1(sc, 0x210014, 0x72); 1522 MEM_WRITE_1(sc, 0x210014, 0x72); 1523 1524 MEM_WRITE_1(sc, 0x210000, 0x00); 1525 MEM_WRITE_1(sc, 0x210000, 0x80); 1526 1527 for (ntries = 0; ntries < 100; ntries++) { 1528 if (MEM_READ_1(sc, 0x210000) & 1) 1529 break; 1530 DELAY(1000); 1531 } 1532 if (ntries == 100) { 1533 printf("%s: timeout waiting for ucode to initialize\n", 1534 sc->sc_dev.dv_xname); 1535 return EIO; 1536 } 1537 1538 MEM_WRITE_4(sc, 0x3000e0, 0); 1539 1540 return 0; 1541} 1542 1543/* set of macros to handle unaligned little endian data in firmware image */ 1544#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1545#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1546int 1547ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1548{ 1549 u_char *p, *end; 1550 uint32_t tmp, dst; 1551 uint16_t len; 1552 int error; 1553 1554 p = fw; 1555 end = fw + size; 1556 while (p < end) { 1557 if (p + 6 > end) 1558 return EINVAL; 1559 1560 dst = GETLE32(p); p += 4; 1561 len = GETLE16(p); p += 2; 1562 1563 if (p + len > end) 1564 return EINVAL; 1565 1566 ipw_write_mem_1(sc, dst, p, len); 1567 p += len; 1568 } 1569 1570 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1571 IPW_IO_LED_OFF); 1572 1573 /* allow interrupts so we know when the firmware is inited */ 1574 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1575 1576 /* tell the adapter to initialize the firmware */ 1577 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1578 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1579 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1580 1581 /* wait at most one second for firmware initialization to complete */ 1582 if ((error = tsleep_nsec(sc, 0, "ipwinit", SEC_TO_NSEC(1))) != 0) { 1583 printf("%s: timeout waiting for firmware initialization to " 1584 "complete\n", sc->sc_dev.dv_xname); 1585 return error; 1586 } 1587 1588 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1589 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1590 IPW_IO_GPIO3_MASK); 1591 1592 return 0; 1593} 1594 1595int 1596ipw_read_firmware(struct ipw_softc *sc, struct ipw_firmware *fw) 1597{ 1598 const struct ipw_firmware_hdr *hdr; 1599 const char *name; 1600 int error; 1601 1602 switch (sc->sc_ic.ic_opmode) { 1603 case IEEE80211_M_STA: 1604 name = "ipw-bss"; 1605 break; 1606#ifndef IEEE80211_STA_ONLY 1607 case IEEE80211_M_IBSS: 1608 name = "ipw-ibss"; 1609 break; 1610#endif 1611 case IEEE80211_M_MONITOR: 1612 name = "ipw-monitor"; 1613 break; 1614 default: 1615 /* should not get there */ 1616 return ENODEV; 1617 } 1618 if ((error = loadfirmware(name, &fw->data, &fw->size)) != 0) 1619 return error; 1620 1621 if (fw->size < sizeof (*hdr)) { 1622 error = EINVAL; 1623 goto fail; 1624 } 1625 hdr = (const struct ipw_firmware_hdr *)fw->data; 1626 fw->main_size = letoh32(hdr->main_size); 1627 fw->ucode_size = letoh32(hdr->ucode_size); 1628 1629 if (fw->size < sizeof (*hdr) + fw->main_size + fw->ucode_size) { 1630 error = EINVAL; 1631 goto fail; 1632 } 1633 fw->main = fw->data + sizeof (*hdr); 1634 fw->ucode = fw->main + fw->main_size; 1635 1636 return 0; 1637 1638fail: free(fw->data, M_DEVBUF, fw->size); 1639 return error; 1640} 1641 1642void 1643ipw_scan(void *arg1) 1644{ 1645 struct ipw_softc *sc = arg1; 1646 struct ifnet *ifp = &sc->sc_ic.ic_if; 1647 struct ipw_scan_options scan; 1648 uint8_t ssid[IEEE80211_NWID_LEN]; 1649 int error; 1650 1651 /* 1652 * Firmware has a bug and does not honour the ``do not associate 1653 * after scan'' bit in the scan command. To prevent the firmware 1654 * from associating after the scan, we set the ESSID to something 1655 * unlikely to be used by a real AP. 1656 * XXX would setting the desired BSSID to a multicast address work? 1657 */ 1658 memset(ssid, '\r', sizeof ssid); 1659 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ssid, sizeof ssid); 1660 if (error != 0) 1661 goto fail; 1662 1663 /* no mandatory BSSID */ 1664 DPRINTF(("Setting mandatory BSSID to null\n")); 1665 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1666 if (error != 0) 1667 goto fail; 1668 1669 scan.flags = htole32(IPW_SCAN_DO_NOT_ASSOCIATE | IPW_SCAN_MIXED_CELL); 1670 scan.channels = htole32(0x3fff); /* scan channels 1-14 */ 1671 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1672 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1673 if (error != 0) 1674 goto fail; 1675 1676 /* start scanning */ 1677 DPRINTF(("Enabling adapter\n")); 1678 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1679 if (error != 0) 1680 goto fail; 1681 1682 return; 1683fail: 1684 printf("%s: scan request failed (error=%d)\n", sc->sc_dev.dv_xname, 1685 error); 1686 ieee80211_end_scan(ifp); 1687} 1688 1689void 1690ipw_auth_and_assoc(void *arg1) 1691{ 1692 struct ipw_softc *sc = arg1; 1693 struct ieee80211com *ic = &sc->sc_ic; 1694 struct ieee80211_node *ni = ic->ic_bss; 1695 struct ipw_scan_options scan; 1696 struct ipw_security security; 1697 struct ipw_assoc_req assoc; 1698 uint32_t data; 1699 uint8_t chan; 1700 int s, error; 1701 1702 DPRINTF(("Disabling adapter\n")); 1703 error = ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1704 if (error != 0) 1705 goto fail; 1706#if 1 1707 /* wait at most one second for card to be disabled */ 1708 s = splnet(); 1709 error = tsleep_nsec(sc, 0, "ipwdis", SEC_TO_NSEC(1)); 1710 splx(s); 1711 if (error != 0) { 1712 printf("%s: timeout waiting for disabled state\n", 1713 sc->sc_dev.dv_xname); 1714 goto fail; 1715 } 1716#else 1717 /* Intel's Linux driver polls for the DISABLED state instead.. */ 1718 for (ntries = 0; ntries < 1000; ntries++) { 1719 if (ipw_read_table1(sc, IPW_INFO_CARD_DISABLED) == 1) 1720 break; 1721 DELAY(10); 1722 } 1723 if (ntries == 1000) { 1724 printf("%s: timeout waiting for disabled state\n", 1725 sc->sc_dev.dv_xname); 1726 goto fail; 1727 } 1728#endif 1729 1730 bzero(&security, sizeof security); 1731 security.authmode = IPW_AUTH_OPEN; 1732 security.ciphers = htole32(IPW_CIPHER_NONE); 1733 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1734 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1735 sizeof security); 1736 if (error != 0) 1737 goto fail; 1738 1739#ifdef IPW_DEBUG 1740 if (ipw_debug > 0) { 1741 printf("Setting ESSID to "); 1742 ieee80211_print_essid(ni->ni_essid, ni->ni_esslen); 1743 printf("\n"); 1744 } 1745#endif 1746 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ni->ni_essid, ni->ni_esslen); 1747 if (error != 0) 1748 goto fail; 1749 1750 DPRINTF(("Setting BSSID to %s\n", ether_sprintf(ni->ni_bssid))); 1751 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, ni->ni_bssid, 1752 IEEE80211_ADDR_LEN); 1753 if (error != 0) 1754 goto fail; 1755 1756 data = htole32((ic->ic_flags & (IEEE80211_F_WEPON | 1757 IEEE80211_F_RSNON)) ? IPW_PRIVACYON : 0); 1758 DPRINTF(("Setting privacy flags to 0x%x\n", letoh32(data))); 1759 error = ipw_cmd(sc, IPW_CMD_SET_PRIVACY_FLAGS, &data, sizeof data); 1760 if (error != 0) 1761 goto fail; 1762 1763 /* let firmware set the capinfo, lintval, and bssid fixed fields */ 1764 bzero(&assoc, sizeof assoc); 1765 if (ic->ic_flags & IEEE80211_F_RSNON) { 1766 uint8_t *frm = assoc.optie; 1767 1768 /* tell firmware to add a WPA or RSN IE in (Re)Assoc req */ 1769 if (ni->ni_rsnprotos & IEEE80211_PROTO_RSN) 1770 frm = ieee80211_add_rsn(frm, ic, ni); 1771 else if (ni->ni_rsnprotos & IEEE80211_PROTO_WPA) 1772 frm = ieee80211_add_wpa(frm, ic, ni); 1773 assoc.optie_len = htole32(frm - assoc.optie); 1774 } 1775 DPRINTF(("Preparing association request (optional IE length=%d)\n", 1776 letoh32(assoc.optie_len))); 1777 error = ipw_cmd(sc, IPW_CMD_SET_ASSOC_REQ, &assoc, sizeof assoc); 1778 if (error != 0) 1779 goto fail; 1780 1781 scan.flags = htole32(IPW_SCAN_MIXED_CELL); 1782 chan = ieee80211_chan2ieee(ic, ni->ni_chan); 1783 scan.channels = htole32(1 << (chan - 1)); 1784 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1785 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1786 if (error != 0) 1787 goto fail; 1788 1789 /* trigger scan+association */ 1790 DPRINTF(("Enabling adapter\n")); 1791 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1792 if (error != 0) 1793 goto fail; 1794 1795 /* 1796 * net80211 won't see the AP's auth response. Move to ASSOC state 1797 * in order to make net80211 accept the AP's assoc response. 1798 */ 1799 ic->ic_newstate(ic, IEEE80211_S_ASSOC, -1); 1800 1801 return; 1802fail: 1803 printf("%s: association failed (error=%d)\n", sc->sc_dev.dv_xname, 1804 error); 1805 ieee80211_begin_scan(&ic->ic_if); 1806} 1807 1808int 1809ipw_config(struct ipw_softc *sc) 1810{ 1811 struct ieee80211com *ic = &sc->sc_ic; 1812 struct ifnet *ifp = &ic->ic_if; 1813 struct ipw_configuration config; 1814 uint32_t data; 1815 int error; 1816 1817 switch (ic->ic_opmode) { 1818 case IEEE80211_M_STA: 1819 data = htole32(IPW_MODE_BSS); 1820 break; 1821#ifndef IEEE80211_STA_ONLY 1822 case IEEE80211_M_IBSS: 1823 data = htole32(IPW_MODE_IBSS); 1824 break; 1825#endif 1826 case IEEE80211_M_MONITOR: 1827 data = htole32(IPW_MODE_MONITOR); 1828 break; 1829 default: 1830 /* should not get there */ 1831 return ENODEV; 1832 } 1833 DPRINTF(("Setting mode to %u\n", letoh32(data))); 1834 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1835 if (error != 0) 1836 return error; 1837 1838 if ( 1839#ifndef IEEE80211_STA_ONLY 1840 ic->ic_opmode == IEEE80211_M_IBSS || 1841#endif 1842 ic->ic_opmode == IEEE80211_M_MONITOR) { 1843 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1844 DPRINTF(("Setting channel to %u\n", letoh32(data))); 1845 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1846 if (error != 0) 1847 return error; 1848 } 1849 1850 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1851 DPRINTF(("Enabling adapter\n")); 1852 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1853 } 1854 1855 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 1856 DPRINTF(("Setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 1857 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1858 IEEE80211_ADDR_LEN); 1859 if (error != 0) 1860 return error; 1861 1862 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1863 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1X_ENABLE); 1864#ifndef IEEE80211_STA_ONLY 1865 if (ic->ic_opmode == IEEE80211_M_IBSS) 1866 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1867#endif 1868 if (ifp->if_flags & IFF_PROMISC) 1869 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1870 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1871 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1872 DPRINTF(("Setting configuration 0x%x\n", config.flags)); 1873 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1874 if (error != 0) 1875 return error; 1876 1877 data = htole32(ic->ic_rtsthreshold); 1878 DPRINTF(("Setting RTS threshold to %u\n", letoh32(data))); 1879 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1880 if (error != 0) 1881 return error; 1882 1883 data = htole32(ic->ic_fragthreshold); 1884 DPRINTF(("Setting frag threshold to %u\n", letoh32(data))); 1885 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1886 if (error != 0) 1887 return error; 1888 1889 data = htole32(0x3); /* 1, 2 */ 1890 DPRINTF(("Setting basic tx rates to 0x%x\n", letoh32(data))); 1891 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1892 if (error != 0) 1893 return error; 1894 1895 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1896 DPRINTF(("Setting tx rates to 0x%x\n", letoh32(data))); 1897 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1898 if (error != 0) 1899 return error; 1900 1901 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1902 DPRINTF(("Setting MSDU tx rates to 0x%x\n", letoh32(data))); 1903 error = ipw_cmd(sc, IPW_CMD_SET_MSDU_TX_RATES, &data, sizeof data); 1904 if (error != 0) 1905 return error; 1906 1907 data = htole32(IPW_POWER_MODE_CAM); 1908 DPRINTF(("Setting power mode to %u\n", letoh32(data))); 1909 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1910 if (error != 0) 1911 return error; 1912 1913#ifndef IEEE80211_STA_ONLY 1914 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1915 data = htole32(32); /* default value */ 1916 DPRINTF(("Setting tx power index to %u\n", letoh32(data))); 1917 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1918 sizeof data); 1919 if (error != 0) 1920 return error; 1921 1922 data = htole32(ic->ic_lintval); 1923 DPRINTF(("Setting beacon interval to %u\n", letoh32(data))); 1924 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1925 sizeof data); 1926 if (error != 0) 1927 return error; 1928 } 1929#endif 1930 return 0; 1931} 1932 1933int 1934ipw_init(struct ifnet *ifp) 1935{ 1936 struct ipw_softc *sc = ifp->if_softc; 1937 struct ieee80211com *ic = &sc->sc_ic; 1938 struct ipw_firmware fw; 1939 int error; 1940 1941 ipw_stop(ifp, 0); 1942 1943 if ((error = ipw_reset(sc)) != 0) { 1944 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 1945 goto fail1; 1946 } 1947 1948 if ((error = ipw_read_firmware(sc, &fw)) != 0) { 1949 printf("%s: error %d, could not read firmware\n", 1950 sc->sc_dev.dv_xname, error); 1951 goto fail1; 1952 } 1953 if ((error = ipw_load_ucode(sc, fw.ucode, fw.ucode_size)) != 0) { 1954 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 1955 goto fail2; 1956 } 1957 1958 ipw_stop_master(sc); 1959 1960 /* 1961 * Setup tx, rx and status rings. 1962 */ 1963 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1964 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1965 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1966 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1967 sc->txold = IPW_NTBD - 1; /* latest bd index ack by firmware */ 1968 sc->txcur = 0; /* bd index to write to */ 1969 sc->txfree = IPW_NTBD - 2; 1970 1971 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1972 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1973 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1974 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1975 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1976 1977 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1978 sc->status_map->dm_segs[0].ds_addr); 1979 1980 if ((error = ipw_load_firmware(sc, fw.main, fw.main_size)) != 0) { 1981 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 1982 goto fail2; 1983 } 1984 free(fw.data, M_DEVBUF, fw.size); 1985 fw.data = NULL; 1986 1987 /* retrieve information tables base addresses */ 1988 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 1989 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 1990 1991 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 1992 1993 if ((error = ipw_config(sc)) != 0) { 1994 printf("%s: device configuration failed\n", 1995 sc->sc_dev.dv_xname); 1996 goto fail1; 1997 } 1998 1999 ifq_clr_oactive(&ifp->if_snd); 2000 ifp->if_flags |= IFF_RUNNING; 2001 2002 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2003 ieee80211_begin_scan(ifp); 2004 else 2005 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2006 2007 return 0; 2008 2009fail2: free(fw.data, M_DEVBUF, fw.size); 2010 fw.data = NULL; 2011fail1: ipw_stop(ifp, 0); 2012 return error; 2013} 2014 2015void 2016ipw_stop(struct ifnet *ifp, int disable) 2017{ 2018 struct ipw_softc *sc = ifp->if_softc; 2019 struct ieee80211com *ic = &sc->sc_ic; 2020 int i; 2021 2022 ipw_stop_master(sc); 2023 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2024 2025 ifp->if_timer = 0; 2026 ifp->if_flags &= ~IFF_RUNNING; 2027 ifq_clr_oactive(&ifp->if_snd); 2028 2029 /* 2030 * Release tx buffers. 2031 */ 2032 for (i = 0; i < IPW_NTBD; i++) 2033 ipw_release_sbd(sc, &sc->stbd_list[i]); 2034 2035 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2036} 2037 2038void 2039ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2040 bus_size_t count) 2041{ 2042 for (; count > 0; offset++, datap++, count--) { 2043 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2044 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2045 } 2046} 2047 2048void 2049ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2050 bus_size_t count) 2051{ 2052 for (; count > 0; offset++, datap++, count--) { 2053 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2054 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2055 } 2056} 2057 2058struct cfdriver ipw_cd = { 2059 NULL, "ipw", DV_IFNET 2060}; 2061