if_ipw.c revision 1.128
1/* $OpenBSD: if_ipw.c,v 1.128 2021/03/12 17:54:50 stsp Exp $ */ 2 3/*- 4 * Copyright (c) 2004-2008 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/* 21 * Driver for Intel PRO/Wireless 2100 802.11 network adapters. 22 */ 23 24#include "bpfilter.h" 25 26#include <sys/param.h> 27#include <sys/sockio.h> 28#include <sys/task.h> 29#include <sys/mbuf.h> 30#include <sys/kernel.h> 31#include <sys/rwlock.h> 32#include <sys/socket.h> 33#include <sys/systm.h> 34#include <sys/conf.h> 35#include <sys/device.h> 36#include <sys/endian.h> 37 38#include <machine/bus.h> 39#include <machine/intr.h> 40 41#include <dev/pci/pcireg.h> 42#include <dev/pci/pcivar.h> 43#include <dev/pci/pcidevs.h> 44 45#if NBPFILTER > 0 46#include <net/bpf.h> 47#endif 48#include <net/if.h> 49#include <net/if_dl.h> 50#include <net/if_media.h> 51 52#include <netinet/in.h> 53#include <netinet/if_ether.h> 54 55#include <net80211/ieee80211_var.h> 56#include <net80211/ieee80211_radiotap.h> 57 58#include <dev/pci/if_ipwreg.h> 59#include <dev/pci/if_ipwvar.h> 60 61int ipw_match(struct device *, void *, void *); 62void ipw_attach(struct device *, struct device *, void *); 63int ipw_activate(struct device *, int); 64void ipw_wakeup(struct ipw_softc *); 65int ipw_dma_alloc(struct ipw_softc *); 66void ipw_release(struct ipw_softc *); 67int ipw_media_change(struct ifnet *); 68void ipw_media_status(struct ifnet *, struct ifmediareq *); 69int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 70uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 71void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 72void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 73void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 74 struct ipw_soft_bd *, struct ipw_soft_buf *, 75 struct mbuf_list *); 76void ipw_notification_intr(struct ipw_softc *, 77 struct ipw_soft_buf *); 78void ipw_rx_intr(struct ipw_softc *); 79void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 80void ipw_tx_intr(struct ipw_softc *); 81int ipw_intr(void *); 82int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 83int ipw_send_mgmt(struct ieee80211com *, struct ieee80211_node *, 84 int, int, int); 85int ipw_tx_start(struct ifnet *, struct mbuf *, 86 struct ieee80211_node *); 87void ipw_start(struct ifnet *); 88void ipw_watchdog(struct ifnet *); 89int ipw_ioctl(struct ifnet *, u_long, caddr_t); 90uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 91void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 92int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 93 uint32_t *); 94void ipw_stop_master(struct ipw_softc *); 95int ipw_reset(struct ipw_softc *); 96int ipw_load_ucode(struct ipw_softc *, u_char *, int); 97int ipw_load_firmware(struct ipw_softc *, u_char *, int); 98int ipw_read_firmware(struct ipw_softc *, struct ipw_firmware *); 99void ipw_scan(void *); 100void ipw_auth_and_assoc(void *); 101int ipw_config(struct ipw_softc *); 102int ipw_init(struct ifnet *); 103void ipw_stop(struct ifnet *, int); 104void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 105 bus_size_t); 106void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 107 bus_size_t); 108 109static __inline uint8_t 110MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 111{ 112 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 113 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 114} 115 116static __inline uint32_t 117MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 118{ 119 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 120 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 121} 122 123#ifdef IPW_DEBUG 124#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 125#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 126int ipw_debug = 0; 127#else 128#define DPRINTF(x) 129#define DPRINTFN(n, x) 130#endif 131 132struct cfattach ipw_ca = { 133 sizeof (struct ipw_softc), ipw_match, ipw_attach, NULL, 134 ipw_activate 135}; 136 137int 138ipw_match(struct device *parent, void *match, void *aux) 139{ 140 struct pci_attach_args *pa = aux; 141 142 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 143 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 144 return 1; 145 146 return 0; 147} 148 149/* Base Address Register */ 150#define IPW_PCI_BAR0 0x10 151 152void 153ipw_attach(struct device *parent, struct device *self, void *aux) 154{ 155 struct ipw_softc *sc = (struct ipw_softc *)self; 156 struct ieee80211com *ic = &sc->sc_ic; 157 struct ifnet *ifp = &ic->ic_if; 158 struct pci_attach_args *pa = aux; 159 const char *intrstr; 160 bus_space_tag_t memt; 161 bus_space_handle_t memh; 162 bus_addr_t base; 163 pci_intr_handle_t ih; 164 pcireg_t data; 165 uint16_t val; 166 int error, i; 167 168 sc->sc_pct = pa->pa_pc; 169 sc->sc_pcitag = pa->pa_tag, 170 171 /* clear device specific PCI configuration register 0x41 */ 172 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 173 data &= ~0x0000ff00; 174 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 175 176 /* map the register window */ 177 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 178 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 179 if (error != 0) { 180 printf(": can't map mem space\n"); 181 return; 182 } 183 184 sc->sc_st = memt; 185 sc->sc_sh = memh; 186 sc->sc_dmat = pa->pa_dmat; 187 188 /* disable interrupts */ 189 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 190 191 if (pci_intr_map(pa, &ih) != 0) { 192 printf(": can't map interrupt\n"); 193 return; 194 } 195 196 intrstr = pci_intr_string(sc->sc_pct, ih); 197 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 198 sc->sc_dev.dv_xname); 199 if (sc->sc_ih == NULL) { 200 printf(": can't establish interrupt"); 201 if (intrstr != NULL) 202 printf(" at %s", intrstr); 203 printf("\n"); 204 return; 205 } 206 printf(": %s", intrstr); 207 208 rw_init(&sc->sc_rwlock, "ipwlock"); 209 task_set(&sc->sc_scantask, ipw_scan, sc); 210 task_set(&sc->sc_authandassoctask, ipw_auth_and_assoc, sc); 211 212 if (ipw_reset(sc) != 0) { 213 printf(": could not reset adapter\n"); 214 return; 215 } 216 217 if (ipw_dma_alloc(sc) != 0) { 218 printf(": failed to allocate DMA resources\n"); 219 return; 220 } 221 222 ic->ic_phytype = IEEE80211_T_DS; 223 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 224 ic->ic_state = IEEE80211_S_INIT; 225 226 /* set device capabilities */ 227 ic->ic_caps = 228#ifndef IEEE80211_STA_ONLY 229 IEEE80211_C_IBSS | /* IBSS mode supported */ 230#endif 231 IEEE80211_C_MONITOR | /* monitor mode supported */ 232 IEEE80211_C_TXPMGT | /* tx power management */ 233 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 234 IEEE80211_C_WEP | /* s/w WEP */ 235 IEEE80211_C_RSN | /* WPA/RSN */ 236 IEEE80211_C_SCANALL; /* h/w scanning */ 237 238 /* read MAC address from EEPROM */ 239 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 240 ic->ic_myaddr[0] = val >> 8; 241 ic->ic_myaddr[1] = val & 0xff; 242 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 243 ic->ic_myaddr[2] = val >> 8; 244 ic->ic_myaddr[3] = val & 0xff; 245 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 246 ic->ic_myaddr[4] = val >> 8; 247 ic->ic_myaddr[5] = val & 0xff; 248 249 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 250 251 /* set supported .11b rates */ 252 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 253 254 /* set supported .11b channels (1 through 14) */ 255 for (i = 1; i <= 14; i++) { 256 ic->ic_channels[i].ic_freq = 257 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 258 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 259 } 260 261 /* IBSS channel undefined for now */ 262 ic->ic_ibss_chan = &ic->ic_channels[0]; 263 264 ifp->if_softc = sc; 265 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 266 ifp->if_ioctl = ipw_ioctl; 267 ifp->if_start = ipw_start; 268 ifp->if_watchdog = ipw_watchdog; 269 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 270 271 if_attach(ifp); 272 ieee80211_ifattach(ifp); 273 /* override state transition machine */ 274 sc->sc_newstate = ic->ic_newstate; 275 ic->ic_newstate = ipw_newstate; 276 ic->ic_send_mgmt = ipw_send_mgmt; 277 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 278 279#if NBPFILTER > 0 280 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 281 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 282 283 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 284 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 285 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 286 287 sc->sc_txtap_len = sizeof sc->sc_txtapu; 288 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 289 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 290#endif 291} 292 293int 294ipw_activate(struct device *self, int act) 295{ 296 struct ipw_softc *sc = (struct ipw_softc *)self; 297 struct ifnet *ifp = &sc->sc_ic.ic_if; 298 299 switch (act) { 300 case DVACT_SUSPEND: 301 if (ifp->if_flags & IFF_RUNNING) 302 ipw_stop(ifp, 0); 303 break; 304 case DVACT_WAKEUP: 305 ipw_wakeup(sc); 306 break; 307 } 308 309 return 0; 310} 311 312void 313ipw_wakeup(struct ipw_softc *sc) 314{ 315 struct ifnet *ifp = &sc->sc_ic.ic_if; 316 pcireg_t data; 317 int s; 318 319 /* clear device specific PCI configuration register 0x41 */ 320 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 321 data &= ~0x0000ff00; 322 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 323 324 rw_enter_write(&sc->sc_rwlock); 325 s = splnet(); 326 327 if (ifp->if_flags & IFF_UP) 328 ipw_init(ifp); 329 330 splx(s); 331 rw_exit_write(&sc->sc_rwlock); 332} 333 334int 335ipw_dma_alloc(struct ipw_softc *sc) 336{ 337 struct ipw_soft_bd *sbd; 338 struct ipw_soft_hdr *shdr; 339 struct ipw_soft_buf *sbuf; 340 int i, nsegs, error; 341 342 /* 343 * Allocate and map tx ring. 344 */ 345 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 346 BUS_DMA_NOWAIT, &sc->tbd_map); 347 if (error != 0) { 348 printf("%s: could not create tx ring DMA map\n", 349 sc->sc_dev.dv_xname); 350 goto fail; 351 } 352 353 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 354 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 355 if (error != 0) { 356 printf("%s: could not allocate tx ring DMA memory\n", 357 sc->sc_dev.dv_xname); 358 goto fail; 359 } 360 361 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 362 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 363 if (error != 0) { 364 printf("%s: can't map tx ring DMA memory\n", 365 sc->sc_dev.dv_xname); 366 goto fail; 367 } 368 369 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 370 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 371 if (error != 0) { 372 printf("%s: could not load tx ring DMA map\n", 373 sc->sc_dev.dv_xname); 374 goto fail; 375 } 376 377 /* 378 * Allocate and map rx ring. 379 */ 380 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 381 BUS_DMA_NOWAIT, &sc->rbd_map); 382 if (error != 0) { 383 printf("%s: could not create rx ring DMA map\n", 384 sc->sc_dev.dv_xname); 385 goto fail; 386 } 387 388 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 389 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 390 if (error != 0) { 391 printf("%s: could not allocate rx ring DMA memory\n", 392 sc->sc_dev.dv_xname); 393 goto fail; 394 } 395 396 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 397 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 398 if (error != 0) { 399 printf("%s: can't map rx ring DMA memory\n", 400 sc->sc_dev.dv_xname); 401 goto fail; 402 } 403 404 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 405 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 406 if (error != 0) { 407 printf("%s: could not load tx ring DMA map\n", 408 sc->sc_dev.dv_xname); 409 goto fail; 410 } 411 412 /* 413 * Allocate and map status ring. 414 */ 415 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 416 0, BUS_DMA_NOWAIT, &sc->status_map); 417 if (error != 0) { 418 printf("%s: could not create status ring DMA map\n", 419 sc->sc_dev.dv_xname); 420 goto fail; 421 } 422 423 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 424 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 425 if (error != 0) { 426 printf("%s: could not allocate status ring DMA memory\n", 427 sc->sc_dev.dv_xname); 428 goto fail; 429 } 430 431 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 432 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 433 if (error != 0) { 434 printf("%s: can't map status ring DMA memory\n", 435 sc->sc_dev.dv_xname); 436 goto fail; 437 } 438 439 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 440 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 441 if (error != 0) { 442 printf("%s: could not load status ring DMA map\n", 443 sc->sc_dev.dv_xname); 444 goto fail; 445 } 446 447 /* 448 * Allocate command DMA map. 449 */ 450 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 451 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 452 if (error != 0) { 453 printf("%s: could not create command DMA map\n", 454 sc->sc_dev.dv_xname); 455 goto fail; 456 } 457 458 /* 459 * Allocate headers DMA maps. 460 */ 461 SLIST_INIT(&sc->free_shdr); 462 for (i = 0; i < IPW_NDATA; i++) { 463 shdr = &sc->shdr_list[i]; 464 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_hdr), 465 1, sizeof (struct ipw_hdr), 0, BUS_DMA_NOWAIT, &shdr->map); 466 if (error != 0) { 467 printf("%s: could not create header DMA map\n", 468 sc->sc_dev.dv_xname); 469 goto fail; 470 } 471 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 472 } 473 474 /* 475 * Allocate tx buffers DMA maps. 476 */ 477 SLIST_INIT(&sc->free_sbuf); 478 for (i = 0; i < IPW_NDATA; i++) { 479 sbuf = &sc->tx_sbuf_list[i]; 480 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, IPW_MAX_NSEG, 481 MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 482 if (error != 0) { 483 printf("%s: could not create tx DMA map\n", 484 sc->sc_dev.dv_xname); 485 goto fail; 486 } 487 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 488 } 489 490 /* 491 * Initialize tx ring. 492 */ 493 for (i = 0; i < IPW_NTBD; i++) { 494 sbd = &sc->stbd_list[i]; 495 sbd->bd = &sc->tbd_list[i]; 496 sbd->type = IPW_SBD_TYPE_NOASSOC; 497 } 498 499 /* 500 * Pre-allocate rx buffers and DMA maps. 501 */ 502 for (i = 0; i < IPW_NRBD; i++) { 503 sbd = &sc->srbd_list[i]; 504 sbuf = &sc->rx_sbuf_list[i]; 505 sbd->bd = &sc->rbd_list[i]; 506 507 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 508 if (sbuf->m == NULL) { 509 printf("%s: could not allocate rx mbuf\n", 510 sc->sc_dev.dv_xname); 511 error = ENOMEM; 512 goto fail; 513 } 514 MCLGET(sbuf->m, M_DONTWAIT); 515 if (!(sbuf->m->m_flags & M_EXT)) { 516 m_freem(sbuf->m); 517 printf("%s: could not allocate rx mbuf cluster\n", 518 sc->sc_dev.dv_xname); 519 error = ENOMEM; 520 goto fail; 521 } 522 523 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 524 0, BUS_DMA_NOWAIT, &sbuf->map); 525 if (error != 0) { 526 printf("%s: could not create rx DMA map\n", 527 sc->sc_dev.dv_xname); 528 goto fail; 529 } 530 531 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 532 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 533 if (error != 0) { 534 printf("%s: can't map rx DMA memory\n", 535 sc->sc_dev.dv_xname); 536 goto fail; 537 } 538 539 sbd->type = IPW_SBD_TYPE_DATA; 540 sbd->priv = sbuf; 541 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 542 sbd->bd->len = htole32(MCLBYTES); 543 } 544 545 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 546 BUS_DMASYNC_PREWRITE); 547 548 return 0; 549 550fail: ipw_release(sc); 551 return error; 552} 553 554void 555ipw_release(struct ipw_softc *sc) 556{ 557 struct ipw_soft_buf *sbuf; 558 int i; 559 560 if (sc->tbd_map != NULL) { 561 if (sc->tbd_list != NULL) { 562 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 563 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 564 IPW_TBD_SZ); 565 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 566 } 567 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 568 } 569 570 if (sc->rbd_map != NULL) { 571 if (sc->rbd_list != NULL) { 572 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 573 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 574 IPW_RBD_SZ); 575 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 576 } 577 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 578 } 579 580 if (sc->status_map != NULL) { 581 if (sc->status_list != NULL) { 582 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 583 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 584 IPW_RBD_SZ); 585 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 586 } 587 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 588 } 589 590 if (sc->cmd_map != NULL) 591 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 592 593 for (i = 0; i < IPW_NDATA; i++) 594 bus_dmamap_destroy(sc->sc_dmat, sc->shdr_list[i].map); 595 596 for (i = 0; i < IPW_NDATA; i++) 597 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 598 599 for (i = 0; i < IPW_NRBD; i++) { 600 sbuf = &sc->rx_sbuf_list[i]; 601 if (sbuf->map != NULL) { 602 if (sbuf->m != NULL) { 603 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 604 m_freem(sbuf->m); 605 } 606 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 607 } 608 } 609 610 task_del(systq, &sc->sc_scantask); 611 task_del(systq, &sc->sc_authandassoctask); 612} 613 614int 615ipw_media_change(struct ifnet *ifp) 616{ 617 int error; 618 619 error = ieee80211_media_change(ifp); 620 if (error != ENETRESET) 621 return error; 622 623 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 624 ipw_init(ifp); 625 626 return 0; 627} 628 629void 630ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 631{ 632 struct ipw_softc *sc = ifp->if_softc; 633 struct ieee80211com *ic = &sc->sc_ic; 634 static const struct { 635 uint32_t val; 636 int rate; 637 } rates[] = { 638 { IPW_RATE_DS1, 2 }, 639 { IPW_RATE_DS2, 4 }, 640 { IPW_RATE_DS5, 11 }, 641 { IPW_RATE_DS11, 22 }, 642 }; 643 uint32_t val; 644 int rate, i; 645 646 imr->ifm_status = IFM_AVALID; 647 imr->ifm_active = IFM_IEEE80211; 648 if (ic->ic_state == IEEE80211_S_RUN) 649 imr->ifm_status |= IFM_ACTIVE; 650 651 /* read current transmission rate from adapter */ 652 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 653 val &= 0xf; 654 655 /* convert rate to 802.11 rate */ 656 for (i = 0; i < nitems(rates) && rates[i].val != val; i++); 657 rate = (i < nitems(rates)) ? rates[i].rate : 0; 658 659 imr->ifm_active |= IFM_IEEE80211_11B; 660 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 661 switch (ic->ic_opmode) { 662 case IEEE80211_M_STA: 663 break; 664#ifndef IEEE80211_STA_ONLY 665 case IEEE80211_M_IBSS: 666 imr->ifm_active |= IFM_IEEE80211_IBSS; 667 break; 668#endif 669 case IEEE80211_M_MONITOR: 670 imr->ifm_active |= IFM_IEEE80211_MONITOR; 671 break; 672 default: 673 /* should not get there */ 674 break; 675 } 676} 677 678int 679ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 680{ 681 struct ipw_softc *sc = ic->ic_softc; 682 683 switch (nstate) { 684 case IEEE80211_S_SCAN: 685 task_add(systq, &sc->sc_scantask); 686 break; 687 688 case IEEE80211_S_AUTH: 689 task_add(systq, &sc->sc_authandassoctask); 690 break; 691 692 case IEEE80211_S_RUN: 693 case IEEE80211_S_INIT: 694 case IEEE80211_S_ASSOC: 695 /* nothing to do */ 696 break; 697 } 698 699 ic->ic_state = nstate; 700 return 0; 701} 702 703/* 704 * Read 16 bits at address 'addr' from the Microwire EEPROM. 705 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 706 */ 707uint16_t 708ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 709{ 710 uint32_t tmp; 711 uint16_t val; 712 int n; 713 714 /* clock C once before the first command */ 715 IPW_EEPROM_CTL(sc, 0); 716 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 717 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 718 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 719 720 /* write start bit (1) */ 721 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 722 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 723 724 /* write READ opcode (10) */ 725 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 726 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 727 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 728 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 729 730 /* write address A7-A0 */ 731 for (n = 7; n >= 0; n--) { 732 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 733 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 734 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 735 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 736 } 737 738 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 739 740 /* read data Q15-Q0 */ 741 val = 0; 742 for (n = 15; n >= 0; n--) { 743 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 744 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 745 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 746 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 747 } 748 749 IPW_EEPROM_CTL(sc, 0); 750 751 /* clear Chip Select and clock C */ 752 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 753 IPW_EEPROM_CTL(sc, 0); 754 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 755 756 return val; 757} 758 759void 760ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 761{ 762 struct ipw_cmd *cmd; 763 764 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 765 BUS_DMASYNC_POSTREAD); 766 767 cmd = mtod(sbuf->m, struct ipw_cmd *); 768 769 DPRINTFN(2, ("received command ack type=%u,status=%u\n", 770 letoh32(cmd->type), letoh32(cmd->status))); 771 772 wakeup(&sc->cmd); 773} 774 775void 776ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 777{ 778 struct ieee80211com *ic = &sc->sc_ic; 779 struct ifnet *ifp = &ic->ic_if; 780 uint32_t state; 781 782 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 783 BUS_DMASYNC_POSTREAD); 784 785 state = letoh32(*mtod(sbuf->m, uint32_t *)); 786 787 DPRINTFN(2, ("firmware state changed to 0x%x\n", state)); 788 789 switch (state) { 790 case IPW_STATE_ASSOCIATED: 791 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 792 break; 793 794 case IPW_STATE_SCANNING: 795 if (ic->ic_state == IEEE80211_S_RUN) 796 ieee80211_begin_scan(ifp); 797 break; 798 799 case IPW_STATE_SCAN_COMPLETE: 800 if (ic->ic_state == IEEE80211_S_SCAN) 801 ieee80211_end_scan(ifp); 802 break; 803 804 case IPW_STATE_ASSOCIATION_LOST: 805 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 806 break; 807 808 case IPW_STATE_DISABLED: 809 wakeup(sc); 810 break; 811 812 case IPW_STATE_RADIO_DISABLED: 813 ipw_stop(&ic->ic_if, 1); 814 break; 815 } 816} 817 818void 819ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 820 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf, struct mbuf_list *ml) 821{ 822 struct ieee80211com *ic = &sc->sc_ic; 823 struct ifnet *ifp = &ic->ic_if; 824 struct mbuf *mnew, *m; 825 struct ieee80211_frame *wh; 826 struct ieee80211_rxinfo rxi; 827 struct ieee80211_node *ni; 828 int error; 829 830 DPRINTFN(5, ("received data frame len=%u,rssi=%u\n", 831 letoh32(status->len), status->rssi)); 832 833 /* 834 * Try to allocate a new mbuf for this ring element and load it before 835 * processing the current mbuf. If the ring element cannot be loaded, 836 * drop the received packet and reuse the old mbuf. In the unlikely 837 * case that the old mbuf can't be reloaded either, explicitly panic. 838 */ 839 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 840 if (mnew == NULL) { 841 ifp->if_ierrors++; 842 return; 843 } 844 MCLGET(mnew, M_DONTWAIT); 845 if (!(mnew->m_flags & M_EXT)) { 846 m_freem(mnew); 847 ifp->if_ierrors++; 848 return; 849 } 850 851 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 852 BUS_DMASYNC_POSTREAD); 853 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 854 855 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(mnew, void *), 856 MCLBYTES, NULL, BUS_DMA_NOWAIT); 857 if (error != 0) { 858 m_freem(mnew); 859 860 /* try to reload the old mbuf */ 861 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 862 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 863 if (error != 0) { 864 /* very unlikely that it will fail... */ 865 panic("%s: could not load old rx mbuf", 866 sc->sc_dev.dv_xname); 867 } 868 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 869 ifp->if_ierrors++; 870 return; 871 } 872 873 m = sbuf->m; 874 sbuf->m = mnew; 875 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 876 877 /* finalize mbuf */ 878 m->m_pkthdr.len = m->m_len = letoh32(status->len); 879 880#if NBPFILTER > 0 881 if (sc->sc_drvbpf != NULL) { 882 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 883 884 tap->wr_flags = 0; 885 tap->wr_antsignal = status->rssi; 886 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 887 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 888 889 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_rxtap_len, 890 m, BPF_DIRECTION_IN); 891 } 892#endif 893 894 wh = mtod(m, struct ieee80211_frame *); 895 ni = ieee80211_find_rxnode(ic, wh); 896 897 /* send the frame to the upper layer */ 898 rxi.rxi_flags = 0; 899 rxi.rxi_rssi = status->rssi; 900 rxi.rxi_tstamp = 0; /* unused */ 901 ieee80211_inputm(ifp, m, ni, &rxi, ml); 902 903 ieee80211_release_node(ic, ni); 904} 905 906void 907ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 908{ 909 DPRINTFN(2, ("received notification\n")); 910} 911 912void 913ipw_rx_intr(struct ipw_softc *sc) 914{ 915 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 916 struct ipw_status *status; 917 struct ipw_soft_bd *sbd; 918 struct ipw_soft_buf *sbuf; 919 uint32_t r, i; 920 921 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 922 923 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 924 925 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 926 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 927 BUS_DMASYNC_POSTREAD); 928 929 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 930 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 931 BUS_DMASYNC_POSTREAD); 932 933 status = &sc->status_list[i]; 934 sbd = &sc->srbd_list[i]; 935 sbuf = sbd->priv; 936 937 switch (letoh16(status->code) & 0xf) { 938 case IPW_STATUS_CODE_COMMAND: 939 ipw_command_intr(sc, sbuf); 940 break; 941 942 case IPW_STATUS_CODE_NEWSTATE: 943 ipw_newstate_intr(sc, sbuf); 944 break; 945 946 case IPW_STATUS_CODE_DATA_802_3: 947 case IPW_STATUS_CODE_DATA_802_11: 948 ipw_data_intr(sc, status, sbd, sbuf, &ml); 949 break; 950 951 case IPW_STATUS_CODE_NOTIFICATION: 952 ipw_notification_intr(sc, sbuf); 953 break; 954 955 default: 956 printf("%s: unknown status code %u\n", 957 sc->sc_dev.dv_xname, letoh16(status->code)); 958 } 959 sbd->bd->flags = 0; 960 961 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 962 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 963 BUS_DMASYNC_PREWRITE); 964 } 965 if_input(&sc->sc_ic.ic_if, &ml); 966 967 /* tell the firmware what we have processed */ 968 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 969 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 970} 971 972void 973ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 974{ 975 struct ieee80211com *ic = &sc->sc_ic; 976 struct ipw_soft_hdr *shdr; 977 struct ipw_soft_buf *sbuf; 978 979 switch (sbd->type) { 980 case IPW_SBD_TYPE_COMMAND: 981 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 982 break; 983 984 case IPW_SBD_TYPE_HEADER: 985 shdr = sbd->priv; 986 bus_dmamap_unload(sc->sc_dmat, shdr->map); 987 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 988 break; 989 990 case IPW_SBD_TYPE_DATA: 991 sbuf = sbd->priv; 992 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 993 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 994 995 m_freem(sbuf->m); 996 997 if (sbuf->ni != NULL) 998 ieee80211_release_node(ic, sbuf->ni); 999 1000 /* kill watchdog timer */ 1001 sc->sc_tx_timer = 0; 1002 break; 1003 } 1004 sbd->type = IPW_SBD_TYPE_NOASSOC; 1005} 1006 1007void 1008ipw_tx_intr(struct ipw_softc *sc) 1009{ 1010 struct ifnet *ifp = &sc->sc_ic.ic_if; 1011 struct ipw_soft_bd *sbd; 1012 uint32_t r, i; 1013 1014 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 1015 1016 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1017 sbd = &sc->stbd_list[i]; 1018 1019 ipw_release_sbd(sc, sbd); 1020 sc->txfree++; 1021 } 1022 1023 /* remember what the firmware has processed */ 1024 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1025 1026 /* call start() since some buffer descriptors have been released */ 1027 ifq_clr_oactive(&ifp->if_snd); 1028 (*ifp->if_start)(ifp); 1029} 1030 1031int 1032ipw_intr(void *arg) 1033{ 1034 struct ipw_softc *sc = arg; 1035 struct ifnet *ifp = &sc->sc_ic.ic_if; 1036 uint32_t r; 1037 1038 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) 1039 return 0; 1040 1041 /* disable interrupts */ 1042 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1043 1044 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1045 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 1046 ipw_stop(ifp, 1); 1047 return 1; 1048 } 1049 1050 if (r & IPW_INTR_FW_INIT_DONE) 1051 wakeup(sc); 1052 1053 if (r & IPW_INTR_RX_TRANSFER) 1054 ipw_rx_intr(sc); 1055 1056 if (r & IPW_INTR_TX_TRANSFER) 1057 ipw_tx_intr(sc); 1058 1059 /* acknowledge interrupts */ 1060 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1061 1062 /* re-enable interrupts */ 1063 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1064 1065 return 1; 1066} 1067 1068int 1069ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1070{ 1071 struct ipw_soft_bd *sbd; 1072 int s, error; 1073 1074 s = splnet(); 1075 1076 sc->cmd.type = htole32(type); 1077 sc->cmd.subtype = htole32(0); 1078 sc->cmd.len = htole32(len); 1079 sc->cmd.seq = htole32(0); 1080 if (data != NULL) 1081 bcopy(data, sc->cmd.data, len); 1082 1083 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 1084 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 1085 if (error != 0) { 1086 printf("%s: can't map command DMA memory\n", 1087 sc->sc_dev.dv_xname); 1088 splx(s); 1089 return error; 1090 } 1091 1092 sbd = &sc->stbd_list[sc->txcur]; 1093 sbd->type = IPW_SBD_TYPE_COMMAND; 1094 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1095 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1096 sbd->bd->nfrag = 1; 1097 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1098 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1099 1100 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1101 BUS_DMASYNC_PREWRITE); 1102 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1103 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1104 BUS_DMASYNC_PREWRITE); 1105 1106 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1107 sc->txfree--; 1108 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1109 1110 DPRINTFN(2, ("sending command type=%u,len=%u\n", type, len)); 1111 1112 /* wait at most one second for command to complete */ 1113 error = tsleep_nsec(&sc->cmd, 0, "ipwcmd", SEC_TO_NSEC(1)); 1114 splx(s); 1115 1116 return error; 1117} 1118 1119/* ARGSUSED */ 1120int 1121ipw_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type, 1122 int arg1, int arg2) 1123{ 1124 return EOPNOTSUPP; 1125} 1126 1127int 1128ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 1129{ 1130 struct ipw_softc *sc = ifp->if_softc; 1131 struct ieee80211com *ic = &sc->sc_ic; 1132 struct ieee80211_frame *wh; 1133 struct ieee80211_key *k; 1134 struct ipw_soft_bd *sbd; 1135 struct ipw_soft_hdr *shdr; 1136 struct ipw_soft_buf *sbuf; 1137 int error, i; 1138 1139 wh = mtod(m, struct ieee80211_frame *); 1140 1141 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1142 k = ieee80211_get_txkey(ic, wh, ni); 1143 1144 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1145 return ENOBUFS; 1146 1147 /* packet header may have moved, reset our local pointer */ 1148 wh = mtod(m, struct ieee80211_frame *); 1149 } 1150 1151#if NBPFILTER > 0 1152 if (sc->sc_drvbpf != NULL) { 1153 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1154 1155 tap->wt_flags = 0; 1156 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1157 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1158 1159 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_txtap_len, 1160 m, BPF_DIRECTION_OUT); 1161 } 1162#endif 1163 1164 shdr = SLIST_FIRST(&sc->free_shdr); 1165 sbuf = SLIST_FIRST(&sc->free_sbuf); 1166 1167 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1168 shdr->hdr.subtype = htole32(0); 1169 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) ? 1 : 0; 1170 shdr->hdr.encrypt = 0; 1171 shdr->hdr.keyidx = 0; 1172 shdr->hdr.keysz = 0; 1173 shdr->hdr.fragmentsz = htole16(0); 1174 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1175 if (ic->ic_opmode == IEEE80211_M_STA) 1176 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1177 else 1178 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1179 1180 /* trim IEEE802.11 header */ 1181 m_adj(m, sizeof (struct ieee80211_frame)); 1182 1183 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 1184 if (error != 0 && error != EFBIG) { 1185 printf("%s: can't map mbuf (error %d)\n", 1186 sc->sc_dev.dv_xname, error); 1187 m_freem(m); 1188 return error; 1189 } 1190 if (error != 0) { 1191 /* too many fragments, linearize */ 1192 if (m_defrag(m, M_DONTWAIT)) { 1193 m_freem(m); 1194 return ENOBUFS; 1195 } 1196 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, 1197 BUS_DMA_NOWAIT); 1198 if (error != 0) { 1199 printf("%s: can't map mbuf (error %d)\n", 1200 sc->sc_dev.dv_xname, error); 1201 m_freem(m); 1202 return error; 1203 } 1204 } 1205 1206 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 1207 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 1208 if (error != 0) { 1209 printf("%s: can't map header DMA memory (error %d)\n", 1210 sc->sc_dev.dv_xname, error); 1211 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1212 m_freem(m); 1213 return error; 1214 } 1215 1216 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1217 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1218 1219 sbd = &sc->stbd_list[sc->txcur]; 1220 sbd->type = IPW_SBD_TYPE_HEADER; 1221 sbd->priv = shdr; 1222 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 1223 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1224 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1225 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1226 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1227 1228 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1229 sc->txcur * sizeof (struct ipw_bd), 1230 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1231 1232 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1233 sc->txfree--; 1234 1235 sbuf->m = m; 1236 sbuf->ni = ni; 1237 1238 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1239 sbd = &sc->stbd_list[sc->txcur]; 1240 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1241 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1242 sbd->bd->nfrag = 0; /* used only in first bd */ 1243 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1244 if (i == sbuf->map->dm_nsegs - 1) { 1245 sbd->type = IPW_SBD_TYPE_DATA; 1246 sbd->priv = sbuf; 1247 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1248 } else { 1249 sbd->type = IPW_SBD_TYPE_NOASSOC; 1250 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1251 } 1252 1253 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1254 sc->txcur * sizeof (struct ipw_bd), 1255 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1256 1257 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1258 sc->txfree--; 1259 } 1260 1261 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1262 BUS_DMASYNC_PREWRITE); 1263 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 1264 BUS_DMASYNC_PREWRITE); 1265 1266 /* inform firmware about this new packet */ 1267 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1268 1269 return 0; 1270} 1271 1272void 1273ipw_start(struct ifnet *ifp) 1274{ 1275 struct ipw_softc *sc = ifp->if_softc; 1276 struct ieee80211com *ic = &sc->sc_ic; 1277 struct ieee80211_node *ni; 1278 struct mbuf *m; 1279 1280 if (ic->ic_state != IEEE80211_S_RUN) 1281 return; 1282 1283 for (;;) { 1284 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1285 ifq_set_oactive(&ifp->if_snd); 1286 break; 1287 } 1288 1289 m = ifq_dequeue(&ifp->if_snd); 1290 if (m == NULL) 1291 break; 1292 1293#if NBPFILTER > 0 1294 if (ifp->if_bpf != NULL) 1295 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1296#endif 1297 1298 m = ieee80211_encap(ifp, m, &ni); 1299 if (m == NULL) 1300 continue; 1301#if NBPFILTER > 0 1302 if (ic->ic_rawbpf != NULL) 1303 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1304#endif 1305 if (ipw_tx_start(ifp, m, ni) != 0) { 1306 if (ni != NULL) 1307 ieee80211_release_node(ic, ni); 1308 ifp->if_oerrors++; 1309 break; 1310 } 1311 1312 /* start watchdog timer */ 1313 sc->sc_tx_timer = 5; 1314 ifp->if_timer = 1; 1315 } 1316} 1317 1318void 1319ipw_watchdog(struct ifnet *ifp) 1320{ 1321 struct ipw_softc *sc = ifp->if_softc; 1322 1323 ifp->if_timer = 0; 1324 1325 if (sc->sc_tx_timer > 0) { 1326 if (--sc->sc_tx_timer == 0) { 1327 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1328 ipw_stop(ifp, 1); 1329 ifp->if_oerrors++; 1330 return; 1331 } 1332 ifp->if_timer = 1; 1333 } 1334 1335 ieee80211_watchdog(ifp); 1336} 1337 1338int 1339ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1340{ 1341 struct ipw_softc *sc = ifp->if_softc; 1342 int s, error = 0; 1343 1344 error = rw_enter(&sc->sc_rwlock, RW_WRITE | RW_INTR); 1345 if (error) 1346 return error; 1347 s = splnet(); 1348 1349 switch (cmd) { 1350 case SIOCSIFADDR: 1351 ifp->if_flags |= IFF_UP; 1352 /* FALLTHROUGH */ 1353 case SIOCSIFFLAGS: 1354 if (ifp->if_flags & IFF_UP) { 1355 if (!(ifp->if_flags & IFF_RUNNING)) 1356 ipw_init(ifp); 1357 } else { 1358 if (ifp->if_flags & IFF_RUNNING) 1359 ipw_stop(ifp, 1); 1360 } 1361 break; 1362 1363 case SIOCG80211TXPOWER: 1364 /* 1365 * If the hardware radio transmitter switch is off, report a 1366 * tx power of IEEE80211_TXPOWER_MIN to indicate that radio 1367 * transmitter is killed. 1368 */ 1369 ((struct ieee80211_txpower *)data)->i_val = 1370 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 1371 IEEE80211_TXPOWER_MIN : sc->sc_ic.ic_txpower; 1372 break; 1373 1374 default: 1375 error = ieee80211_ioctl(ifp, cmd, data); 1376 } 1377 1378 if (error == ENETRESET) { 1379 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1380 (IFF_UP | IFF_RUNNING)) 1381 ipw_init(ifp); 1382 error = 0; 1383 } 1384 1385 splx(s); 1386 rw_exit_write(&sc->sc_rwlock); 1387 return error; 1388} 1389 1390uint32_t 1391ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1392{ 1393 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1394} 1395 1396void 1397ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1398{ 1399 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1400} 1401 1402int 1403ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1404{ 1405 uint32_t addr, info; 1406 uint16_t count, size; 1407 uint32_t total; 1408 1409 /* addr[4] + count[2] + size[2] */ 1410 addr = MEM_READ_4(sc, sc->table2_base + off); 1411 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1412 1413 count = info >> 16; 1414 size = info & 0xffff; 1415 total = count * size; 1416 1417 if (total > *len) { 1418 *len = total; 1419 return EINVAL; 1420 } 1421 *len = total; 1422 ipw_read_mem_1(sc, addr, buf, total); 1423 1424 return 0; 1425} 1426 1427void 1428ipw_stop_master(struct ipw_softc *sc) 1429{ 1430 uint32_t tmp; 1431 int ntries; 1432 1433 /* disable interrupts */ 1434 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1435 1436 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1437 for (ntries = 0; ntries < 50; ntries++) { 1438 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1439 break; 1440 DELAY(10); 1441 } 1442 if (ntries == 50) 1443 printf("%s: timeout waiting for master\n", 1444 sc->sc_dev.dv_xname); 1445 1446 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1447 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1448} 1449 1450int 1451ipw_reset(struct ipw_softc *sc) 1452{ 1453 uint32_t tmp; 1454 int ntries; 1455 1456 ipw_stop_master(sc); 1457 1458 /* move adapter to D0 state */ 1459 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1460 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1461 1462 /* wait for clock stabilization */ 1463 for (ntries = 0; ntries < 1000; ntries++) { 1464 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1465 break; 1466 DELAY(200); 1467 } 1468 if (ntries == 1000) 1469 return EIO; 1470 1471 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1472 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1473 1474 DELAY(10); 1475 1476 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1477 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1478 1479 return 0; 1480} 1481 1482int 1483ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1484{ 1485 int ntries; 1486 1487 /* voodoo from the Intel Linux driver */ 1488 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1489 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1490 1491 MEM_WRITE_2(sc, 0x220000, 0x0703); 1492 MEM_WRITE_2(sc, 0x220000, 0x0707); 1493 1494 MEM_WRITE_1(sc, 0x210014, 0x72); 1495 MEM_WRITE_1(sc, 0x210014, 0x72); 1496 1497 MEM_WRITE_1(sc, 0x210000, 0x40); 1498 MEM_WRITE_1(sc, 0x210000, 0x00); 1499 MEM_WRITE_1(sc, 0x210000, 0x40); 1500 1501 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1502 1503 MEM_WRITE_1(sc, 0x210000, 0x00); 1504 MEM_WRITE_1(sc, 0x210000, 0x00); 1505 MEM_WRITE_1(sc, 0x210000, 0x80); 1506 1507 MEM_WRITE_2(sc, 0x220000, 0x0703); 1508 MEM_WRITE_2(sc, 0x220000, 0x0707); 1509 1510 MEM_WRITE_1(sc, 0x210014, 0x72); 1511 MEM_WRITE_1(sc, 0x210014, 0x72); 1512 1513 MEM_WRITE_1(sc, 0x210000, 0x00); 1514 MEM_WRITE_1(sc, 0x210000, 0x80); 1515 1516 for (ntries = 0; ntries < 100; ntries++) { 1517 if (MEM_READ_1(sc, 0x210000) & 1) 1518 break; 1519 DELAY(1000); 1520 } 1521 if (ntries == 100) { 1522 printf("%s: timeout waiting for ucode to initialize\n", 1523 sc->sc_dev.dv_xname); 1524 return EIO; 1525 } 1526 1527 MEM_WRITE_4(sc, 0x3000e0, 0); 1528 1529 return 0; 1530} 1531 1532/* set of macros to handle unaligned little endian data in firmware image */ 1533#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1534#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1535int 1536ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1537{ 1538 u_char *p, *end; 1539 uint32_t tmp, dst; 1540 uint16_t len; 1541 int error; 1542 1543 p = fw; 1544 end = fw + size; 1545 while (p < end) { 1546 if (p + 6 > end) 1547 return EINVAL; 1548 1549 dst = GETLE32(p); p += 4; 1550 len = GETLE16(p); p += 2; 1551 1552 if (p + len > end) 1553 return EINVAL; 1554 1555 ipw_write_mem_1(sc, dst, p, len); 1556 p += len; 1557 } 1558 1559 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1560 IPW_IO_LED_OFF); 1561 1562 /* allow interrupts so we know when the firmware is inited */ 1563 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1564 1565 /* tell the adapter to initialize the firmware */ 1566 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1567 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1568 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1569 1570 /* wait at most one second for firmware initialization to complete */ 1571 if ((error = tsleep_nsec(sc, 0, "ipwinit", SEC_TO_NSEC(1))) != 0) { 1572 printf("%s: timeout waiting for firmware initialization to " 1573 "complete\n", sc->sc_dev.dv_xname); 1574 return error; 1575 } 1576 1577 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1578 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1579 IPW_IO_GPIO3_MASK); 1580 1581 return 0; 1582} 1583 1584int 1585ipw_read_firmware(struct ipw_softc *sc, struct ipw_firmware *fw) 1586{ 1587 const struct ipw_firmware_hdr *hdr; 1588 const char *name; 1589 int error; 1590 1591 switch (sc->sc_ic.ic_opmode) { 1592 case IEEE80211_M_STA: 1593 name = "ipw-bss"; 1594 break; 1595#ifndef IEEE80211_STA_ONLY 1596 case IEEE80211_M_IBSS: 1597 name = "ipw-ibss"; 1598 break; 1599#endif 1600 case IEEE80211_M_MONITOR: 1601 name = "ipw-monitor"; 1602 break; 1603 default: 1604 /* should not get there */ 1605 return ENODEV; 1606 } 1607 if ((error = loadfirmware(name, &fw->data, &fw->size)) != 0) 1608 return error; 1609 1610 if (fw->size < sizeof (*hdr)) { 1611 error = EINVAL; 1612 goto fail; 1613 } 1614 hdr = (const struct ipw_firmware_hdr *)fw->data; 1615 fw->main_size = letoh32(hdr->main_size); 1616 fw->ucode_size = letoh32(hdr->ucode_size); 1617 1618 if (fw->size < sizeof (*hdr) + fw->main_size + fw->ucode_size) { 1619 error = EINVAL; 1620 goto fail; 1621 } 1622 fw->main = fw->data + sizeof (*hdr); 1623 fw->ucode = fw->main + fw->main_size; 1624 1625 return 0; 1626 1627fail: free(fw->data, M_DEVBUF, fw->size); 1628 return error; 1629} 1630 1631void 1632ipw_scan(void *arg1) 1633{ 1634 struct ipw_softc *sc = arg1; 1635 struct ifnet *ifp = &sc->sc_ic.ic_if; 1636 struct ipw_scan_options scan; 1637 uint8_t ssid[IEEE80211_NWID_LEN]; 1638 int error; 1639 1640 /* 1641 * Firmware has a bug and does not honour the ``do not associate 1642 * after scan'' bit in the scan command. To prevent the firmware 1643 * from associating after the scan, we set the ESSID to something 1644 * unlikely to be used by a real AP. 1645 * XXX would setting the desired BSSID to a multicast address work? 1646 */ 1647 memset(ssid, '\r', sizeof ssid); 1648 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ssid, sizeof ssid); 1649 if (error != 0) 1650 goto fail; 1651 1652 /* no mandatory BSSID */ 1653 DPRINTF(("Setting mandatory BSSID to null\n")); 1654 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1655 if (error != 0) 1656 goto fail; 1657 1658 scan.flags = htole32(IPW_SCAN_DO_NOT_ASSOCIATE | IPW_SCAN_MIXED_CELL); 1659 scan.channels = htole32(0x3fff); /* scan channels 1-14 */ 1660 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1661 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1662 if (error != 0) 1663 goto fail; 1664 1665 /* start scanning */ 1666 DPRINTF(("Enabling adapter\n")); 1667 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1668 if (error != 0) 1669 goto fail; 1670 1671 return; 1672fail: 1673 printf("%s: scan request failed (error=%d)\n", sc->sc_dev.dv_xname, 1674 error); 1675 ieee80211_end_scan(ifp); 1676} 1677 1678void 1679ipw_auth_and_assoc(void *arg1) 1680{ 1681 struct ipw_softc *sc = arg1; 1682 struct ieee80211com *ic = &sc->sc_ic; 1683 struct ieee80211_node *ni = ic->ic_bss; 1684 struct ipw_scan_options scan; 1685 struct ipw_security security; 1686 struct ipw_assoc_req assoc; 1687 uint32_t data; 1688 uint8_t chan; 1689 int s, error; 1690 1691 DPRINTF(("Disabling adapter\n")); 1692 error = ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1693 if (error != 0) 1694 goto fail; 1695#if 1 1696 /* wait at most one second for card to be disabled */ 1697 s = splnet(); 1698 error = tsleep_nsec(sc, 0, "ipwdis", SEC_TO_NSEC(1)); 1699 splx(s); 1700 if (error != 0) { 1701 printf("%s: timeout waiting for disabled state\n", 1702 sc->sc_dev.dv_xname); 1703 goto fail; 1704 } 1705#else 1706 /* Intel's Linux driver polls for the DISABLED state instead.. */ 1707 for (ntries = 0; ntries < 1000; ntries++) { 1708 if (ipw_read_table1(sc, IPW_INFO_CARD_DISABLED) == 1) 1709 break; 1710 DELAY(10); 1711 } 1712 if (ntries == 1000) { 1713 printf("%s: timeout waiting for disabled state\n", 1714 sc->sc_dev.dv_xname); 1715 goto fail; 1716 } 1717#endif 1718 1719 bzero(&security, sizeof security); 1720 security.authmode = IPW_AUTH_OPEN; 1721 security.ciphers = htole32(IPW_CIPHER_NONE); 1722 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1723 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1724 sizeof security); 1725 if (error != 0) 1726 goto fail; 1727 1728#ifdef IPW_DEBUG 1729 if (ipw_debug > 0) { 1730 printf("Setting ESSID to "); 1731 ieee80211_print_essid(ni->ni_essid, ni->ni_esslen); 1732 printf("\n"); 1733 } 1734#endif 1735 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ni->ni_essid, ni->ni_esslen); 1736 if (error != 0) 1737 goto fail; 1738 1739 DPRINTF(("Setting BSSID to %s\n", ether_sprintf(ni->ni_bssid))); 1740 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, ni->ni_bssid, 1741 IEEE80211_ADDR_LEN); 1742 if (error != 0) 1743 goto fail; 1744 1745 data = htole32((ic->ic_flags & (IEEE80211_F_WEPON | 1746 IEEE80211_F_RSNON)) ? IPW_PRIVACYON : 0); 1747 DPRINTF(("Setting privacy flags to 0x%x\n", letoh32(data))); 1748 error = ipw_cmd(sc, IPW_CMD_SET_PRIVACY_FLAGS, &data, sizeof data); 1749 if (error != 0) 1750 goto fail; 1751 1752 /* let firmware set the capinfo, lintval, and bssid fixed fields */ 1753 bzero(&assoc, sizeof assoc); 1754 if (ic->ic_flags & IEEE80211_F_RSNON) { 1755 uint8_t *frm = assoc.optie; 1756 1757 /* tell firmware to add a WPA or RSN IE in (Re)Assoc req */ 1758 if (ni->ni_rsnprotos & IEEE80211_PROTO_RSN) 1759 frm = ieee80211_add_rsn(frm, ic, ni); 1760 else if (ni->ni_rsnprotos & IEEE80211_PROTO_WPA) 1761 frm = ieee80211_add_wpa(frm, ic, ni); 1762 assoc.optie_len = htole32(frm - assoc.optie); 1763 } 1764 DPRINTF(("Preparing assocation request (optional IE length=%d)\n", 1765 letoh32(assoc.optie_len))); 1766 error = ipw_cmd(sc, IPW_CMD_SET_ASSOC_REQ, &assoc, sizeof assoc); 1767 if (error != 0) 1768 goto fail; 1769 1770 scan.flags = htole32(IPW_SCAN_MIXED_CELL); 1771 chan = ieee80211_chan2ieee(ic, ni->ni_chan); 1772 scan.channels = htole32(1 << (chan - 1)); 1773 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1774 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1775 if (error != 0) 1776 goto fail; 1777 1778 /* trigger scan+association */ 1779 DPRINTF(("Enabling adapter\n")); 1780 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1781 if (error != 0) 1782 goto fail; 1783 1784 /* 1785 * net80211 won't see the AP's auth response. Move to ASSOC state 1786 * in order to make net80211 accept the AP's assoc response. 1787 */ 1788 ic->ic_newstate(ic, IEEE80211_S_ASSOC, -1); 1789 1790 return; 1791fail: 1792 printf("%s: association failed (error=%d)\n", sc->sc_dev.dv_xname, 1793 error); 1794 ieee80211_begin_scan(&ic->ic_if); 1795} 1796 1797int 1798ipw_config(struct ipw_softc *sc) 1799{ 1800 struct ieee80211com *ic = &sc->sc_ic; 1801 struct ifnet *ifp = &ic->ic_if; 1802 struct ipw_configuration config; 1803 uint32_t data; 1804 int error; 1805 1806 switch (ic->ic_opmode) { 1807 case IEEE80211_M_STA: 1808 data = htole32(IPW_MODE_BSS); 1809 break; 1810#ifndef IEEE80211_STA_ONLY 1811 case IEEE80211_M_IBSS: 1812 data = htole32(IPW_MODE_IBSS); 1813 break; 1814#endif 1815 case IEEE80211_M_MONITOR: 1816 data = htole32(IPW_MODE_MONITOR); 1817 break; 1818 default: 1819 /* should not get there */ 1820 return ENODEV; 1821 } 1822 DPRINTF(("Setting mode to %u\n", letoh32(data))); 1823 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1824 if (error != 0) 1825 return error; 1826 1827 if ( 1828#ifndef IEEE80211_STA_ONLY 1829 ic->ic_opmode == IEEE80211_M_IBSS || 1830#endif 1831 ic->ic_opmode == IEEE80211_M_MONITOR) { 1832 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1833 DPRINTF(("Setting channel to %u\n", letoh32(data))); 1834 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1835 if (error != 0) 1836 return error; 1837 } 1838 1839 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1840 DPRINTF(("Enabling adapter\n")); 1841 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1842 } 1843 1844 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 1845 DPRINTF(("Setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 1846 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1847 IEEE80211_ADDR_LEN); 1848 if (error != 0) 1849 return error; 1850 1851 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1852 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1X_ENABLE); 1853#ifndef IEEE80211_STA_ONLY 1854 if (ic->ic_opmode == IEEE80211_M_IBSS) 1855 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1856#endif 1857 if (ifp->if_flags & IFF_PROMISC) 1858 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1859 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1860 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1861 DPRINTF(("Setting configuration 0x%x\n", config.flags)); 1862 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1863 if (error != 0) 1864 return error; 1865 1866 data = htole32(ic->ic_rtsthreshold); 1867 DPRINTF(("Setting RTS threshold to %u\n", letoh32(data))); 1868 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1869 if (error != 0) 1870 return error; 1871 1872 data = htole32(ic->ic_fragthreshold); 1873 DPRINTF(("Setting frag threshold to %u\n", letoh32(data))); 1874 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1875 if (error != 0) 1876 return error; 1877 1878 data = htole32(0x3); /* 1, 2 */ 1879 DPRINTF(("Setting basic tx rates to 0x%x\n", letoh32(data))); 1880 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1881 if (error != 0) 1882 return error; 1883 1884 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1885 DPRINTF(("Setting tx rates to 0x%x\n", letoh32(data))); 1886 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1887 if (error != 0) 1888 return error; 1889 1890 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1891 DPRINTF(("Setting MSDU tx rates to 0x%x\n", letoh32(data))); 1892 error = ipw_cmd(sc, IPW_CMD_SET_MSDU_TX_RATES, &data, sizeof data); 1893 if (error != 0) 1894 return error; 1895 1896 data = htole32(IPW_POWER_MODE_CAM); 1897 DPRINTF(("Setting power mode to %u\n", letoh32(data))); 1898 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1899 if (error != 0) 1900 return error; 1901 1902#ifndef IEEE80211_STA_ONLY 1903 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1904 data = htole32(32); /* default value */ 1905 DPRINTF(("Setting tx power index to %u\n", letoh32(data))); 1906 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1907 sizeof data); 1908 if (error != 0) 1909 return error; 1910 1911 data = htole32(ic->ic_lintval); 1912 DPRINTF(("Setting beacon interval to %u\n", letoh32(data))); 1913 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1914 sizeof data); 1915 if (error != 0) 1916 return error; 1917 } 1918#endif 1919 return 0; 1920} 1921 1922int 1923ipw_init(struct ifnet *ifp) 1924{ 1925 struct ipw_softc *sc = ifp->if_softc; 1926 struct ieee80211com *ic = &sc->sc_ic; 1927 struct ipw_firmware fw; 1928 int error; 1929 1930 ipw_stop(ifp, 0); 1931 1932 if ((error = ipw_reset(sc)) != 0) { 1933 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 1934 goto fail1; 1935 } 1936 1937 if ((error = ipw_read_firmware(sc, &fw)) != 0) { 1938 printf("%s: error %d, could not read firmware\n", 1939 sc->sc_dev.dv_xname, error); 1940 goto fail1; 1941 } 1942 if ((error = ipw_load_ucode(sc, fw.ucode, fw.ucode_size)) != 0) { 1943 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 1944 goto fail2; 1945 } 1946 1947 ipw_stop_master(sc); 1948 1949 /* 1950 * Setup tx, rx and status rings. 1951 */ 1952 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1953 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1954 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1955 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1956 sc->txold = IPW_NTBD - 1; /* latest bd index ack by firmware */ 1957 sc->txcur = 0; /* bd index to write to */ 1958 sc->txfree = IPW_NTBD - 2; 1959 1960 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1961 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1962 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1963 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1964 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1965 1966 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1967 sc->status_map->dm_segs[0].ds_addr); 1968 1969 if ((error = ipw_load_firmware(sc, fw.main, fw.main_size)) != 0) { 1970 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 1971 goto fail2; 1972 } 1973 free(fw.data, M_DEVBUF, fw.size); 1974 fw.data = NULL; 1975 1976 /* retrieve information tables base addresses */ 1977 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 1978 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 1979 1980 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 1981 1982 if ((error = ipw_config(sc)) != 0) { 1983 printf("%s: device configuration failed\n", 1984 sc->sc_dev.dv_xname); 1985 goto fail1; 1986 } 1987 1988 ifq_clr_oactive(&ifp->if_snd); 1989 ifp->if_flags |= IFF_RUNNING; 1990 1991 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1992 ieee80211_begin_scan(ifp); 1993 else 1994 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1995 1996 return 0; 1997 1998fail2: free(fw.data, M_DEVBUF, fw.size); 1999 fw.data = NULL; 2000fail1: ipw_stop(ifp, 0); 2001 return error; 2002} 2003 2004void 2005ipw_stop(struct ifnet *ifp, int disable) 2006{ 2007 struct ipw_softc *sc = ifp->if_softc; 2008 struct ieee80211com *ic = &sc->sc_ic; 2009 int i; 2010 2011 ipw_stop_master(sc); 2012 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2013 2014 ifp->if_timer = 0; 2015 ifp->if_flags &= ~IFF_RUNNING; 2016 ifq_clr_oactive(&ifp->if_snd); 2017 2018 /* 2019 * Release tx buffers. 2020 */ 2021 for (i = 0; i < IPW_NTBD; i++) 2022 ipw_release_sbd(sc, &sc->stbd_list[i]); 2023 2024 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2025} 2026 2027void 2028ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2029 bus_size_t count) 2030{ 2031 for (; count > 0; offset++, datap++, count--) { 2032 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2033 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2034 } 2035} 2036 2037void 2038ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2039 bus_size_t count) 2040{ 2041 for (; count > 0; offset++, datap++, count--) { 2042 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2043 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2044 } 2045} 2046 2047struct cfdriver ipw_cd = { 2048 NULL, "ipw", DV_IFNET 2049}; 2050