if_ipw.c revision 1.111
1/* $OpenBSD: if_ipw.c,v 1.111 2015/11/20 03:35:23 dlg Exp $ */ 2 3/*- 4 * Copyright (c) 2004-2008 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/* 21 * Driver for Intel PRO/Wireless 2100 802.11 network adapters. 22 */ 23 24#include "bpfilter.h" 25 26#include <sys/param.h> 27#include <sys/sockio.h> 28#include <sys/task.h> 29#include <sys/mbuf.h> 30#include <sys/kernel.h> 31#include <sys/socket.h> 32#include <sys/systm.h> 33#include <sys/conf.h> 34#include <sys/device.h> 35#include <sys/endian.h> 36 37#include <machine/bus.h> 38#include <machine/intr.h> 39 40#include <dev/pci/pcireg.h> 41#include <dev/pci/pcivar.h> 42#include <dev/pci/pcidevs.h> 43 44#if NBPFILTER > 0 45#include <net/bpf.h> 46#endif 47#include <net/if.h> 48#include <net/if_arp.h> 49#include <net/if_dl.h> 50#include <net/if_media.h> 51#include <net/if_types.h> 52 53#include <netinet/in.h> 54#include <netinet/if_ether.h> 55 56#include <net80211/ieee80211_var.h> 57#include <net80211/ieee80211_radiotap.h> 58 59#include <dev/pci/if_ipwreg.h> 60#include <dev/pci/if_ipwvar.h> 61 62int ipw_match(struct device *, void *, void *); 63void ipw_attach(struct device *, struct device *, void *); 64int ipw_activate(struct device *, int); 65void ipw_wakeup(struct ipw_softc *); 66int ipw_dma_alloc(struct ipw_softc *); 67void ipw_release(struct ipw_softc *); 68int ipw_media_change(struct ifnet *); 69void ipw_media_status(struct ifnet *, struct ifmediareq *); 70int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 71uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 72void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 73void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 74void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 75 struct ipw_soft_bd *, struct ipw_soft_buf *); 76void ipw_notification_intr(struct ipw_softc *, 77 struct ipw_soft_buf *); 78void ipw_rx_intr(struct ipw_softc *); 79void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 80void ipw_tx_intr(struct ipw_softc *); 81int ipw_intr(void *); 82int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 83int ipw_send_mgmt(struct ieee80211com *, struct ieee80211_node *, 84 int, int, int); 85int ipw_tx_start(struct ifnet *, struct mbuf *, 86 struct ieee80211_node *); 87void ipw_start(struct ifnet *); 88void ipw_watchdog(struct ifnet *); 89int ipw_ioctl(struct ifnet *, u_long, caddr_t); 90uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 91void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 92int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 93 uint32_t *); 94void ipw_stop_master(struct ipw_softc *); 95int ipw_reset(struct ipw_softc *); 96int ipw_load_ucode(struct ipw_softc *, u_char *, int); 97int ipw_load_firmware(struct ipw_softc *, u_char *, int); 98int ipw_read_firmware(struct ipw_softc *, struct ipw_firmware *); 99void ipw_scan(void *); 100void ipw_auth_and_assoc(void *); 101int ipw_config(struct ipw_softc *); 102int ipw_init(struct ifnet *); 103void ipw_stop(struct ifnet *, int); 104void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 105 bus_size_t); 106void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 107 bus_size_t); 108 109static __inline uint8_t 110MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 111{ 112 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 113 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 114} 115 116static __inline uint32_t 117MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 118{ 119 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 120 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 121} 122 123#ifdef IPW_DEBUG 124#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 125#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 126int ipw_debug = 0; 127#else 128#define DPRINTF(x) 129#define DPRINTFN(n, x) 130#endif 131 132struct cfattach ipw_ca = { 133 sizeof (struct ipw_softc), ipw_match, ipw_attach, NULL, 134 ipw_activate 135}; 136 137int 138ipw_match(struct device *parent, void *match, void *aux) 139{ 140 struct pci_attach_args *pa = aux; 141 142 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 143 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 144 return 1; 145 146 return 0; 147} 148 149/* Base Address Register */ 150#define IPW_PCI_BAR0 0x10 151 152void 153ipw_attach(struct device *parent, struct device *self, void *aux) 154{ 155 struct ipw_softc *sc = (struct ipw_softc *)self; 156 struct ieee80211com *ic = &sc->sc_ic; 157 struct ifnet *ifp = &ic->ic_if; 158 struct pci_attach_args *pa = aux; 159 const char *intrstr; 160 bus_space_tag_t memt; 161 bus_space_handle_t memh; 162 bus_addr_t base; 163 pci_intr_handle_t ih; 164 pcireg_t data; 165 uint16_t val; 166 int error, i; 167 168 sc->sc_pct = pa->pa_pc; 169 sc->sc_pcitag = pa->pa_tag, 170 171 /* clear device specific PCI configuration register 0x41 */ 172 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 173 data &= ~0x0000ff00; 174 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 175 176 /* map the register window */ 177 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 178 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 179 if (error != 0) { 180 printf(": can't map mem space\n"); 181 return; 182 } 183 184 sc->sc_st = memt; 185 sc->sc_sh = memh; 186 sc->sc_dmat = pa->pa_dmat; 187 188 /* disable interrupts */ 189 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 190 191 if (pci_intr_map(pa, &ih) != 0) { 192 printf(": can't map interrupt\n"); 193 return; 194 } 195 196 intrstr = pci_intr_string(sc->sc_pct, ih); 197 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 198 sc->sc_dev.dv_xname); 199 if (sc->sc_ih == NULL) { 200 printf(": can't establish interrupt"); 201 if (intrstr != NULL) 202 printf(" at %s", intrstr); 203 printf("\n"); 204 return; 205 } 206 printf(": %s", intrstr); 207 208 task_set(&sc->sc_scantask, ipw_scan, sc); 209 task_set(&sc->sc_authandassoctask, ipw_auth_and_assoc, sc); 210 211 if (ipw_reset(sc) != 0) { 212 printf(": could not reset adapter\n"); 213 return; 214 } 215 216 if (ipw_dma_alloc(sc) != 0) { 217 printf(": failed to allocate DMA resources\n"); 218 return; 219 } 220 221 ic->ic_phytype = IEEE80211_T_DS; 222 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 223 ic->ic_state = IEEE80211_S_INIT; 224 225 /* set device capabilities */ 226 ic->ic_caps = 227#ifndef IEEE80211_STA_ONLY 228 IEEE80211_C_IBSS | /* IBSS mode supported */ 229#endif 230 IEEE80211_C_MONITOR | /* monitor mode supported */ 231 IEEE80211_C_TXPMGT | /* tx power management */ 232 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 233 IEEE80211_C_WEP | /* s/w WEP */ 234 IEEE80211_C_RSN | /* WPA/RSN */ 235 IEEE80211_C_SCANALL; /* h/w scanning */ 236 237 /* read MAC address from EEPROM */ 238 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 239 ic->ic_myaddr[0] = val >> 8; 240 ic->ic_myaddr[1] = val & 0xff; 241 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 242 ic->ic_myaddr[2] = val >> 8; 243 ic->ic_myaddr[3] = val & 0xff; 244 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 245 ic->ic_myaddr[4] = val >> 8; 246 ic->ic_myaddr[5] = val & 0xff; 247 248 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 249 250 /* set supported .11b rates */ 251 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 252 253 /* set supported .11b channels (1 through 14) */ 254 for (i = 1; i <= 14; i++) { 255 ic->ic_channels[i].ic_freq = 256 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 257 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 258 } 259 260 /* IBSS channel undefined for now */ 261 ic->ic_ibss_chan = &ic->ic_channels[0]; 262 263 ifp->if_softc = sc; 264 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 265 ifp->if_ioctl = ipw_ioctl; 266 ifp->if_start = ipw_start; 267 ifp->if_watchdog = ipw_watchdog; 268 IFQ_SET_READY(&ifp->if_snd); 269 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 270 271 if_attach(ifp); 272 ieee80211_ifattach(ifp); 273 /* override state transition machine */ 274 sc->sc_newstate = ic->ic_newstate; 275 ic->ic_newstate = ipw_newstate; 276 ic->ic_send_mgmt = ipw_send_mgmt; 277 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 278 279#if NBPFILTER > 0 280 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 281 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 282 283 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 284 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 285 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 286 287 sc->sc_txtap_len = sizeof sc->sc_txtapu; 288 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 289 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 290#endif 291} 292 293int 294ipw_activate(struct device *self, int act) 295{ 296 struct ipw_softc *sc = (struct ipw_softc *)self; 297 struct ifnet *ifp = &sc->sc_ic.ic_if; 298 299 switch (act) { 300 case DVACT_SUSPEND: 301 if (ifp->if_flags & IFF_RUNNING) 302 ipw_stop(ifp, 0); 303 break; 304 case DVACT_WAKEUP: 305 ipw_wakeup(sc); 306 break; 307 } 308 309 return 0; 310} 311 312void 313ipw_wakeup(struct ipw_softc *sc) 314{ 315 struct ifnet *ifp = &sc->sc_ic.ic_if; 316 pcireg_t data; 317 int s; 318 319 /* clear device specific PCI configuration register 0x41 */ 320 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 321 data &= ~0x0000ff00; 322 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 323 324 s = splnet(); 325 while (sc->sc_flags & IPW_FLAG_BUSY) 326 tsleep(&sc->sc_flags, PZERO, "ipwpwr", 0); 327 sc->sc_flags |= IPW_FLAG_BUSY; 328 329 if (ifp->if_flags & IFF_UP) 330 ipw_init(ifp); 331 332 sc->sc_flags &= ~IPW_FLAG_BUSY; 333 wakeup(&sc->sc_flags); 334 splx(s); 335} 336 337int 338ipw_dma_alloc(struct ipw_softc *sc) 339{ 340 struct ipw_soft_bd *sbd; 341 struct ipw_soft_hdr *shdr; 342 struct ipw_soft_buf *sbuf; 343 int i, nsegs, error; 344 345 /* 346 * Allocate and map tx ring. 347 */ 348 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 349 BUS_DMA_NOWAIT, &sc->tbd_map); 350 if (error != 0) { 351 printf("%s: could not create tx ring DMA map\n", 352 sc->sc_dev.dv_xname); 353 goto fail; 354 } 355 356 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 357 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 358 if (error != 0) { 359 printf("%s: could not allocate tx ring DMA memory\n", 360 sc->sc_dev.dv_xname); 361 goto fail; 362 } 363 364 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 365 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 366 if (error != 0) { 367 printf("%s: can't map tx ring DMA memory\n", 368 sc->sc_dev.dv_xname); 369 goto fail; 370 } 371 372 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 373 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 374 if (error != 0) { 375 printf("%s: could not load tx ring DMA map\n", 376 sc->sc_dev.dv_xname); 377 goto fail; 378 } 379 380 /* 381 * Allocate and map rx ring. 382 */ 383 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 384 BUS_DMA_NOWAIT, &sc->rbd_map); 385 if (error != 0) { 386 printf("%s: could not create rx ring DMA map\n", 387 sc->sc_dev.dv_xname); 388 goto fail; 389 } 390 391 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 392 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 393 if (error != 0) { 394 printf("%s: could not allocate rx ring DMA memory\n", 395 sc->sc_dev.dv_xname); 396 goto fail; 397 } 398 399 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 400 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 401 if (error != 0) { 402 printf("%s: can't map rx ring DMA memory\n", 403 sc->sc_dev.dv_xname); 404 goto fail; 405 } 406 407 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 408 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 409 if (error != 0) { 410 printf("%s: could not load tx ring DMA map\n", 411 sc->sc_dev.dv_xname); 412 goto fail; 413 } 414 415 /* 416 * Allocate and map status ring. 417 */ 418 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 419 0, BUS_DMA_NOWAIT, &sc->status_map); 420 if (error != 0) { 421 printf("%s: could not create status ring DMA map\n", 422 sc->sc_dev.dv_xname); 423 goto fail; 424 } 425 426 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 427 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 428 if (error != 0) { 429 printf("%s: could not allocate status ring DMA memory\n", 430 sc->sc_dev.dv_xname); 431 goto fail; 432 } 433 434 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 435 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 436 if (error != 0) { 437 printf("%s: can't map status ring DMA memory\n", 438 sc->sc_dev.dv_xname); 439 goto fail; 440 } 441 442 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 443 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 444 if (error != 0) { 445 printf("%s: could not load status ring DMA map\n", 446 sc->sc_dev.dv_xname); 447 goto fail; 448 } 449 450 /* 451 * Allocate command DMA map. 452 */ 453 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 454 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 455 if (error != 0) { 456 printf("%s: could not create command DMA map\n", 457 sc->sc_dev.dv_xname); 458 goto fail; 459 } 460 461 /* 462 * Allocate headers DMA maps. 463 */ 464 SLIST_INIT(&sc->free_shdr); 465 for (i = 0; i < IPW_NDATA; i++) { 466 shdr = &sc->shdr_list[i]; 467 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_hdr), 468 1, sizeof (struct ipw_hdr), 0, BUS_DMA_NOWAIT, &shdr->map); 469 if (error != 0) { 470 printf("%s: could not create header DMA map\n", 471 sc->sc_dev.dv_xname); 472 goto fail; 473 } 474 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 475 } 476 477 /* 478 * Allocate tx buffers DMA maps. 479 */ 480 SLIST_INIT(&sc->free_sbuf); 481 for (i = 0; i < IPW_NDATA; i++) { 482 sbuf = &sc->tx_sbuf_list[i]; 483 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, IPW_MAX_NSEG, 484 MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 485 if (error != 0) { 486 printf("%s: could not create tx DMA map\n", 487 sc->sc_dev.dv_xname); 488 goto fail; 489 } 490 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 491 } 492 493 /* 494 * Initialize tx ring. 495 */ 496 for (i = 0; i < IPW_NTBD; i++) { 497 sbd = &sc->stbd_list[i]; 498 sbd->bd = &sc->tbd_list[i]; 499 sbd->type = IPW_SBD_TYPE_NOASSOC; 500 } 501 502 /* 503 * Pre-allocate rx buffers and DMA maps. 504 */ 505 for (i = 0; i < IPW_NRBD; i++) { 506 sbd = &sc->srbd_list[i]; 507 sbuf = &sc->rx_sbuf_list[i]; 508 sbd->bd = &sc->rbd_list[i]; 509 510 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 511 if (sbuf->m == NULL) { 512 printf("%s: could not allocate rx mbuf\n", 513 sc->sc_dev.dv_xname); 514 error = ENOMEM; 515 goto fail; 516 } 517 MCLGET(sbuf->m, M_DONTWAIT); 518 if (!(sbuf->m->m_flags & M_EXT)) { 519 m_freem(sbuf->m); 520 printf("%s: could not allocate rx mbuf cluster\n", 521 sc->sc_dev.dv_xname); 522 error = ENOMEM; 523 goto fail; 524 } 525 526 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 527 0, BUS_DMA_NOWAIT, &sbuf->map); 528 if (error != 0) { 529 printf("%s: could not create rx DMA map\n", 530 sc->sc_dev.dv_xname); 531 goto fail; 532 } 533 534 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 535 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 536 if (error != 0) { 537 printf("%s: can't map rx DMA memory\n", 538 sc->sc_dev.dv_xname); 539 goto fail; 540 } 541 542 sbd->type = IPW_SBD_TYPE_DATA; 543 sbd->priv = sbuf; 544 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 545 sbd->bd->len = htole32(MCLBYTES); 546 } 547 548 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 549 BUS_DMASYNC_PREWRITE); 550 551 return 0; 552 553fail: ipw_release(sc); 554 return error; 555} 556 557void 558ipw_release(struct ipw_softc *sc) 559{ 560 struct ipw_soft_buf *sbuf; 561 int i; 562 563 if (sc->tbd_map != NULL) { 564 if (sc->tbd_list != NULL) { 565 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 566 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 567 IPW_TBD_SZ); 568 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 569 } 570 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 571 } 572 573 if (sc->rbd_map != NULL) { 574 if (sc->rbd_list != NULL) { 575 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 576 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 577 IPW_RBD_SZ); 578 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 579 } 580 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 581 } 582 583 if (sc->status_map != NULL) { 584 if (sc->status_list != NULL) { 585 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 586 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 587 IPW_RBD_SZ); 588 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 589 } 590 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 591 } 592 593 if (sc->cmd_map != NULL) 594 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 595 596 for (i = 0; i < IPW_NDATA; i++) 597 bus_dmamap_destroy(sc->sc_dmat, sc->shdr_list[i].map); 598 599 for (i = 0; i < IPW_NDATA; i++) 600 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 601 602 for (i = 0; i < IPW_NRBD; i++) { 603 sbuf = &sc->rx_sbuf_list[i]; 604 if (sbuf->map != NULL) { 605 if (sbuf->m != NULL) { 606 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 607 m_freem(sbuf->m); 608 } 609 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 610 } 611 } 612 613 task_del(systq, &sc->sc_scantask); 614 task_del(systq, &sc->sc_authandassoctask); 615} 616 617int 618ipw_media_change(struct ifnet *ifp) 619{ 620 int error; 621 622 error = ieee80211_media_change(ifp); 623 if (error != ENETRESET) 624 return error; 625 626 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 627 ipw_init(ifp); 628 629 return 0; 630} 631 632void 633ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 634{ 635 struct ipw_softc *sc = ifp->if_softc; 636 struct ieee80211com *ic = &sc->sc_ic; 637 static const struct { 638 uint32_t val; 639 int rate; 640 } rates[] = { 641 { IPW_RATE_DS1, 2 }, 642 { IPW_RATE_DS2, 4 }, 643 { IPW_RATE_DS5, 11 }, 644 { IPW_RATE_DS11, 22 }, 645 }; 646 uint32_t val; 647 int rate, i; 648 649 imr->ifm_status = IFM_AVALID; 650 imr->ifm_active = IFM_IEEE80211; 651 if (ic->ic_state == IEEE80211_S_RUN) 652 imr->ifm_status |= IFM_ACTIVE; 653 654 /* read current transmission rate from adapter */ 655 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 656 val &= 0xf; 657 658 /* convert rate to 802.11 rate */ 659 for (i = 0; i < nitems(rates) && rates[i].val != val; i++); 660 rate = (i < nitems(rates)) ? rates[i].rate : 0; 661 662 imr->ifm_active |= IFM_IEEE80211_11B; 663 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 664 switch (ic->ic_opmode) { 665 case IEEE80211_M_STA: 666 break; 667#ifndef IEEE80211_STA_ONLY 668 case IEEE80211_M_IBSS: 669 imr->ifm_active |= IFM_IEEE80211_IBSS; 670 break; 671#endif 672 case IEEE80211_M_MONITOR: 673 imr->ifm_active |= IFM_IEEE80211_MONITOR; 674 break; 675 default: 676 /* should not get there */ 677 break; 678 } 679} 680 681int 682ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 683{ 684 struct ipw_softc *sc = ic->ic_softc; 685 686 switch (nstate) { 687 case IEEE80211_S_SCAN: 688 task_add(systq, &sc->sc_scantask); 689 break; 690 691 case IEEE80211_S_AUTH: 692 task_add(systq, &sc->sc_authandassoctask); 693 break; 694 695 case IEEE80211_S_RUN: 696 case IEEE80211_S_INIT: 697 case IEEE80211_S_ASSOC: 698 /* nothing to do */ 699 break; 700 } 701 702 ic->ic_state = nstate; 703 return 0; 704} 705 706/* 707 * Read 16 bits at address 'addr' from the Microwire EEPROM. 708 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 709 */ 710uint16_t 711ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 712{ 713 uint32_t tmp; 714 uint16_t val; 715 int n; 716 717 /* clock C once before the first command */ 718 IPW_EEPROM_CTL(sc, 0); 719 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 720 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 721 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 722 723 /* write start bit (1) */ 724 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 725 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 726 727 /* write READ opcode (10) */ 728 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 729 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 730 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 731 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 732 733 /* write address A7-A0 */ 734 for (n = 7; n >= 0; n--) { 735 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 736 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 737 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 738 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 739 } 740 741 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 742 743 /* read data Q15-Q0 */ 744 val = 0; 745 for (n = 15; n >= 0; n--) { 746 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 747 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 748 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 749 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 750 } 751 752 IPW_EEPROM_CTL(sc, 0); 753 754 /* clear Chip Select and clock C */ 755 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 756 IPW_EEPROM_CTL(sc, 0); 757 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 758 759 return val; 760} 761 762void 763ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 764{ 765 struct ipw_cmd *cmd; 766 767 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 768 BUS_DMASYNC_POSTREAD); 769 770 cmd = mtod(sbuf->m, struct ipw_cmd *); 771 772 DPRINTFN(2, ("received command ack type=%u,status=%u\n", 773 letoh32(cmd->type), letoh32(cmd->status))); 774 775 wakeup(&sc->cmd); 776} 777 778void 779ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 780{ 781 struct ieee80211com *ic = &sc->sc_ic; 782 struct ifnet *ifp = &ic->ic_if; 783 uint32_t state; 784 785 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 786 BUS_DMASYNC_POSTREAD); 787 788 state = letoh32(*mtod(sbuf->m, uint32_t *)); 789 790 DPRINTFN(2, ("firmware state changed to 0x%x\n", state)); 791 792 switch (state) { 793 case IPW_STATE_ASSOCIATED: 794 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 795 break; 796 797 case IPW_STATE_SCANNING: 798 if (ic->ic_state == IEEE80211_S_RUN) 799 ieee80211_begin_scan(ifp); 800 break; 801 802 case IPW_STATE_SCAN_COMPLETE: 803 if (ic->ic_state == IEEE80211_S_SCAN) 804 ieee80211_end_scan(ifp); 805 break; 806 807 case IPW_STATE_ASSOCIATION_LOST: 808 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 809 break; 810 811 case IPW_STATE_DISABLED: 812 wakeup(sc); 813 break; 814 815 case IPW_STATE_RADIO_DISABLED: 816 ifp->if_flags &= ~IFF_UP; 817 ipw_stop(&ic->ic_if, 1); 818 break; 819 } 820} 821 822void 823ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 824 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 825{ 826 struct ieee80211com *ic = &sc->sc_ic; 827 struct ifnet *ifp = &ic->ic_if; 828 struct mbuf *mnew, *m; 829 struct ieee80211_frame *wh; 830 struct ieee80211_rxinfo rxi; 831 struct ieee80211_node *ni; 832 int error; 833 834 DPRINTFN(5, ("received data frame len=%u,rssi=%u\n", 835 letoh32(status->len), status->rssi)); 836 837 /* 838 * Try to allocate a new mbuf for this ring element and load it before 839 * processing the current mbuf. If the ring element cannot be loaded, 840 * drop the received packet and reuse the old mbuf. In the unlikely 841 * case that the old mbuf can't be reloaded either, explicitly panic. 842 */ 843 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 844 if (mnew == NULL) { 845 ifp->if_ierrors++; 846 return; 847 } 848 MCLGET(mnew, M_DONTWAIT); 849 if (!(mnew->m_flags & M_EXT)) { 850 m_freem(mnew); 851 ifp->if_ierrors++; 852 return; 853 } 854 855 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 856 BUS_DMASYNC_POSTREAD); 857 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 858 859 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(mnew, void *), 860 MCLBYTES, NULL, BUS_DMA_NOWAIT); 861 if (error != 0) { 862 m_freem(mnew); 863 864 /* try to reload the old mbuf */ 865 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 866 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 867 if (error != 0) { 868 /* very unlikely that it will fail... */ 869 panic("%s: could not load old rx mbuf", 870 sc->sc_dev.dv_xname); 871 } 872 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 873 ifp->if_ierrors++; 874 return; 875 } 876 877 m = sbuf->m; 878 sbuf->m = mnew; 879 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 880 881 /* finalize mbuf */ 882 m->m_pkthdr.len = m->m_len = letoh32(status->len); 883 884#if NBPFILTER > 0 885 if (sc->sc_drvbpf != NULL) { 886 struct mbuf mb; 887 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 888 889 tap->wr_flags = 0; 890 tap->wr_antsignal = status->rssi; 891 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 892 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 893 894 mb.m_data = (caddr_t)tap; 895 mb.m_len = sc->sc_rxtap_len; 896 mb.m_next = m; 897 mb.m_nextpkt = NULL; 898 mb.m_type = 0; 899 mb.m_flags = 0; 900 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 901 } 902#endif 903 904 wh = mtod(m, struct ieee80211_frame *); 905 ni = ieee80211_find_rxnode(ic, wh); 906 907 /* send the frame to the upper layer */ 908 rxi.rxi_flags = 0; 909 rxi.rxi_rssi = status->rssi; 910 rxi.rxi_tstamp = 0; /* unused */ 911 ieee80211_input(ifp, m, ni, &rxi); 912 913 ieee80211_release_node(ic, ni); 914} 915 916void 917ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 918{ 919 DPRINTFN(2, ("received notification\n")); 920} 921 922void 923ipw_rx_intr(struct ipw_softc *sc) 924{ 925 struct ipw_status *status; 926 struct ipw_soft_bd *sbd; 927 struct ipw_soft_buf *sbuf; 928 uint32_t r, i; 929 930 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 931 932 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 933 934 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 935 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 936 BUS_DMASYNC_POSTREAD); 937 938 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 939 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 940 BUS_DMASYNC_POSTREAD); 941 942 status = &sc->status_list[i]; 943 sbd = &sc->srbd_list[i]; 944 sbuf = sbd->priv; 945 946 switch (letoh16(status->code) & 0xf) { 947 case IPW_STATUS_CODE_COMMAND: 948 ipw_command_intr(sc, sbuf); 949 break; 950 951 case IPW_STATUS_CODE_NEWSTATE: 952 ipw_newstate_intr(sc, sbuf); 953 break; 954 955 case IPW_STATUS_CODE_DATA_802_3: 956 case IPW_STATUS_CODE_DATA_802_11: 957 ipw_data_intr(sc, status, sbd, sbuf); 958 break; 959 960 case IPW_STATUS_CODE_NOTIFICATION: 961 ipw_notification_intr(sc, sbuf); 962 break; 963 964 default: 965 printf("%s: unknown status code %u\n", 966 sc->sc_dev.dv_xname, letoh16(status->code)); 967 } 968 sbd->bd->flags = 0; 969 970 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 971 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 972 BUS_DMASYNC_PREWRITE); 973 } 974 975 /* tell the firmware what we have processed */ 976 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 977 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 978} 979 980void 981ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 982{ 983 struct ieee80211com *ic = &sc->sc_ic; 984 struct ipw_soft_hdr *shdr; 985 struct ipw_soft_buf *sbuf; 986 987 switch (sbd->type) { 988 case IPW_SBD_TYPE_COMMAND: 989 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 990 break; 991 992 case IPW_SBD_TYPE_HEADER: 993 shdr = sbd->priv; 994 bus_dmamap_unload(sc->sc_dmat, shdr->map); 995 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 996 break; 997 998 case IPW_SBD_TYPE_DATA: 999 sbuf = sbd->priv; 1000 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1001 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1002 1003 m_freem(sbuf->m); 1004 1005 if (sbuf->ni != NULL) 1006 ieee80211_release_node(ic, sbuf->ni); 1007 1008 /* kill watchdog timer */ 1009 sc->sc_tx_timer = 0; 1010 break; 1011 } 1012 sbd->type = IPW_SBD_TYPE_NOASSOC; 1013} 1014 1015void 1016ipw_tx_intr(struct ipw_softc *sc) 1017{ 1018 struct ifnet *ifp = &sc->sc_ic.ic_if; 1019 struct ipw_soft_bd *sbd; 1020 uint32_t r, i; 1021 1022 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 1023 1024 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1025 sbd = &sc->stbd_list[i]; 1026 1027 if (sbd->type == IPW_SBD_TYPE_DATA) 1028 ifp->if_opackets++; 1029 1030 ipw_release_sbd(sc, sbd); 1031 sc->txfree++; 1032 } 1033 1034 /* remember what the firmware has processed */ 1035 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1036 1037 /* call start() since some buffer descriptors have been released */ 1038 ifp->if_flags &= ~IFF_OACTIVE; 1039 (*ifp->if_start)(ifp); 1040} 1041 1042int 1043ipw_intr(void *arg) 1044{ 1045 struct ipw_softc *sc = arg; 1046 struct ifnet *ifp = &sc->sc_ic.ic_if; 1047 uint32_t r; 1048 1049 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) 1050 return 0; 1051 1052 /* disable interrupts */ 1053 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1054 1055 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1056 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 1057 ifp->if_flags &= ~IFF_UP; 1058 ipw_stop(ifp, 1); 1059 return 1; 1060 } 1061 1062 if (r & IPW_INTR_FW_INIT_DONE) 1063 wakeup(sc); 1064 1065 if (r & IPW_INTR_RX_TRANSFER) 1066 ipw_rx_intr(sc); 1067 1068 if (r & IPW_INTR_TX_TRANSFER) 1069 ipw_tx_intr(sc); 1070 1071 /* acknowledge interrupts */ 1072 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1073 1074 /* re-enable interrupts */ 1075 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1076 1077 return 1; 1078} 1079 1080int 1081ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1082{ 1083 struct ipw_soft_bd *sbd; 1084 int s, error; 1085 1086 s = splnet(); 1087 1088 sc->cmd.type = htole32(type); 1089 sc->cmd.subtype = htole32(0); 1090 sc->cmd.len = htole32(len); 1091 sc->cmd.seq = htole32(0); 1092 if (data != NULL) 1093 bcopy(data, sc->cmd.data, len); 1094 1095 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 1096 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 1097 if (error != 0) { 1098 printf("%s: can't map command DMA memory\n", 1099 sc->sc_dev.dv_xname); 1100 splx(s); 1101 return error; 1102 } 1103 1104 sbd = &sc->stbd_list[sc->txcur]; 1105 sbd->type = IPW_SBD_TYPE_COMMAND; 1106 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1107 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1108 sbd->bd->nfrag = 1; 1109 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1110 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1111 1112 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1113 BUS_DMASYNC_PREWRITE); 1114 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1115 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1116 BUS_DMASYNC_PREWRITE); 1117 1118 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1119 sc->txfree--; 1120 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1121 1122 DPRINTFN(2, ("sending command type=%u,len=%u\n", type, len)); 1123 1124 /* wait at most one second for command to complete */ 1125 error = tsleep(&sc->cmd, 0, "ipwcmd", hz); 1126 splx(s); 1127 1128 return error; 1129} 1130 1131/* ARGSUSED */ 1132int 1133ipw_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type, 1134 int arg1, int arg2) 1135{ 1136 return EOPNOTSUPP; 1137} 1138 1139int 1140ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 1141{ 1142 struct ipw_softc *sc = ifp->if_softc; 1143 struct ieee80211com *ic = &sc->sc_ic; 1144 struct ieee80211_frame *wh; 1145 struct ieee80211_key *k; 1146 struct ipw_soft_bd *sbd; 1147 struct ipw_soft_hdr *shdr; 1148 struct ipw_soft_buf *sbuf; 1149 int error, i; 1150 1151 wh = mtod(m, struct ieee80211_frame *); 1152 1153 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1154 k = ieee80211_get_txkey(ic, wh, ni); 1155 1156 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1157 return ENOBUFS; 1158 1159 /* packet header may have moved, reset our local pointer */ 1160 wh = mtod(m, struct ieee80211_frame *); 1161 } 1162 1163#if NBPFILTER > 0 1164 if (sc->sc_drvbpf != NULL) { 1165 struct mbuf mb; 1166 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1167 1168 tap->wt_flags = 0; 1169 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1170 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1171 1172 mb.m_data = (caddr_t)tap; 1173 mb.m_len = sc->sc_txtap_len; 1174 mb.m_next = m; 1175 mb.m_nextpkt = NULL; 1176 mb.m_type = 0; 1177 mb.m_flags = 0; 1178 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1179 } 1180#endif 1181 1182 shdr = SLIST_FIRST(&sc->free_shdr); 1183 sbuf = SLIST_FIRST(&sc->free_sbuf); 1184 1185 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1186 shdr->hdr.subtype = htole32(0); 1187 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) ? 1 : 0; 1188 shdr->hdr.encrypt = 0; 1189 shdr->hdr.keyidx = 0; 1190 shdr->hdr.keysz = 0; 1191 shdr->hdr.fragmentsz = htole16(0); 1192 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1193 if (ic->ic_opmode == IEEE80211_M_STA) 1194 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1195 else 1196 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1197 1198 /* trim IEEE802.11 header */ 1199 m_adj(m, sizeof (struct ieee80211_frame)); 1200 1201 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 1202 if (error != 0 && error != EFBIG) { 1203 printf("%s: can't map mbuf (error %d)\n", 1204 sc->sc_dev.dv_xname, error); 1205 m_freem(m); 1206 return error; 1207 } 1208 if (error != 0) { 1209 /* too many fragments, linearize */ 1210 if (m_defrag(m, M_DONTWAIT)) { 1211 m_freem(m); 1212 return ENOBUFS; 1213 } 1214 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, 1215 BUS_DMA_NOWAIT); 1216 if (error != 0) { 1217 printf("%s: can't map mbuf (error %d)\n", 1218 sc->sc_dev.dv_xname, error); 1219 m_freem(m); 1220 return error; 1221 } 1222 } 1223 1224 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 1225 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 1226 if (error != 0) { 1227 printf("%s: can't map header DMA memory (error %d)\n", 1228 sc->sc_dev.dv_xname, error); 1229 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1230 m_freem(m); 1231 return error; 1232 } 1233 1234 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1235 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1236 1237 sbd = &sc->stbd_list[sc->txcur]; 1238 sbd->type = IPW_SBD_TYPE_HEADER; 1239 sbd->priv = shdr; 1240 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 1241 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1242 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1243 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1244 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1245 1246 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1247 sc->txcur * sizeof (struct ipw_bd), 1248 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1249 1250 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1251 sc->txfree--; 1252 1253 sbuf->m = m; 1254 sbuf->ni = ni; 1255 1256 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1257 sbd = &sc->stbd_list[sc->txcur]; 1258 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1259 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1260 sbd->bd->nfrag = 0; /* used only in first bd */ 1261 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1262 if (i == sbuf->map->dm_nsegs - 1) { 1263 sbd->type = IPW_SBD_TYPE_DATA; 1264 sbd->priv = sbuf; 1265 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1266 } else { 1267 sbd->type = IPW_SBD_TYPE_NOASSOC; 1268 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1269 } 1270 1271 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1272 sc->txcur * sizeof (struct ipw_bd), 1273 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1274 1275 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1276 sc->txfree--; 1277 } 1278 1279 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1280 BUS_DMASYNC_PREWRITE); 1281 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 1282 BUS_DMASYNC_PREWRITE); 1283 1284 /* inform firmware about this new packet */ 1285 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1286 1287 return 0; 1288} 1289 1290void 1291ipw_start(struct ifnet *ifp) 1292{ 1293 struct ipw_softc *sc = ifp->if_softc; 1294 struct ieee80211com *ic = &sc->sc_ic; 1295 struct ieee80211_node *ni; 1296 struct mbuf *m; 1297 1298 if (ic->ic_state != IEEE80211_S_RUN) 1299 return; 1300 1301 for (;;) { 1302 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1303 ifp->if_flags |= IFF_OACTIVE; 1304 break; 1305 } 1306 1307 IFQ_DEQUEUE(&ifp->if_snd, m); 1308 if (m == NULL) 1309 break; 1310 1311#if NBPFILTER > 0 1312 if (ifp->if_bpf != NULL) 1313 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1314#endif 1315 1316 m = ieee80211_encap(ifp, m, &ni); 1317 if (m == NULL) 1318 continue; 1319#if NBPFILTER > 0 1320 if (ic->ic_rawbpf != NULL) 1321 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1322#endif 1323 if (ipw_tx_start(ifp, m, ni) != 0) { 1324 if (ni != NULL) 1325 ieee80211_release_node(ic, ni); 1326 ifp->if_oerrors++; 1327 break; 1328 } 1329 1330 /* start watchdog timer */ 1331 sc->sc_tx_timer = 5; 1332 ifp->if_timer = 1; 1333 } 1334} 1335 1336void 1337ipw_watchdog(struct ifnet *ifp) 1338{ 1339 struct ipw_softc *sc = ifp->if_softc; 1340 1341 ifp->if_timer = 0; 1342 1343 if (sc->sc_tx_timer > 0) { 1344 if (--sc->sc_tx_timer == 0) { 1345 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1346 ifp->if_flags &= ~IFF_UP; 1347 ipw_stop(ifp, 1); 1348 ifp->if_oerrors++; 1349 return; 1350 } 1351 ifp->if_timer = 1; 1352 } 1353 1354 ieee80211_watchdog(ifp); 1355} 1356 1357int 1358ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1359{ 1360 struct ipw_softc *sc = ifp->if_softc; 1361 struct ieee80211com *ic = &sc->sc_ic; 1362 struct ifreq *ifr; 1363 int s, error = 0; 1364 1365 s = splnet(); 1366 /* 1367 * Prevent processes from entering this function while another 1368 * process is tsleep'ing in it. 1369 */ 1370 while ((sc->sc_flags & IPW_FLAG_BUSY) && error == 0) 1371 error = tsleep(&sc->sc_flags, PCATCH, "ipwioc", 0); 1372 if (error != 0) { 1373 splx(s); 1374 return error; 1375 } 1376 sc->sc_flags |= IPW_FLAG_BUSY; 1377 1378 switch (cmd) { 1379 case SIOCSIFADDR: 1380 ifp->if_flags |= IFF_UP; 1381 /* FALLTHROUGH */ 1382 case SIOCSIFFLAGS: 1383 if (ifp->if_flags & IFF_UP) { 1384 if (!(ifp->if_flags & IFF_RUNNING)) 1385 ipw_init(ifp); 1386 } else { 1387 if (ifp->if_flags & IFF_RUNNING) 1388 ipw_stop(ifp, 1); 1389 } 1390 break; 1391 1392 case SIOCADDMULTI: 1393 case SIOCDELMULTI: 1394 ifr = (struct ifreq *)data; 1395 error = (cmd == SIOCADDMULTI) ? 1396 ether_addmulti(ifr, &ic->ic_ac) : 1397 ether_delmulti(ifr, &ic->ic_ac); 1398 1399 if (error == ENETRESET) 1400 error = 0; 1401 break; 1402 1403 case SIOCG80211TXPOWER: 1404 /* 1405 * If the hardware radio transmitter switch is off, report a 1406 * tx power of IEEE80211_TXPOWER_MIN to indicate that radio 1407 * transmitter is killed. 1408 */ 1409 ((struct ieee80211_txpower *)data)->i_val = 1410 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 1411 IEEE80211_TXPOWER_MIN : sc->sc_ic.ic_txpower; 1412 break; 1413 1414 default: 1415 error = ieee80211_ioctl(ifp, cmd, data); 1416 } 1417 1418 if (error == ENETRESET) { 1419 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1420 (IFF_UP | IFF_RUNNING)) 1421 ipw_init(ifp); 1422 error = 0; 1423 } 1424 1425 sc->sc_flags &= ~IPW_FLAG_BUSY; 1426 wakeup(&sc->sc_flags); 1427 splx(s); 1428 return error; 1429} 1430 1431uint32_t 1432ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1433{ 1434 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1435} 1436 1437void 1438ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1439{ 1440 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1441} 1442 1443int 1444ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1445{ 1446 uint32_t addr, info; 1447 uint16_t count, size; 1448 uint32_t total; 1449 1450 /* addr[4] + count[2] + size[2] */ 1451 addr = MEM_READ_4(sc, sc->table2_base + off); 1452 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1453 1454 count = info >> 16; 1455 size = info & 0xffff; 1456 total = count * size; 1457 1458 if (total > *len) { 1459 *len = total; 1460 return EINVAL; 1461 } 1462 *len = total; 1463 ipw_read_mem_1(sc, addr, buf, total); 1464 1465 return 0; 1466} 1467 1468void 1469ipw_stop_master(struct ipw_softc *sc) 1470{ 1471 uint32_t tmp; 1472 int ntries; 1473 1474 /* disable interrupts */ 1475 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1476 1477 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1478 for (ntries = 0; ntries < 50; ntries++) { 1479 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1480 break; 1481 DELAY(10); 1482 } 1483 if (ntries == 50) 1484 printf("%s: timeout waiting for master\n", 1485 sc->sc_dev.dv_xname); 1486 1487 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1488 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1489 1490 sc->sc_flags &= ~IPW_FLAG_FW_INITED; 1491} 1492 1493int 1494ipw_reset(struct ipw_softc *sc) 1495{ 1496 uint32_t tmp; 1497 int ntries; 1498 1499 ipw_stop_master(sc); 1500 1501 /* move adapter to D0 state */ 1502 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1503 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1504 1505 /* wait for clock stabilization */ 1506 for (ntries = 0; ntries < 1000; ntries++) { 1507 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1508 break; 1509 DELAY(200); 1510 } 1511 if (ntries == 1000) 1512 return EIO; 1513 1514 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1515 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1516 1517 DELAY(10); 1518 1519 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1520 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1521 1522 return 0; 1523} 1524 1525int 1526ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1527{ 1528 int ntries; 1529 1530 /* voodoo from the Intel Linux driver */ 1531 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1532 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1533 1534 MEM_WRITE_2(sc, 0x220000, 0x0703); 1535 MEM_WRITE_2(sc, 0x220000, 0x0707); 1536 1537 MEM_WRITE_1(sc, 0x210014, 0x72); 1538 MEM_WRITE_1(sc, 0x210014, 0x72); 1539 1540 MEM_WRITE_1(sc, 0x210000, 0x40); 1541 MEM_WRITE_1(sc, 0x210000, 0x00); 1542 MEM_WRITE_1(sc, 0x210000, 0x40); 1543 1544 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1545 1546 MEM_WRITE_1(sc, 0x210000, 0x00); 1547 MEM_WRITE_1(sc, 0x210000, 0x00); 1548 MEM_WRITE_1(sc, 0x210000, 0x80); 1549 1550 MEM_WRITE_2(sc, 0x220000, 0x0703); 1551 MEM_WRITE_2(sc, 0x220000, 0x0707); 1552 1553 MEM_WRITE_1(sc, 0x210014, 0x72); 1554 MEM_WRITE_1(sc, 0x210014, 0x72); 1555 1556 MEM_WRITE_1(sc, 0x210000, 0x00); 1557 MEM_WRITE_1(sc, 0x210000, 0x80); 1558 1559 for (ntries = 0; ntries < 100; ntries++) { 1560 if (MEM_READ_1(sc, 0x210000) & 1) 1561 break; 1562 DELAY(1000); 1563 } 1564 if (ntries == 100) { 1565 printf("%s: timeout waiting for ucode to initialize\n", 1566 sc->sc_dev.dv_xname); 1567 return EIO; 1568 } 1569 1570 MEM_WRITE_4(sc, 0x3000e0, 0); 1571 1572 return 0; 1573} 1574 1575/* set of macros to handle unaligned little endian data in firmware image */ 1576#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1577#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1578int 1579ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1580{ 1581 u_char *p, *end; 1582 uint32_t tmp, dst; 1583 uint16_t len; 1584 int error; 1585 1586 p = fw; 1587 end = fw + size; 1588 while (p < end) { 1589 if (p + 6 > end) 1590 return EINVAL; 1591 1592 dst = GETLE32(p); p += 4; 1593 len = GETLE16(p); p += 2; 1594 1595 if (p + len > end) 1596 return EINVAL; 1597 1598 ipw_write_mem_1(sc, dst, p, len); 1599 p += len; 1600 } 1601 1602 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1603 IPW_IO_LED_OFF); 1604 1605 /* allow interrupts so we know when the firmware is inited */ 1606 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1607 1608 /* tell the adapter to initialize the firmware */ 1609 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1610 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1611 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1612 1613 /* wait at most one second for firmware initialization to complete */ 1614 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1615 printf("%s: timeout waiting for firmware initialization to " 1616 "complete\n", sc->sc_dev.dv_xname); 1617 return error; 1618 } 1619 1620 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1621 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1622 IPW_IO_GPIO3_MASK); 1623 1624 return 0; 1625} 1626 1627int 1628ipw_read_firmware(struct ipw_softc *sc, struct ipw_firmware *fw) 1629{ 1630 const struct ipw_firmware_hdr *hdr; 1631 const char *name; 1632 int error; 1633 1634 switch (sc->sc_ic.ic_opmode) { 1635 case IEEE80211_M_STA: 1636 name = "ipw-bss"; 1637 break; 1638#ifndef IEEE80211_STA_ONLY 1639 case IEEE80211_M_IBSS: 1640 name = "ipw-ibss"; 1641 break; 1642#endif 1643 case IEEE80211_M_MONITOR: 1644 name = "ipw-monitor"; 1645 break; 1646 default: 1647 /* should not get there */ 1648 return ENODEV; 1649 } 1650 if ((error = loadfirmware(name, &fw->data, &fw->size)) != 0) 1651 return error; 1652 1653 if (fw->size < sizeof (*hdr)) { 1654 error = EINVAL; 1655 goto fail; 1656 } 1657 hdr = (const struct ipw_firmware_hdr *)fw->data; 1658 fw->main_size = letoh32(hdr->main_size); 1659 fw->ucode_size = letoh32(hdr->ucode_size); 1660 1661 if (fw->size < sizeof (*hdr) + fw->main_size + fw->ucode_size) { 1662 error = EINVAL; 1663 goto fail; 1664 } 1665 fw->main = fw->data + sizeof (*hdr); 1666 fw->ucode = fw->main + fw->main_size; 1667 1668 return 0; 1669 1670fail: free(fw->data, M_DEVBUF, fw->size); 1671 return error; 1672} 1673 1674void 1675ipw_scan(void *arg1) 1676{ 1677 struct ipw_softc *sc = arg1; 1678 struct ifnet *ifp = &sc->sc_ic.ic_if; 1679 struct ipw_scan_options scan; 1680 uint8_t ssid[IEEE80211_NWID_LEN]; 1681 int error; 1682 1683 /* 1684 * Firmware has a bug and does not honour the ``do not associate 1685 * after scan'' bit in the scan command. To prevent the firmware 1686 * from associating after the scan, we set the ESSID to something 1687 * unlikely to be used by a real AP. 1688 * XXX would setting the desired BSSID to a multicast address work? 1689 */ 1690 memset(ssid, '\r', sizeof ssid); 1691 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ssid, sizeof ssid); 1692 if (error != 0) 1693 goto fail; 1694 1695 /* no mandatory BSSID */ 1696 DPRINTF(("Setting mandatory BSSID to null\n")); 1697 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1698 if (error != 0) 1699 goto fail; 1700 1701 scan.flags = htole32(IPW_SCAN_DO_NOT_ASSOCIATE | IPW_SCAN_MIXED_CELL); 1702 scan.channels = htole32(0x3fff); /* scan channels 1-14 */ 1703 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1704 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1705 if (error != 0) 1706 goto fail; 1707 1708 /* start scanning */ 1709 DPRINTF(("Enabling adapter\n")); 1710 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1711 if (error != 0) 1712 goto fail; 1713 1714 return; 1715fail: 1716 printf("%s: scan request failed (error=%d)\n", sc->sc_dev.dv_xname, 1717 error); 1718 ieee80211_end_scan(ifp); 1719} 1720 1721void 1722ipw_auth_and_assoc(void *arg1) 1723{ 1724 struct ipw_softc *sc = arg1; 1725 struct ieee80211com *ic = &sc->sc_ic; 1726 struct ieee80211_node *ni = ic->ic_bss; 1727 struct ipw_scan_options scan; 1728 struct ipw_security security; 1729 struct ipw_assoc_req assoc; 1730 uint32_t data; 1731 uint8_t chan; 1732 int s, error; 1733 1734 DPRINTF(("Disabling adapter\n")); 1735 error = ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1736 if (error != 0) 1737 goto fail; 1738#if 1 1739 /* wait at most one second for card to be disabled */ 1740 s = splnet(); 1741 error = tsleep(sc, 0, "ipwdis", hz); 1742 splx(s); 1743 if (error != 0) { 1744 printf("%s: timeout waiting for disabled state\n", 1745 sc->sc_dev.dv_xname); 1746 goto fail; 1747 } 1748#else 1749 /* Intel's Linux driver polls for the DISABLED state instead.. */ 1750 for (ntries = 0; ntries < 1000; ntries++) { 1751 if (ipw_read_table1(sc, IPW_INFO_CARD_DISABLED) == 1) 1752 break; 1753 DELAY(10); 1754 } 1755 if (ntries == 1000) { 1756 printf("%s: timeout waiting for disabled state\n", 1757 sc->sc_dev.dv_xname); 1758 goto fail; 1759 } 1760#endif 1761 1762 bzero(&security, sizeof security); 1763 security.authmode = IPW_AUTH_OPEN; 1764 security.ciphers = htole32(IPW_CIPHER_NONE); 1765 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1766 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1767 sizeof security); 1768 if (error != 0) 1769 goto fail; 1770 1771#ifdef IPW_DEBUG 1772 if (ipw_debug > 0) { 1773 printf("Setting ESSID to "); 1774 ieee80211_print_essid(ni->ni_essid, ni->ni_esslen); 1775 printf("\n"); 1776 } 1777#endif 1778 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ni->ni_essid, ni->ni_esslen); 1779 if (error != 0) 1780 goto fail; 1781 1782 DPRINTF(("Setting BSSID to %s\n", ether_sprintf(ni->ni_bssid))); 1783 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, ni->ni_bssid, 1784 IEEE80211_ADDR_LEN); 1785 if (error != 0) 1786 goto fail; 1787 1788 data = htole32((ic->ic_flags & (IEEE80211_F_WEPON | 1789 IEEE80211_F_RSNON)) ? IPW_PRIVACYON : 0); 1790 DPRINTF(("Setting privacy flags to 0x%x\n", letoh32(data))); 1791 error = ipw_cmd(sc, IPW_CMD_SET_PRIVACY_FLAGS, &data, sizeof data); 1792 if (error != 0) 1793 goto fail; 1794 1795 /* let firmware set the capinfo, lintval, and bssid fixed fields */ 1796 bzero(&assoc, sizeof assoc); 1797 if (ic->ic_flags & IEEE80211_F_RSNON) { 1798 uint8_t *frm = assoc.optie; 1799 1800 /* tell firmware to add a WPA or RSN IE in (Re)Assoc req */ 1801 if (ni->ni_rsnprotos & IEEE80211_PROTO_RSN) 1802 frm = ieee80211_add_rsn(frm, ic, ni); 1803 else if (ni->ni_rsnprotos & IEEE80211_PROTO_WPA) 1804 frm = ieee80211_add_wpa(frm, ic, ni); 1805 assoc.optie_len = htole32(frm - assoc.optie); 1806 } 1807 DPRINTF(("Preparing assocation request (optional IE length=%d)\n", 1808 letoh32(assoc.optie_len))); 1809 error = ipw_cmd(sc, IPW_CMD_SET_ASSOC_REQ, &assoc, sizeof assoc); 1810 if (error != 0) 1811 goto fail; 1812 1813 scan.flags = htole32(IPW_SCAN_MIXED_CELL); 1814 chan = ieee80211_chan2ieee(ic, ni->ni_chan); 1815 scan.channels = htole32(1 << (chan - 1)); 1816 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1817 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1818 if (error != 0) 1819 goto fail; 1820 1821 /* trigger scan+association */ 1822 DPRINTF(("Enabling adapter\n")); 1823 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1824 if (error != 0) 1825 goto fail; 1826 1827 return; 1828fail: 1829 printf("%s: association failed (error=%d)\n", sc->sc_dev.dv_xname, 1830 error); 1831 ieee80211_begin_scan(&ic->ic_if); 1832} 1833 1834int 1835ipw_config(struct ipw_softc *sc) 1836{ 1837 struct ieee80211com *ic = &sc->sc_ic; 1838 struct ifnet *ifp = &ic->ic_if; 1839 struct ipw_configuration config; 1840 uint32_t data; 1841 int error; 1842 1843 switch (ic->ic_opmode) { 1844 case IEEE80211_M_STA: 1845 data = htole32(IPW_MODE_BSS); 1846 break; 1847#ifndef IEEE80211_STA_ONLY 1848 case IEEE80211_M_IBSS: 1849 data = htole32(IPW_MODE_IBSS); 1850 break; 1851#endif 1852 case IEEE80211_M_MONITOR: 1853 data = htole32(IPW_MODE_MONITOR); 1854 break; 1855 default: 1856 /* should not get there */ 1857 return ENODEV; 1858 } 1859 DPRINTF(("Setting mode to %u\n", letoh32(data))); 1860 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1861 if (error != 0) 1862 return error; 1863 1864 if ( 1865#ifndef IEEE80211_STA_ONLY 1866 ic->ic_opmode == IEEE80211_M_IBSS || 1867#endif 1868 ic->ic_opmode == IEEE80211_M_MONITOR) { 1869 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1870 DPRINTF(("Setting channel to %u\n", letoh32(data))); 1871 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1872 if (error != 0) 1873 return error; 1874 } 1875 1876 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1877 DPRINTF(("Enabling adapter\n")); 1878 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1879 } 1880 1881 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 1882 DPRINTF(("Setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 1883 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1884 IEEE80211_ADDR_LEN); 1885 if (error != 0) 1886 return error; 1887 1888 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1889 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1X_ENABLE); 1890#ifndef IEEE80211_STA_ONLY 1891 if (ic->ic_opmode == IEEE80211_M_IBSS) 1892 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1893#endif 1894 if (ifp->if_flags & IFF_PROMISC) 1895 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1896 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1897 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1898 DPRINTF(("Setting configuration 0x%x\n", config.flags)); 1899 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1900 if (error != 0) 1901 return error; 1902 1903 data = htole32(ic->ic_rtsthreshold); 1904 DPRINTF(("Setting RTS threshold to %u\n", letoh32(data))); 1905 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1906 if (error != 0) 1907 return error; 1908 1909 data = htole32(ic->ic_fragthreshold); 1910 DPRINTF(("Setting frag threshold to %u\n", letoh32(data))); 1911 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1912 if (error != 0) 1913 return error; 1914 1915 data = htole32(0x3); /* 1, 2 */ 1916 DPRINTF(("Setting basic tx rates to 0x%x\n", letoh32(data))); 1917 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1918 if (error != 0) 1919 return error; 1920 1921 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1922 DPRINTF(("Setting tx rates to 0x%x\n", letoh32(data))); 1923 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1924 if (error != 0) 1925 return error; 1926 1927 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1928 DPRINTF(("Setting MSDU tx rates to 0x%x\n", letoh32(data))); 1929 error = ipw_cmd(sc, IPW_CMD_SET_MSDU_TX_RATES, &data, sizeof data); 1930 if (error != 0) 1931 return error; 1932 1933 data = htole32(IPW_POWER_MODE_CAM); 1934 DPRINTF(("Setting power mode to %u\n", letoh32(data))); 1935 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1936 if (error != 0) 1937 return error; 1938 1939#ifndef IEEE80211_STA_ONLY 1940 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1941 data = htole32(32); /* default value */ 1942 DPRINTF(("Setting tx power index to %u\n", letoh32(data))); 1943 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1944 sizeof data); 1945 if (error != 0) 1946 return error; 1947 1948 data = htole32(ic->ic_lintval); 1949 DPRINTF(("Setting beacon interval to %u\n", letoh32(data))); 1950 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1951 sizeof data); 1952 if (error != 0) 1953 return error; 1954 } 1955#endif 1956 return 0; 1957} 1958 1959int 1960ipw_init(struct ifnet *ifp) 1961{ 1962 struct ipw_softc *sc = ifp->if_softc; 1963 struct ieee80211com *ic = &sc->sc_ic; 1964 struct ipw_firmware fw; 1965 int error; 1966 1967 ipw_stop(ifp, 0); 1968 1969 if ((error = ipw_reset(sc)) != 0) { 1970 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 1971 goto fail1; 1972 } 1973 1974 if ((error = ipw_read_firmware(sc, &fw)) != 0) { 1975 printf("%s: error %d, could not read firmware\n", 1976 sc->sc_dev.dv_xname, error); 1977 goto fail1; 1978 } 1979 if ((error = ipw_load_ucode(sc, fw.ucode, fw.ucode_size)) != 0) { 1980 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 1981 goto fail2; 1982 } 1983 1984 ipw_stop_master(sc); 1985 1986 /* 1987 * Setup tx, rx and status rings. 1988 */ 1989 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1990 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1991 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1992 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1993 sc->txold = IPW_NTBD - 1; /* latest bd index ack by firmware */ 1994 sc->txcur = 0; /* bd index to write to */ 1995 sc->txfree = IPW_NTBD - 2; 1996 1997 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1998 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1999 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 2000 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 2001 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 2002 2003 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 2004 sc->status_map->dm_segs[0].ds_addr); 2005 2006 if ((error = ipw_load_firmware(sc, fw.main, fw.main_size)) != 0) { 2007 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 2008 goto fail2; 2009 } 2010 sc->sc_flags |= IPW_FLAG_FW_INITED; 2011 free(fw.data, M_DEVBUF, fw.size); 2012 fw.data = NULL; 2013 2014 /* retrieve information tables base addresses */ 2015 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2016 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2017 2018 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2019 2020 if ((error = ipw_config(sc)) != 0) { 2021 printf("%s: device configuration failed\n", 2022 sc->sc_dev.dv_xname); 2023 goto fail1; 2024 } 2025 2026 ifp->if_flags &= ~IFF_OACTIVE; 2027 ifp->if_flags |= IFF_RUNNING; 2028 2029 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2030 ieee80211_begin_scan(ifp); 2031 else 2032 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2033 2034 return 0; 2035 2036fail2: free(fw.data, M_DEVBUF, fw.size); 2037 fw.data = NULL; 2038fail1: ipw_stop(ifp, 0); 2039 return error; 2040} 2041 2042void 2043ipw_stop(struct ifnet *ifp, int disable) 2044{ 2045 struct ipw_softc *sc = ifp->if_softc; 2046 struct ieee80211com *ic = &sc->sc_ic; 2047 int i; 2048 2049 ipw_stop_master(sc); 2050 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2051 2052 ifp->if_timer = 0; 2053 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2054 2055 /* 2056 * Release tx buffers. 2057 */ 2058 for (i = 0; i < IPW_NTBD; i++) 2059 ipw_release_sbd(sc, &sc->stbd_list[i]); 2060 2061 /* in case we were scanning, release the scan "lock" */ 2062 ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; 2063 2064 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2065} 2066 2067void 2068ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2069 bus_size_t count) 2070{ 2071 for (; count > 0; offset++, datap++, count--) { 2072 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2073 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2074 } 2075} 2076 2077void 2078ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2079 bus_size_t count) 2080{ 2081 for (; count > 0; offset++, datap++, count--) { 2082 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2083 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2084 } 2085} 2086 2087struct cfdriver ipw_cd = { 2088 NULL, "ipw", DV_IFNET 2089}; 2090