if_ipw.c revision 1.101
1/* $OpenBSD: if_ipw.c,v 1.101 2014/07/22 13:12:11 mpi Exp $ */ 2 3/*- 4 * Copyright (c) 2004-2008 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/* 21 * Driver for Intel PRO/Wireless 2100 802.11 network adapters. 22 */ 23 24#include "bpfilter.h" 25 26#include <sys/param.h> 27#include <sys/sockio.h> 28#include <sys/workq.h> 29#include <sys/mbuf.h> 30#include <sys/kernel.h> 31#include <sys/socket.h> 32#include <sys/systm.h> 33#include <sys/conf.h> 34#include <sys/device.h> 35 36#include <machine/bus.h> 37#include <machine/endian.h> 38#include <machine/intr.h> 39 40#include <dev/pci/pcireg.h> 41#include <dev/pci/pcivar.h> 42#include <dev/pci/pcidevs.h> 43 44#if NBPFILTER > 0 45#include <net/bpf.h> 46#endif 47#include <net/if.h> 48#include <net/if_arp.h> 49#include <net/if_dl.h> 50#include <net/if_media.h> 51#include <net/if_types.h> 52 53#include <netinet/in.h> 54#include <netinet/if_ether.h> 55 56#include <net80211/ieee80211_var.h> 57#include <net80211/ieee80211_radiotap.h> 58 59#include <dev/pci/if_ipwreg.h> 60#include <dev/pci/if_ipwvar.h> 61 62int ipw_match(struct device *, void *, void *); 63void ipw_attach(struct device *, struct device *, void *); 64int ipw_activate(struct device *, int); 65void ipw_wakeup(struct ipw_softc *); 66int ipw_dma_alloc(struct ipw_softc *); 67void ipw_release(struct ipw_softc *); 68int ipw_media_change(struct ifnet *); 69void ipw_media_status(struct ifnet *, struct ifmediareq *); 70int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 71uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 72void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 73void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 74void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 75 struct ipw_soft_bd *, struct ipw_soft_buf *); 76void ipw_notification_intr(struct ipw_softc *, 77 struct ipw_soft_buf *); 78void ipw_rx_intr(struct ipw_softc *); 79void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 80void ipw_tx_intr(struct ipw_softc *); 81int ipw_intr(void *); 82int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 83int ipw_send_mgmt(struct ieee80211com *, struct ieee80211_node *, 84 int, int, int); 85int ipw_tx_start(struct ifnet *, struct mbuf *, 86 struct ieee80211_node *); 87void ipw_start(struct ifnet *); 88void ipw_watchdog(struct ifnet *); 89int ipw_ioctl(struct ifnet *, u_long, caddr_t); 90uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 91void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 92int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 93 uint32_t *); 94void ipw_stop_master(struct ipw_softc *); 95int ipw_reset(struct ipw_softc *); 96int ipw_load_ucode(struct ipw_softc *, u_char *, int); 97int ipw_load_firmware(struct ipw_softc *, u_char *, int); 98int ipw_read_firmware(struct ipw_softc *, struct ipw_firmware *); 99void ipw_scan(void *, void *); 100void ipw_auth_and_assoc(void *, void *); 101int ipw_config(struct ipw_softc *); 102int ipw_init(struct ifnet *); 103void ipw_stop(struct ifnet *, int); 104void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 105 bus_size_t); 106void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 107 bus_size_t); 108 109static __inline uint8_t 110MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 111{ 112 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 113 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 114} 115 116static __inline uint32_t 117MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 118{ 119 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 120 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 121} 122 123#ifdef IPW_DEBUG 124#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 125#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 126int ipw_debug = 0; 127#else 128#define DPRINTF(x) 129#define DPRINTFN(n, x) 130#endif 131 132struct cfattach ipw_ca = { 133 sizeof (struct ipw_softc), ipw_match, ipw_attach, NULL, 134 ipw_activate 135}; 136 137int 138ipw_match(struct device *parent, void *match, void *aux) 139{ 140 struct pci_attach_args *pa = aux; 141 142 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 143 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 144 return 1; 145 146 return 0; 147} 148 149/* Base Address Register */ 150#define IPW_PCI_BAR0 0x10 151 152void 153ipw_attach(struct device *parent, struct device *self, void *aux) 154{ 155 struct ipw_softc *sc = (struct ipw_softc *)self; 156 struct ieee80211com *ic = &sc->sc_ic; 157 struct ifnet *ifp = &ic->ic_if; 158 struct pci_attach_args *pa = aux; 159 const char *intrstr; 160 bus_space_tag_t memt; 161 bus_space_handle_t memh; 162 bus_addr_t base; 163 pci_intr_handle_t ih; 164 pcireg_t data; 165 uint16_t val; 166 int error, i; 167 168 sc->sc_pct = pa->pa_pc; 169 sc->sc_pcitag = pa->pa_tag, 170 171 /* clear device specific PCI configuration register 0x41 */ 172 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 173 data &= ~0x0000ff00; 174 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 175 176 /* map the register window */ 177 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 178 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 179 if (error != 0) { 180 printf(": can't map mem space\n"); 181 return; 182 } 183 184 sc->sc_st = memt; 185 sc->sc_sh = memh; 186 sc->sc_dmat = pa->pa_dmat; 187 188 /* disable interrupts */ 189 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 190 191 if (pci_intr_map(pa, &ih) != 0) { 192 printf(": can't map interrupt\n"); 193 return; 194 } 195 196 intrstr = pci_intr_string(sc->sc_pct, ih); 197 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 198 sc->sc_dev.dv_xname); 199 if (sc->sc_ih == NULL) { 200 printf(": can't establish interrupt"); 201 if (intrstr != NULL) 202 printf(" at %s", intrstr); 203 printf("\n"); 204 return; 205 } 206 printf(": %s", intrstr); 207 208 if (ipw_reset(sc) != 0) { 209 printf(": could not reset adapter\n"); 210 return; 211 } 212 213 if (ipw_dma_alloc(sc) != 0) { 214 printf(": failed to allocate DMA resources\n"); 215 return; 216 } 217 218 ic->ic_phytype = IEEE80211_T_DS; 219 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 220 ic->ic_state = IEEE80211_S_INIT; 221 222 /* set device capabilities */ 223 ic->ic_caps = 224#ifndef IEEE80211_STA_ONLY 225 IEEE80211_C_IBSS | /* IBSS mode supported */ 226#endif 227 IEEE80211_C_MONITOR | /* monitor mode supported */ 228 IEEE80211_C_TXPMGT | /* tx power management */ 229 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 230 IEEE80211_C_WEP | /* s/w WEP */ 231 IEEE80211_C_RSN | /* WPA/RSN */ 232 IEEE80211_C_SCANALL; /* h/w scanning */ 233 234 /* read MAC address from EEPROM */ 235 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 236 ic->ic_myaddr[0] = val >> 8; 237 ic->ic_myaddr[1] = val & 0xff; 238 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 239 ic->ic_myaddr[2] = val >> 8; 240 ic->ic_myaddr[3] = val & 0xff; 241 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 242 ic->ic_myaddr[4] = val >> 8; 243 ic->ic_myaddr[5] = val & 0xff; 244 245 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 246 247 /* set supported .11b rates */ 248 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 249 250 /* set supported .11b channels (1 through 14) */ 251 for (i = 1; i <= 14; i++) { 252 ic->ic_channels[i].ic_freq = 253 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 254 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 255 } 256 257 /* IBSS channel undefined for now */ 258 ic->ic_ibss_chan = &ic->ic_channels[0]; 259 260 ifp->if_softc = sc; 261 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 262 ifp->if_ioctl = ipw_ioctl; 263 ifp->if_start = ipw_start; 264 ifp->if_watchdog = ipw_watchdog; 265 IFQ_SET_READY(&ifp->if_snd); 266 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 267 268 if_attach(ifp); 269 ieee80211_ifattach(ifp); 270 /* override state transition machine */ 271 sc->sc_newstate = ic->ic_newstate; 272 ic->ic_newstate = ipw_newstate; 273 ic->ic_send_mgmt = ipw_send_mgmt; 274 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 275 276#if NBPFILTER > 0 277 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 278 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 279 280 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 281 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 282 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 283 284 sc->sc_txtap_len = sizeof sc->sc_txtapu; 285 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 286 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 287#endif 288} 289 290int 291ipw_activate(struct device *self, int act) 292{ 293 struct ipw_softc *sc = (struct ipw_softc *)self; 294 struct ifnet *ifp = &sc->sc_ic.ic_if; 295 296 switch (act) { 297 case DVACT_SUSPEND: 298 if (ifp->if_flags & IFF_RUNNING) 299 ipw_stop(ifp, 0); 300 break; 301 case DVACT_WAKEUP: 302 ipw_wakeup(sc); 303 break; 304 } 305 306 return 0; 307} 308 309void 310ipw_wakeup(struct ipw_softc *sc) 311{ 312 struct ifnet *ifp = &sc->sc_ic.ic_if; 313 pcireg_t data; 314 int s; 315 316 /* clear device specific PCI configuration register 0x41 */ 317 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 318 data &= ~0x0000ff00; 319 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 320 321 s = splnet(); 322 while (sc->sc_flags & IPW_FLAG_BUSY) 323 tsleep(&sc->sc_flags, PZERO, "ipwpwr", 0); 324 sc->sc_flags |= IPW_FLAG_BUSY; 325 326 if (ifp->if_flags & IFF_UP) 327 ipw_init(ifp); 328 329 sc->sc_flags &= ~IPW_FLAG_BUSY; 330 wakeup(&sc->sc_flags); 331 splx(s); 332} 333 334int 335ipw_dma_alloc(struct ipw_softc *sc) 336{ 337 struct ipw_soft_bd *sbd; 338 struct ipw_soft_hdr *shdr; 339 struct ipw_soft_buf *sbuf; 340 int i, nsegs, error; 341 342 /* 343 * Allocate and map tx ring. 344 */ 345 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 346 BUS_DMA_NOWAIT, &sc->tbd_map); 347 if (error != 0) { 348 printf("%s: could not create tx ring DMA map\n", 349 sc->sc_dev.dv_xname); 350 goto fail; 351 } 352 353 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 354 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 355 if (error != 0) { 356 printf("%s: could not allocate tx ring DMA memory\n", 357 sc->sc_dev.dv_xname); 358 goto fail; 359 } 360 361 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 362 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 363 if (error != 0) { 364 printf("%s: can't map tx ring DMA memory\n", 365 sc->sc_dev.dv_xname); 366 goto fail; 367 } 368 369 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 370 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 371 if (error != 0) { 372 printf("%s: could not load tx ring DMA map\n", 373 sc->sc_dev.dv_xname); 374 goto fail; 375 } 376 377 /* 378 * Allocate and map rx ring. 379 */ 380 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 381 BUS_DMA_NOWAIT, &sc->rbd_map); 382 if (error != 0) { 383 printf("%s: could not create rx ring DMA map\n", 384 sc->sc_dev.dv_xname); 385 goto fail; 386 } 387 388 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 389 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 390 if (error != 0) { 391 printf("%s: could not allocate rx ring DMA memory\n", 392 sc->sc_dev.dv_xname); 393 goto fail; 394 } 395 396 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 397 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 398 if (error != 0) { 399 printf("%s: can't map rx ring DMA memory\n", 400 sc->sc_dev.dv_xname); 401 goto fail; 402 } 403 404 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 405 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 406 if (error != 0) { 407 printf("%s: could not load tx ring DMA map\n", 408 sc->sc_dev.dv_xname); 409 goto fail; 410 } 411 412 /* 413 * Allocate and map status ring. 414 */ 415 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 416 0, BUS_DMA_NOWAIT, &sc->status_map); 417 if (error != 0) { 418 printf("%s: could not create status ring DMA map\n", 419 sc->sc_dev.dv_xname); 420 goto fail; 421 } 422 423 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 424 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 425 if (error != 0) { 426 printf("%s: could not allocate status ring DMA memory\n", 427 sc->sc_dev.dv_xname); 428 goto fail; 429 } 430 431 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 432 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 433 if (error != 0) { 434 printf("%s: can't map status ring DMA memory\n", 435 sc->sc_dev.dv_xname); 436 goto fail; 437 } 438 439 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 440 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 441 if (error != 0) { 442 printf("%s: could not load status ring DMA map\n", 443 sc->sc_dev.dv_xname); 444 goto fail; 445 } 446 447 /* 448 * Allocate command DMA map. 449 */ 450 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 451 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 452 if (error != 0) { 453 printf("%s: could not create command DMA map\n", 454 sc->sc_dev.dv_xname); 455 goto fail; 456 } 457 458 /* 459 * Allocate headers DMA maps. 460 */ 461 SLIST_INIT(&sc->free_shdr); 462 for (i = 0; i < IPW_NDATA; i++) { 463 shdr = &sc->shdr_list[i]; 464 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_hdr), 465 1, sizeof (struct ipw_hdr), 0, BUS_DMA_NOWAIT, &shdr->map); 466 if (error != 0) { 467 printf("%s: could not create header DMA map\n", 468 sc->sc_dev.dv_xname); 469 goto fail; 470 } 471 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 472 } 473 474 /* 475 * Allocate tx buffers DMA maps. 476 */ 477 SLIST_INIT(&sc->free_sbuf); 478 for (i = 0; i < IPW_NDATA; i++) { 479 sbuf = &sc->tx_sbuf_list[i]; 480 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, IPW_MAX_NSEG, 481 MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 482 if (error != 0) { 483 printf("%s: could not create tx DMA map\n", 484 sc->sc_dev.dv_xname); 485 goto fail; 486 } 487 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 488 } 489 490 /* 491 * Initialize tx ring. 492 */ 493 for (i = 0; i < IPW_NTBD; i++) { 494 sbd = &sc->stbd_list[i]; 495 sbd->bd = &sc->tbd_list[i]; 496 sbd->type = IPW_SBD_TYPE_NOASSOC; 497 } 498 499 /* 500 * Pre-allocate rx buffers and DMA maps. 501 */ 502 for (i = 0; i < IPW_NRBD; i++) { 503 sbd = &sc->srbd_list[i]; 504 sbuf = &sc->rx_sbuf_list[i]; 505 sbd->bd = &sc->rbd_list[i]; 506 507 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 508 if (sbuf->m == NULL) { 509 printf("%s: could not allocate rx mbuf\n", 510 sc->sc_dev.dv_xname); 511 error = ENOMEM; 512 goto fail; 513 } 514 MCLGET(sbuf->m, M_DONTWAIT); 515 if (!(sbuf->m->m_flags & M_EXT)) { 516 m_freem(sbuf->m); 517 printf("%s: could not allocate rx mbuf cluster\n", 518 sc->sc_dev.dv_xname); 519 error = ENOMEM; 520 goto fail; 521 } 522 523 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 524 0, BUS_DMA_NOWAIT, &sbuf->map); 525 if (error != 0) { 526 printf("%s: could not create rx DMA map\n", 527 sc->sc_dev.dv_xname); 528 goto fail; 529 } 530 531 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 532 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 533 if (error != 0) { 534 printf("%s: can't map rx DMA memory\n", 535 sc->sc_dev.dv_xname); 536 goto fail; 537 } 538 539 sbd->type = IPW_SBD_TYPE_DATA; 540 sbd->priv = sbuf; 541 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 542 sbd->bd->len = htole32(MCLBYTES); 543 } 544 545 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 546 BUS_DMASYNC_PREWRITE); 547 548 return 0; 549 550fail: ipw_release(sc); 551 return error; 552} 553 554void 555ipw_release(struct ipw_softc *sc) 556{ 557 struct ipw_soft_buf *sbuf; 558 int i; 559 560 if (sc->tbd_map != NULL) { 561 if (sc->tbd_list != NULL) { 562 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 563 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 564 IPW_TBD_SZ); 565 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 566 } 567 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 568 } 569 570 if (sc->rbd_map != NULL) { 571 if (sc->rbd_list != NULL) { 572 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 573 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 574 IPW_RBD_SZ); 575 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 576 } 577 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 578 } 579 580 if (sc->status_map != NULL) { 581 if (sc->status_list != NULL) { 582 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 583 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 584 IPW_RBD_SZ); 585 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 586 } 587 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 588 } 589 590 if (sc->cmd_map != NULL) 591 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 592 593 for (i = 0; i < IPW_NDATA; i++) 594 bus_dmamap_destroy(sc->sc_dmat, sc->shdr_list[i].map); 595 596 for (i = 0; i < IPW_NDATA; i++) 597 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 598 599 for (i = 0; i < IPW_NRBD; i++) { 600 sbuf = &sc->rx_sbuf_list[i]; 601 if (sbuf->map != NULL) { 602 if (sbuf->m != NULL) { 603 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 604 m_freem(sbuf->m); 605 } 606 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 607 } 608 } 609} 610 611int 612ipw_media_change(struct ifnet *ifp) 613{ 614 int error; 615 616 error = ieee80211_media_change(ifp); 617 if (error != ENETRESET) 618 return error; 619 620 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 621 ipw_init(ifp); 622 623 return 0; 624} 625 626void 627ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 628{ 629 struct ipw_softc *sc = ifp->if_softc; 630 struct ieee80211com *ic = &sc->sc_ic; 631 static const struct { 632 uint32_t val; 633 int rate; 634 } rates[] = { 635 { IPW_RATE_DS1, 2 }, 636 { IPW_RATE_DS2, 4 }, 637 { IPW_RATE_DS5, 11 }, 638 { IPW_RATE_DS11, 22 }, 639 }; 640 uint32_t val; 641 int rate, i; 642 643 imr->ifm_status = IFM_AVALID; 644 imr->ifm_active = IFM_IEEE80211; 645 if (ic->ic_state == IEEE80211_S_RUN) 646 imr->ifm_status |= IFM_ACTIVE; 647 648 /* read current transmission rate from adapter */ 649 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 650 val &= 0xf; 651 652 /* convert rate to 802.11 rate */ 653 for (i = 0; i < nitems(rates) && rates[i].val != val; i++); 654 rate = (i < nitems(rates)) ? rates[i].rate : 0; 655 656 imr->ifm_active |= IFM_IEEE80211_11B; 657 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 658 switch (ic->ic_opmode) { 659 case IEEE80211_M_STA: 660 break; 661#ifndef IEEE80211_STA_ONLY 662 case IEEE80211_M_IBSS: 663 imr->ifm_active |= IFM_IEEE80211_IBSS; 664 break; 665#endif 666 case IEEE80211_M_MONITOR: 667 imr->ifm_active |= IFM_IEEE80211_MONITOR; 668 break; 669 default: 670 /* should not get there */ 671 break; 672 } 673} 674 675int 676ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 677{ 678 struct ipw_softc *sc = ic->ic_softc; 679 int error; 680 681 switch (nstate) { 682 case IEEE80211_S_SCAN: 683 error = workq_add_task(NULL, 0, ipw_scan, sc, NULL); 684 if (error != 0) 685 return error; 686 break; 687 688 case IEEE80211_S_AUTH: 689 error = workq_add_task(NULL, 0, ipw_auth_and_assoc, sc, NULL); 690 if (error != 0) 691 return error; 692 break; 693 694 case IEEE80211_S_RUN: 695 case IEEE80211_S_INIT: 696 case IEEE80211_S_ASSOC: 697 /* nothing to do */ 698 break; 699 } 700 701 ic->ic_state = nstate; 702 return 0; 703} 704 705/* 706 * Read 16 bits at address 'addr' from the Microwire EEPROM. 707 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 708 */ 709uint16_t 710ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 711{ 712 uint32_t tmp; 713 uint16_t val; 714 int n; 715 716 /* clock C once before the first command */ 717 IPW_EEPROM_CTL(sc, 0); 718 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 719 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 720 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 721 722 /* write start bit (1) */ 723 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 724 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 725 726 /* write READ opcode (10) */ 727 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 728 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 729 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 730 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 731 732 /* write address A7-A0 */ 733 for (n = 7; n >= 0; n--) { 734 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 735 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 736 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 737 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 738 } 739 740 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 741 742 /* read data Q15-Q0 */ 743 val = 0; 744 for (n = 15; n >= 0; n--) { 745 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 746 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 747 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 748 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 749 } 750 751 IPW_EEPROM_CTL(sc, 0); 752 753 /* clear Chip Select and clock C */ 754 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 755 IPW_EEPROM_CTL(sc, 0); 756 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 757 758 return val; 759} 760 761void 762ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 763{ 764 struct ipw_cmd *cmd; 765 766 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 767 BUS_DMASYNC_POSTREAD); 768 769 cmd = mtod(sbuf->m, struct ipw_cmd *); 770 771 DPRINTFN(2, ("received command ack type=%u,status=%u\n", 772 letoh32(cmd->type), letoh32(cmd->status))); 773 774 wakeup(&sc->cmd); 775} 776 777void 778ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 779{ 780 struct ieee80211com *ic = &sc->sc_ic; 781 struct ifnet *ifp = &ic->ic_if; 782 uint32_t state; 783 784 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 785 BUS_DMASYNC_POSTREAD); 786 787 state = letoh32(*mtod(sbuf->m, uint32_t *)); 788 789 DPRINTFN(2, ("firmware state changed to 0x%x\n", state)); 790 791 switch (state) { 792 case IPW_STATE_ASSOCIATED: 793 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 794 break; 795 796 case IPW_STATE_SCANNING: 797 if (ic->ic_state == IEEE80211_S_RUN) 798 ieee80211_begin_scan(ifp); 799 break; 800 801 case IPW_STATE_SCAN_COMPLETE: 802 if (ic->ic_state == IEEE80211_S_SCAN) 803 ieee80211_end_scan(ifp); 804 break; 805 806 case IPW_STATE_ASSOCIATION_LOST: 807 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 808 break; 809 810 case IPW_STATE_DISABLED: 811 wakeup(sc); 812 break; 813 814 case IPW_STATE_RADIO_DISABLED: 815 ifp->if_flags &= ~IFF_UP; 816 ipw_stop(&ic->ic_if, 1); 817 break; 818 } 819} 820 821void 822ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 823 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 824{ 825 struct ieee80211com *ic = &sc->sc_ic; 826 struct ifnet *ifp = &ic->ic_if; 827 struct mbuf *mnew, *m; 828 struct ieee80211_frame *wh; 829 struct ieee80211_rxinfo rxi; 830 struct ieee80211_node *ni; 831 int error; 832 833 DPRINTFN(5, ("received data frame len=%u,rssi=%u\n", 834 letoh32(status->len), status->rssi)); 835 836 /* 837 * Try to allocate a new mbuf for this ring element and load it before 838 * processing the current mbuf. If the ring element cannot be loaded, 839 * drop the received packet and reuse the old mbuf. In the unlikely 840 * case that the old mbuf can't be reloaded either, explicitly panic. 841 */ 842 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 843 if (mnew == NULL) { 844 ifp->if_ierrors++; 845 return; 846 } 847 MCLGET(mnew, M_DONTWAIT); 848 if (!(mnew->m_flags & M_EXT)) { 849 m_freem(mnew); 850 ifp->if_ierrors++; 851 return; 852 } 853 854 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 855 BUS_DMASYNC_POSTREAD); 856 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 857 858 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(mnew, void *), 859 MCLBYTES, NULL, BUS_DMA_NOWAIT); 860 if (error != 0) { 861 m_freem(mnew); 862 863 /* try to reload the old mbuf */ 864 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 865 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 866 if (error != 0) { 867 /* very unlikely that it will fail... */ 868 panic("%s: could not load old rx mbuf", 869 sc->sc_dev.dv_xname); 870 } 871 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 872 ifp->if_ierrors++; 873 return; 874 } 875 876 m = sbuf->m; 877 sbuf->m = mnew; 878 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 879 880 /* finalize mbuf */ 881 m->m_pkthdr.rcvif = ifp; 882 m->m_pkthdr.len = m->m_len = letoh32(status->len); 883 884#if NBPFILTER > 0 885 if (sc->sc_drvbpf != NULL) { 886 struct mbuf mb; 887 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 888 889 tap->wr_flags = 0; 890 tap->wr_antsignal = status->rssi; 891 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 892 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 893 894 mb.m_data = (caddr_t)tap; 895 mb.m_len = sc->sc_rxtap_len; 896 mb.m_next = m; 897 mb.m_nextpkt = NULL; 898 mb.m_type = 0; 899 mb.m_flags = 0; 900 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 901 } 902#endif 903 904 wh = mtod(m, struct ieee80211_frame *); 905 ni = ieee80211_find_rxnode(ic, wh); 906 907 /* send the frame to the upper layer */ 908 rxi.rxi_flags = 0; 909 rxi.rxi_rssi = status->rssi; 910 rxi.rxi_tstamp = 0; /* unused */ 911 ieee80211_input(ifp, m, ni, &rxi); 912 913 ieee80211_release_node(ic, ni); 914} 915 916void 917ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 918{ 919 DPRINTFN(2, ("received notification\n")); 920} 921 922void 923ipw_rx_intr(struct ipw_softc *sc) 924{ 925 struct ipw_status *status; 926 struct ipw_soft_bd *sbd; 927 struct ipw_soft_buf *sbuf; 928 uint32_t r, i; 929 930 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 931 932 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 933 934 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 935 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 936 BUS_DMASYNC_POSTREAD); 937 938 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 939 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 940 BUS_DMASYNC_POSTREAD); 941 942 status = &sc->status_list[i]; 943 sbd = &sc->srbd_list[i]; 944 sbuf = sbd->priv; 945 946 switch (letoh16(status->code) & 0xf) { 947 case IPW_STATUS_CODE_COMMAND: 948 ipw_command_intr(sc, sbuf); 949 break; 950 951 case IPW_STATUS_CODE_NEWSTATE: 952 ipw_newstate_intr(sc, sbuf); 953 break; 954 955 case IPW_STATUS_CODE_DATA_802_3: 956 case IPW_STATUS_CODE_DATA_802_11: 957 ipw_data_intr(sc, status, sbd, sbuf); 958 break; 959 960 case IPW_STATUS_CODE_NOTIFICATION: 961 ipw_notification_intr(sc, sbuf); 962 break; 963 964 default: 965 printf("%s: unknown status code %u\n", 966 sc->sc_dev.dv_xname, letoh16(status->code)); 967 } 968 sbd->bd->flags = 0; 969 970 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 971 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 972 BUS_DMASYNC_PREWRITE); 973 } 974 975 /* tell the firmware what we have processed */ 976 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 977 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 978} 979 980void 981ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 982{ 983 struct ieee80211com *ic = &sc->sc_ic; 984 struct ipw_soft_hdr *shdr; 985 struct ipw_soft_buf *sbuf; 986 987 switch (sbd->type) { 988 case IPW_SBD_TYPE_COMMAND: 989 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 990 break; 991 992 case IPW_SBD_TYPE_HEADER: 993 shdr = sbd->priv; 994 bus_dmamap_unload(sc->sc_dmat, shdr->map); 995 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 996 break; 997 998 case IPW_SBD_TYPE_DATA: 999 sbuf = sbd->priv; 1000 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1001 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1002 1003 m_freem(sbuf->m); 1004 1005 if (sbuf->ni != NULL) 1006 ieee80211_release_node(ic, sbuf->ni); 1007 1008 /* kill watchdog timer */ 1009 sc->sc_tx_timer = 0; 1010 break; 1011 } 1012 sbd->type = IPW_SBD_TYPE_NOASSOC; 1013} 1014 1015void 1016ipw_tx_intr(struct ipw_softc *sc) 1017{ 1018 struct ifnet *ifp = &sc->sc_ic.ic_if; 1019 struct ipw_soft_bd *sbd; 1020 uint32_t r, i; 1021 1022 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 1023 1024 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1025 sbd = &sc->stbd_list[i]; 1026 1027 if (sbd->type == IPW_SBD_TYPE_DATA) 1028 ifp->if_opackets++; 1029 1030 ipw_release_sbd(sc, sbd); 1031 sc->txfree++; 1032 } 1033 1034 /* remember what the firmware has processed */ 1035 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1036 1037 /* call start() since some buffer descriptors have been released */ 1038 ifp->if_flags &= ~IFF_OACTIVE; 1039 (*ifp->if_start)(ifp); 1040} 1041 1042int 1043ipw_intr(void *arg) 1044{ 1045 struct ipw_softc *sc = arg; 1046 struct ifnet *ifp = &sc->sc_ic.ic_if; 1047 uint32_t r; 1048 1049 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) 1050 return 0; 1051 1052 /* disable interrupts */ 1053 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1054 1055 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1056 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 1057 ifp->if_flags &= ~IFF_UP; 1058 ipw_stop(ifp, 1); 1059 return 1; 1060 } 1061 1062 if (r & IPW_INTR_FW_INIT_DONE) 1063 wakeup(sc); 1064 1065 if (r & IPW_INTR_RX_TRANSFER) 1066 ipw_rx_intr(sc); 1067 1068 if (r & IPW_INTR_TX_TRANSFER) 1069 ipw_tx_intr(sc); 1070 1071 /* acknowledge interrupts */ 1072 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1073 1074 /* re-enable interrupts */ 1075 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1076 1077 return 1; 1078} 1079 1080int 1081ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1082{ 1083 struct ipw_soft_bd *sbd; 1084 int s, error; 1085 1086 s = splnet(); 1087 1088 sc->cmd.type = htole32(type); 1089 sc->cmd.subtype = htole32(0); 1090 sc->cmd.len = htole32(len); 1091 sc->cmd.seq = htole32(0); 1092 if (data != NULL) 1093 bcopy(data, sc->cmd.data, len); 1094 1095 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 1096 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 1097 if (error != 0) { 1098 printf("%s: can't map command DMA memory\n", 1099 sc->sc_dev.dv_xname); 1100 splx(s); 1101 return error; 1102 } 1103 1104 sbd = &sc->stbd_list[sc->txcur]; 1105 sbd->type = IPW_SBD_TYPE_COMMAND; 1106 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1107 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1108 sbd->bd->nfrag = 1; 1109 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1110 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1111 1112 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1113 BUS_DMASYNC_PREWRITE); 1114 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1115 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1116 BUS_DMASYNC_PREWRITE); 1117 1118 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1119 sc->txfree--; 1120 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1121 1122 DPRINTFN(2, ("sending command type=%u,len=%u\n", type, len)); 1123 1124 /* wait at most one second for command to complete */ 1125 error = tsleep(&sc->cmd, 0, "ipwcmd", hz); 1126 splx(s); 1127 1128 return error; 1129} 1130 1131/* ARGSUSED */ 1132int 1133ipw_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type, 1134 int arg1, int arg2) 1135{ 1136 return EOPNOTSUPP; 1137} 1138 1139int 1140ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 1141{ 1142 struct ipw_softc *sc = ifp->if_softc; 1143 struct ieee80211com *ic = &sc->sc_ic; 1144 struct ieee80211_frame *wh; 1145 struct ieee80211_key *k; 1146 struct mbuf *m1; 1147 struct ipw_soft_bd *sbd; 1148 struct ipw_soft_hdr *shdr; 1149 struct ipw_soft_buf *sbuf; 1150 int error, i; 1151 1152 wh = mtod(m, struct ieee80211_frame *); 1153 1154 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1155 k = ieee80211_get_txkey(ic, wh, ni); 1156 1157 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1158 return ENOBUFS; 1159 1160 /* packet header may have moved, reset our local pointer */ 1161 wh = mtod(m, struct ieee80211_frame *); 1162 } 1163 1164#if NBPFILTER > 0 1165 if (sc->sc_drvbpf != NULL) { 1166 struct mbuf mb; 1167 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1168 1169 tap->wt_flags = 0; 1170 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1171 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1172 1173 mb.m_data = (caddr_t)tap; 1174 mb.m_len = sc->sc_txtap_len; 1175 mb.m_next = m; 1176 mb.m_nextpkt = NULL; 1177 mb.m_type = 0; 1178 mb.m_flags = 0; 1179 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1180 } 1181#endif 1182 1183 shdr = SLIST_FIRST(&sc->free_shdr); 1184 sbuf = SLIST_FIRST(&sc->free_sbuf); 1185 1186 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1187 shdr->hdr.subtype = htole32(0); 1188 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) ? 1 : 0; 1189 shdr->hdr.encrypt = 0; 1190 shdr->hdr.keyidx = 0; 1191 shdr->hdr.keysz = 0; 1192 shdr->hdr.fragmentsz = htole16(0); 1193 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1194 if (ic->ic_opmode == IEEE80211_M_STA) 1195 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1196 else 1197 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1198 1199 /* trim IEEE802.11 header */ 1200 m_adj(m, sizeof (struct ieee80211_frame)); 1201 1202 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 1203 if (error != 0 && error != EFBIG) { 1204 printf("%s: can't map mbuf (error %d)\n", 1205 sc->sc_dev.dv_xname, error); 1206 m_freem(m); 1207 return error; 1208 } 1209 if (error != 0) { 1210 /* too many fragments, linearize */ 1211 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1212 if (m1 == NULL) { 1213 m_freem(m); 1214 return ENOBUFS; 1215 } 1216 if (m->m_pkthdr.len > MHLEN) { 1217 MCLGET(m1, M_DONTWAIT); 1218 if (!(m1->m_flags & M_EXT)) { 1219 m_freem(m); 1220 m_freem(m1); 1221 return ENOBUFS; 1222 } 1223 } 1224 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, caddr_t)); 1225 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 1226 m_freem(m); 1227 m = m1; 1228 1229 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, 1230 BUS_DMA_NOWAIT); 1231 if (error != 0) { 1232 printf("%s: can't map mbuf (error %d)\n", 1233 sc->sc_dev.dv_xname, error); 1234 m_freem(m); 1235 return error; 1236 } 1237 } 1238 1239 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 1240 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 1241 if (error != 0) { 1242 printf("%s: can't map header DMA memory (error %d)\n", 1243 sc->sc_dev.dv_xname, error); 1244 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1245 m_freem(m); 1246 return error; 1247 } 1248 1249 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1250 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1251 1252 sbd = &sc->stbd_list[sc->txcur]; 1253 sbd->type = IPW_SBD_TYPE_HEADER; 1254 sbd->priv = shdr; 1255 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 1256 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1257 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1258 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1259 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1260 1261 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1262 sc->txcur * sizeof (struct ipw_bd), 1263 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1264 1265 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1266 sc->txfree--; 1267 1268 sbuf->m = m; 1269 sbuf->ni = ni; 1270 1271 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1272 sbd = &sc->stbd_list[sc->txcur]; 1273 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1274 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1275 sbd->bd->nfrag = 0; /* used only in first bd */ 1276 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1277 if (i == sbuf->map->dm_nsegs - 1) { 1278 sbd->type = IPW_SBD_TYPE_DATA; 1279 sbd->priv = sbuf; 1280 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1281 } else { 1282 sbd->type = IPW_SBD_TYPE_NOASSOC; 1283 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1284 } 1285 1286 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1287 sc->txcur * sizeof (struct ipw_bd), 1288 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1289 1290 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1291 sc->txfree--; 1292 } 1293 1294 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1295 BUS_DMASYNC_PREWRITE); 1296 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 1297 BUS_DMASYNC_PREWRITE); 1298 1299 /* inform firmware about this new packet */ 1300 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1301 1302 return 0; 1303} 1304 1305void 1306ipw_start(struct ifnet *ifp) 1307{ 1308 struct ipw_softc *sc = ifp->if_softc; 1309 struct ieee80211com *ic = &sc->sc_ic; 1310 struct ieee80211_node *ni; 1311 struct mbuf *m; 1312 1313 if (ic->ic_state != IEEE80211_S_RUN) 1314 return; 1315 1316 for (;;) { 1317 IFQ_POLL(&ifp->if_snd, m); 1318 if (m == NULL) 1319 break; 1320 1321 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1322 ifp->if_flags |= IFF_OACTIVE; 1323 break; 1324 } 1325 IFQ_DEQUEUE(&ifp->if_snd, m); 1326#if NBPFILTER > 0 1327 if (ifp->if_bpf != NULL) 1328 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1329#endif 1330 m = ieee80211_encap(ifp, m, &ni); 1331 if (m == NULL) 1332 continue; 1333#if NBPFILTER > 0 1334 if (ic->ic_rawbpf != NULL) 1335 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1336#endif 1337 if (ipw_tx_start(ifp, m, ni) != 0) { 1338 if (ni != NULL) 1339 ieee80211_release_node(ic, ni); 1340 ifp->if_oerrors++; 1341 break; 1342 } 1343 1344 /* start watchdog timer */ 1345 sc->sc_tx_timer = 5; 1346 ifp->if_timer = 1; 1347 } 1348} 1349 1350void 1351ipw_watchdog(struct ifnet *ifp) 1352{ 1353 struct ipw_softc *sc = ifp->if_softc; 1354 1355 ifp->if_timer = 0; 1356 1357 if (sc->sc_tx_timer > 0) { 1358 if (--sc->sc_tx_timer == 0) { 1359 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1360 ifp->if_flags &= ~IFF_UP; 1361 ipw_stop(ifp, 1); 1362 ifp->if_oerrors++; 1363 return; 1364 } 1365 ifp->if_timer = 1; 1366 } 1367 1368 ieee80211_watchdog(ifp); 1369} 1370 1371int 1372ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1373{ 1374 struct ipw_softc *sc = ifp->if_softc; 1375 struct ieee80211com *ic = &sc->sc_ic; 1376 struct ifaddr *ifa; 1377 struct ifreq *ifr; 1378 int s, error = 0; 1379 1380 s = splnet(); 1381 /* 1382 * Prevent processes from entering this function while another 1383 * process is tsleep'ing in it. 1384 */ 1385 while ((sc->sc_flags & IPW_FLAG_BUSY) && error == 0) 1386 error = tsleep(&sc->sc_flags, PCATCH, "ipwioc", 0); 1387 if (error != 0) { 1388 splx(s); 1389 return error; 1390 } 1391 sc->sc_flags |= IPW_FLAG_BUSY; 1392 1393 switch (cmd) { 1394 case SIOCSIFADDR: 1395 ifa = (struct ifaddr *)data; 1396 ifp->if_flags |= IFF_UP; 1397#ifdef INET 1398 if (ifa->ifa_addr->sa_family == AF_INET) 1399 arp_ifinit(&ic->ic_ac, ifa); 1400#endif 1401 /* FALLTHROUGH */ 1402 case SIOCSIFFLAGS: 1403 if (ifp->if_flags & IFF_UP) { 1404 if (!(ifp->if_flags & IFF_RUNNING)) 1405 ipw_init(ifp); 1406 } else { 1407 if (ifp->if_flags & IFF_RUNNING) 1408 ipw_stop(ifp, 1); 1409 } 1410 break; 1411 1412 case SIOCADDMULTI: 1413 case SIOCDELMULTI: 1414 ifr = (struct ifreq *)data; 1415 error = (cmd == SIOCADDMULTI) ? 1416 ether_addmulti(ifr, &ic->ic_ac) : 1417 ether_delmulti(ifr, &ic->ic_ac); 1418 1419 if (error == ENETRESET) 1420 error = 0; 1421 break; 1422 1423 case SIOCG80211TXPOWER: 1424 /* 1425 * If the hardware radio transmitter switch is off, report a 1426 * tx power of IEEE80211_TXPOWER_MIN to indicate that radio 1427 * transmitter is killed. 1428 */ 1429 ((struct ieee80211_txpower *)data)->i_val = 1430 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 1431 IEEE80211_TXPOWER_MIN : sc->sc_ic.ic_txpower; 1432 break; 1433 1434 default: 1435 error = ieee80211_ioctl(ifp, cmd, data); 1436 } 1437 1438 if (error == ENETRESET) { 1439 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1440 (IFF_UP | IFF_RUNNING)) 1441 ipw_init(ifp); 1442 error = 0; 1443 } 1444 1445 sc->sc_flags &= ~IPW_FLAG_BUSY; 1446 wakeup(&sc->sc_flags); 1447 splx(s); 1448 return error; 1449} 1450 1451uint32_t 1452ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1453{ 1454 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1455} 1456 1457void 1458ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1459{ 1460 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1461} 1462 1463int 1464ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1465{ 1466 uint32_t addr, info; 1467 uint16_t count, size; 1468 uint32_t total; 1469 1470 /* addr[4] + count[2] + size[2] */ 1471 addr = MEM_READ_4(sc, sc->table2_base + off); 1472 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1473 1474 count = info >> 16; 1475 size = info & 0xffff; 1476 total = count * size; 1477 1478 if (total > *len) { 1479 *len = total; 1480 return EINVAL; 1481 } 1482 *len = total; 1483 ipw_read_mem_1(sc, addr, buf, total); 1484 1485 return 0; 1486} 1487 1488void 1489ipw_stop_master(struct ipw_softc *sc) 1490{ 1491 uint32_t tmp; 1492 int ntries; 1493 1494 /* disable interrupts */ 1495 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1496 1497 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1498 for (ntries = 0; ntries < 50; ntries++) { 1499 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1500 break; 1501 DELAY(10); 1502 } 1503 if (ntries == 50) 1504 printf("%s: timeout waiting for master\n", 1505 sc->sc_dev.dv_xname); 1506 1507 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1508 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1509 1510 sc->sc_flags &= ~IPW_FLAG_FW_INITED; 1511} 1512 1513int 1514ipw_reset(struct ipw_softc *sc) 1515{ 1516 uint32_t tmp; 1517 int ntries; 1518 1519 ipw_stop_master(sc); 1520 1521 /* move adapter to D0 state */ 1522 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1523 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1524 1525 /* wait for clock stabilization */ 1526 for (ntries = 0; ntries < 1000; ntries++) { 1527 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1528 break; 1529 DELAY(200); 1530 } 1531 if (ntries == 1000) 1532 return EIO; 1533 1534 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1535 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1536 1537 DELAY(10); 1538 1539 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1540 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1541 1542 return 0; 1543} 1544 1545int 1546ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1547{ 1548 int ntries; 1549 1550 /* voodoo from the Intel Linux driver */ 1551 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1552 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1553 1554 MEM_WRITE_2(sc, 0x220000, 0x0703); 1555 MEM_WRITE_2(sc, 0x220000, 0x0707); 1556 1557 MEM_WRITE_1(sc, 0x210014, 0x72); 1558 MEM_WRITE_1(sc, 0x210014, 0x72); 1559 1560 MEM_WRITE_1(sc, 0x210000, 0x40); 1561 MEM_WRITE_1(sc, 0x210000, 0x00); 1562 MEM_WRITE_1(sc, 0x210000, 0x40); 1563 1564 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1565 1566 MEM_WRITE_1(sc, 0x210000, 0x00); 1567 MEM_WRITE_1(sc, 0x210000, 0x00); 1568 MEM_WRITE_1(sc, 0x210000, 0x80); 1569 1570 MEM_WRITE_2(sc, 0x220000, 0x0703); 1571 MEM_WRITE_2(sc, 0x220000, 0x0707); 1572 1573 MEM_WRITE_1(sc, 0x210014, 0x72); 1574 MEM_WRITE_1(sc, 0x210014, 0x72); 1575 1576 MEM_WRITE_1(sc, 0x210000, 0x00); 1577 MEM_WRITE_1(sc, 0x210000, 0x80); 1578 1579 for (ntries = 0; ntries < 100; ntries++) { 1580 if (MEM_READ_1(sc, 0x210000) & 1) 1581 break; 1582 DELAY(1000); 1583 } 1584 if (ntries == 100) { 1585 printf("%s: timeout waiting for ucode to initialize\n", 1586 sc->sc_dev.dv_xname); 1587 return EIO; 1588 } 1589 1590 MEM_WRITE_4(sc, 0x3000e0, 0); 1591 1592 return 0; 1593} 1594 1595/* set of macros to handle unaligned little endian data in firmware image */ 1596#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1597#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1598int 1599ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1600{ 1601 u_char *p, *end; 1602 uint32_t tmp, dst; 1603 uint16_t len; 1604 int error; 1605 1606 p = fw; 1607 end = fw + size; 1608 while (p < end) { 1609 if (p + 6 > end) 1610 return EINVAL; 1611 1612 dst = GETLE32(p); p += 4; 1613 len = GETLE16(p); p += 2; 1614 1615 if (p + len > end) 1616 return EINVAL; 1617 1618 ipw_write_mem_1(sc, dst, p, len); 1619 p += len; 1620 } 1621 1622 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1623 IPW_IO_LED_OFF); 1624 1625 /* allow interrupts so we know when the firmware is inited */ 1626 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1627 1628 /* tell the adapter to initialize the firmware */ 1629 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1630 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1631 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1632 1633 /* wait at most one second for firmware initialization to complete */ 1634 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1635 printf("%s: timeout waiting for firmware initialization to " 1636 "complete\n", sc->sc_dev.dv_xname); 1637 return error; 1638 } 1639 1640 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1641 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1642 IPW_IO_GPIO3_MASK); 1643 1644 return 0; 1645} 1646 1647int 1648ipw_read_firmware(struct ipw_softc *sc, struct ipw_firmware *fw) 1649{ 1650 const struct ipw_firmware_hdr *hdr; 1651 const char *name; 1652 size_t size; 1653 int error; 1654 1655 switch (sc->sc_ic.ic_opmode) { 1656 case IEEE80211_M_STA: 1657 name = "ipw-bss"; 1658 break; 1659#ifndef IEEE80211_STA_ONLY 1660 case IEEE80211_M_IBSS: 1661 name = "ipw-ibss"; 1662 break; 1663#endif 1664 case IEEE80211_M_MONITOR: 1665 name = "ipw-monitor"; 1666 break; 1667 default: 1668 /* should not get there */ 1669 return ENODEV; 1670 } 1671 if ((error = loadfirmware(name, &fw->data, &size)) != 0) 1672 return error; 1673 1674 if (size < sizeof (*hdr)) { 1675 error = EINVAL; 1676 goto fail; 1677 } 1678 hdr = (const struct ipw_firmware_hdr *)fw->data; 1679 fw->main_size = letoh32(hdr->main_size); 1680 fw->ucode_size = letoh32(hdr->ucode_size); 1681 1682 if (size < sizeof (*hdr) + fw->main_size + fw->ucode_size) { 1683 error = EINVAL; 1684 goto fail; 1685 } 1686 fw->main = fw->data + sizeof (*hdr); 1687 fw->ucode = fw->main + fw->main_size; 1688 1689 return 0; 1690 1691fail: free(fw->data, M_DEVBUF, 0); 1692 return error; 1693} 1694 1695void 1696ipw_scan(void *arg1, void *arg2) 1697{ 1698 struct ipw_softc *sc = arg1; 1699 struct ifnet *ifp = &sc->sc_ic.ic_if; 1700 struct ipw_scan_options scan; 1701 uint8_t ssid[IEEE80211_NWID_LEN]; 1702 int error; 1703 1704 /* 1705 * Firmware has a bug and does not honour the ``do not associate 1706 * after scan'' bit in the scan command. To prevent the firmware 1707 * from associating after the scan, we set the ESSID to something 1708 * unlikely to be used by a real AP. 1709 * XXX would setting the desired BSSID to a multicast address work? 1710 */ 1711 memset(ssid, '\r', sizeof ssid); 1712 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ssid, sizeof ssid); 1713 if (error != 0) 1714 goto fail; 1715 1716 /* no mandatory BSSID */ 1717 DPRINTF(("Setting mandatory BSSID to null\n")); 1718 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1719 if (error != 0) 1720 goto fail; 1721 1722 scan.flags = htole32(IPW_SCAN_DO_NOT_ASSOCIATE | IPW_SCAN_MIXED_CELL); 1723 scan.channels = htole32(0x3fff); /* scan channels 1-14 */ 1724 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1725 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1726 if (error != 0) 1727 goto fail; 1728 1729 /* start scanning */ 1730 DPRINTF(("Enabling adapter\n")); 1731 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1732 if (error != 0) 1733 goto fail; 1734 1735 return; 1736fail: 1737 printf("%s: scan request failed (error=%d)\n", sc->sc_dev.dv_xname, 1738 error); 1739 ieee80211_end_scan(ifp); 1740} 1741 1742void 1743ipw_auth_and_assoc(void *arg1, void *arg2) 1744{ 1745 struct ipw_softc *sc = arg1; 1746 struct ieee80211com *ic = &sc->sc_ic; 1747 struct ieee80211_node *ni = ic->ic_bss; 1748 struct ipw_scan_options scan; 1749 struct ipw_security security; 1750 struct ipw_assoc_req assoc; 1751 uint32_t data; 1752 uint8_t chan; 1753 int s, error; 1754 1755 DPRINTF(("Disabling adapter\n")); 1756 error = ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1757 if (error != 0) 1758 goto fail; 1759#if 1 1760 /* wait at most one second for card to be disabled */ 1761 s = splnet(); 1762 error = tsleep(sc, 0, "ipwdis", hz); 1763 splx(s); 1764 if (error != 0) { 1765 printf("%s: timeout waiting for disabled state\n", 1766 sc->sc_dev.dv_xname); 1767 goto fail; 1768 } 1769#else 1770 /* Intel's Linux driver polls for the DISABLED state instead.. */ 1771 for (ntries = 0; ntries < 1000; ntries++) { 1772 if (ipw_read_table1(sc, IPW_INFO_CARD_DISABLED) == 1) 1773 break; 1774 DELAY(10); 1775 } 1776 if (ntries == 1000) { 1777 printf("%s: timeout waiting for disabled state\n", 1778 sc->sc_dev.dv_xname); 1779 goto fail; 1780 } 1781#endif 1782 1783 bzero(&security, sizeof security); 1784 security.authmode = IPW_AUTH_OPEN; 1785 security.ciphers = htole32(IPW_CIPHER_NONE); 1786 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1787 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1788 sizeof security); 1789 if (error != 0) 1790 goto fail; 1791 1792#ifdef IPW_DEBUG 1793 if (ipw_debug > 0) { 1794 printf("Setting ESSID to "); 1795 ieee80211_print_essid(ni->ni_essid, ni->ni_esslen); 1796 printf("\n"); 1797 } 1798#endif 1799 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ni->ni_essid, ni->ni_esslen); 1800 if (error != 0) 1801 goto fail; 1802 1803 DPRINTF(("Setting BSSID to %s\n", ether_sprintf(ni->ni_bssid))); 1804 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, ni->ni_bssid, 1805 IEEE80211_ADDR_LEN); 1806 if (error != 0) 1807 goto fail; 1808 1809 data = htole32((ic->ic_flags & (IEEE80211_F_WEPON | 1810 IEEE80211_F_RSNON)) ? IPW_PRIVACYON : 0); 1811 DPRINTF(("Setting privacy flags to 0x%x\n", letoh32(data))); 1812 error = ipw_cmd(sc, IPW_CMD_SET_PRIVACY_FLAGS, &data, sizeof data); 1813 if (error != 0) 1814 goto fail; 1815 1816 /* let firmware set the capinfo, lintval, and bssid fixed fields */ 1817 bzero(&assoc, sizeof assoc); 1818 if (ic->ic_flags & IEEE80211_F_RSNON) { 1819 uint8_t *frm = assoc.optie; 1820 1821 /* tell firmware to add a WPA or RSN IE in (Re)Assoc req */ 1822 if (ni->ni_rsnprotos & IEEE80211_PROTO_RSN) 1823 frm = ieee80211_add_rsn(frm, ic, ni); 1824 else if (ni->ni_rsnprotos & IEEE80211_PROTO_WPA) 1825 frm = ieee80211_add_wpa(frm, ic, ni); 1826 assoc.optie_len = htole32(frm - assoc.optie); 1827 } 1828 DPRINTF(("Preparing assocation request (optional IE length=%d)\n", 1829 letoh32(assoc.optie_len))); 1830 error = ipw_cmd(sc, IPW_CMD_SET_ASSOC_REQ, &assoc, sizeof assoc); 1831 if (error != 0) 1832 goto fail; 1833 1834 scan.flags = htole32(IPW_SCAN_MIXED_CELL); 1835 chan = ieee80211_chan2ieee(ic, ni->ni_chan); 1836 scan.channels = htole32(1 << (chan - 1)); 1837 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1838 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1839 if (error != 0) 1840 goto fail; 1841 1842 /* trigger scan+association */ 1843 DPRINTF(("Enabling adapter\n")); 1844 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1845 if (error != 0) 1846 goto fail; 1847 1848 return; 1849fail: 1850 printf("%s: association failed (error=%d)\n", sc->sc_dev.dv_xname, 1851 error); 1852 ieee80211_begin_scan(&ic->ic_if); 1853} 1854 1855int 1856ipw_config(struct ipw_softc *sc) 1857{ 1858 struct ieee80211com *ic = &sc->sc_ic; 1859 struct ifnet *ifp = &ic->ic_if; 1860 struct ipw_configuration config; 1861 uint32_t data; 1862 int error; 1863 1864 switch (ic->ic_opmode) { 1865 case IEEE80211_M_STA: 1866 data = htole32(IPW_MODE_BSS); 1867 break; 1868#ifndef IEEE80211_STA_ONLY 1869 case IEEE80211_M_IBSS: 1870 data = htole32(IPW_MODE_IBSS); 1871 break; 1872#endif 1873 case IEEE80211_M_MONITOR: 1874 data = htole32(IPW_MODE_MONITOR); 1875 break; 1876 default: 1877 /* should not get there */ 1878 return ENODEV; 1879 } 1880 DPRINTF(("Setting mode to %u\n", letoh32(data))); 1881 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1882 if (error != 0) 1883 return error; 1884 1885 if ( 1886#ifndef IEEE80211_STA_ONLY 1887 ic->ic_opmode == IEEE80211_M_IBSS || 1888#endif 1889 ic->ic_opmode == IEEE80211_M_MONITOR) { 1890 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1891 DPRINTF(("Setting channel to %u\n", letoh32(data))); 1892 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1893 if (error != 0) 1894 return error; 1895 } 1896 1897 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1898 DPRINTF(("Enabling adapter\n")); 1899 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1900 } 1901 1902 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 1903 DPRINTF(("Setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 1904 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1905 IEEE80211_ADDR_LEN); 1906 if (error != 0) 1907 return error; 1908 1909 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1910 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1X_ENABLE); 1911#ifndef IEEE80211_STA_ONLY 1912 if (ic->ic_opmode == IEEE80211_M_IBSS) 1913 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1914#endif 1915 if (ifp->if_flags & IFF_PROMISC) 1916 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1917 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1918 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1919 DPRINTF(("Setting configuration 0x%x\n", config.flags)); 1920 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1921 if (error != 0) 1922 return error; 1923 1924 data = htole32(ic->ic_rtsthreshold); 1925 DPRINTF(("Setting RTS threshold to %u\n", letoh32(data))); 1926 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1927 if (error != 0) 1928 return error; 1929 1930 data = htole32(ic->ic_fragthreshold); 1931 DPRINTF(("Setting frag threshold to %u\n", letoh32(data))); 1932 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1933 if (error != 0) 1934 return error; 1935 1936 data = htole32(0x3); /* 1, 2 */ 1937 DPRINTF(("Setting basic tx rates to 0x%x\n", letoh32(data))); 1938 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1939 if (error != 0) 1940 return error; 1941 1942 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1943 DPRINTF(("Setting tx rates to 0x%x\n", letoh32(data))); 1944 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1945 if (error != 0) 1946 return error; 1947 1948 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1949 DPRINTF(("Setting MSDU tx rates to 0x%x\n", letoh32(data))); 1950 error = ipw_cmd(sc, IPW_CMD_SET_MSDU_TX_RATES, &data, sizeof data); 1951 if (error != 0) 1952 return error; 1953 1954 data = htole32(IPW_POWER_MODE_CAM); 1955 DPRINTF(("Setting power mode to %u\n", letoh32(data))); 1956 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1957 if (error != 0) 1958 return error; 1959 1960#ifndef IEEE80211_STA_ONLY 1961 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1962 data = htole32(32); /* default value */ 1963 DPRINTF(("Setting tx power index to %u\n", letoh32(data))); 1964 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1965 sizeof data); 1966 if (error != 0) 1967 return error; 1968 1969 data = htole32(ic->ic_lintval); 1970 DPRINTF(("Setting beacon interval to %u\n", letoh32(data))); 1971 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1972 sizeof data); 1973 if (error != 0) 1974 return error; 1975 } 1976#endif 1977 return 0; 1978} 1979 1980int 1981ipw_init(struct ifnet *ifp) 1982{ 1983 struct ipw_softc *sc = ifp->if_softc; 1984 struct ieee80211com *ic = &sc->sc_ic; 1985 struct ipw_firmware fw; 1986 int error; 1987 1988 ipw_stop(ifp, 0); 1989 1990 if ((error = ipw_reset(sc)) != 0) { 1991 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 1992 goto fail1; 1993 } 1994 1995 if ((error = ipw_read_firmware(sc, &fw)) != 0) { 1996 printf("%s: error %d, could not read firmware\n", 1997 sc->sc_dev.dv_xname, error); 1998 goto fail1; 1999 } 2000 if ((error = ipw_load_ucode(sc, fw.ucode, fw.ucode_size)) != 0) { 2001 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 2002 goto fail2; 2003 } 2004 2005 ipw_stop_master(sc); 2006 2007 /* 2008 * Setup tx, rx and status rings. 2009 */ 2010 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2011 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 2012 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 2013 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 2014 sc->txold = IPW_NTBD - 1; /* latest bd index ack by firmware */ 2015 sc->txcur = 0; /* bd index to write to */ 2016 sc->txfree = IPW_NTBD - 2; 2017 2018 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2019 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 2020 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 2021 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 2022 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 2023 2024 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 2025 sc->status_map->dm_segs[0].ds_addr); 2026 2027 if ((error = ipw_load_firmware(sc, fw.main, fw.main_size)) != 0) { 2028 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 2029 goto fail2; 2030 } 2031 sc->sc_flags |= IPW_FLAG_FW_INITED; 2032 free(fw.data, M_DEVBUF, 0); 2033 fw.data = NULL; 2034 2035 /* retrieve information tables base addresses */ 2036 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2037 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2038 2039 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2040 2041 if ((error = ipw_config(sc)) != 0) { 2042 printf("%s: device configuration failed\n", 2043 sc->sc_dev.dv_xname); 2044 goto fail1; 2045 } 2046 2047 ifp->if_flags &= ~IFF_OACTIVE; 2048 ifp->if_flags |= IFF_RUNNING; 2049 2050 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2051 ieee80211_begin_scan(ifp); 2052 else 2053 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2054 2055 return 0; 2056 2057fail2: free(fw.data, M_DEVBUF, 0); 2058 fw.data = NULL; 2059fail1: ipw_stop(ifp, 0); 2060 return error; 2061} 2062 2063void 2064ipw_stop(struct ifnet *ifp, int disable) 2065{ 2066 struct ipw_softc *sc = ifp->if_softc; 2067 struct ieee80211com *ic = &sc->sc_ic; 2068 int i; 2069 2070 ipw_stop_master(sc); 2071 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2072 2073 ifp->if_timer = 0; 2074 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2075 2076 /* 2077 * Release tx buffers. 2078 */ 2079 for (i = 0; i < IPW_NTBD; i++) 2080 ipw_release_sbd(sc, &sc->stbd_list[i]); 2081 2082 /* in case we were scanning, release the scan "lock" */ 2083 ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; 2084 2085 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2086} 2087 2088void 2089ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2090 bus_size_t count) 2091{ 2092 for (; count > 0; offset++, datap++, count--) { 2093 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2094 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2095 } 2096} 2097 2098void 2099ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2100 bus_size_t count) 2101{ 2102 for (; count > 0; offset++, datap++, count--) { 2103 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2104 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2105 } 2106} 2107 2108struct cfdriver ipw_cd = { 2109 NULL, "ipw", DV_IFNET 2110}; 2111