if_ipw.c revision 1.10
1/* $Id: if_ipw.c,v 1.10 2004/10/27 21:19:43 damien Exp $ */ 2 3/*- 4 * Copyright (c) 2004 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/*- 31 * Intel(R) PRO/Wireless 2100 MiniPCI driver 32 * www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 33 */ 34 35#include "bpfilter.h" 36 37#include <sys/param.h> 38#include <sys/sockio.h> 39#include <sys/sysctl.h> 40#include <sys/mbuf.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43#include <sys/systm.h> 44#include <sys/malloc.h> 45#include <sys/conf.h> 46 47#include <machine/bus.h> 48#include <machine/endian.h> 49#include <machine/intr.h> 50 51#include <dev/pci/pcireg.h> 52#include <dev/pci/pcivar.h> 53#include <dev/pci/pcidevs.h> 54 55#if NBPFILTER > 0 56#include <net/bpf.h> 57#endif 58#include <net/if.h> 59#include <net/if_arp.h> 60#include <net/if_dl.h> 61#include <net/if_media.h> 62#include <net/if_types.h> 63 64#include <netinet/in.h> 65#include <netinet/in_systm.h> 66#include <netinet/in_var.h> 67#include <netinet/if_ether.h> 68#include <netinet/ip.h> 69 70#include <net80211/ieee80211_var.h> 71#include <net80211/ieee80211_radiotap.h> 72 73#include <dev/pci/if_ipwreg.h> 74#include <dev/pci/if_ipwvar.h> 75 76static const struct ieee80211_rateset ipw_rateset_11b = 77 { 4, { 2, 4, 11, 22 } }; 78 79int ipw_match(struct device *, void *, void *); 80void ipw_attach(struct device *, struct device *, void *); 81int ipw_detach(struct device *, int); 82int ipw_media_change(struct ifnet *); 83void ipw_media_status(struct ifnet *, struct ifmediareq *); 84int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 85void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 86void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 87void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 88 struct ipw_soft_bd *, struct ipw_soft_buf *); 89void ipw_notification_intr(struct ipw_softc *, struct ipw_soft_buf *); 90void ipw_rx_intr(struct ipw_softc *); 91void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 92void ipw_tx_intr(struct ipw_softc *); 93int ipw_intr(void *); 94int ipw_cmd(struct ipw_softc *, u_int32_t, void *, u_int32_t); 95int ipw_tx_start(struct ifnet *, struct mbuf *, struct ieee80211_node *); 96void ipw_start(struct ifnet *); 97void ipw_watchdog(struct ifnet *); 98int ipw_get_table1(struct ipw_softc *, u_int32_t *); 99int ipw_get_radio(struct ipw_softc *, int *); 100int ipw_ioctl(struct ifnet *, u_long, caddr_t); 101u_int32_t ipw_read_table1(struct ipw_softc *, u_int32_t); 102void ipw_write_table1(struct ipw_softc *, u_int32_t, u_int32_t); 103int ipw_read_table2(struct ipw_softc *, u_int32_t, void *, u_int32_t *); 104int ipw_tx_init(struct ipw_softc *); 105void ipw_tx_stop(struct ipw_softc *); 106int ipw_rx_init(struct ipw_softc *); 107void ipw_rx_stop(struct ipw_softc *); 108void ipw_reset(struct ipw_softc *); 109int ipw_clock_sync(struct ipw_softc *); 110int ipw_load_ucode(struct ipw_softc *, u_char *, int); 111int ipw_load_firmware(struct ipw_softc *, u_char *, int); 112int ipw_firmware_init(struct ipw_softc *, u_char *); 113int ipw_config(struct ipw_softc *); 114int ipw_init(struct ifnet *); 115void ipw_stop(struct ifnet *, int); 116void ipw_read_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, bus_size_t); 117void ipw_write_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, bus_size_t); 118void ipw_zero_mem_4(struct ipw_softc *, bus_size_t, bus_size_t); 119 120static __inline u_int8_t MEM_READ_1(struct ipw_softc *sc, u_int32_t addr) 121{ 122 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 123 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 124} 125 126static __inline u_int32_t MEM_READ_4(struct ipw_softc *sc, u_int32_t addr) 127{ 128 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 129 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 130} 131 132#ifdef IPW_DEBUG 133#define DPRINTF(x) if (ipw_debug > 0) printf x 134#define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 135int ipw_debug = 0; 136#else 137#define DPRINTF(x) 138#define DPRINTFN(n, x) 139#endif 140 141struct cfattach ipw_ca = { 142 sizeof (struct ipw_softc), ipw_match, ipw_attach, ipw_detach 143}; 144 145int 146ipw_match(struct device *parent, void *match, void *aux) 147{ 148 struct pci_attach_args *pa = aux; 149 150 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 151 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_2100_3B) 152 return 1; 153 154 return 0; 155} 156 157/* Base Address Register */ 158#define IPW_PCI_BAR0 0x10 159 160void 161ipw_attach(struct device *parent, struct device *self, void *aux) 162{ 163 struct ipw_softc *sc = (struct ipw_softc *)self; 164 struct ieee80211com *ic = &sc->sc_ic; 165 struct ifnet *ifp = &ic->ic_if; 166 struct pci_attach_args *pa = aux; 167 const char *intrstr; 168 bus_space_tag_t memt; 169 bus_space_handle_t memh; 170 bus_addr_t base; 171 pci_intr_handle_t ih; 172 pcireg_t data; 173 int error, i; 174 175 sc->sc_pct = pa->pa_pc; 176 177 data = pci_conf_read(sc->sc_pct, pa->pa_tag, 0x40); 178 data &= ~0x00ff0000; 179 pci_conf_write(sc->sc_pct, pa->pa_tag, 0x40, data); 180 181 /* enable bus-mastering */ 182 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 183 data |= PCI_COMMAND_MASTER_ENABLE; 184 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 185 186 /* map the register window */ 187 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 188 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 189 if (error != 0) { 190 printf(": could not map memory space\n"); 191 return; 192 } 193 194 sc->sc_st = memt; 195 sc->sc_sh = memh; 196 sc->sc_dmat = pa->pa_dmat; 197 198 /* disable interrupts */ 199 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 200 201 if (pci_intr_map(pa, &ih) != 0) { 202 printf(": could not map interrupt\n"); 203 return; 204 } 205 206 intrstr = pci_intr_string(sc->sc_pct, ih); 207 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 208 sc->sc_dev.dv_xname); 209 if (sc->sc_ih == NULL) { 210 printf(": could not establish interrupt"); 211 if (intrstr != NULL) 212 printf(" at %s", intrstr); 213 printf("\n"); 214 return; 215 } 216 printf(": %s\n", intrstr); 217 218 ic->ic_phytype = IEEE80211_T_DS; 219 ic->ic_opmode = IEEE80211_M_STA; 220 ic->ic_state = IEEE80211_S_INIT; 221 222 /* set device capabilities */ 223 ic->ic_caps = IEEE80211_C_IBSS | IEEE80211_C_MONITOR | 224 IEEE80211_C_PMGT | IEEE80211_C_TXPMGT | IEEE80211_C_WEP; 225 226 /* set supported .11b rates */ 227 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 228 229 /* set supported .11b channels (1 through 14) */ 230 for (i = 1; i <= 14; i++) { 231 ic->ic_channels[i].ic_freq = 232 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 233 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 234 } 235 236 /* default to authmode OPEN */ 237 sc->authmode = IEEE80211_AUTH_OPEN; 238 239 /* IBSS channel undefined for now */ 240 ic->ic_ibss_chan = &ic->ic_channels[0]; 241 242 ifp->if_softc = sc; 243 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 244 ifp->if_init = ipw_init; 245 ifp->if_ioctl = ipw_ioctl; 246 ifp->if_start = ipw_start; 247 ifp->if_watchdog = ipw_watchdog; 248 IFQ_SET_READY(&ifp->if_snd); 249 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 250 251 if_attach(ifp); 252 ieee80211_ifattach(ifp); 253 /* override state transition machine */ 254 sc->sc_newstate = ic->ic_newstate; 255 ic->ic_newstate = ipw_newstate; 256 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 257 258#if NBPFILTER > 0 259 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 260 sizeof (struct ieee80211_frame) + 64); 261 262 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 263 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 264 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 265 266 sc->sc_txtap_len = sizeof sc->sc_txtapu; 267 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 268 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 269#endif 270} 271 272int 273ipw_detach(struct device* self, int flags) 274{ 275 struct ipw_softc *sc = (struct ipw_softc *)self; 276 struct ifnet *ifp = &sc->sc_ic.ic_if; 277 278 ipw_reset(sc); 279 280#if NBPFILTER > 0 281 bpfdetach(ifp); 282#endif 283 ieee80211_ifdetach(ifp); 284 if_detach(ifp); 285 286 if (sc->sc_ih != NULL) { 287 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 288 sc->sc_ih = NULL; 289 } 290 291 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 292 293 return 0; 294} 295 296int 297ipw_media_change(struct ifnet *ifp) 298{ 299 int error; 300 301 error = ieee80211_media_change(ifp); 302 if (error != ENETRESET) 303 return error; 304 305 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 306 ipw_init(ifp); 307 308 return 0; 309} 310 311void 312ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 313{ 314 struct ipw_softc *sc = ifp->if_softc; 315 struct ieee80211com *ic = &sc->sc_ic; 316#define N(a) (sizeof (a) / sizeof (a[0])) 317 static const struct { 318 u_int32_t val; 319 int rate; 320 } rates[] = { 321 { IPW_RATE_DS1, 2 }, 322 { IPW_RATE_DS2, 4 }, 323 { IPW_RATE_DS5, 11 }, 324 { IPW_RATE_DS11, 22 }, 325 }; 326 u_int32_t val; 327 int rate, i; 328 329 imr->ifm_status = IFM_AVALID; 330 imr->ifm_active = IFM_IEEE80211; 331 if (ic->ic_state == IEEE80211_S_RUN) 332 imr->ifm_status |= IFM_ACTIVE; 333 334 /* read current transmission rate from adapter */ 335 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 336 val &= 0xf; 337 338 /* convert rate to 802.11 rate */ 339 for (i = 0; i < N(rates) && rates[i].val != val; i++); 340 rate = (i < N(rates)) ? rates[i].rate : 0; 341 342 imr->ifm_active |= IFM_IEEE80211_11B; 343 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 344 switch (ic->ic_opmode) { 345 case IEEE80211_M_STA: 346 break; 347 348 case IEEE80211_M_IBSS: 349 imr->ifm_active |= IFM_IEEE80211_ADHOC; 350 break; 351 352 case IEEE80211_M_MONITOR: 353 imr->ifm_active |= IFM_IEEE80211_MONITOR; 354 break; 355 356 case IEEE80211_M_AHDEMO: 357 case IEEE80211_M_HOSTAP: 358 /* should not get there */ 359 break; 360 } 361#undef N 362} 363 364int 365ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 366{ 367 struct ipw_softc *sc = ic->ic_softc; 368 struct ieee80211_node *ni = ic->ic_bss; 369 u_int32_t val, len; 370 371 switch (nstate) { 372 case IEEE80211_S_RUN: 373 len = IEEE80211_NWID_LEN; 374 ipw_read_table2(sc, IPW_INFO_CURRENT_SSID, ni->ni_essid, &len); 375 ni->ni_esslen = len; 376 377 val = ipw_read_table1(sc, IPW_INFO_CURRENT_CHANNEL); 378 ni->ni_chan = &ic->ic_channels[val]; 379 380 DELAY(100); /* firmware needs a short delay here */ 381 382 len = IEEE80211_ADDR_LEN; 383 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, ni->ni_bssid, &len); 384 break; 385 386 case IEEE80211_S_INIT: 387 case IEEE80211_S_SCAN: 388 case IEEE80211_S_AUTH: 389 case IEEE80211_S_ASSOC: 390 break; 391 } 392 393 ic->ic_state = nstate; 394 return 0; 395} 396 397void 398ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 399{ 400 struct ipw_cmd *cmd; 401 402 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 403 BUS_DMASYNC_POSTREAD); 404 405 cmd = mtod(sbuf->m, struct ipw_cmd *); 406 407 DPRINTFN(2, ("RX!CMD!%u!%u!%u!%u!%u\n", 408 letoh32(cmd->type), letoh32(cmd->subtype), letoh32(cmd->seq), 409 letoh32(cmd->len), letoh32(cmd->status))); 410 411 /* 412 * Wake up processes waiting for command ack. In the case of the 413 * IPW_CMD_DISABLE command, wake up the process only when the adapter 414 * enters the IPW_STATE_DISABLED state. This is notified in 415 * ipw_newstate_intr(). 416 */ 417 if (letoh32(cmd->type) != IPW_CMD_DISABLE) 418 wakeup(sc->cmd); 419} 420 421void 422ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 423{ 424 struct ieee80211com *ic = &sc->sc_ic; 425 u_int32_t state; 426 427 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 428 BUS_DMASYNC_POSTREAD); 429 430 state = letoh32(*mtod(sbuf->m, u_int32_t *)); 431 432 DPRINTFN(2, ("RX!NEWSTATE!%u\n", state)); 433 434 switch (state) { 435 case IPW_STATE_ASSOCIATED: 436 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 437 break; 438 439 case IPW_STATE_SCANNING: 440 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 441 break; 442 443 case IPW_STATE_ASSOCIATION_LOST: 444 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 445 break; 446 447 case IPW_STATE_DISABLED: 448 wakeup(sc->cmd); 449 break; 450 451 case IPW_STATE_RADIO_DISABLED: 452 /* XXX should turn the interface down */ 453 break; 454 } 455} 456 457void 458ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 459 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 460{ 461 struct ieee80211com *ic = &sc->sc_ic; 462 struct ifnet *ifp = &ic->ic_if; 463 struct mbuf *m; 464 struct ieee80211_frame *wh; 465 struct ieee80211_node *ni; 466 int error; 467 468 DPRINTFN(5, ("RX!DATA!%u!%u\n", letoh32(status->len), status->rssi)); 469 470 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 471 BUS_DMASYNC_POSTREAD); 472 473 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 474 475 /* Finalize mbuf */ 476 m = sbuf->m; 477 m->m_pkthdr.rcvif = ifp; 478 m->m_pkthdr.len = m->m_len = letoh32(status->len); 479 480#if NBPFILTER > 0 481 if (sc->sc_drvbpf != NULL) { 482 struct mbuf mb; 483 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 484 485 tap->wr_flags = 0; 486 tap->wr_antsignal = status->rssi; 487 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 488 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 489 490 M_DUP_PKTHDR(&mb, m); 491 mb.m_data = (caddr_t)tap; 492 mb.m_len = sc->sc_rxtap_len; 493 mb.m_next = m; 494 mb.m_pkthdr.len += mb.m_len; 495 bpf_mtap(sc->sc_drvbpf, &mb); 496 } 497#endif 498 499 wh = mtod(m, struct ieee80211_frame *); 500 501 ni = ieee80211_find_rxnode(ic, wh); 502 503 /* Send it up to the upper layer */ 504 ieee80211_input(ifp, m, ni, status->rssi, 0); 505 506 if (ni == ic->ic_bss) 507 ieee80211_unref_node(&ni); 508 else 509 ieee80211_free_node(ic, ni); 510 511 MGETHDR(m, M_DONTWAIT, MT_DATA); 512 if (m == NULL) { 513 printf("%s: could not allocate rx mbuf\n", 514 sc->sc_dev.dv_xname); 515 return; 516 } 517 MCLGET(m, M_DONTWAIT); 518 if (!(m->m_flags & M_EXT)) { 519 m_freem(m); 520 printf("%s: could not allocate rx mbuf cluster\n", 521 sc->sc_dev.dv_xname); 522 return; 523 } 524 525 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(m, void *), 526 MCLBYTES, NULL, BUS_DMA_NOWAIT); 527 if (error != 0) { 528 printf("%s: could not map rxbuf dma memory\n", 529 sc->sc_dev.dv_xname); 530 m_freem(m); 531 return; 532 } 533 534 sbuf->m = m; 535 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 536} 537 538void 539ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 540{ 541 DPRINTFN(2, ("RX!NOTIFICATION\n")); 542} 543 544void 545ipw_rx_intr(struct ipw_softc *sc) 546{ 547 struct ipw_status *status; 548 struct ipw_soft_bd *sbd; 549 struct ipw_soft_buf *sbuf; 550 u_int32_t r, i; 551 552 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 553 554 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 555 556 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 557 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 558 BUS_DMASYNC_POSTREAD); 559 560 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 561 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 562 BUS_DMASYNC_POSTREAD); 563 564 status = &sc->status_list[i]; 565 sbd = &sc->srbd_list[i]; 566 sbuf = sbd->priv; 567 568 switch (letoh16(status->code) & 0xf) { 569 case IPW_STATUS_CODE_COMMAND: 570 ipw_command_intr(sc, sbuf); 571 break; 572 573 case IPW_STATUS_CODE_NEWSTATE: 574 ipw_newstate_intr(sc, sbuf); 575 break; 576 577 case IPW_STATUS_CODE_DATA_802_3: 578 case IPW_STATUS_CODE_DATA_802_11: 579 ipw_data_intr(sc, status, sbd, sbuf); 580 break; 581 582 case IPW_STATUS_CODE_NOTIFICATION: 583 ipw_notification_intr(sc, sbuf); 584 break; 585 586 default: 587 printf("%s: unknown status code %u\n", 588 sc->sc_dev.dv_xname, letoh16(status->code)); 589 } 590 sbd->bd->flags = 0; 591 592 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 593 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 594 BUS_DMASYNC_PREWRITE); 595 } 596 597 /* Tell the firmware what we have processed */ 598 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 599 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 600} 601 602void 603ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 604{ 605 struct ieee80211com *ic; 606 struct ipw_soft_hdr *shdr; 607 struct ipw_soft_buf *sbuf; 608 609 switch (sbd->type) { 610 case IPW_SBD_TYPE_COMMAND: 611 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 612 break; 613 614 case IPW_SBD_TYPE_HEADER: 615 shdr = sbd->priv; 616 bus_dmamap_unload(sc->sc_dmat, shdr->map); 617 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 618 break; 619 620 case IPW_SBD_TYPE_DATA: 621 ic = &sc->sc_ic; 622 sbuf = sbd->priv; 623 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 624 m_freem(sbuf->m); 625 if (sbuf->ni != NULL && sbuf->ni != ic->ic_bss) 626 ieee80211_free_node(ic, sbuf->ni); 627 /* kill watchdog timer */ 628 sc->sc_tx_timer = 0; 629 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 630 break; 631 } 632 sbd->type = IPW_SBD_TYPE_NOASSOC; 633} 634 635void 636ipw_tx_intr(struct ipw_softc *sc) 637{ 638 struct ifnet *ifp = &sc->sc_ic.ic_if; 639 u_int32_t r, i; 640 641 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 642 643 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) 644 ipw_release_sbd(sc, &sc->stbd_list[i]); 645 646 /* Remember what the firmware has processed */ 647 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 648 649 /* Call start() since some buffer descriptors have been released */ 650 ifp->if_flags &= ~IFF_OACTIVE; 651 (*ifp->if_start)(ifp); 652} 653 654int 655ipw_intr(void *arg) 656{ 657 struct ipw_softc *sc = arg; 658 u_int32_t r; 659 660 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0) 661 return 0; 662 663 /* Disable interrupts */ 664 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 665 666 DPRINTFN(8, ("INTR!0x%08x\n", r)); 667 668 if (r & IPW_INTR_RX_TRANSFER) 669 ipw_rx_intr(sc); 670 671 if (r & IPW_INTR_TX_TRANSFER) 672 ipw_tx_intr(sc); 673 674 if (r & IPW_INTR_FW_INIT_DONE) { 675 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 676 wakeup(sc); 677 } 678 679 /* Acknowledge interrupts */ 680 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 681 682 /* Re-enable interrupts */ 683 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 684 685 return 0; 686} 687 688int 689ipw_cmd(struct ipw_softc *sc, u_int32_t type, void *data, u_int32_t len) 690{ 691 struct ipw_soft_bd *sbd; 692 int error; 693 694 sbd = &sc->stbd_list[sc->txcur]; 695 696 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, sc->cmd, 697 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 698 if (error != 0) { 699 printf("%s: could not map cmd dma memory\n", 700 sc->sc_dev.dv_xname); 701 return error; 702 } 703 704 sc->cmd->type = htole32(type); 705 sc->cmd->subtype = htole32(0); 706 sc->cmd->len = htole32(len); 707 sc->cmd->seq = htole32(0); 708 if (data != NULL) 709 bcopy(data, sc->cmd->data, len); 710 711 sbd->type = IPW_SBD_TYPE_COMMAND; 712 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 713 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 714 sbd->bd->nfrag = 1; 715 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 716 IPW_BD_FLAG_TX_LAST_FRAGMENT; 717 718 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 719 BUS_DMASYNC_PREWRITE); 720 721 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 722 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 723 BUS_DMASYNC_PREWRITE); 724 725 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 726 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 727 728 DPRINTFN(2, ("TX!CMD!%u!%u!%u!%u\n", type, 0, 0, len)); 729 730 /* Wait at most one second for command to complete */ 731 return tsleep(sc->cmd, 0, "ipwcmd", hz); 732} 733 734int 735ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 736{ 737 struct ipw_softc *sc = ifp->if_softc; 738 struct ieee80211com *ic = &sc->sc_ic; 739 struct ieee80211_frame *wh; 740 struct ipw_soft_bd *sbd; 741 struct ipw_soft_hdr *shdr; 742 struct ipw_soft_buf *sbuf; 743 int error, i; 744 745 if (ic->ic_flags & IEEE80211_F_WEPON) { 746 m = ieee80211_wep_crypt(ifp, m, 1); 747 if (m == NULL) 748 return ENOBUFS; 749 } 750 751#if NBPFILTER > 0 752 if (sc->sc_drvbpf != NULL) { 753 struct mbuf mb; 754 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 755 756 tap->wt_flags = 0; 757 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 758 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 759 760 M_DUP_PKTHDR(&mb, m); 761 mb.m_data = (caddr_t)tap; 762 mb.m_len = sc->sc_txtap_len; 763 mb.m_next = m; 764 mb.m_pkthdr.len += mb.m_len; 765 bpf_mtap(sc->sc_drvbpf, &mb); 766 } 767#endif 768 769 wh = mtod(m, struct ieee80211_frame *); 770 771 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 772 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 773 774 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 775 shdr->hdr.subtype = htole32(0); 776 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 777 shdr->hdr.encrypt = 0; 778 shdr->hdr.keyidx = 0; 779 shdr->hdr.keysz = 0; 780 shdr->hdr.fragmentsz = htole16(0); 781 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 782 if (ic->ic_opmode == IEEE80211_M_STA) 783 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 784 else 785 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 786 787 /* trim IEEE802.11 header */ 788 m_adj(m, sizeof (struct ieee80211_frame)); 789 790 /* 791 * We need to map the mbuf first to know how many buffer descriptors 792 * are needed for this transfer. 793 */ 794 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 795 if (error != 0) { 796 printf("%s: could not map mbuf (error %d)\n", 797 sc->sc_dev.dv_xname, error); 798 m_freem(m); 799 return error; 800 } 801 802 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 803 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 804 if (error != 0) { 805 printf("%s: could not map header (error %d)\n", 806 sc->sc_dev.dv_xname, error); 807 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 808 m_freem(m); 809 return error; 810 } 811 812 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 813 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 814 815 sbd = &sc->stbd_list[sc->txcur]; 816 sbd->type = IPW_SBD_TYPE_HEADER; 817 sbd->priv = shdr; 818 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 819 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 820 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 821 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 822 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 823 824 DPRINTFN(5, ("TX!HDR!%u!%u!%u!%u", shdr->hdr.type, shdr->hdr.subtype, 825 shdr->hdr.encrypted, shdr->hdr.encrypt)); 826 DPRINTFN(5, ("!%s", ether_sprintf(shdr->hdr.src_addr))); 827 DPRINTFN(5, ("!%s\n", ether_sprintf(shdr->hdr.dst_addr))); 828 829 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 830 sc->txcur * sizeof (struct ipw_bd), 831 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 832 833 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 834 835 sbuf->m = m; 836 sbuf->ni = ni; 837 838 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 839 sbd = &sc->stbd_list[sc->txcur]; 840 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 841 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 842 sbd->bd->nfrag = 0; /* used only in first bd */ 843 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 844 if (i == sbuf->map->dm_nsegs - 1) { 845 sbd->type = IPW_SBD_TYPE_DATA; 846 sbd->priv = sbuf; 847 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 848 } else { 849 sbd->type = IPW_SBD_TYPE_NOASSOC; 850 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 851 } 852 853 DPRINTFN(5, ("TX!FRAG!%d!%d\n", i, 854 sbuf->map->dm_segs[i].ds_len)); 855 856 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 857 sc->txcur * sizeof (struct ipw_bd), 858 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 859 860 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 861 } 862 863 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 864 BUS_DMASYNC_PREWRITE); 865 866 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 867 BUS_DMASYNC_PREWRITE); 868 869 /* Inform firmware about this new packet */ 870 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 871 872 return 0; 873} 874 875void 876ipw_start(struct ifnet *ifp) 877{ 878 struct ipw_softc *sc = ifp->if_softc; 879 struct ieee80211com *ic = &sc->sc_ic; 880 struct mbuf *m; 881 struct ieee80211_node *ni; 882 883 for (;;) { 884 IF_DEQUEUE(&ifp->if_snd, m); 885 if (m == NULL) 886 break; 887 888#if NBPFILTER > 0 889 if (ifp->if_bpf != NULL) 890 bpf_mtap(ifp->if_bpf, m); 891#endif 892 893 m = ieee80211_encap(ifp, m, &ni); 894 if (m == NULL) 895 continue; 896 897#if NBPFILTER > 0 898 if (ic->ic_rawbpf != NULL) 899 bpf_mtap(ic->ic_rawbpf, m); 900#endif 901 902 if (ipw_tx_start(ifp, m, ni) != 0) { 903 if (ni != NULL && ni != ic->ic_bss) 904 ieee80211_free_node(ic, ni); 905 break; 906 } 907 908 /* start watchdog timer */ 909 sc->sc_tx_timer = 5; 910 ifp->if_timer = 1; 911 } 912} 913 914void 915ipw_watchdog(struct ifnet *ifp) 916{ 917 struct ipw_softc *sc = ifp->if_softc; 918 919 ifp->if_timer = 0; 920 921 if (sc->sc_tx_timer > 0) { 922 if (--sc->sc_tx_timer == 0) { 923 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 924#ifdef notyet 925 ipw_init(ifp); 926#endif 927 return; 928 } 929 ifp->if_timer = 1; 930 } 931 932 ieee80211_watchdog(ifp); 933} 934 935int 936ipw_get_table1(struct ipw_softc *sc, u_int32_t *tbl) 937{ 938 u_int32_t i, size, buf[256]; 939 940 if (!(sc->flags & IPW_FLAG_FW_INITED)) 941 return ENOTTY; 942 943 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 944 945 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 946 for (i = 1; i < size; i++) 947 buf[i] = MEM_READ_4(sc, CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA)); 948 949 return copyout(buf, tbl, size * sizeof (u_int32_t)); 950} 951 952int 953ipw_get_radio(struct ipw_softc *sc, int *ret) 954{ 955 int val; 956 957 if (!(sc->flags & IPW_FLAG_FW_INITED)) 958 return ENOTTY; 959 960 val = (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 0 : 1; 961 return copyout(&val, ret, sizeof val); 962} 963 964int 965ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 966{ 967 struct ipw_softc *sc = ifp->if_softc; 968 struct ifreq *ifr; 969 struct ifaddr *ifa; 970 int s, error = 0; 971 972 s = splnet(); 973 974 switch (cmd) { 975 case SIOCSIFADDR: 976 ifa = (struct ifaddr *) data; 977 ifp->if_flags |= IFF_UP; 978 switch (ifa->ifa_addr->sa_family) { 979#ifdef INET 980 case AF_INET: 981 arp_ifinit(&sc->sc_ic.ic_ac, ifa); 982 ipw_init(ifp); 983 break; 984#endif 985 default: 986 ipw_init(ifp); 987 } 988 break; 989 990 case SIOCSIFFLAGS: 991 if (ifp->if_flags & IFF_UP) { 992 if (!(ifp->if_flags & IFF_RUNNING)) 993 ipw_init(ifp); 994 } else { 995 if (ifp->if_flags & IFF_RUNNING) 996 ipw_stop(ifp, 1); 997 } 998 break; 999 1000 case SIOCGTABLE1: 1001 ifr = (struct ifreq *)data; 1002 error = ipw_get_table1(sc, (u_int32_t *)ifr->ifr_data); 1003 break; 1004 1005 case SIOCGRADIO: 1006 ifr = (struct ifreq *)data; 1007 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1008 break; 1009 1010 case SIOCSLOADFW: 1011 /* only super-user can do that! */ 1012 if ((error = suser(curproc, 0)) != 0) 1013 break; 1014 1015 ifr = (struct ifreq *)data; 1016 error = ipw_firmware_init(sc, (u_char *)ifr->ifr_data); 1017 break; 1018 1019 case SIOCSKILLFW: 1020 /* only super-user can do that! */ 1021 if ((error = suser(curproc, 0)) != 0) 1022 break; 1023 1024 ipw_reset(sc); 1025 break; 1026 1027 case SIOCG80211AUTH: 1028 ((struct ieee80211_auth *)data)->i_authtype = sc->authmode; 1029 break; 1030 1031 case SIOCS80211AUTH: 1032 /* only super-user can do that! */ 1033 if ((error = suser(curproc, 0)) != 0) 1034 break; 1035 1036 sc->authmode = ((struct ieee80211_auth *)data)->i_authtype; 1037 break; 1038 1039 default: 1040 error = ieee80211_ioctl(ifp, cmd, data); 1041 } 1042 1043 if (error == ENETRESET && cmd != SIOCADDMULTI) { 1044 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1045 (IFF_UP | IFF_RUNNING)) 1046 ipw_init(ifp); 1047 error = 0; 1048 } 1049 1050 splx(s); 1051 return error; 1052} 1053 1054u_int32_t 1055ipw_read_table1(struct ipw_softc *sc, u_int32_t off) 1056{ 1057 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1058} 1059 1060void 1061ipw_write_table1(struct ipw_softc *sc, u_int32_t off, u_int32_t info) 1062{ 1063 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1064} 1065 1066int 1067ipw_read_table2(struct ipw_softc *sc, u_int32_t off, void *buf, u_int32_t *len) 1068{ 1069 u_int32_t addr, info; 1070 u_int16_t count, size; 1071 u_int32_t total; 1072 1073 /* addr[4] + count[2] + size[2] */ 1074 addr = MEM_READ_4(sc, sc->table2_base + off); 1075 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1076 1077 count = info >> 16; 1078 size = info & 0xffff; 1079 total = count * size; 1080 1081 if (total > *len) { 1082 *len = total; 1083 return EINVAL; 1084 } 1085 1086 *len = total; 1087 ipw_read_mem_1(sc, addr, buf, total); 1088 1089 return 0; 1090} 1091 1092int 1093ipw_tx_init(struct ipw_softc *sc) 1094{ 1095 char *errmsg; 1096 struct ipw_bd *bd; 1097 struct ipw_soft_bd *sbd; 1098 struct ipw_soft_hdr *shdr; 1099 struct ipw_soft_buf *sbuf; 1100 int error, i, nsegs; 1101 1102 /* Allocate transmission buffer descriptors */ 1103 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 1104 BUS_DMA_NOWAIT, &sc->tbd_map); 1105 if (error != 0) { 1106 errmsg = "could not create tbd dma map"; 1107 goto fail; 1108 } 1109 1110 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 1111 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1112 if (error != 0) { 1113 errmsg = "could not allocate tbd dma memory"; 1114 goto fail; 1115 } 1116 1117 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 1118 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 1119 if (error != 0) { 1120 errmsg = "could not map tbd dma memory"; 1121 goto fail; 1122 } 1123 1124 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 1125 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 1126 if (error != 0) { 1127 errmsg = "could not load tbd dma memory"; 1128 goto fail; 1129 } 1130 1131 sc->stbd_list = malloc(IPW_NTBD * sizeof (struct ipw_soft_bd), 1132 M_DEVBUF, M_NOWAIT); 1133 if (sc->stbd_list == NULL) { 1134 errmsg = "could not allocate soft tbd"; 1135 error = ENOMEM; 1136 goto fail; 1137 } 1138 sbd = sc->stbd_list; 1139 bd = sc->tbd_list; 1140 for (i = 0; i < IPW_NTBD; i++, sbd++, bd++) { 1141 sbd->type = IPW_SBD_TYPE_NOASSOC; 1142 sbd->bd = bd; 1143 } 1144 1145 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1146 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1147 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1148 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1149 sc->txold = IPW_NTBD - 1; /* latest bd index ack'ed by firmware */ 1150 sc->txcur = 0; /* bd index to write to */ 1151 1152 /* Allocate a DMA-able command */ 1153 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 1154 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 1155 if (error != 0) { 1156 errmsg = "could not create cmd dma map"; 1157 goto fail; 1158 } 1159 1160 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 1161 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1162 if (error != 0) { 1163 errmsg = "could not allocate cmd dma memory"; 1164 goto fail; 1165 } 1166 1167 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 1168 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 1169 if (error != 0) { 1170 errmsg = "could not map cmd dma memory"; 1171 goto fail; 1172 } 1173 1174 /* Allocate a pool of DMA-able headers */ 1175 sc->shdr_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_hdr), 1176 M_DEVBUF, M_NOWAIT); 1177 if (sc->shdr_list == NULL) { 1178 errmsg = "could not allocate soft hdr"; 1179 error = ENOMEM; 1180 goto fail; 1181 } 1182 TAILQ_INIT(&sc->sc_free_shdr); 1183 for (i = 0, shdr = sc->shdr_list; i < IPW_NDATA; i++, shdr++) { 1184 error = bus_dmamap_create(sc->sc_dmat, 1185 sizeof (struct ipw_soft_hdr), 1, 1186 sizeof (struct ipw_soft_hdr), 0, BUS_DMA_NOWAIT, 1187 &shdr->map); 1188 if (error != 0) { 1189 errmsg = "could not create hdr dma map"; 1190 goto fail; 1191 } 1192 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1193 } 1194 1195 /* Allocate a pool of DMA-able buffers */ 1196 sc->tx_sbuf_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_buf), 1197 M_DEVBUF, M_NOWAIT); 1198 if (sc->tx_sbuf_list == NULL) { 1199 errmsg = "could not allocate soft txbuf"; 1200 error = ENOMEM; 1201 goto fail; 1202 } 1203 TAILQ_INIT(&sc->sc_free_sbuf); 1204 for (i = 0, sbuf = sc->tx_sbuf_list; i < IPW_NDATA; i++, sbuf++) { 1205 error = bus_dmamap_create(sc->sc_dmat, IPW_NDATA * MCLBYTES, 1206 IPW_NDATA, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1207 if (error != 0) { 1208 errmsg = "could not create txbuf dma map"; 1209 goto fail; 1210 } 1211 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1212 } 1213 1214 return 0; 1215 1216fail: printf("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1217 ipw_tx_stop(sc); 1218 1219 return error; 1220} 1221 1222void 1223ipw_tx_stop(struct ipw_softc *sc) 1224{ 1225 struct ipw_soft_hdr *shdr; 1226 struct ipw_soft_buf *sbuf; 1227 int i; 1228 1229 if (sc->tbd_map != NULL) { 1230 if (sc->tbd_list != NULL) { 1231 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 1232 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 1233 IPW_TBD_SZ); 1234 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 1235 sc->tbd_list = NULL; 1236 } 1237 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 1238 sc->tbd_map = NULL; 1239 } 1240 1241 if (sc->stbd_list != NULL) { 1242 for (i = 0; i < IPW_NTBD; i++) 1243 ipw_release_sbd(sc, &sc->stbd_list[i]); 1244 free(sc->stbd_list, M_DEVBUF); 1245 sc->stbd_list = NULL; 1246 } 1247 1248 if (sc->cmd_map != NULL) { 1249 if (sc->cmd != NULL) { 1250 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->cmd, 1251 sizeof (struct ipw_cmd)); 1252 bus_dmamem_free(sc->sc_dmat, &sc->cmd_seg, 1); 1253 sc->cmd = NULL; 1254 } 1255 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 1256 sc->cmd_map = NULL; 1257 } 1258 1259 if (sc->shdr_list != NULL) { 1260 TAILQ_FOREACH(shdr, &sc->sc_free_shdr, next) 1261 bus_dmamap_destroy(sc->sc_dmat, shdr->map); 1262 free(sc->shdr_list, M_DEVBUF); 1263 sc->shdr_list = NULL; 1264 } 1265 1266 1267 if (sc->tx_sbuf_list != NULL) { 1268 TAILQ_FOREACH(sbuf, &sc->sc_free_sbuf, next) 1269 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1270 free(sc->tx_sbuf_list, M_DEVBUF); 1271 sc->tx_sbuf_list = NULL; 1272 } 1273} 1274 1275int 1276ipw_rx_init(struct ipw_softc *sc) 1277{ 1278 char *errmsg; 1279 struct ipw_bd *bd; 1280 struct ipw_soft_bd *sbd; 1281 struct ipw_soft_buf *sbuf; 1282 int error, i, nsegs; 1283 1284 /* Allocate reception buffer descriptors */ 1285 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 1286 BUS_DMA_NOWAIT, &sc->rbd_map); 1287 if (error != 0) { 1288 errmsg = "could not create rbd dma map"; 1289 goto fail; 1290 } 1291 1292 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 1293 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1294 if (error != 0) { 1295 errmsg = "could not allocate rbd dma memory"; 1296 goto fail; 1297 } 1298 1299 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 1300 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 1301 if (error != 0) { 1302 errmsg = "could not map rbd dma memory"; 1303 goto fail; 1304 } 1305 1306 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 1307 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 1308 if (error != 0) { 1309 errmsg = "could not load rbd dma memory"; 1310 goto fail; 1311 } 1312 1313 sc->srbd_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_bd), 1314 M_DEVBUF, M_NOWAIT); 1315 if (sc->srbd_list == NULL) { 1316 errmsg = "could not allocate soft rbd"; 1317 error = ENOMEM; 1318 goto fail; 1319 } 1320 sbd = sc->srbd_list; 1321 bd = sc->rbd_list; 1322 for (i = 0; i < IPW_NRBD; i++, sbd++, bd++) { 1323 sbd->type = IPW_SBD_TYPE_NOASSOC; 1324 sbd->bd = bd; 1325 } 1326 1327 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1328 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1329 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1330 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1331 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1332 1333 /* Allocate status descriptors */ 1334 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 1335 0, BUS_DMA_NOWAIT, &sc->status_map); 1336 if (error != 0) { 1337 errmsg = "could not create status dma map"; 1338 goto fail; 1339 } 1340 1341 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 1342 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1343 if (error != 0) { 1344 errmsg = "could not allocate status dma memory"; 1345 goto fail; 1346 } 1347 1348 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 1349 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 1350 if (error != 0) { 1351 errmsg = "could not map status dma memory"; 1352 goto fail; 1353 } 1354 1355 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 1356 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 1357 if (error != 0) { 1358 errmsg = "could not load status dma memory"; 1359 goto fail; 1360 } 1361 1362 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1363 sc->status_map->dm_segs[0].ds_addr); 1364 1365 sc->rx_sbuf_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_buf), 1366 M_DEVBUF, M_NOWAIT); 1367 if (sc->rx_sbuf_list == NULL) { 1368 errmsg = "could not allocate soft rxbuf"; 1369 error = ENOMEM; 1370 goto fail; 1371 } 1372 1373 sbuf = sc->rx_sbuf_list; 1374 sbd = sc->srbd_list; 1375 for (i = 0; i < IPW_NRBD; i++, sbuf++, sbd++) { 1376 1377 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 1378 if (sbuf->m == NULL) { 1379 errmsg = "could not allocate rx mbuf"; 1380 error = ENOMEM; 1381 goto fail; 1382 } 1383 MCLGET(sbuf->m, M_DONTWAIT); 1384 if (!(sbuf->m->m_flags & M_EXT)) { 1385 m_freem(sbuf->m); 1386 errmsg = "could not allocate rx mbuf cluster"; 1387 error = ENOMEM; 1388 goto fail; 1389 } 1390 1391 error = bus_dmamap_create(sc->sc_dmat, IPW_NRBD * MCLBYTES, 1392 IPW_NRBD, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1393 if (error != 0) { 1394 m_freem(sbuf->m); 1395 errmsg = "could not create rxbuf dma map"; 1396 goto fail; 1397 } 1398 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 1399 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1400 if (error != 0) { 1401 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1402 m_freem(sbuf->m); 1403 errmsg = "could not map rxbuf dma memory"; 1404 goto fail; 1405 } 1406 sbd->type = IPW_SBD_TYPE_DATA; 1407 sbd->priv = sbuf; 1408 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1409 sbd->bd->len = htole32(MCLBYTES); 1410 } 1411 1412 return 0; 1413 1414fail: printf("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1415 ipw_rx_stop(sc); 1416 1417 return error; 1418} 1419 1420void 1421ipw_rx_stop(struct ipw_softc *sc) 1422{ 1423 struct ipw_soft_bd *sbd; 1424 struct ipw_soft_buf *sbuf; 1425 int i; 1426 1427 if (sc->rbd_map != NULL) { 1428 if (sc->rbd_list != NULL) { 1429 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 1430 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 1431 IPW_RBD_SZ); 1432 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 1433 sc->rbd_list = NULL; 1434 } 1435 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 1436 sc->rbd_map = NULL; 1437 } 1438 1439 if (sc->status_map != NULL) { 1440 if (sc->status_list != NULL) { 1441 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 1442 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 1443 IPW_STATUS_SZ); 1444 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 1445 sc->status_list = NULL; 1446 } 1447 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 1448 sc->status_map = NULL; 1449 } 1450 1451 if (sc->srbd_list != NULL) { 1452 for (i = 0, sbd = sc->srbd_list; i < IPW_NRBD; i++, sbd++) { 1453 if (sbd->type == IPW_SBD_TYPE_NOASSOC) 1454 continue; 1455 1456 sbuf = sbd->priv; 1457 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1458 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1459 m_freem(sbuf->m); 1460 } 1461 free(sc->srbd_list, M_DEVBUF); 1462 sc->srbd_list = NULL; 1463 } 1464 1465 if (sc->rx_sbuf_list != NULL) { 1466 free(sc->rx_sbuf_list, M_DEVBUF); 1467 sc->rx_sbuf_list = NULL; 1468 } 1469} 1470 1471void 1472ipw_reset(struct ipw_softc *sc) 1473{ 1474 struct ifnet *ifp = &sc->sc_ic.ic_if; 1475 int ntries; 1476 1477 ipw_stop(ifp, 1); 1478 1479 if (sc->flags & IPW_FLAG_FW_INITED) { 1480 ipw_cmd(sc, IPW_CMD_DISABLE_PHY, NULL, 0); 1481 ipw_cmd(sc, IPW_CMD_PREPARE_POWER_DOWN, NULL, 0); 1482 1483 sc->flags &= ~IPW_FLAG_FW_INITED; 1484 } 1485 1486 /* Disable interrupts */ 1487 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1488 1489 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1490 for (ntries = 0; ntries < 5; ntries++) { 1491 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1492 break; 1493 DELAY(10); 1494 } 1495 1496 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1497 1498 ipw_rx_stop(sc); 1499 ipw_tx_stop(sc); 1500 1501 ifp->if_flags &= ~IFF_UP; 1502} 1503 1504int 1505ipw_clock_sync(struct ipw_softc *sc) 1506{ 1507 int ntries; 1508 u_int32_t r; 1509 1510 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1511 for (ntries = 0; ntries < 1000; ntries++) { 1512 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_PRINCETON_RESET) 1513 break; 1514 DELAY(10); 1515 } 1516 if (ntries == 1000) 1517 return EIO; 1518 1519 CSR_WRITE_4(sc, IPW_CSR_CTL, IPW_CTL_INIT); 1520 for (ntries = 0; ntries < 1000; ntries++) { 1521 if ((r = CSR_READ_4(sc, IPW_CSR_CTL)) & IPW_CTL_CLOCK_READY) 1522 break; 1523 DELAY(200); 1524 } 1525 if (ntries == 1000) 1526 return EIO; 1527 1528 CSR_WRITE_4(sc, IPW_CSR_CTL, r | IPW_CTL_ALLOW_STANDBY); 1529 1530 return 0; 1531} 1532 1533int 1534ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1535{ 1536 int ntries; 1537 1538 MEM_WRITE_2(sc, 0x220000, 0x0703); 1539 MEM_WRITE_2(sc, 0x220000, 0x0707); 1540 1541 MEM_WRITE_1(sc, 0x210014, 0x72); 1542 MEM_WRITE_1(sc, 0x210014, 0x72); 1543 1544 MEM_WRITE_1(sc, 0x210000, 0x40); 1545 MEM_WRITE_1(sc, 0x210000, 0x00); 1546 MEM_WRITE_1(sc, 0x210000, 0x40); 1547 1548 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1549 1550 MEM_WRITE_1(sc, 0x210000, 0x00); 1551 MEM_WRITE_1(sc, 0x210000, 0x00); 1552 MEM_WRITE_1(sc, 0x210000, 0x80); 1553 1554 MEM_WRITE_2(sc, 0x220000, 0x0703); 1555 MEM_WRITE_2(sc, 0x220000, 0x0707); 1556 1557 MEM_WRITE_1(sc, 0x210014, 0x72); 1558 MEM_WRITE_1(sc, 0x210014, 0x72); 1559 1560 MEM_WRITE_1(sc, 0x210000, 0x00); 1561 MEM_WRITE_1(sc, 0x210000, 0x80); 1562 1563 for (ntries = 0; ntries < 10; ntries++) { 1564 if (MEM_READ_1(sc, 0x210000) & 1) 1565 break; 1566 DELAY(10); 1567 } 1568 if (ntries == 10) 1569 return EIO; 1570 1571 return 0; 1572} 1573 1574/* set of macros to handle unaligned little endian data in firmware image */ 1575#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1576#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1577int 1578ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1579{ 1580 u_char *p, *end; 1581 u_int32_t dst; 1582 u_int16_t len; 1583 1584 p = fw; 1585 end = fw + size; 1586 while (p < end) { 1587 if (p + 6 > end) 1588 return EINVAL; 1589 1590 dst = GETLE32(p); p += 4; 1591 len = GETLE16(p); p += 2; 1592 1593 if (p + len > end) 1594 return EINVAL; 1595 1596 ipw_write_mem_1(sc, dst, p, len); 1597 p += len; 1598 } 1599 return 0; 1600} 1601 1602int 1603ipw_firmware_init(struct ipw_softc *sc, u_char *data) 1604{ 1605 struct ieee80211com *ic = &sc->sc_ic; 1606 struct ifnet *ifp = &ic->ic_if; 1607 struct ipw_fw_hdr hdr; 1608 u_int32_t r, len, fw_size, uc_size; 1609 u_char *fw, *uc; 1610 int error; 1611 1612 ipw_reset(sc); 1613 1614 if ((error = copyin(data, &hdr, sizeof hdr)) != 0) 1615 goto fail1; 1616 1617 fw_size = letoh32(hdr.fw_size); 1618 uc_size = letoh32(hdr.uc_size); 1619 data += sizeof hdr; 1620 1621 if ((fw = malloc(fw_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1622 error = ENOMEM; 1623 goto fail1; 1624 } 1625 1626 if ((error = copyin(data, fw, fw_size)) != 0) 1627 goto fail2; 1628 1629 data += fw_size; 1630 1631 if ((uc = malloc(uc_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1632 error = ENOMEM; 1633 goto fail2; 1634 } 1635 1636 if ((error = copyin(data, uc, uc_size)) != 0) 1637 goto fail3; 1638 1639 if ((error = ipw_clock_sync(sc)) != 0) { 1640 printf("%s: clock synchronization failed\n", 1641 sc->sc_dev.dv_xname); 1642 goto fail3; 1643 } 1644 1645 MEM_WRITE_4(sc, 0x003000e0, 0x80000000); 1646 1647 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1648 1649 if ((error = ipw_load_ucode(sc, uc, uc_size)) != 0) { 1650 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 1651 goto fail3; 1652 } 1653 1654 MEM_WRITE_4(sc, 0x003000e0, 0); 1655 1656 if ((error = ipw_clock_sync(sc)) != 0) { 1657 printf("%s: clock synchronization failed\n", 1658 sc->sc_dev.dv_xname); 1659 goto fail3; 1660 } 1661 1662 if ((error = ipw_load_firmware(sc, fw, fw_size))) { 1663 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 1664 goto fail3; 1665 } 1666 1667 ipw_zero_mem_4(sc, 0x0002f200, 196); 1668 ipw_zero_mem_4(sc, 0x0002f610, 8); 1669 ipw_zero_mem_4(sc, 0x0002fa00, 8); 1670 ipw_zero_mem_4(sc, 0x0002fc00, 4); 1671 ipw_zero_mem_4(sc, 0x0002ff80, 32); 1672 1673 if ((error = ipw_rx_init(sc)) != 0) { 1674 printf("%s: could not initialize rx queue\n", 1675 sc->sc_dev.dv_xname); 1676 goto fail3; 1677 } 1678 1679 if ((error = ipw_tx_init(sc)) != 0) { 1680 printf("%s: could not initialize tx queue\n", 1681 sc->sc_dev.dv_xname); 1682 goto fail3; 1683 } 1684 1685 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1686 IPW_IO_LED_OFF); 1687 1688 /* Allow interrupts so we know when the firmware is inited */ 1689 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1690 1691 /* Tell the adapter to initialize the firmware */ 1692 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1693 1694 /* Wait at most one second for firmware initialization to complete */ 1695 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1696 printf("%s: timeout waiting for firmware initialization to " 1697 "complete\n", sc->sc_dev.dv_xname); 1698 goto fail3; 1699 } 1700 1701 /* Firmware initialization completed */ 1702 sc->flags |= IPW_FLAG_FW_INITED; 1703 1704 free(uc, M_DEVBUF); 1705 free(fw, M_DEVBUF); 1706 1707 r = CSR_READ_4(sc, IPW_CSR_IO); 1708 CSR_WRITE_4(sc, IPW_CSR_IO, r | IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1709 1710 /* Retrieve information tables base addresses */ 1711 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 1712 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 1713 1714 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 1715 1716 /* Retrieve adapter MAC address */ 1717 len = IEEE80211_ADDR_LEN; 1718 ipw_read_table2(sc, IPW_INFO_ADAPTER_MAC, ic->ic_myaddr, &len); 1719 1720 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1721 1722 return 0; 1723 1724fail3: free(uc, M_DEVBUF); 1725fail2: free(fw, M_DEVBUF); 1726fail1: ipw_reset(sc); 1727 1728 return error; 1729} 1730 1731int 1732ipw_config(struct ipw_softc *sc) 1733{ 1734 struct ieee80211com *ic = &sc->sc_ic; 1735 struct ifnet *ifp = &ic->ic_if; 1736 struct ipw_security security; 1737 struct ieee80211_wepkey *k; 1738 struct ipw_wep_key wepkey; 1739 struct ipw_scan_options options; 1740 struct ipw_configuration config; 1741 u_int32_t data; 1742 int error, i; 1743 1744 switch (ic->ic_opmode) { 1745 case IEEE80211_M_STA: 1746 case IEEE80211_M_HOSTAP: 1747 data = htole32(IPW_MODE_BSS); 1748 break; 1749 1750 case IEEE80211_M_IBSS: 1751 case IEEE80211_M_AHDEMO: 1752 data = htole32(IPW_MODE_IBSS); 1753 break; 1754 1755 case IEEE80211_M_MONITOR: 1756 data = htole32(IPW_MODE_MONITOR); 1757 break; 1758 } 1759 DPRINTF(("Setting adapter mode to %u\n", data)); 1760 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1761 if (error != 0) 1762 return error; 1763 1764 if (ic->ic_opmode == IEEE80211_M_IBSS || 1765 ic->ic_opmode == IEEE80211_M_MONITOR) { 1766 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1767 DPRINTF(("Setting adapter channel to %u\n", data)); 1768 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1769 if (error != 0) 1770 return error; 1771 } 1772 1773 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1774 DPRINTF(("Enabling adapter\n")); 1775 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1776 } 1777 1778 DPRINTF(("Setting adapter MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1779 IEEE80211_ADDR_COPY(((struct arpcom *)ifp)->ac_enaddr, ic->ic_myaddr); 1780 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1781 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1782 IEEE80211_ADDR_LEN); 1783 if (error != 0) 1784 return error; 1785 1786 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1787 IPW_CFG_PREAMBLE_LEN | IPW_CFG_802_1x_ENABLE); 1788 if (ic->ic_opmode == IEEE80211_M_IBSS) 1789 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1790 if (ifp->if_flags & IFF_PROMISC) 1791 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1792 config.channels = htole32(0x3fff); /* channels 1-14 */ 1793 config.ibss_chan = htole32(0x7ff); 1794 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1795 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1796 if (error != 0) 1797 return error; 1798 1799 data = htole32(0x3); /* 1, 2 */ 1800 DPRINTF(("Setting adapter basic tx rates to 0x%x\n", data)); 1801 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1802 if (error != 0) 1803 return error; 1804 1805 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1806 DPRINTF(("Setting adapter tx rates to 0x%x\n", data)); 1807 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1808 if (error != 0) 1809 return error; 1810 1811 data = htole32(IPW_POWER_MODE_CAM); 1812 DPRINTF(("Setting adapter power mode to %u\n", data)); 1813 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1814 if (error != 0) 1815 return error; 1816 1817 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1818 data = htole32(ic->ic_txpower); 1819 DPRINTF(("Setting adapter tx power index to %u\n", data)); 1820 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1821 sizeof data); 1822 if (error != 0) 1823 return error; 1824 } 1825 1826 data = htole32(ic->ic_rtsthreshold); 1827 DPRINTF(("Setting adapter RTS threshold to %u\n", data)); 1828 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1829 if (error != 0) 1830 return error; 1831 1832 data = htole32(ic->ic_fragthreshold); 1833 DPRINTF(("Setting adapter frag threshold to %u\n", data)); 1834 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1835 if (error != 0) 1836 return error; 1837 1838#ifdef IPW_DEBUG 1839 if (ipw_debug > 0) { 1840 printf("Setting adapter ESSID to "); 1841 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1842 printf("\n"); 1843 } 1844#endif 1845 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1846 ic->ic_des_esslen); 1847 if (error != 0) 1848 return error; 1849 1850 /* no mandatory BSSID */ 1851 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1852 if (error != 0) 1853 return error; 1854 1855 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1856 DPRINTF(("Setting adapter desired BSSID to %s\n", 1857 ether_sprintf(ic->ic_des_bssid))); 1858 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1859 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1860 if (error != 0) 1861 return error; 1862 } 1863 1864 security.authmode = (sc->authmode == IEEE80211_AUTH_SHARED) ? 1865 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 1866 security.ciphers = htole32(IPW_CIPHER_NONE); 1867 security.version = htole16(0); 1868 security.replay_counters_number = 0; 1869 security.unicast_using_group = 0; 1870 DPRINTF(("Setting adapter authmode to %u\n", security.authmode)); 1871 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1872 sizeof security); 1873 if (error != 0) 1874 return error; 1875 1876 if (ic->ic_flags & IEEE80211_F_WEPON) { 1877 k = ic->ic_nw_keys; 1878 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1879 if (k->wk_len == 0) 1880 continue; 1881 1882 wepkey.idx = i; 1883 wepkey.len = k->wk_len; 1884 bzero(wepkey.key, sizeof wepkey.key); 1885 bcopy(k->wk_key, wepkey.key, k->wk_len); 1886 DPRINTF(("Setting wep key index %d len %d\n", 1887 wepkey.idx, wepkey.len)); 1888 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1889 sizeof wepkey); 1890 if (error != 0) 1891 return error; 1892 } 1893 1894 data = htole32(ic->ic_wep_txkey); 1895 DPRINTF(("Setting adapter tx key index to %u\n", data)); 1896 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1897 sizeof data); 1898 if (error != 0) 1899 return error; 1900 } 1901 1902 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_WEPON) ? 0x8 : 0); 1903 DPRINTF(("Setting adapter wep flags to 0x%x\n", data)); 1904 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1905 if (error != 0) 1906 return error; 1907 1908 if (ic->ic_opmode == IEEE80211_M_IBSS || 1909 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1910 data = htole32(ic->ic_lintval); 1911 DPRINTF(("Setting adapter beacon interval to %u\n", data)); 1912 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1913 sizeof data); 1914 if (error != 0) 1915 return error; 1916 } 1917 1918 options.flags = htole32(0); 1919 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1920 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1921 if (error != 0) 1922 return error; 1923 1924 /* finally, enable adapter (start scanning for an access point) */ 1925 DPRINTF(("Enabling adapter\n")); 1926 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1927} 1928 1929int 1930ipw_init(struct ifnet *ifp) 1931{ 1932 struct ipw_softc *sc = ifp->if_softc; 1933 1934 /* exit immediately if firmware has not been ioctl'd */ 1935 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 1936 ifp->if_flags &= ~IFF_UP; 1937 return EIO; 1938 } 1939 1940 ipw_stop(ifp, 0); 1941 1942 if (ipw_config(sc) != 0) { 1943 printf("%s: device configuration failed\n", 1944 sc->sc_dev.dv_xname); 1945 goto fail; 1946 } 1947 1948 ifp->if_flags &= ~IFF_OACTIVE; 1949 ifp->if_flags |= IFF_RUNNING; 1950 1951 return 0; 1952 1953fail: ipw_stop(ifp, 0); 1954 1955 return EIO; 1956} 1957 1958void 1959ipw_stop(struct ifnet *ifp, int disable) 1960{ 1961 struct ipw_softc *sc = ifp->if_softc; 1962 struct ieee80211com *ic = &sc->sc_ic; 1963 1964 if (ifp->if_flags & IFF_RUNNING) { 1965 DPRINTF(("Disabling adapter\n")); 1966 ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1967 } 1968 1969 ifp->if_timer = 0; 1970 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1971 1972 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1973} 1974 1975void 1976ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1977 bus_size_t count) 1978{ 1979 for (; count > 0; offset++, datap++, count--) { 1980 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1981 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 1982 } 1983} 1984 1985void 1986ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1987 bus_size_t count) 1988{ 1989 for (; count > 0; offset++, datap++, count--) { 1990 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1991 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 1992 } 1993} 1994 1995void 1996ipw_zero_mem_4(struct ipw_softc *sc, bus_size_t offset, bus_size_t count) 1997{ 1998 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, offset); 1999 while (count-- > 0) 2000 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_DATA, 0); 2001} 2002 2003struct cfdriver ipw_cd = { 2004 0, "ipw", DV_IFNET 2005}; 2006