if_igc.h revision 1.1 
1/*	$OpenBSD: if_igc.h,v 1.1 2021/10/31 14:52:57 patrick Exp $	*/
2/*-
3 * SPDX-License-Identifier: BSD-2-Clause
4 *
5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
6 * All rights reserved.
7 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate)
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD$
31 */
32
33#ifndef _IGC_H_
34#define _IGC_H_
35
36#include <dev/pci/igc_api.h>
37#include <dev/pci/igc_i225.h>
38
39/*
40 * IGC_MAX_TXD: Maximum number of Transmit Descriptors
41 * Valid Range: 128-4096
42 * Default Value: 1024
43 *   This value is the number of transmit descriptors allocated by the driver.
44 *   Increasing this value allows the driver to queue more transmits. Each
45 *   descriptor is 16 bytes.
46 *   Since TDLEN should be multiple of 128bytes, the number of transmit
47 *   desscriptors should meet the following condition.
48 *      (num_tx_desc * sizeof(struct igc_tx_desc)) % 128 == 0
49 */
50#define IGC_MIN_TXD		128
51#define IGC_MAX_TXD		4096
52#define IGC_DEFAULT_TXD		1024
53#define IGC_DEFAULT_MULTI_TXD	4096
54#define IGC_MAX_TXD		4096
55
56/*
57 * IGC_MAX_RXD - Maximum number of receive Descriptors
58 * Valid Range: 128-4096
59 * Default Value: 1024
60 *   This value is the number of receive descriptors allocated by the driver.
61 *   Increasing this value allows the driver to buffer more incoming packets.
62 *   Each descriptor is 16 bytes.  A receive buffer is also allocated for each
63 *   descriptor. The maximum MTU size is 16110.
64 *   Since TDLEN should be multiple of 128bytes, the number of transmit
65 *   desscriptors should meet the following condition.
66 *      (num_tx_desc * sizeof(struct igc_tx_desc)) % 128 == 0
67 */
68#define IGC_MIN_RXD		128
69#define IGC_MAX_RXD		4096
70#define IGC_DEFAULT_RXD		1024
71#define IGC_DEFAULT_MULTI_RXD	4096
72#define IGC_MAX_RXD		4096
73
74/*
75 * IGC_TIDV_VAL - Transmit Interrupt Delay Value
76 * Valid Range: 0-65535 (0=off)
77 * Default Value: 64
78 *   This value delays the generation of transmit interrupts in units of
79 *   1.024 microseconds. Transmit interrupt reduction can improve CPU
80 *   efficiency if properly tuned for specific network traffic. If the
81 *   system is reporting dropped transmits, this value may be set too high
82 *   causing the driver to run out of available transmit descriptors.
83 */
84#define IGC_TIDV_VAL		64
85
86/*
87 * IGC_TADV_VAL - Transmit Absolute Interrupt Delay Value
88 * Valid Range: 0-65535 (0=off)
89 * Default Value: 64
90 *   This value, in units of 1.024 microseconds, limits the delay in which a
91 *   transmit interrupt is generated. Useful only if IGC_TIDV is non-zero,
92 *   this value ensures that an interrupt is generated after the initial
93 *   packet is sent on the wire within the set amount of time.  Proper tuning,
94 *   along with IGC_TIDV_VAL, may improve traffic throughput in specific
95 *   network conditions.
96 */
97#define IGC_TADV_VAL		64
98
99/*
100 * IGC_RDTR_VAL - Receive Interrupt Delay Timer (Packet Timer)
101 * Valid Range: 0-65535 (0=off)
102 * Default Value: 0
103 *   This value delays the generation of receive interrupts in units of 1.024
104 *   microseconds.  Receive interrupt reduction can improve CPU efficiency if
105 *   properly tuned for specific network traffic. Increasing this value adds
106 *   extra latency to frame reception and can end up decreasing the throughput
107 *   of TCP traffic. If the system is reporting dropped receives, this value
108 *   may be set too high, causing the driver to run out of available receive
109 *   descriptors.
110 *
111 *   CAUTION: When setting IGC_RDTR to a value other than 0, adapters
112 *            may hang (stop transmitting) under certain network conditions.
113 *            If this occurs a WATCHDOG message is logged in the system
114 *            event log. In addition, the controller is automatically reset,
115 *            restoring the network connection. To eliminate the potential
116 *            for the hang ensure that IGC_RDTR is set to 0.
117 */
118#define IGC_RDTR_VAL		0
119
120/*
121 * Receive Interrupt Absolute Delay Timer
122 * Valid Range: 0-65535 (0=off)
123 * Default Value: 64
124 *   This value, in units of 1.024 microseconds, limits the delay in which a
125 *   receive interrupt is generated. Useful only if IGC_RDTR is non-zero,
126 *   this value ensures that an interrupt is generated after the initial
127 *   packet is received within the set amount of time.  Proper tuning,
128 *   along with IGC_RDTR, may improve traffic throughput in specific network
129 *   conditions.
130 */
131#define IGC_RADV_VAL		64
132
133/*
134 * This parameter controls whether or not autonegotation is enabled.
135 *              0 - Disable autonegotiation
136 *              1 - Enable  autonegotiation
137 */
138#define DO_AUTO_NEG		true
139
140#define AUTONEG_ADV_DEFAULT						\
141	(ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF |	\
142	ADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL)
143
144#define AUTO_ALL_MODES		0
145
146/*
147 * Micellaneous constants
148 */
149#define MAX_NUM_MULTICAST_ADDRESSES	128
150#define IGC_FC_PAUSE_TIME		0x0680
151
152#define IGC_TXPBSIZE		20408
153#define IGC_PKTTYPE_MASK	0x0000FFF0
154#define IGC_DMCTLX_DCFLUSH_DIS	0x80000000	/* Disable DMA Coalesce Flush */
155
156#define IGC_RX_PTHRESH		8
157#define IGC_RX_HTHRESH		8
158#define IGC_RX_WTHRESH		4
159
160#define IGC_TX_PTHRESH		8
161#define IGC_TX_HTHRESH		1
162
163/*
164 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
165 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
166 * also optimize cache line size effect. H/W supports up to cache line size 128.
167 */
168#define IGC_DBA_ALIGN		128
169
170/*
171 * This parameter controls the duration of transmit watchdog timer.
172 */
173#define IGC_TX_TIMEOUT		5	/* set to 5 seconds */
174
175#define IGC_PCIREG		PCI_MAPREG_START
176
177#define IGC_MAX_VECTORS		8
178
179/* Enable/disable debugging statements in shared code */
180#define DBG	0
181
182#define DEBUGOUT(...)							\
183	do { if (DBG) printf(__VA_ARGS__); } while (0)
184#define DEBUGOUT1(...)		DEBUGOUT(__VA_ARGS__)
185#define DEBUGOUT2(...)		DEBUGOUT(__VA_ARGS__)
186#define DEBUGOUT3(...)		DEBUGOUT(__VA_ARGS__)
187#define DEBUGOUT7(...)		DEBUGOUT(__VA_ARGS__)
188#define DEBUGFUNC(F)		DEBUGOUT(F "\n")
189
190/* Compatibility glue. */
191#define roundup2(size, unit)	(((size) + (unit) - 1) & ~((unit) - 1))
192#define msec_delay(x)		DELAY(1000 * (x))
193
194#define IGC_MAX_SCATTER		40
195#define IGC_TSO_SIZE		65535
196
197#define MAX_INTS_PER_SEC	8000
198#define DEFAULT_ITR		(1000000000/(MAX_INTS_PER_SEC * 256))
199
200/* Forward declaration. */
201struct igc_hw;
202
203struct igc_osdep {
204	bus_dma_tag_t		os_dmat;
205	bus_space_tag_t		os_memt;
206	bus_space_handle_t	os_memh;
207
208	bus_size_t		os_memsize;
209	bus_addr_t		os_membase;
210
211	void			*os_sc;
212	struct pci_attach_args	os_pa;
213};
214
215
216struct igc_tx_buf {
217	uint32_t	eop_index;
218	struct mbuf	*m_head;
219	bus_dmamap_t	map;
220};
221
222struct igc_rx_buf {
223	struct mbuf	*buf;
224	struct mbuf	*fmp;	/* First mbuf pointers. */
225	bus_dmamap_t	map;
226};
227
228/*
229 * Bus dma allocation structure used by igc_dma_malloc and igc_dma_free.
230 */
231struct igc_dma_alloc {
232	caddr_t			dma_vaddr;
233	bus_dma_tag_t		dma_tag;
234	bus_dmamap_t		dma_map;
235	bus_dma_segment_t	dma_seg;
236	bus_size_t		dma_size;
237	int			dma_nseg;
238};
239
240/*
241 * Driver queue struct: this is the interrupt container
242 * for the associated tx and rx ring.
243 */
244struct igc_queue {
245	struct igc_softc	*sc;
246	uint32_t		msix;
247	uint32_t		eims;
248	uint32_t		eitr_setting;
249	char			name[16];
250	pci_intr_handle_t	ih;
251	void			*tag;
252	struct tx_ring		*txr;
253	struct rx_ring		*rxr;
254};
255
256/*
257 * The transmit ring, one per tx queue.
258 */
259struct tx_ring {
260	struct igc_softc	*sc;
261	struct ifqueue		*ifq;
262	uint32_t		me;
263	uint32_t		watchdog_timer;
264	union igc_adv_tx_desc	*tx_base;
265	struct igc_tx_buf	*tx_buffers;
266	struct igc_dma_alloc	txdma;
267	uint32_t		next_avail_desc;
268	uint32_t		next_to_clean;
269	bus_dma_tag_t		txtag;
270};
271
272/*
273 * The Receive ring, one per rx queue.
274 */
275struct rx_ring {
276	struct igc_softc	*sc;
277	struct ifiqueue		*ifiq;
278	uint32_t		me;
279	union igc_adv_rx_desc	*rx_base;
280	struct igc_rx_buf	*rx_buffers;
281	struct igc_dma_alloc	rxdma;
282	uint32_t		last_desc_filled;
283	uint32_t		next_to_check;
284	struct timeout		rx_refill;
285	struct if_rxring	rx_ring;
286};
287
288/* Our adapter structure. */
289struct igc_softc {
290	struct device		sc_dev;
291	struct arpcom		sc_ac;
292	struct ifmedia		media;
293	struct intrmap		*sc_intrmap;
294
295	struct igc_osdep	osdep;
296	struct igc_hw		hw;
297
298	uint16_t		fc;
299	uint16_t		link_active;
300	uint16_t		link_speed;
301	uint16_t		link_duplex;
302	uint32_t		dmac;
303
304	void			*tag;
305
306	int			num_tx_desc;
307	int			num_rx_desc;
308
309	uint32_t		max_frame_size;
310	uint32_t		rx_mbuf_sz;
311	uint32_t		linkvec;
312	uint32_t		msix_linkmask;
313	uint32_t		msix_queuesmask;
314
315	unsigned int		sc_nqueues;
316	struct igc_queue	*queues;
317
318	struct tx_ring		*tx_rings;
319	struct rx_ring		*rx_rings;
320
321	/* Multicast array memory */
322	uint8_t			*mta;
323};
324
325#define DEVNAME(_sc)    ((_sc)->sc_dev.dv_xname)
326
327/* Register READ/WRITE macros */
328#define IGC_WRITE_FLUSH(a)	IGC_READ_REG(a, IGC_STATUS)
329#define IGC_READ_REG(a, reg)						\
330        bus_space_read_4(((struct igc_osdep *)(a)->back)->os_memt,	\
331        ((struct igc_osdep *)(a)->back)->os_memh, reg)
332#define IGC_WRITE_REG(a, reg, value)					\
333        bus_space_write_4(((struct igc_osdep *)(a)->back)->os_memt,	\
334        ((struct igc_osdep *)(a)->back)->os_memh, reg, value)
335#define IGC_READ_REG_ARRAY(a, reg, off)					\
336        bus_space_read_4(((struct igc_osdep *)(a)->back)->os_memt,	\
337        ((struct igc_osdep *)(a)->back)->os_memh, (reg + ((off) << 2)))
338#define IGC_WRITE_REG_ARRAY(a, reg, off, value)				\
339        bus_space_write_4(((struct igc_osdep *)(a)->back)->os_memt,	\
340        ((struct igc_osdep *)(a)->back)->os_memh,			\
341	(reg + ((off) << 2)),value)
342
343#endif /* _IGC_H_ */
344