if_casvar.h revision 1.3
1/* $OpenBSD: if_casvar.h,v 1.3 2007/02/27 21:19:40 kettenis Exp $ */ 2 3/* 4 * 5 * Copyright (C) 2007 Mark Kettenis. 6 * Copyright (C) 2001 Eduardo Horvath. 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33#ifndef _IF_CASVAR_H 34#define _IF_CASVAR_H 35 36#include <sys/queue.h> 37#include <sys/timeout.h> 38 39/* 40 * Misc. definitions for Sun Cassini ethernet controllers. 41 */ 42 43/* 44 * Transmit descriptor ring size. This is arbitrary, but allocate 45 * enough descriptors for 64 pending transmissions and 16 segments 46 * per packet. 47 */ 48#define CAS_NTXSEGS 16 49 50#define CAS_TXQUEUELEN 64 51#define CAS_NTXDESC (CAS_TXQUEUELEN * CAS_NTXSEGS) 52#define CAS_NTXDESC_MASK (CAS_NTXDESC - 1) 53#define CAS_NEXTTX(x) ((x + 1) & CAS_NTXDESC_MASK) 54 55struct cas_sxd { 56 struct mbuf *sd_mbuf; 57 bus_dmamap_t sd_map; 58}; 59 60/* 61 * Receive descriptor ring size. We have one Rx buffer per incoming 62 * packet, so this logic is a little simpler. 63 */ 64#define CAS_NRXDESC 128 65#define CAS_NRXDESC_MASK (CAS_NRXDESC - 1) 66 67/* 68 * Receive completion ring size. 69 */ 70#define CAS_NRXCOMP 256 71#define CAS_NRXCOMP_MASK (CAS_NRXCOMP - 1) 72#define CAS_NEXTRX(x) ((x + 1) & CAS_NRXCOMP_MASK) 73 74/* 75 * Control structures are DMA'd to the Cassini chip. We allocate them in 76 * a single clump that maps to a single DMA segment to make several things 77 * easier. 78 */ 79struct cas_control_data { 80 /* 81 * The transmit descriptors. 82 */ 83 struct cas_desc ccd_txdescs[CAS_NTXDESC]; 84 85 /* 86 * The receive completions. 87 */ 88 struct cas_comp ccd_rxcomps[CAS_NRXCOMP]; 89 90 /* 91 * The receive descriptors. 92 */ 93 struct cas_desc ccd_rxdescs[CAS_NRXDESC]; 94}; 95 96#define CAS_CDOFF(x) offsetof(struct cas_control_data, x) 97#define CAS_CDTXOFF(x) CAS_CDOFF(ccd_txdescs[(x)]) 98#define CAS_CDRXOFF(x) CAS_CDOFF(ccd_rxdescs[(x)]) 99#define CAS_CDRXCOFF(x) CAS_CDOFF(ccd_rxcomps[(x)]) 100 101/* 102 * Software state for receive jobs. 103 */ 104struct cas_rxsoft { 105 bus_dmamap_t rxs_dmamap; /* our DMA map */ 106 bus_dma_segment_t rxs_dmaseg; /* our DMA segment */ 107 caddr_t rxs_kva; 108}; 109 110/* 111 * Software state per device. 112 */ 113struct cas_softc { 114 struct device sc_dev; /* generic device information */ 115 struct arpcom sc_arpcom; /* ethernet common data */ 116 struct mii_data sc_mii; /* MII media control */ 117#define sc_media sc_mii.mii_media/* shorthand */ 118 struct timeout sc_tick_ch; /* tick callout */ 119 120 bus_space_tag_t sc_memt; 121 bus_space_handle_t sc_memh; 122 void *sc_ih; 123 124 bus_dma_tag_t sc_dmatag; /* bus dma tag */ 125 bus_dmamap_t sc_dmamap; /* bus dma handle */ 126 int sc_burst; /* DVMA burst size in effect */ 127 int sc_phys[2]; /* MII instance -> PHY map */ 128 129 int sc_if_flags; 130 131 int sc_mif_config; /* Selected MII reg setting */ 132 133 /* 134 * Ring buffer DMA stuff. 135 */ 136 bus_dma_segment_t sc_cdseg; /* control data memory */ 137 int sc_cdnseg; /* number of segments */ 138 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 139#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 140 141 /* 142 * Software state for transmit and receive descriptors. 143 */ 144 struct cas_sxd sc_txd[CAS_NTXDESC]; 145 u_int32_t sc_tx_cnt, sc_tx_prod, sc_tx_cons; 146 147 struct cas_rxsoft sc_rxsoft[CAS_NRXDESC]; 148 149 /* 150 * Control data structures. 151 */ 152 struct cas_control_data *sc_control_data; 153#define sc_txdescs sc_control_data->ccd_txdescs 154#define sc_rxdescs sc_control_data->ccd_rxdescs 155#define sc_rxcomps sc_control_data->ccd_rxcomps 156 157 int sc_rxptr; /* next ready RX descriptor/descsoft */ 158 int sc_rxfifosize; 159 int sc_rxdptr; 160 161 /* ========== */ 162 int sc_inited; 163 int sc_debug; 164 void *sc_sh; /* shutdownhook cookie */ 165}; 166 167#define CAS_DMA_READ(v) letoh64(v) 168#define CAS_DMA_WRITE(v) htole64(v) 169 170/* 171 * This macro returns the current media entry for *non-MII* media. 172 */ 173#define CAS_CURRENT_MEDIA(sc) \ 174 (IFM_SUBTYPE((sc)->sc_mii.mii_media.ifm_cur->ifm_media) != IFM_AUTO ? \ 175 (sc)->sc_mii.mii_media.ifm_cur : (sc)->sc_nway_active) 176 177/* 178 * This macro determines if a change to media-related OPMODE bits requires 179 * a chip reset. 180 */ 181#define CAS_MEDIA_NEEDSRESET(sc, newbits) \ 182 (((sc)->sc_opmode & OPMODE_MEDIA_BITS) != \ 183 ((newbits) & OPMODE_MEDIA_BITS)) 184 185#define CAS_CDTXADDR(sc, x) ((sc)->sc_cddma + CAS_CDTXOFF((x))) 186#define CAS_CDRXADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXOFF((x))) 187#define CAS_CDRXCADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXCOFF((x))) 188 189#define CAS_CDTXSYNC(sc, x, n, ops) \ 190do { \ 191 int __x, __n; \ 192 \ 193 __x = (x); \ 194 __n = (n); \ 195 \ 196 /* If it will wrap around, sync to the end of the ring. */ \ 197 if ((__x + __n) > CAS_NTXDESC) { \ 198 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 199 CAS_CDTXOFF(__x), sizeof(struct cas_desc) * \ 200 (CAS_NTXDESC - __x), (ops)); \ 201 __n -= (CAS_NTXDESC - __x); \ 202 __x = 0; \ 203 } \ 204 \ 205 /* Now sync whatever is left. */ \ 206 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 207 CAS_CDTXOFF(__x), sizeof(struct cas_desc) * __n, (ops)); \ 208} while (0) 209 210#define CAS_CDRXSYNC(sc, x, ops) \ 211 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 212 CAS_CDRXOFF((x)), sizeof(struct cas_desc), (ops)) 213 214#define CAS_CDRXCSYNC(sc, x, ops) \ 215 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 216 CAS_CDRXCOFF((x)), sizeof(struct cas_desc), (ops)) 217 218#define CAS_INIT_RXDESC(sc, d, s) \ 219do { \ 220 struct cas_rxsoft *__rxs = &sc->sc_rxsoft[(s)]; \ 221 struct cas_desc *__rxd = &sc->sc_rxdescs[(d)]; \ 222 \ 223 __rxd->cd_addr = \ 224 CAS_DMA_WRITE(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 225 __rxd->cd_flags = \ 226 CAS_DMA_WRITE((s)); \ 227 CAS_CDRXSYNC((sc), (d), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 228} while (0) 229 230#endif 231