if_casvar.h revision 1.1
1/* $OpenBSD: if_casvar.h,v 1.1 2007/02/24 20:13:34 kettenis Exp $ */ 2 3/* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32#ifndef _IF_CASVAR_H 33#define _IF_CASVAR_H 34 35#include <sys/queue.h> 36#include <sys/timeout.h> 37 38/* 39 * Misc. definitions for Sun Cassini ethernet controllers. 40 */ 41 42/* 43 * Transmit descriptor list size. This is arbitrary, but allocate 44 * enough descriptors for 64 pending transmissions and 16 segments 45 * per packet. 46 */ 47#define CAS_NTXSEGS 16 48 49#define CAS_TXQUEUELEN 64 50#define CAS_NTXDESC (CAS_TXQUEUELEN * CAS_NTXSEGS) 51#define CAS_NTXDESC_MASK (CAS_NTXDESC - 1) 52#define CAS_NEXTTX(x) ((x + 1) & CAS_NTXDESC_MASK) 53 54struct cas_sxd { 55 struct mbuf *sd_mbuf; 56 bus_dmamap_t sd_map; 57}; 58 59/* 60 * Receive descriptor list size. We have one Rx buffer per incoming 61 * packet, so this logic is a little simpler. 62 */ 63#define CAS_NRXDESC 128 64#define CAS_NRXDESC_MASK (CAS_NRXDESC - 1) 65#define CAS_NEXTRX(x) ((x + 1) & CAS_NRXDESC_MASK) 66 67/* 68 * Control structures are DMA'd to the GEM chip. We allocate them in 69 * a single clump that maps to a single DMA segment to make several things 70 * easier. 71 */ 72struct cas_control_data { 73 /* 74 * The transmit descriptors. 75 */ 76 struct cas_desc gcd_txdescs[CAS_NTXDESC]; 77 78 /* 79 * The receive descriptors. 80 */ 81 struct cas_desc gcd_rxdescs[CAS_NRXDESC]; 82}; 83 84#define CAS_CDOFF(x) offsetof(struct cas_control_data, x) 85#define CAS_CDTXOFF(x) CAS_CDOFF(gcd_txdescs[(x)]) 86#define CAS_CDRXOFF(x) CAS_CDOFF(gcd_rxdescs[(x)]) 87 88/* 89 * Software state for receive jobs. 90 */ 91struct cas_rxsoft { 92 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 93 bus_dmamap_t rxs_dmamap; /* our DMA map */ 94}; 95 96 97/* 98 * Table which describes the transmit threshold mode. We generally 99 * start at index 0. Whenever we get a transmit underrun, we increment 100 * our index, falling back if we encounter the NULL terminator. 101 */ 102struct cas_txthresh_tab { 103 u_int32_t txth_opmode; /* OPMODE bits */ 104 const char *txth_name; /* name of mode */ 105}; 106 107/* 108 * Some misc. statics, useful for debugging. 109 */ 110struct cas_stats { 111 u_long ts_tx_uf; /* transmit underflow errors */ 112 u_long ts_tx_to; /* transmit jabber timeouts */ 113 u_long ts_tx_ec; /* excessive collision count */ 114 u_long ts_tx_lc; /* late collision count */ 115}; 116 117/* 118 * Software state per device. 119 */ 120struct cas_softc { 121 struct device sc_dev; /* generic device information */ 122 struct arpcom sc_arpcom; /* ethernet common data */ 123 struct mii_data sc_mii; /* MII media control */ 124#define sc_media sc_mii.mii_media/* shorthand */ 125 struct timeout sc_tick_ch; /* tick callout */ 126 127 bus_space_tag_t sc_memt; 128 bus_space_handle_t sc_memh; 129 void *sc_ih; 130 131 bus_dma_tag_t sc_dmatag; /* bus dma tag */ 132 bus_dmamap_t sc_dmamap; /* bus dma handle */ 133 int sc_burst; /* DVMA burst size in effect */ 134 int sc_phys[2]; /* MII instance -> PHY map */ 135 136 int sc_if_flags; 137 138 int sc_mif_config; /* Selected MII reg setting */ 139 140 void *sc_sdhook; /* shutdown hook */ 141 void *sc_powerhook; /* power management hook */ 142 143 struct cas_stats sc_stats; /* debugging stats */ 144 145 /* 146 * Ring buffer DMA stuff. 147 */ 148 bus_dma_segment_t sc_cdseg; /* control data memory */ 149 int sc_cdnseg; /* number of segments */ 150 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 151#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 152 153 /* 154 * Software state for transmit and receive descriptors. 155 */ 156 struct cas_sxd sc_txd[CAS_NTXDESC]; 157 u_int32_t sc_tx_cnt, sc_tx_prod, sc_tx_cons; 158 159 struct cas_rxsoft sc_rxsoft[CAS_NRXDESC]; 160 161 /* 162 * Control data structures. 163 */ 164 struct cas_control_data *sc_control_data; 165#define sc_txdescs sc_control_data->gcd_txdescs 166#define sc_rxdescs sc_control_data->gcd_rxdescs 167 168 int sc_txfree; /* number of free Tx descriptors */ 169 int sc_txnext; /* next ready Tx descriptor */ 170 171 u_int32_t sc_tdctl_ch; /* conditional desc chaining */ 172 u_int32_t sc_tdctl_er; /* conditional desc end-of-ring */ 173 174 u_int32_t sc_setup_fsls; /* FS|LS on setup descriptor */ 175 176 int sc_rxptr; /* next ready RX descriptor/descsoft */ 177 int sc_rxfifosize; 178 179 /* ========== */ 180 int sc_inited; 181 int sc_debug; 182 void *sc_sh; /* shutdownhook cookie */ 183}; 184 185#define CAS_DMA_READ(sc, v) letoh64(v) 186#define CAS_DMA_WRITE(sc, v) htole64(v) 187 188/* 189 * This macro returns the current media entry for *non-MII* media. 190 */ 191#define CAS_CURRENT_MEDIA(sc) \ 192 (IFM_SUBTYPE((sc)->sc_mii.mii_media.ifm_cur->ifm_media) != IFM_AUTO ? \ 193 (sc)->sc_mii.mii_media.ifm_cur : (sc)->sc_nway_active) 194 195/* 196 * This macro determines if a change to media-related OPMODE bits requires 197 * a chip reset. 198 */ 199#define CAS_MEDIA_NEEDSRESET(sc, newbits) \ 200 (((sc)->sc_opmode & OPMODE_MEDIA_BITS) != \ 201 ((newbits) & OPMODE_MEDIA_BITS)) 202 203#define CAS_CDTXADDR(sc, x) ((sc)->sc_cddma + CAS_CDTXOFF((x))) 204#define CAS_CDRXADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXOFF((x))) 205 206#define CAS_CDSPADDR(sc) ((sc)->sc_cddma + CAS_CDSPOFF) 207 208#define CAS_CDTXSYNC(sc, x, n, ops) \ 209do { \ 210 int __x, __n; \ 211 \ 212 __x = (x); \ 213 __n = (n); \ 214 \ 215 /* If it will wrap around, sync to the end of the ring. */ \ 216 if ((__x + __n) > CAS_NTXDESC) { \ 217 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 218 CAS_CDTXOFF(__x), sizeof(struct cas_desc) * \ 219 (CAS_NTXDESC - __x), (ops)); \ 220 __n -= (CAS_NTXDESC - __x); \ 221 __x = 0; \ 222 } \ 223 \ 224 /* Now sync whatever is left. */ \ 225 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 226 CAS_CDTXOFF(__x), sizeof(struct cas_desc) * __n, (ops)); \ 227} while (0) 228 229#define CAS_CDRXSYNC(sc, x, ops) \ 230 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 231 CAS_CDRXOFF((x)), sizeof(struct cas_desc), (ops)) 232 233#define CAS_CDSPSYNC(sc, ops) \ 234 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 235 CAS_CDSPOFF, CAS_SETUP_PACKET_LEN, (ops)) 236 237#define CAS_INIT_RXDESC(sc, x) \ 238do { \ 239 struct cas_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 240 struct cas_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 241 struct mbuf *__m = __rxs->rxs_mbuf; \ 242 \ 243 __m->m_data = __m->m_ext.ext_buf; \ 244 __rxd->gd_addr = \ 245 CAS_DMA_WRITE((sc), __rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 246 __rxd->gd_flags = \ 247 CAS_DMA_WRITE((sc), \ 248 (((__m->m_ext.ext_size)<<CAS_RD_BUFSHIFT) \ 249 & CAS_RD_BUFSIZE) | CAS_RD_OWN); \ 250 CAS_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 251} while (0) 252 253#ifdef _KERNEL 254int cas_mediachange(struct ifnet *); 255void cas_mediastatus(struct ifnet *, struct ifmediareq *); 256 257void cas_config(struct cas_softc *); 258void cas_reset(struct cas_softc *); 259int cas_intr(void *); 260#endif /* _KERNEL */ 261 262 263#endif 264