if_bnxreg.h revision 1.4
1/* $OpenBSD: if_bnxreg.h,v 1.4 2006/08/09 16:13:06 brad Exp $ */ 2 3/*- 4 * Copyright (c) 2006 Broadcom Corporation 5 * David Christensen <davidch@broadcom.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written consent. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.4 2006/05/04 00:34:07 mjacob Exp $ 32 */ 33 34#ifndef _BNX_H_DEFINED 35#define _BNX_H_DEFINED 36 37#include "bpfilter.h" 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/sockio.h> 42#include <sys/mbuf.h> 43#include <sys/malloc.h> 44#include <sys/kernel.h> 45#include <sys/device.h> 46#include <sys/socket.h> 47#include <sys/timeout.h> 48 49#include <net/if.h> 50#include <net/if_dl.h> 51#include <net/if_media.h> 52 53#ifdef INET 54#include <netinet/in.h> 55#include <netinet/in_systm.h> 56#include <netinet/in_var.h> 57#include <netinet/ip.h> 58#include <netinet/if_ether.h> 59#endif 60 61#if NVLAN > 0 62#include <net/if_types.h> 63#include <net/if_vlan_var.h> 64#endif 65 66#if NBPFILTER > 0 67#include <net/bpf.h> 68#endif 69 70#include <dev/pci/pcireg.h> 71#include <dev/pci/pcivar.h> 72#include <dev/pci/pcidevs.h> 73 74#include <dev/mii/mii.h> 75#include <dev/mii/miivar.h> 76#include <dev/mii/miidevs.h> 77#include <dev/mii/brgphyreg.h> 78 79/****************************************************************************/ 80/* Conversion to OpenBSD type definitions. */ 81/****************************************************************************/ 82#define u64 uint64_t 83#define u32 uint32_t 84#define u16 uint16_t 85#define u8 uint8_t 86 87#if BYTE_ORDER == BIG_ENDIAN 88#define __BIG_ENDIAN 1 89#undef __LITTLE_ENDIAN 90#else 91#undef __BIG_ENDIAN 92#define __LITTLE_ENDIAN 1 93#endif 94 95/****************************************************************************/ 96/* Debugging macros and definitions. */ 97/****************************************************************************/ 98#define BNX_CP_LOAD 0x00000001 99#define BNX_CP_SEND 0x00000002 100#define BNX_CP_RECV 0x00000004 101#define BNX_CP_INTR 0x00000008 102#define BNX_CP_UNLOAD 0x00000010 103#define BNX_CP_RESET 0x00000020 104#define BNX_CP_ALL 0x00FFFFFF 105 106#define BNX_CP_MASK 0x00FFFFFF 107 108#define BNX_LEVEL_FATAL 0x00000000 109#define BNX_LEVEL_WARN 0x01000000 110#define BNX_LEVEL_INFO 0x02000000 111#define BNX_LEVEL_VERBOSE 0x03000000 112#define BNX_LEVEL_EXCESSIVE 0x04000000 113 114#define BNX_LEVEL_MASK 0xFF000000 115 116#define BNX_WARN_LOAD (BNX_CP_LOAD | BNX_LEVEL_WARN) 117#define BNX_INFO_LOAD (BNX_CP_LOAD | BNX_LEVEL_INFO) 118#define BNX_VERBOSE_LOAD (BNX_CP_LOAD | BNX_LEVEL_VERBOSE) 119#define BNX_EXCESSIVE_LOAD (BNX_CP_LOAD | BNX_LEVEL_EXCESSIVE) 120 121#define BNX_WARN_SEND (BNX_CP_SEND | BNX_LEVEL_WARN) 122#define BNX_INFO_SEND (BNX_CP_SEND | BNX_LEVEL_INFO) 123#define BNX_VERBOSE_SEND (BNX_CP_SEND | BNX_LEVEL_VERBOSE) 124#define BNX_EXCESSIVE_SEND (BNX_CP_SEND | BNX_LEVEL_EXCESSIVE) 125 126#define BNX_WARN_RECV (BNX_CP_RECV | BNX_LEVEL_WARN) 127#define BNX_INFO_RECV (BNX_CP_RECV | BNX_LEVEL_INFO) 128#define BNX_VERBOSE_RECV (BNX_CP_RECV | BNX_LEVEL_VERBOSE) 129#define BNX_EXCESSIVE_RECV (BNX_CP_RECV | BNX_LEVEL_EXCESSIVE) 130 131#define BNX_WARN_INTR (BNX_CP_INTR | BNX_LEVEL_WARN) 132#define BNX_INFO_INTR (BNX_CP_INTR | BNX_LEVEL_INFO) 133#define BNX_VERBOSE_INTR (BNX_CP_INTR | BNX_LEVEL_VERBOSE) 134#define BNX_EXCESSIVE_INTR (BNX_CP_INTR | BNX_LEVEL_EXCESSIVE) 135 136#define BNX_WARN_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_WARN) 137#define BNX_INFO_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_INFO) 138#define BNX_VERBOSE_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_VERBOSE) 139#define BNX_EXCESSIVE_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_EXCESSIVE) 140 141#define BNX_WARN_RESET (BNX_CP_RESET | BNX_LEVEL_WARN) 142#define BNX_INFO_RESET (BNX_CP_RESET | BNX_LEVEL_INFO) 143#define BNX_VERBOSE_RESET (BNX_CP_RESET | BNX_LEVEL_VERBOSE) 144#define BNX_EXCESSIVE_RESET (BNX_CP_RESET | BNX_LEVEL_EXCESSIVE) 145 146#define BNX_FATAL (BNX_CP_ALL | BNX_LEVEL_FATAL) 147#define BNX_WARN (BNX_CP_ALL | BNX_LEVEL_WARN) 148#define BNX_INFO (BNX_CP_ALL | BNX_LEVEL_INFO) 149#define BNX_VERBOSE (BNX_CP_ALL | BNX_LEVEL_VERBOSE) 150#define BNX_EXCESSIVE (BNX_CP_ALL | BNX_LEVEL_EXCESSIVE) 151 152#define BNX_CODE_PATH(cp) ((cp & BNX_CP_MASK) & bnx_debug) 153#define BNX_MSG_LEVEL(lv) ((lv & BNX_LEVEL_MASK) <= (bnx_debug & BNX_LEVEL_MASK)) 154#define BNX_LOG_MSG(m) (BNX_CODE_PATH(m) && BNX_MSG_LEVEL(m)) 155 156#ifdef BNX_DEBUG 157 158/* Print a message based on the logging level and code path. */ 159#define DBPRINT(sc, level, format, args...) \ 160 if (BNX_LOG_MSG(level)) { \ 161 printf("%s: " format, sc->bnx_dev.dv_xname, ## args); \ 162 } 163 164/* Runs a particular command based on the logging level and code path. */ 165#define DBRUN(m, args...) \ 166 if (BNX_LOG_MSG(m)) { \ 167 args; \ 168 } 169 170/* Runs a particular command based on the logging level. */ 171#define DBRUNLV(level, args...) \ 172 if (BNX_MSG_LEVEL(level)) { \ 173 args; \ 174 } 175 176/* Runs a particular command based on the code path. */ 177#define DBRUNCP(cp, args...) \ 178 if (BNX_CODE_PATH(cp)) { \ 179 args; \ 180 } 181 182/* Runs a particular command based on a condition. */ 183#define DBRUNIF(cond, args...) \ 184 if (cond) { \ 185 args; \ 186 } 187#if 0 188/* Needed for random() function which is only used in debugging. */ 189#include <sys/random.h> 190#endif 191 192/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */ 193#define DB_RANDOMFALSE(defects) (random() > defects) 194#define DB_OR_RANDOMFALSE(defects) || (random() > defects) 195#define DB_AND_RANDOMFALSE(defects) && (random() > ddfects) 196 197/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */ 198#define DB_RANDOMTRUE(defects) (random() < defects) 199#define DB_OR_RANDOMTRUE(defects) || (random() < defects) 200#define DB_AND_RANDOMTRUE(defects) && (random() < defects) 201 202#else 203 204#define DBPRINT(level, format, args...) 205#define DBRUN(m, args...) 206#define DBRUNLV(level, args...) 207#define DBRUNCP(cp, args...) 208#define DBRUNIF(cond, args...) 209#define DB_RANDOMFALSE(defects) 210#define DB_OR_RANDOMFALSE(percent) 211#define DB_AND_RANDOMFALSE(percent) 212#define DB_RANDOMTRUE(defects) 213#define DB_OR_RANDOMTRUE(percent) 214#define DB_AND_RANDOMTRUE(percent) 215 216#endif /* BNX_DEBUG */ 217 218 219/****************************************************************************/ 220/* Device identification definitions. */ 221/****************************************************************************/ 222#define BRCM_VENDORID 0x14E4 223#define BRCM_DEVICEID_BCM5706 0x164A 224#define BRCM_DEVICEID_BCM5706S 0x16AA 225#define BRCM_DEVICEID_BCM5708 0x164C 226#define BRCM_DEVICEID_BCM5708S 0x16AC 227 228#define HP_VENDORID 0x103C 229 230#define PCI_ANY_ID (u_int16_t) (~0U) 231 232/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 233 234#define BNX_CHIP_NUM(sc) (((sc)->bnx_chipid) & 0xffff0000) 235#define BNX_CHIP_NUM_5706 0x57060000 236#define BNX_CHIP_NUM_5708 0x57080000 237 238#define BNX_CHIP_REV(sc) (((sc)->bnx_chipid) & 0x0000f000) 239#define BNX_CHIP_REV_Ax 0x00000000 240#define BNX_CHIP_REV_Bx 0x00001000 241#define BNX_CHIP_REV_Cx 0x00002000 242 243#define BNX_CHIP_METAL(sc) (((sc)->bnx_chipid) & 0x00000ff0) 244#define BNX_CHIP_BOND(bp) (((sc)->bnx_chipid) & 0x0000000f) 245 246#define BNX_CHIP_ID(sc) (((sc)->bnx_chipid) & 0xfffffff0) 247#define BNX_CHIP_ID_5706_A0 0x57060000 248#define BNX_CHIP_ID_5706_A1 0x57060010 249#define BNX_CHIP_ID_5706_A2 0x57060020 250#define BNX_CHIP_ID_5708_A0 0x57080000 251#define BNX_CHIP_ID_5708_B0 0x57081000 252#define BNX_CHIP_ID_5708_B1 0x57081010 253 254#define BNX_CHIP_BOND_ID(sc) (((sc)->bnx_chipid) & 0xf) 255 256/* A serdes chip will have the first bit of the bond id set. */ 257#define BNX_CHIP_BOND_ID_SERDES_BIT 0x01 258 259 260/* shorthand one */ 261#define BNX_ASICREV(x) ((x) >> 28) 262#define BNX_ASICREV_BCM5700 0x06 263 264/* chip revisions */ 265#define BNX_CHIPREV(x) ((x) >> 24) 266#define BNX_CHIPREV_5700_AX 0x70 267#define BNX_CHIPREV_5700_BX 0x71 268#define BNX_CHIPREV_5700_CX 0x72 269#define BNX_CHIPREV_5701_AX 0x00 270 271struct bnx_type { 272 u_int16_t bnx_vid; 273 u_int16_t bnx_did; 274 u_int16_t bnx_svid; 275 u_int16_t bnx_sdid; 276 char *bnx_name; 277}; 278 279/****************************************************************************/ 280/* Byte order conversions. */ 281/****************************************************************************/ 282#define bnx_htobe16(x) htobe16(x) 283#define bnx_htobe32(x) htobe32(x) 284#define bnx_htobe64(x) htobe64(x) 285#define bnx_htole16(x) htole16(x) 286#define bnx_htole32(x) htole32(x) 287#define bnx_htole64(x) htole64(x) 288 289#define bnx_be16toh(x) betoh16(x) 290#define bnx_be32toh(x) betoh32(x) 291#define bnx_be64toh(x) betoh64(x) 292#define bnx_le16toh(x) letoh16(x) 293#define bnx_le32toh(x) letoh32(x) 294#define bnx_le64toh(x) letoh64(x) 295 296 297/****************************************************************************/ 298/* NVRAM Access */ 299/****************************************************************************/ 300 301/* Buffered flash (Atmel: AT45DB011B) specific information */ 302#define SEEPROM_PAGE_BITS 2 303#define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) 304#define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) 305#define SEEPROM_PAGE_SIZE 4 306#define SEEPROM_TOTAL_SIZE 65536 307 308#define BUFFERED_FLASH_PAGE_BITS 9 309#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) 310#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) 311#define BUFFERED_FLASH_PAGE_SIZE 264 312#define BUFFERED_FLASH_TOTAL_SIZE 0x21000 313 314#define SAIFUN_FLASH_PAGE_BITS 8 315#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) 316#define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) 317#define SAIFUN_FLASH_PAGE_SIZE 256 318#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 319 320#define ST_MICRO_FLASH_PAGE_BITS 8 321#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS) 322#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) 323#define ST_MICRO_FLASH_PAGE_SIZE 256 324#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 325 326#define NVRAM_TIMEOUT_COUNT 30000 327#define BNX_FLASHDESC_MAX 64 328 329#define FLASH_STRAP_MASK (BNX_NVM_CFG1_FLASH_MODE | \ 330 BNX_NVM_CFG1_BUFFER_MODE | \ 331 BNX_NVM_CFG1_PROTECT_MODE | \ 332 BNX_NVM_CFG1_FLASH_SIZE) 333 334#define FLASH_BACKUP_STRAP_MASK (0xf << 26) 335 336struct flash_spec { 337 u32 strapping; 338 u32 config1; 339 u32 config2; 340 u32 config3; 341 u32 write1; 342 u32 buffered; 343 u32 page_bits; 344 u32 page_size; 345 u32 addr_mask; 346 u32 total_size; 347 u8 *name; 348}; 349 350 351/****************************************************************************/ 352/* Shared Memory layout */ 353/* The BNX bootcode will initialize this data area with port configurtion */ 354/* information which can be accessed by the driver. */ 355/****************************************************************************/ 356 357/* 358 * This value (in milliseconds) determines the frequency of the driver 359 * issuing the PULSE message code. The firmware monitors this periodic 360 * pulse to determine when to switch to an OS-absent mode. 361 */ 362#define DRV_PULSE_PERIOD_MS 250 363 364/* 365 * This value (in milliseconds) determines how long the driver should 366 * wait for an acknowledgement from the firmware before timing out. Once 367 * the firmware has timed out, the driver will assume there is no firmware 368 * running and there won't be any firmware-driver synchronization during a 369 * driver reset. 370 */ 371#define FW_ACK_TIME_OUT_MS 100 372 373 374#define BNX_DRV_RESET_SIGNATURE 0x00000000 375#define BNX_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */ 376 377#define BNX_DRV_MB 0x00000004 378#define BNX_DRV_MSG_CODE 0xff000000 379#define BNX_DRV_MSG_CODE_RESET 0x01000000 380#define BNX_DRV_MSG_CODE_UNLOAD 0x02000000 381#define BNX_DRV_MSG_CODE_SHUTDOWN 0x03000000 382#define BNX_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 383#define BNX_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 384#define BNX_DRV_MSG_CODE_PULSE 0x06000000 385#define BNX_DRV_MSG_CODE_DIAG 0x07000000 386#define BNX_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 387 388#define BNX_DRV_MSG_DATA 0x00ff0000 389#define BNX_DRV_MSG_DATA_WAIT0 0x00010000 390#define BNX_DRV_MSG_DATA_WAIT1 0x00020000 391#define BNX_DRV_MSG_DATA_WAIT2 0x00030000 392#define BNX_DRV_MSG_DATA_WAIT3 0x00040000 393 394#define BNX_DRV_MSG_SEQ 0x0000ffff 395 396#define BNX_FW_MB 0x00000008 397#define BNX_FW_MSG_ACK 0x0000ffff 398#define BNX_FW_MSG_STATUS_MASK 0x00ff0000 399#define BNX_FW_MSG_STATUS_OK 0x00000000 400#define BNX_FW_MSG_STATUS_FAILURE 0x00ff0000 401 402#define BNX_LINK_STATUS 0x0000000c 403#define BNX_LINK_STATUS_INIT_VALUE 0xffffffff 404#define BNX_LINK_STATUS_LINK_UP 0x1 405#define BNX_LINK_STATUS_LINK_DOWN 0x0 406#define BNX_LINK_STATUS_SPEED_MASK 0x1e 407#define BNX_LINK_STATUS_AN_INCOMPLETE (0<<1) 408#define BNX_LINK_STATUS_10HALF (1<<1) 409#define BNX_LINK_STATUS_10FULL (2<<1) 410#define BNX_LINK_STATUS_100HALF (3<<1) 411#define BNX_LINK_STATUS_100BASE_T4 (4<<1) 412#define BNX_LINK_STATUS_100FULL (5<<1) 413#define BNX_LINK_STATUS_1000HALF (6<<1) 414#define BNX_LINK_STATUS_1000FULL (7<<1) 415#define BNX_LINK_STATUS_2500HALF (8<<1) 416#define BNX_LINK_STATUS_2500FULL (9<<1) 417#define BNX_LINK_STATUS_AN_ENABLED (1<<5) 418#define BNX_LINK_STATUS_AN_COMPLETE (1<<6) 419#define BNX_LINK_STATUS_PARALLEL_DET (1<<7) 420#define BNX_LINK_STATUS_RESERVED (1<<8) 421#define BNX_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) 422#define BNX_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) 423#define BNX_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) 424#define BNX_LINK_STATUS_PARTNER_AD_100FULL (1<<12) 425#define BNX_LINK_STATUS_PARTNER_AD_100HALF (1<<13) 426#define BNX_LINK_STATUS_PARTNER_AD_10FULL (1<<14) 427#define BNX_LINK_STATUS_PARTNER_AD_10HALF (1<<15) 428#define BNX_LINK_STATUS_TX_FC_ENABLED (1<<16) 429#define BNX_LINK_STATUS_RX_FC_ENABLED (1<<17) 430#define BNX_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) 431#define BNX_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) 432#define BNX_LINK_STATUS_SERDES_LINK (1<<20) 433#define BNX_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) 434#define BNX_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) 435 436#define BNX_DRV_PULSE_MB 0x00000010 437#define BNX_DRV_PULSE_SEQ_MASK 0x00007fff 438 439/* Indicate to the firmware not to go into the 440 * OS absent when it is not getting driver pulse. 441 * This is used for debugging. */ 442#define BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 443 444#define BNX_DEV_INFO_SIGNATURE 0x00000020 445#define BNX_DEV_INFO_SIGNATURE_MAGIC 0x44564900 446#define BNX_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 447#define BNX_DEV_INFO_FEATURE_CFG_VALID 0x01 448#define BNX_DEV_INFO_SECONDARY_PORT 0x80 449#define BNX_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 450 451#define BNX_SHARED_HW_CFG_PART_NUM 0x00000024 452 453#define BNX_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034 454#define BNX_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 455#define BNX_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 456#define BNX_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 457#define BNX_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff 458 459#define BNX_SHARED_HW_CFG_POWER_CONSUMED 0x00000038 460#define BNX_SHARED_HW_CFG_CONFIG 0x0000003c 461#define BNX_SHARED_HW_CFG_DESIGN_NIC 0 462#define BNX_SHARED_HW_CFG_DESIGN_LOM 0x1 463#define BNX_SHARED_HW_CFG_PHY_COPPER 0 464#define BNX_SHARED_HW_CFG_PHY_FIBER 0x2 465#define BNX_SHARED_HW_CFG_PHY_2_5G 0x20 466#define BNX_SHARED_HW_CFG_PHY_BACKPLANE 0x40 467#define BNX_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 468#define BNX_SHARED_HW_CFG_LED_MODE_MASK 0x300 469#define BNX_SHARED_HW_CFG_LED_MODE_MAC 0 470#define BNX_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 471#define BNX_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 472 473#define BNX_SHARED_HW_CFG_CONFIG2 0x00000040 474#define BNX_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000 475 476#define BNX_DEV_INFO_BC_REV 0x0000004c 477 478#define BNX_PORT_HW_CFG_MAC_UPPER 0x00000050 479#define BNX_PORT_HW_CFG_UPPERMAC_MASK 0xffff 480 481#define BNX_PORT_HW_CFG_MAC_LOWER 0x00000054 482#define BNX_PORT_HW_CFG_CONFIG 0x00000058 483#define BNX_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff 484#define BNX_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 485#define BNX_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 486#define BNX_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 487#define BNX_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000 488 489#define BNX_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 490#define BNX_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c 491#define BNX_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070 492#define BNX_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074 493#define BNX_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078 494#define BNX_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c 495 496#define BNX_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4 497 498#define BNX_DEV_INFO_FORMAT_REV 0x000000c4 499#define BNX_DEV_INFO_FORMAT_REV_MASK 0xff000000 500#define BNX_DEV_INFO_FORMAT_REV_ID ('A' << 24) 501 502#define BNX_SHARED_FEATURE 0x000000c8 503#define BNX_SHARED_FEATURE_MASK 0xffffffff 504 505#define BNX_PORT_FEATURE 0x000000d8 506#define BNX_PORT2_FEATURE 0x00000014c 507#define BNX_PORT_FEATURE_WOL_ENABLED 0x01000000 508#define BNX_PORT_FEATURE_MBA_ENABLED 0x02000000 509#define BNX_PORT_FEATURE_ASF_ENABLED 0x04000000 510#define BNX_PORT_FEATURE_IMD_ENABLED 0x08000000 511#define BNX_PORT_FEATURE_BAR1_SIZE_MASK 0xf 512#define BNX_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 513#define BNX_PORT_FEATURE_BAR1_SIZE_64K 0x1 514#define BNX_PORT_FEATURE_BAR1_SIZE_128K 0x2 515#define BNX_PORT_FEATURE_BAR1_SIZE_256K 0x3 516#define BNX_PORT_FEATURE_BAR1_SIZE_512K 0x4 517#define BNX_PORT_FEATURE_BAR1_SIZE_1M 0x5 518#define BNX_PORT_FEATURE_BAR1_SIZE_2M 0x6 519#define BNX_PORT_FEATURE_BAR1_SIZE_4M 0x7 520#define BNX_PORT_FEATURE_BAR1_SIZE_8M 0x8 521#define BNX_PORT_FEATURE_BAR1_SIZE_16M 0x9 522#define BNX_PORT_FEATURE_BAR1_SIZE_32M 0xa 523#define BNX_PORT_FEATURE_BAR1_SIZE_64M 0xb 524#define BNX_PORT_FEATURE_BAR1_SIZE_128M 0xc 525#define BNX_PORT_FEATURE_BAR1_SIZE_256M 0xd 526#define BNX_PORT_FEATURE_BAR1_SIZE_512M 0xe 527#define BNX_PORT_FEATURE_BAR1_SIZE_1G 0xf 528 529#define BNX_PORT_FEATURE_WOL 0xdc 530#define BNX_PORT2_FEATURE_WOL 0x150 531#define BNX_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4 532#define BNX_PORT_FEATURE_WOL_DEFAULT_MASK 0x30 533#define BNX_PORT_FEATURE_WOL_DEFAULT_DISABLE 0 534#define BNX_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10 535#define BNX_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20 536#define BNX_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 537#define BNX_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf 538#define BNX_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0 539#define BNX_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1 540#define BNX_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2 541#define BNX_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3 542#define BNX_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4 543#define BNX_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5 544#define BNX_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6 545#define BNX_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 546#define BNX_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 547#define BNX_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 548 549#define BNX_PORT_FEATURE_MBA 0xe0 550#define BNX_PORT2_FEATURE_MBA 0x154 551#define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 552#define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3 553#define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 554#define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 555#define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 556#define BNX_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 557#define BNX_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c 558#define BNX_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0 559#define BNX_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4 560#define BNX_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8 561#define BNX_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc 562#define BNX_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10 563#define BNX_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14 564#define BNX_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18 565#define BNX_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 566#define BNX_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0 567#define BNX_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80 568#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 569#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 570#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 571#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 572#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 573#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 574#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 575#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 576#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 577#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 578#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 579#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 580#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 581#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 582#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 583#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 584#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 585#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 586#define BNX_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 587#define BNX_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 588#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 589#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 590#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 591#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 592#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 593#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 594 595#define BNX_PORT_FEATURE_IMD 0xe4 596#define BNX_PORT2_FEATURE_IMD 0x158 597#define BNX_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0 598#define BNX_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1 599 600#define BNX_PORT_FEATURE_VLAN 0xe8 601#define BNX_PORT2_FEATURE_VLAN 0x15c 602#define BNX_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff 603#define BNX_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 604 605#define BNX_BC_STATE_RESET_TYPE 0x000001c0 606#define BNX_BC_STATE_RESET_TYPE_SIG 0x00005254 607#define BNX_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff 608#define BNX_BC_STATE_RESET_TYPE_NONE (BNX_BC_STATE_RESET_TYPE_SIG | \ 609 0x00010000) 610#define BNX_BC_STATE_RESET_TYPE_PCI (BNX_BC_STATE_RESET_TYPE_SIG | \ 611 0x00020000) 612#define BNX_BC_STATE_RESET_TYPE_VAUX (BNX_BC_STATE_RESET_TYPE_SIG | \ 613 0x00030000) 614#define BNX_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE 615#define BNX_BC_STATE_RESET_TYPE_DRV_RESET (BNX_BC_STATE_RESET_TYPE_SIG | \ 616 DRV_MSG_CODE_RESET) 617#define BNX_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX_BC_STATE_RESET_TYPE_SIG | \ 618 DRV_MSG_CODE_UNLOAD) 619#define BNX_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX_BC_STATE_RESET_TYPE_SIG | \ 620 DRV_MSG_CODE_SHUTDOWN) 621#define BNX_BC_STATE_RESET_TYPE_DRV_WOL (BNX_BC_STATE_RESET_TYPE_SIG | \ 622 DRV_MSG_CODE_WOL) 623#define BNX_BC_STATE_RESET_TYPE_DRV_DIAG (BNX_BC_STATE_RESET_TYPE_SIG | \ 624 DRV_MSG_CODE_DIAG) 625#define BNX_BC_STATE_RESET_TYPE_VALUE(msg) (BNX_BC_STATE_RESET_TYPE_SIG | \ 626 (msg)) 627 628#define BNX_BC_STATE 0x000001c4 629#define BNX_BC_STATE_ERR_MASK 0x0000ff00 630#define BNX_BC_STATE_SIGN 0x42530000 631#define BNX_BC_STATE_SIGN_MASK 0xffff0000 632#define BNX_BC_STATE_BC1_START (BNX_BC_STATE_SIGN | 0x1) 633#define BNX_BC_STATE_GET_NVM_CFG1 (BNX_BC_STATE_SIGN | 0x2) 634#define BNX_BC_STATE_PROG_BAR (BNX_BC_STATE_SIGN | 0x3) 635#define BNX_BC_STATE_INIT_VID (BNX_BC_STATE_SIGN | 0x4) 636#define BNX_BC_STATE_GET_NVM_CFG2 (BNX_BC_STATE_SIGN | 0x5) 637#define BNX_BC_STATE_APPLY_WKARND (BNX_BC_STATE_SIGN | 0x6) 638#define BNX_BC_STATE_LOAD_BC2 (BNX_BC_STATE_SIGN | 0x7) 639#define BNX_BC_STATE_GOING_BC2 (BNX_BC_STATE_SIGN | 0x8) 640#define BNX_BC_STATE_GOING_DIAG (BNX_BC_STATE_SIGN | 0x9) 641#define BNX_BC_STATE_RT_FINAL_INIT (BNX_BC_STATE_SIGN | 0x81) 642#define BNX_BC_STATE_RT_WKARND (BNX_BC_STATE_SIGN | 0x82) 643#define BNX_BC_STATE_RT_DRV_PULSE (BNX_BC_STATE_SIGN | 0x83) 644#define BNX_BC_STATE_RT_FIOEVTS (BNX_BC_STATE_SIGN | 0x84) 645#define BNX_BC_STATE_RT_DRV_CMD (BNX_BC_STATE_SIGN | 0x85) 646#define BNX_BC_STATE_RT_LOW_POWER (BNX_BC_STATE_SIGN | 0x86) 647#define BNX_BC_STATE_RT_SET_WOL (BNX_BC_STATE_SIGN | 0x87) 648#define BNX_BC_STATE_RT_OTHER_FW (BNX_BC_STATE_SIGN | 0x88) 649#define BNX_BC_STATE_RT_GOING_D3 (BNX_BC_STATE_SIGN | 0x89) 650#define BNX_BC_STATE_ERR_BAD_VERSION (BNX_BC_STATE_SIGN | 0x0100) 651#define BNX_BC_STATE_ERR_BAD_BC2_CRC (BNX_BC_STATE_SIGN | 0x0200) 652#define BNX_BC_STATE_ERR_BC1_LOOP (BNX_BC_STATE_SIGN | 0x0300) 653#define BNX_BC_STATE_ERR_UNKNOWN_CMD (BNX_BC_STATE_SIGN | 0x0400) 654#define BNX_BC_STATE_ERR_DRV_DEAD (BNX_BC_STATE_SIGN | 0x0500) 655#define BNX_BC_STATE_ERR_NO_RXP (BNX_BC_STATE_SIGN | 0x0600) 656#define BNX_BC_STATE_ERR_TOO_MANY_RBUF (BNX_BC_STATE_SIGN | 0x0700) 657 658#define BNX_BC_STATE_DEBUG_CMD 0x1dc 659#define BNX_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 660#define BNX_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 661#define BNX_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff 662#define BNX_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff 663 664#define HOST_VIEW_SHMEM_BASE 0x167c00 665 666/* 667 * PCI registers defined in the PCI 2.2 spec. 668 */ 669#define BNX_PCI_BAR0 0x10 670#define BNX_PCI_PCIX_CMD 0x42 671 672/****************************************************************************/ 673/* Convenience definitions. */ 674/****************************************************************************/ 675#define BNX_PRINTF(sc, fmt, args...) printf("%s: " fmt, sc->bnx_dev.dv_xname, ##args) 676 677#define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val) 678#define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val) 679#define REG_RD(sc, reg) bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg) 680#define REG_RD_IND(sc, offset) bnx_reg_rd_ind(sc, offset) 681#define REG_WR_IND(sc, offset, val) bnx_reg_wr_ind(sc, offset, val) 682#define CTX_WR(sc, cid_addr, offset, val) bnx_ctx_wr(sc, cid_addr, offset, val) 683#define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) 684#define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) 685#define PCI_SETBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 686#define PCI_CLRBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 687 688#define BNX_STATS(x) (u_long) stats->stat_ ## x ## _lo 689 690#ifdef __LP64__ 691#define BNX_ADDR_LO(y) ((u64)(y) & 0xffffffff) 692#define BNX_ADDR_HI(y) ((u64)(y) >> 32) 693#else 694#define BNX_ADDR_LO(y) ((u32)(y)) 695#define BNX_ADDR_HI(y) ((u32)0) 696#endif 697 698/* 699 * The following data structures are generated from RTL code. 700 * Do not modify any values below this line. 701 */ 702 703/****************************************************************************/ 704/* Do not modify any of the following data structures, they are generated */ 705/* from RTL code. */ 706/* */ 707/* Begin machine generated definitions. */ 708/****************************************************************************/ 709 710/* 711 * tx_bd definition 712 */ 713struct tx_bd { 714 u32 tx_bd_haddr_hi; 715 u32 tx_bd_haddr_lo; 716 u32 tx_bd_mss_nbytes; 717 u32 tx_bd_vlan_tag_flags; 718 #define TX_BD_FLAGS_CONN_FAULT (1<<0) 719 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) 720 #define TX_BD_FLAGS_IP_CKSUM (1<<2) 721 #define TX_BD_FLAGS_VLAN_TAG (1<<3) 722 #define TX_BD_FLAGS_COAL_NOW (1<<4) 723 #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) 724 #define TX_BD_FLAGS_END (1<<6) 725 #define TX_BD_FLAGS_START (1<<7) 726 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) 727 #define TX_BD_FLAGS_SW_FLAGS (1<<13) 728 #define TX_BD_FLAGS_SW_SNAP (1<<14) 729 #define TX_BD_FLAGS_SW_LSO (1<<15) 730 731}; 732 733 734/* 735 * rx_bd definition 736 */ 737struct rx_bd { 738 u32 rx_bd_haddr_hi; 739 u32 rx_bd_haddr_lo; 740 u32 rx_bd_len; 741 u32 rx_bd_flags; 742 #define RX_BD_FLAGS_NOPUSH (1<<0) 743 #define RX_BD_FLAGS_DUMMY (1<<1) 744 #define RX_BD_FLAGS_END (1<<2) 745 #define RX_BD_FLAGS_START (1<<3) 746 747}; 748 749 750/* 751 * status_block definition 752 */ 753struct status_block { 754 u32 status_attn_bits; 755 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) 756 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) 757 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) 758 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) 759 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) 760 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) 761 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) 762 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) 763 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) 764 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) 765 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) 766 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) 767 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) 768 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) 769 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) 770 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) 771 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) 772 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) 773 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) 774 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) 775 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) 776 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) 777 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) 778 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) 779 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) 780 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) 781 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) 782 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) 783 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) 784 785 u32 status_attn_bits_ack; 786#if defined(__BIG_ENDIAN) 787 u16 status_tx_quick_consumer_index0; 788 u16 status_tx_quick_consumer_index1; 789 u16 status_tx_quick_consumer_index2; 790 u16 status_tx_quick_consumer_index3; 791 u16 status_rx_quick_consumer_index0; 792 u16 status_rx_quick_consumer_index1; 793 u16 status_rx_quick_consumer_index2; 794 u16 status_rx_quick_consumer_index3; 795 u16 status_rx_quick_consumer_index4; 796 u16 status_rx_quick_consumer_index5; 797 u16 status_rx_quick_consumer_index6; 798 u16 status_rx_quick_consumer_index7; 799 u16 status_rx_quick_consumer_index8; 800 u16 status_rx_quick_consumer_index9; 801 u16 status_rx_quick_consumer_index10; 802 u16 status_rx_quick_consumer_index11; 803 u16 status_rx_quick_consumer_index12; 804 u16 status_rx_quick_consumer_index13; 805 u16 status_rx_quick_consumer_index14; 806 u16 status_rx_quick_consumer_index15; 807 u16 status_completion_producer_index; 808 u16 status_cmd_consumer_index; 809 u16 status_idx; 810 u16 status_unused; 811#elif defined(__LITTLE_ENDIAN) 812 u16 status_tx_quick_consumer_index1; 813 u16 status_tx_quick_consumer_index0; 814 u16 status_tx_quick_consumer_index3; 815 u16 status_tx_quick_consumer_index2; 816 u16 status_rx_quick_consumer_index1; 817 u16 status_rx_quick_consumer_index0; 818 u16 status_rx_quick_consumer_index3; 819 u16 status_rx_quick_consumer_index2; 820 u16 status_rx_quick_consumer_index5; 821 u16 status_rx_quick_consumer_index4; 822 u16 status_rx_quick_consumer_index7; 823 u16 status_rx_quick_consumer_index6; 824 u16 status_rx_quick_consumer_index9; 825 u16 status_rx_quick_consumer_index8; 826 u16 status_rx_quick_consumer_index11; 827 u16 status_rx_quick_consumer_index10; 828 u16 status_rx_quick_consumer_index13; 829 u16 status_rx_quick_consumer_index12; 830 u16 status_rx_quick_consumer_index15; 831 u16 status_rx_quick_consumer_index14; 832 u16 status_cmd_consumer_index; 833 u16 status_completion_producer_index; 834 u16 status_unused; 835 u16 status_idx; 836#endif 837}; 838 839 840/* 841 * statistics_block definition 842 */ 843struct statistics_block { 844 u32 stat_IfHCInOctets_hi; 845 u32 stat_IfHCInOctets_lo; 846 u32 stat_IfHCInBadOctets_hi; 847 u32 stat_IfHCInBadOctets_lo; 848 u32 stat_IfHCOutOctets_hi; 849 u32 stat_IfHCOutOctets_lo; 850 u32 stat_IfHCOutBadOctets_hi; 851 u32 stat_IfHCOutBadOctets_lo; 852 u32 stat_IfHCInUcastPkts_hi; 853 u32 stat_IfHCInUcastPkts_lo; 854 u32 stat_IfHCInMulticastPkts_hi; 855 u32 stat_IfHCInMulticastPkts_lo; 856 u32 stat_IfHCInBroadcastPkts_hi; 857 u32 stat_IfHCInBroadcastPkts_lo; 858 u32 stat_IfHCOutUcastPkts_hi; 859 u32 stat_IfHCOutUcastPkts_lo; 860 u32 stat_IfHCOutMulticastPkts_hi; 861 u32 stat_IfHCOutMulticastPkts_lo; 862 u32 stat_IfHCOutBroadcastPkts_hi; 863 u32 stat_IfHCOutBroadcastPkts_lo; 864 u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 865 u32 stat_Dot3StatsCarrierSenseErrors; 866 u32 stat_Dot3StatsFCSErrors; 867 u32 stat_Dot3StatsAlignmentErrors; 868 u32 stat_Dot3StatsSingleCollisionFrames; 869 u32 stat_Dot3StatsMultipleCollisionFrames; 870 u32 stat_Dot3StatsDeferredTransmissions; 871 u32 stat_Dot3StatsExcessiveCollisions; 872 u32 stat_Dot3StatsLateCollisions; 873 u32 stat_EtherStatsCollisions; 874 u32 stat_EtherStatsFragments; 875 u32 stat_EtherStatsJabbers; 876 u32 stat_EtherStatsUndersizePkts; 877 u32 stat_EtherStatsOverrsizePkts; 878 u32 stat_EtherStatsPktsRx64Octets; 879 u32 stat_EtherStatsPktsRx65Octetsto127Octets; 880 u32 stat_EtherStatsPktsRx128Octetsto255Octets; 881 u32 stat_EtherStatsPktsRx256Octetsto511Octets; 882 u32 stat_EtherStatsPktsRx512Octetsto1023Octets; 883 u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; 884 u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; 885 u32 stat_EtherStatsPktsTx64Octets; 886 u32 stat_EtherStatsPktsTx65Octetsto127Octets; 887 u32 stat_EtherStatsPktsTx128Octetsto255Octets; 888 u32 stat_EtherStatsPktsTx256Octetsto511Octets; 889 u32 stat_EtherStatsPktsTx512Octetsto1023Octets; 890 u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; 891 u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; 892 u32 stat_XonPauseFramesReceived; 893 u32 stat_XoffPauseFramesReceived; 894 u32 stat_OutXonSent; 895 u32 stat_OutXoffSent; 896 u32 stat_FlowControlDone; 897 u32 stat_MacControlFramesReceived; 898 u32 stat_XoffStateEntered; 899 u32 stat_IfInFramesL2FilterDiscards; 900 u32 stat_IfInRuleCheckerDiscards; 901 u32 stat_IfInFTQDiscards; 902 u32 stat_IfInMBUFDiscards; 903 u32 stat_IfInRuleCheckerP4Hit; 904 u32 stat_CatchupInRuleCheckerDiscards; 905 u32 stat_CatchupInFTQDiscards; 906 u32 stat_CatchupInMBUFDiscards; 907 u32 stat_CatchupInRuleCheckerP4Hit; 908 u32 stat_GenStat00; 909 u32 stat_GenStat01; 910 u32 stat_GenStat02; 911 u32 stat_GenStat03; 912 u32 stat_GenStat04; 913 u32 stat_GenStat05; 914 u32 stat_GenStat06; 915 u32 stat_GenStat07; 916 u32 stat_GenStat08; 917 u32 stat_GenStat09; 918 u32 stat_GenStat10; 919 u32 stat_GenStat11; 920 u32 stat_GenStat12; 921 u32 stat_GenStat13; 922 u32 stat_GenStat14; 923 u32 stat_GenStat15; 924}; 925 926 927/* 928 * l2_fhdr definition 929 */ 930struct l2_fhdr { 931 u32 l2_fhdr_status; 932 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) 933 #define L2_FHDR_STATUS_RULE_P2 (1<<3) 934 #define L2_FHDR_STATUS_RULE_P3 (1<<4) 935 #define L2_FHDR_STATUS_RULE_P4 (1<<5) 936 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) 937 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) 938 #define L2_FHDR_STATUS_RSS_HASH (1<<8) 939 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) 940 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) 941 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) 942 943 #define L2_FHDR_ERRORS_BAD_CRC (1<<17) 944 #define L2_FHDR_ERRORS_PHY_DECODE (1<<18) 945 #define L2_FHDR_ERRORS_ALIGNMENT (1<<19) 946 #define L2_FHDR_ERRORS_TOO_SHORT (1<<20) 947 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) 948 #define L2_FHDR_ERRORS_TCP_XSUM (1<<28) 949 #define L2_FHDR_ERRORS_UDP_XSUM (1<<31) 950 951 u32 l2_fhdr_hash; 952#if defined(__BIG_ENDIAN) 953 u16 l2_fhdr_pkt_len; 954 u16 l2_fhdr_vlan_tag; 955 u16 l2_fhdr_ip_xsum; 956 u16 l2_fhdr_tcp_udp_xsum; 957#elif defined(__LITTLE_ENDIAN) 958 u16 l2_fhdr_vlan_tag; 959 u16 l2_fhdr_pkt_len; 960 u16 l2_fhdr_tcp_udp_xsum; 961 u16 l2_fhdr_ip_xsum; 962#endif 963}; 964 965 966/* 967 * l2_context definition 968 */ 969#define BNX_L2CTX_TYPE 0x00000000 970#define BNX_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) 971#define BNX_L2CTX_TYPE_TYPE (0xf<<28) 972#define BNX_L2CTX_TYPE_TYPE_EMPTY (0<<28) 973#define BNX_L2CTX_TYPE_TYPE_L2 (1<<28) 974 975#define BNX_L2CTX_TX_HOST_BIDX 0x00000088 976#define BNX_L2CTX_EST_NBD 0x00000088 977#define BNX_L2CTX_CMD_TYPE 0x00000088 978#define BNX_L2CTX_CMD_TYPE_TYPE (0xf<<24) 979#define BNX_L2CTX_CMD_TYPE_TYPE_L2 (0<<24) 980#define BNX_L2CTX_CMD_TYPE_TYPE_TCP (1<<24) 981 982#define BNX_L2CTX_TX_HOST_BSEQ 0x00000090 983#define BNX_L2CTX_TSCH_BSEQ 0x00000094 984#define BNX_L2CTX_TBDR_BSEQ 0x00000098 985#define BNX_L2CTX_TBDR_BOFF 0x0000009c 986#define BNX_L2CTX_TBDR_BIDX 0x0000009c 987#define BNX_L2CTX_TBDR_BHADDR_HI 0x000000a0 988#define BNX_L2CTX_TBDR_BHADDR_LO 0x000000a4 989#define BNX_L2CTX_TXP_BOFF 0x000000a8 990#define BNX_L2CTX_TXP_BIDX 0x000000a8 991#define BNX_L2CTX_TXP_BSEQ 0x000000ac 992 993 994/* 995 * l2_bd_chain_context definition 996 */ 997#define BNX_L2CTX_BD_PRE_READ 0x00000000 998#define BNX_L2CTX_CTX_SIZE 0x00000000 999#define BNX_L2CTX_CTX_TYPE 0x00000000 1000#define BNX_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) 1001#define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) 1002#define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) 1003#define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) 1004 1005#define BNX_L2CTX_HOST_BDIDX 0x00000004 1006#define BNX_L2CTX_HOST_BSEQ 0x00000008 1007#define BNX_L2CTX_NX_BSEQ 0x0000000c 1008#define BNX_L2CTX_NX_BDHADDR_HI 0x00000010 1009#define BNX_L2CTX_NX_BDHADDR_LO 0x00000014 1010#define BNX_L2CTX_NX_BDIDX 0x00000018 1011 1012 1013/* 1014 * pci_config_l definition 1015 * offset: 0000 1016 */ 1017#define BNX_PCICFG_MISC_CONFIG 0x00000068 1018#define BNX_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) 1019#define BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) 1020#define BNX_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) 1021#define BNX_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) 1022#define BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) 1023#define BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) 1024#define BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) 1025#define BNX_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) 1026#define BNX_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) 1027#define BNX_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) 1028#define BNX_PCICFG_MISC_CONFIG_ASIC_REV (0xffffL<<16) 1029 1030#define BNX_PCICFG_MISC_STATUS 0x0000006c 1031#define BNX_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0) 1032#define BNX_PCICFG_MISC_STATUS_32BIT_DET (1L<<1) 1033#define BNX_PCICFG_MISC_STATUS_M66EN (1L<<2) 1034#define BNX_PCICFG_MISC_STATUS_PCIX_DET (1L<<3) 1035#define BNX_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4) 1036#define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4) 1037#define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) 1038#define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) 1039#define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) 1040 1041#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 1042#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1043#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1044#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1045#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1046#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1047#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1048#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1049#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1050#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1051#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1052#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1053#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1054#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1055#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1056#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1057#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1058#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1059#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1060#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1061#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1062#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1063#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1064#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1065#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1066#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1067#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1068#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1069#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1070#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1071 1072#define BNX_PCICFG_REG_WINDOW_ADDRESS 0x00000078 1073#define BNX_PCICFG_REG_WINDOW 0x00000080 1074#define BNX_PCICFG_INT_ACK_CMD 0x00000084 1075#define BNX_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) 1076#define BNX_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) 1077#define BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) 1078#define BNX_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) 1079 1080#define BNX_PCICFG_STATUS_BIT_SET_CMD 0x00000088 1081#define BNX_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c 1082#define BNX_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090 1083#define BNX_PCICFG_MAILBOX_QUEUE_DATA 0x00000094 1084 1085 1086/* 1087 * pci_reg definition 1088 * offset: 0x400 1089 */ 1090#define BNX_PCI_GRC_WINDOW_ADDR 0x00000400 1091#define BNX_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8) 1092 1093#define BNX_PCI_CONFIG_1 0x00000404 1094#define BNX_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) 1095#define BNX_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) 1096#define BNX_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) 1097#define BNX_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8) 1098#define BNX_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8) 1099#define BNX_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8) 1100#define BNX_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8) 1101#define BNX_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8) 1102#define BNX_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8) 1103#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11) 1104#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11) 1105#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11) 1106#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11) 1107#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11) 1108#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11) 1109#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) 1110#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) 1111#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) 1112 1113#define BNX_PCI_CONFIG_2 0x00000408 1114#define BNX_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 1115#define BNX_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 1116#define BNX_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 1117#define BNX_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 1118#define BNX_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 1119#define BNX_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 1120#define BNX_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 1121#define BNX_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 1122#define BNX_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 1123#define BNX_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 1124#define BNX_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 1125#define BNX_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 1126#define BNX_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 1127#define BNX_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 1128#define BNX_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 1129#define BNX_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 1130#define BNX_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 1131#define BNX_PCI_CONFIG_2_BAR1_64ENA (1L<<4) 1132#define BNX_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 1133#define BNX_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 1134#define BNX_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 1135#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 1136#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 1137#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8) 1138#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8) 1139#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8) 1140#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8) 1141#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8) 1142#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8) 1143#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8) 1144#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8) 1145#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8) 1146#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8) 1147#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8) 1148#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8) 1149#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8) 1150#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8) 1151#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8) 1152#define BNX_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16) 1153#define BNX_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21) 1154#define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21) 1155#define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21) 1156#define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21) 1157#define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21) 1158#define BNX_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) 1159#define BNX_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) 1160#define BNX_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) 1161 1162#define BNX_PCI_CONFIG_3 0x0000040c 1163#define BNX_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 1164#define BNX_PCI_CONFIG_3_FORCE_PME (1L<<24) 1165#define BNX_PCI_CONFIG_3_PME_STATUS (1L<<25) 1166#define BNX_PCI_CONFIG_3_PME_ENABLE (1L<<26) 1167#define BNX_PCI_CONFIG_3_PM_STATE (0x3L<<27) 1168#define BNX_PCI_CONFIG_3_VAUX_PRESET (1L<<30) 1169#define BNX_PCI_CONFIG_3_PCI_POWER (1L<<31) 1170 1171#define BNX_PCI_PM_DATA_A 0x00000410 1172#define BNX_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0) 1173#define BNX_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8) 1174#define BNX_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16) 1175#define BNX_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24) 1176 1177#define BNX_PCI_PM_DATA_B 0x00000414 1178#define BNX_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0) 1179#define BNX_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8) 1180#define BNX_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16) 1181#define BNX_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24) 1182 1183#define BNX_PCI_SWAP_DIAG0 0x00000418 1184#define BNX_PCI_SWAP_DIAG1 0x0000041c 1185#define BNX_PCI_EXP_ROM_ADDR 0x00000420 1186#define BNX_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2) 1187#define BNX_PCI_EXP_ROM_ADDR_REQ (1L<<31) 1188 1189#define BNX_PCI_EXP_ROM_DATA 0x00000424 1190#define BNX_PCI_VPD_INTF 0x00000428 1191#define BNX_PCI_VPD_INTF_INTF_REQ (1L<<0) 1192 1193#define BNX_PCI_VPD_ADDR_FLAG 0x0000042c 1194#define BNX_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) 1195#define BNX_PCI_VPD_ADDR_FLAG_WR (1<<15) 1196 1197#define BNX_PCI_VPD_DATA 0x00000430 1198#define BNX_PCI_ID_VAL1 0x00000434 1199#define BNX_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0) 1200#define BNX_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16) 1201 1202#define BNX_PCI_ID_VAL2 0x00000438 1203#define BNX_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0) 1204#define BNX_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16) 1205 1206#define BNX_PCI_ID_VAL3 0x0000043c 1207#define BNX_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0) 1208#define BNX_PCI_ID_VAL3_REVISION_ID (0xffL<<24) 1209 1210#define BNX_PCI_ID_VAL4 0x00000440 1211#define BNX_PCI_ID_VAL4_CAP_ENA (0xfL<<0) 1212#define BNX_PCI_ID_VAL4_CAP_ENA_0 (0L<<0) 1213#define BNX_PCI_ID_VAL4_CAP_ENA_1 (1L<<0) 1214#define BNX_PCI_ID_VAL4_CAP_ENA_2 (2L<<0) 1215#define BNX_PCI_ID_VAL4_CAP_ENA_3 (3L<<0) 1216#define BNX_PCI_ID_VAL4_CAP_ENA_4 (4L<<0) 1217#define BNX_PCI_ID_VAL4_CAP_ENA_5 (5L<<0) 1218#define BNX_PCI_ID_VAL4_CAP_ENA_6 (6L<<0) 1219#define BNX_PCI_ID_VAL4_CAP_ENA_7 (7L<<0) 1220#define BNX_PCI_ID_VAL4_CAP_ENA_8 (8L<<0) 1221#define BNX_PCI_ID_VAL4_CAP_ENA_9 (9L<<0) 1222#define BNX_PCI_ID_VAL4_CAP_ENA_10 (10L<<0) 1223#define BNX_PCI_ID_VAL4_CAP_ENA_11 (11L<<0) 1224#define BNX_PCI_ID_VAL4_CAP_ENA_12 (12L<<0) 1225#define BNX_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) 1226#define BNX_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) 1227#define BNX_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) 1228#define BNX_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) 1229#define BNX_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) 1230#define BNX_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) 1231#define BNX_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) 1232#define BNX_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) 1233#define BNX_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) 1234#define BNX_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) 1235#define BNX_PCI_ID_VAL4_MSI_ENABLE (1L<<15) 1236#define BNX_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) 1237#define BNX_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) 1238#define BNX_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21) 1239#define BNX_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) 1240#define BNX_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26) 1241 1242#define BNX_PCI_ID_VAL5 0x00000444 1243#define BNX_PCI_ID_VAL5_D1_SUPPORT (1L<<0) 1244#define BNX_PCI_ID_VAL5_D2_SUPPORT (1L<<1) 1245#define BNX_PCI_ID_VAL5_PME_IN_D0 (1L<<2) 1246#define BNX_PCI_ID_VAL5_PME_IN_D1 (1L<<3) 1247#define BNX_PCI_ID_VAL5_PME_IN_D2 (1L<<4) 1248#define BNX_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) 1249 1250#define BNX_PCI_PCIX_EXTENDED_STATUS 0x00000448 1251#define BNX_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) 1252#define BNX_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9) 1253#define BNX_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16) 1254#define BNX_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24) 1255 1256#define BNX_PCI_ID_VAL6 0x0000044c 1257#define BNX_PCI_ID_VAL6_MAX_LAT (0xffL<<0) 1258#define BNX_PCI_ID_VAL6_MIN_GNT (0xffL<<8) 1259#define BNX_PCI_ID_VAL6_BIST (0xffL<<16) 1260 1261#define BNX_PCI_MSI_DATA 0x00000450 1262#define BNX_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) 1263 1264#define BNX_PCI_MSI_ADDR_H 0x00000454 1265#define BNX_PCI_MSI_ADDR_L 0x00000458 1266 1267 1268/* 1269 * misc_reg definition 1270 * offset: 0x800 1271 */ 1272#define BNX_MISC_COMMAND 0x00000800 1273#define BNX_MISC_COMMAND_ENABLE_ALL (1L<<0) 1274#define BNX_MISC_COMMAND_DISABLE_ALL (1L<<1) 1275#define BNX_MISC_COMMAND_CORE_RESET (1L<<4) 1276#define BNX_MISC_COMMAND_HARD_RESET (1L<<5) 1277#define BNX_MISC_COMMAND_PAR_ERROR (1L<<8) 1278#define BNX_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) 1279 1280#define BNX_MISC_CFG 0x00000804 1281#define BNX_MISC_CFG_PCI_GRC_TMOUT (1L<<0) 1282#define BNX_MISC_CFG_NVM_WR_EN (0x3L<<1) 1283#define BNX_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) 1284#define BNX_MISC_CFG_NVM_WR_EN_PCI (1L<<1) 1285#define BNX_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1) 1286#define BNX_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) 1287#define BNX_MISC_CFG_BIST_EN (1L<<3) 1288#define BNX_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) 1289#define BNX_MISC_CFG_BYPASS_BSCAN (1L<<5) 1290#define BNX_MISC_CFG_BYPASS_EJTAG (1L<<6) 1291#define BNX_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) 1292#define BNX_MISC_CFG_LEDMODE (0x3L<<8) 1293#define BNX_MISC_CFG_LEDMODE_MAC (0L<<8) 1294#define BNX_MISC_CFG_LEDMODE_GPHY1 (1L<<8) 1295#define BNX_MISC_CFG_LEDMODE_GPHY2 (2L<<8) 1296 1297#define BNX_MISC_ID 0x00000808 1298#define BNX_MISC_ID_BOND_ID (0xfL<<0) 1299#define BNX_MISC_ID_CHIP_METAL (0xffL<<4) 1300#define BNX_MISC_ID_CHIP_REV (0xfL<<12) 1301#define BNX_MISC_ID_CHIP_NUM (0xffffL<<16) 1302 1303#define BNX_MISC_ENABLE_STATUS_BITS 0x0000080c 1304#define BNX_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1305#define BNX_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1) 1306#define BNX_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1307#define BNX_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1308#define BNX_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4) 1309#define BNX_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5) 1310#define BNX_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1311#define BNX_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1312#define BNX_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1313#define BNX_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9) 1314#define BNX_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1315#define BNX_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1316#define BNX_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12) 1317#define BNX_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13) 1318#define BNX_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1319#define BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15) 1320#define BNX_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1321#define BNX_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17) 1322#define BNX_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18) 1323#define BNX_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19) 1324#define BNX_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1325#define BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21) 1326#define BNX_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1327#define BNX_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1328#define BNX_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1329#define BNX_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) 1330#define BNX_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) 1331#define BNX_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) 1332 1333#define BNX_MISC_ENABLE_SET_BITS 0x00000810 1334#define BNX_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1335#define BNX_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1) 1336#define BNX_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1337#define BNX_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1338#define BNX_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4) 1339#define BNX_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5) 1340#define BNX_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1341#define BNX_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1342#define BNX_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1343#define BNX_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9) 1344#define BNX_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1345#define BNX_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1346#define BNX_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12) 1347#define BNX_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13) 1348#define BNX_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1349#define BNX_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15) 1350#define BNX_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1351#define BNX_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17) 1352#define BNX_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18) 1353#define BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19) 1354#define BNX_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1355#define BNX_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21) 1356#define BNX_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1357#define BNX_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1358#define BNX_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1359#define BNX_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) 1360#define BNX_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) 1361#define BNX_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) 1362 1363#define BNX_MISC_ENABLE_CLR_BITS 0x00000814 1364#define BNX_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1365#define BNX_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1) 1366#define BNX_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1367#define BNX_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1368#define BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4) 1369#define BNX_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5) 1370#define BNX_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1371#define BNX_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1372#define BNX_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1373#define BNX_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9) 1374#define BNX_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1375#define BNX_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1376#define BNX_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12) 1377#define BNX_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13) 1378#define BNX_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1379#define BNX_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15) 1380#define BNX_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1381#define BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17) 1382#define BNX_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18) 1383#define BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19) 1384#define BNX_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1385#define BNX_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21) 1386#define BNX_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1387#define BNX_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1388#define BNX_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1389#define BNX_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) 1390#define BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) 1391#define BNX_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) 1392 1393#define BNX_MISC_CLOCK_CONTROL_BITS 0x00000818 1394#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1395#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1396#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1397#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1398#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1399#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1400#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1401#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1402#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1403#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1404#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1405#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1406#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1407#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1408#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1409#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1410#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1411#define BNX_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1412#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1413#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1414#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1415#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1416#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1417#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1418#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1419#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1420#define BNX_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1421#define BNX_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1422#define BNX_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1423 1424#define BNX_MISC_GPIO 0x0000081c 1425#define BNX_MISC_GPIO_VALUE (0xffL<<0) 1426#define BNX_MISC_GPIO_SET (0xffL<<8) 1427#define BNX_MISC_GPIO_CLR (0xffL<<16) 1428#define BNX_MISC_GPIO_FLOAT (0xffL<<24) 1429 1430#define BNX_MISC_GPIO_INT 0x00000820 1431#define BNX_MISC_GPIO_INT_INT_STATE (0xfL<<0) 1432#define BNX_MISC_GPIO_INT_OLD_VALUE (0xfL<<8) 1433#define BNX_MISC_GPIO_INT_OLD_SET (0xfL<<16) 1434#define BNX_MISC_GPIO_INT_OLD_CLR (0xfL<<24) 1435 1436#define BNX_MISC_CONFIG_LFSR 0x00000824 1437#define BNX_MISC_CONFIG_LFSR_DIV (0xffffL<<0) 1438 1439#define BNX_MISC_LFSR_MASK_BITS 0x00000828 1440#define BNX_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1441#define BNX_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1) 1442#define BNX_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1443#define BNX_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1444#define BNX_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4) 1445#define BNX_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5) 1446#define BNX_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1447#define BNX_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1448#define BNX_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1449#define BNX_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9) 1450#define BNX_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1451#define BNX_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1452#define BNX_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12) 1453#define BNX_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13) 1454#define BNX_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1455#define BNX_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15) 1456#define BNX_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1457#define BNX_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17) 1458#define BNX_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18) 1459#define BNX_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19) 1460#define BNX_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1461#define BNX_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21) 1462#define BNX_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1463#define BNX_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1464#define BNX_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1465#define BNX_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) 1466#define BNX_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) 1467#define BNX_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) 1468 1469#define BNX_MISC_ARB_REQ0 0x0000082c 1470#define BNX_MISC_ARB_REQ1 0x00000830 1471#define BNX_MISC_ARB_REQ2 0x00000834 1472#define BNX_MISC_ARB_REQ3 0x00000838 1473#define BNX_MISC_ARB_REQ4 0x0000083c 1474#define BNX_MISC_ARB_FREE0 0x00000840 1475#define BNX_MISC_ARB_FREE1 0x00000844 1476#define BNX_MISC_ARB_FREE2 0x00000848 1477#define BNX_MISC_ARB_FREE3 0x0000084c 1478#define BNX_MISC_ARB_FREE4 0x00000850 1479#define BNX_MISC_ARB_REQ_STATUS0 0x00000854 1480#define BNX_MISC_ARB_REQ_STATUS1 0x00000858 1481#define BNX_MISC_ARB_REQ_STATUS2 0x0000085c 1482#define BNX_MISC_ARB_REQ_STATUS3 0x00000860 1483#define BNX_MISC_ARB_REQ_STATUS4 0x00000864 1484#define BNX_MISC_ARB_GNT0 0x00000868 1485#define BNX_MISC_ARB_GNT0_0 (0x7L<<0) 1486#define BNX_MISC_ARB_GNT0_1 (0x7L<<4) 1487#define BNX_MISC_ARB_GNT0_2 (0x7L<<8) 1488#define BNX_MISC_ARB_GNT0_3 (0x7L<<12) 1489#define BNX_MISC_ARB_GNT0_4 (0x7L<<16) 1490#define BNX_MISC_ARB_GNT0_5 (0x7L<<20) 1491#define BNX_MISC_ARB_GNT0_6 (0x7L<<24) 1492#define BNX_MISC_ARB_GNT0_7 (0x7L<<28) 1493 1494#define BNX_MISC_ARB_GNT1 0x0000086c 1495#define BNX_MISC_ARB_GNT1_8 (0x7L<<0) 1496#define BNX_MISC_ARB_GNT1_9 (0x7L<<4) 1497#define BNX_MISC_ARB_GNT1_10 (0x7L<<8) 1498#define BNX_MISC_ARB_GNT1_11 (0x7L<<12) 1499#define BNX_MISC_ARB_GNT1_12 (0x7L<<16) 1500#define BNX_MISC_ARB_GNT1_13 (0x7L<<20) 1501#define BNX_MISC_ARB_GNT1_14 (0x7L<<24) 1502#define BNX_MISC_ARB_GNT1_15 (0x7L<<28) 1503 1504#define BNX_MISC_ARB_GNT2 0x00000870 1505#define BNX_MISC_ARB_GNT2_16 (0x7L<<0) 1506#define BNX_MISC_ARB_GNT2_17 (0x7L<<4) 1507#define BNX_MISC_ARB_GNT2_18 (0x7L<<8) 1508#define BNX_MISC_ARB_GNT2_19 (0x7L<<12) 1509#define BNX_MISC_ARB_GNT2_20 (0x7L<<16) 1510#define BNX_MISC_ARB_GNT2_21 (0x7L<<20) 1511#define BNX_MISC_ARB_GNT2_22 (0x7L<<24) 1512#define BNX_MISC_ARB_GNT2_23 (0x7L<<28) 1513 1514#define BNX_MISC_ARB_GNT3 0x00000874 1515#define BNX_MISC_ARB_GNT3_24 (0x7L<<0) 1516#define BNX_MISC_ARB_GNT3_25 (0x7L<<4) 1517#define BNX_MISC_ARB_GNT3_26 (0x7L<<8) 1518#define BNX_MISC_ARB_GNT3_27 (0x7L<<12) 1519#define BNX_MISC_ARB_GNT3_28 (0x7L<<16) 1520#define BNX_MISC_ARB_GNT3_29 (0x7L<<20) 1521#define BNX_MISC_ARB_GNT3_30 (0x7L<<24) 1522#define BNX_MISC_ARB_GNT3_31 (0x7L<<28) 1523 1524#define BNX_MISC_PRBS_CONTROL 0x00000878 1525#define BNX_MISC_PRBS_CONTROL_EN (1L<<0) 1526#define BNX_MISC_PRBS_CONTROL_RSTB (1L<<1) 1527#define BNX_MISC_PRBS_CONTROL_INV (1L<<2) 1528#define BNX_MISC_PRBS_CONTROL_ERR_CLR (1L<<3) 1529#define BNX_MISC_PRBS_CONTROL_ORDER (0x3L<<4) 1530#define BNX_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4) 1531#define BNX_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4) 1532#define BNX_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4) 1533#define BNX_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4) 1534 1535#define BNX_MISC_PRBS_STATUS 0x0000087c 1536#define BNX_MISC_PRBS_STATUS_LOCK (1L<<0) 1537#define BNX_MISC_PRBS_STATUS_STKY (1L<<1) 1538#define BNX_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2) 1539#define BNX_MISC_PRBS_STATUS_STATE (0xfL<<16) 1540 1541#define BNX_MISC_SM_ASF_CONTROL 0x00000880 1542#define BNX_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) 1543#define BNX_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1) 1544#define BNX_MISC_SM_ASF_CONTROL_WG_TO (1L<<2) 1545#define BNX_MISC_SM_ASF_CONTROL_HB_TO (1L<<3) 1546#define BNX_MISC_SM_ASF_CONTROL_PA_TO (1L<<4) 1547#define BNX_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) 1548#define BNX_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) 1549#define BNX_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) 1550#define BNX_MISC_SM_ASF_CONTROL_RES (0xfL<<8) 1551#define BNX_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) 1552#define BNX_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) 1553#define BNX_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) 1554#define BNX_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) 1555#define BNX_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16) 1556#define BNX_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24) 1557#define BNX_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) 1558#define BNX_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) 1559 1560#define BNX_MISC_SMB_IN 0x00000884 1561#define BNX_MISC_SMB_IN_DAT_IN (0xffL<<0) 1562#define BNX_MISC_SMB_IN_RDY (1L<<8) 1563#define BNX_MISC_SMB_IN_DONE (1L<<9) 1564#define BNX_MISC_SMB_IN_FIRSTBYTE (1L<<10) 1565#define BNX_MISC_SMB_IN_STATUS (0x7L<<11) 1566#define BNX_MISC_SMB_IN_STATUS_OK (0x0L<<11) 1567#define BNX_MISC_SMB_IN_STATUS_PEC (0x1L<<11) 1568#define BNX_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11) 1569#define BNX_MISC_SMB_IN_STATUS_STOP (0x3L<<11) 1570#define BNX_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11) 1571 1572#define BNX_MISC_SMB_OUT 0x00000888 1573#define BNX_MISC_SMB_OUT_DAT_OUT (0xffL<<0) 1574#define BNX_MISC_SMB_OUT_RDY (1L<<8) 1575#define BNX_MISC_SMB_OUT_START (1L<<9) 1576#define BNX_MISC_SMB_OUT_LAST (1L<<10) 1577#define BNX_MISC_SMB_OUT_ACC_TYPE (1L<<11) 1578#define BNX_MISC_SMB_OUT_ENB_PEC (1L<<12) 1579#define BNX_MISC_SMB_OUT_GET_RX_LEN (1L<<13) 1580#define BNX_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14) 1581#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) 1582#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) 1583#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) 1584#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20) 1585#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) 1586#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) 1587#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) 1588#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) 1589#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) 1590#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20) 1591#define BNX_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) 1592#define BNX_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) 1593#define BNX_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) 1594#define BNX_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27) 1595#define BNX_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28) 1596 1597#define BNX_MISC_SMB_WATCHDOG 0x0000088c 1598#define BNX_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0) 1599 1600#define BNX_MISC_SMB_HEARTBEAT 0x00000890 1601#define BNX_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0) 1602 1603#define BNX_MISC_SMB_POLL_ASF 0x00000894 1604#define BNX_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0) 1605 1606#define BNX_MISC_SMB_POLL_LEGACY 0x00000898 1607#define BNX_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0) 1608 1609#define BNX_MISC_SMB_RETRAN 0x0000089c 1610#define BNX_MISC_SMB_RETRAN_RETRAN (0xffL<<0) 1611 1612#define BNX_MISC_SMB_TIMESTAMP 0x000008a0 1613#define BNX_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0) 1614 1615#define BNX_MISC_PERR_ENA0 0x000008a4 1616#define BNX_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0) 1617#define BNX_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1) 1618#define BNX_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2) 1619#define BNX_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3) 1620#define BNX_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4) 1621#define BNX_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5) 1622#define BNX_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6) 1623#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7) 1624#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8) 1625#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9) 1626#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10) 1627#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11) 1628#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12) 1629#define BNX_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13) 1630#define BNX_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14) 1631#define BNX_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15) 1632#define BNX_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16) 1633#define BNX_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17) 1634#define BNX_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18) 1635#define BNX_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19) 1636#define BNX_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20) 1637#define BNX_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21) 1638#define BNX_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22) 1639#define BNX_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23) 1640#define BNX_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24) 1641#define BNX_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25) 1642#define BNX_MISC_PERR_ENA0_RBDC_MISC (1L<<26) 1643#define BNX_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27) 1644#define BNX_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28) 1645#define BNX_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) 1646#define BNX_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) 1647#define BNX_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) 1648 1649#define BNX_MISC_PERR_ENA1 0x000008a8 1650#define BNX_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) 1651#define BNX_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1) 1652#define BNX_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2) 1653#define BNX_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3) 1654#define BNX_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4) 1655#define BNX_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5) 1656#define BNX_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6) 1657#define BNX_MISC_PERR_ENA1_TBDC_MISC (1L<<7) 1658#define BNX_MISC_PERR_ENA1_TDMA_MISC (1L<<8) 1659#define BNX_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9) 1660#define BNX_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10) 1661#define BNX_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11) 1662#define BNX_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12) 1663#define BNX_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13) 1664#define BNX_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14) 1665#define BNX_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15) 1666#define BNX_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16) 1667#define BNX_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17) 1668#define BNX_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18) 1669#define BNX_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19) 1670#define BNX_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20) 1671#define BNX_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21) 1672#define BNX_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22) 1673#define BNX_MISC_PERR_ENA1_CSQ_MISC (1L<<23) 1674#define BNX_MISC_PERR_ENA1_CPQ_MISC (1L<<24) 1675#define BNX_MISC_PERR_ENA1_MCPQ_MISC (1L<<25) 1676#define BNX_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26) 1677#define BNX_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27) 1678#define BNX_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28) 1679#define BNX_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) 1680#define BNX_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) 1681#define BNX_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) 1682 1683#define BNX_MISC_PERR_ENA2 0x000008ac 1684#define BNX_MISC_PERR_ENA2_COMQ_MISC (1L<<0) 1685#define BNX_MISC_PERR_ENA2_COMXQ_MISC (1L<<1) 1686#define BNX_MISC_PERR_ENA2_COMTQ_MISC (1L<<2) 1687#define BNX_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3) 1688#define BNX_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4) 1689#define BNX_MISC_PERR_ENA2_TXPQ_MISC (1L<<5) 1690#define BNX_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) 1691#define BNX_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) 1692#define BNX_MISC_PERR_ENA2_TASQ_MISC (1L<<8) 1693 1694#define BNX_MISC_DEBUG_VECTOR_SEL 0x000008b0 1695#define BNX_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) 1696#define BNX_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) 1697 1698#define BNX_MISC_VREG_CONTROL 0x000008b4 1699#define BNX_MISC_VREG_CONTROL_1_2 (0xfL<<0) 1700#define BNX_MISC_VREG_CONTROL_2_5 (0xfL<<4) 1701 1702#define BNX_MISC_FINAL_CLK_CTL_VAL 0x000008b8 1703#define BNX_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) 1704 1705#define BNX_MISC_UNUSED0 0x000008bc 1706 1707 1708/* 1709 * nvm_reg definition 1710 * offset: 0x6400 1711 */ 1712#define BNX_NVM_COMMAND 0x00006400 1713#define BNX_NVM_COMMAND_RST (1L<<0) 1714#define BNX_NVM_COMMAND_DONE (1L<<3) 1715#define BNX_NVM_COMMAND_DOIT (1L<<4) 1716#define BNX_NVM_COMMAND_WR (1L<<5) 1717#define BNX_NVM_COMMAND_ERASE (1L<<6) 1718#define BNX_NVM_COMMAND_FIRST (1L<<7) 1719#define BNX_NVM_COMMAND_LAST (1L<<8) 1720#define BNX_NVM_COMMAND_WREN (1L<<16) 1721#define BNX_NVM_COMMAND_WRDI (1L<<17) 1722#define BNX_NVM_COMMAND_EWSR (1L<<18) 1723#define BNX_NVM_COMMAND_WRSR (1L<<19) 1724 1725#define BNX_NVM_STATUS 0x00006404 1726#define BNX_NVM_STATUS_PI_FSM_STATE (0xfL<<0) 1727#define BNX_NVM_STATUS_EE_FSM_STATE (0xfL<<4) 1728#define BNX_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) 1729 1730#define BNX_NVM_WRITE 0x00006408 1731#define BNX_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) 1732#define BNX_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0) 1733#define BNX_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0) 1734#define BNX_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0) 1735#define BNX_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0) 1736#define BNX_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0) 1737#define BNX_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0) 1738#define BNX_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0) 1739 1740#define BNX_NVM_ADDR 0x0000640c 1741#define BNX_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 1742#define BNX_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0) 1743#define BNX_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0) 1744#define BNX_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0) 1745#define BNX_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0) 1746#define BNX_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0) 1747#define BNX_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) 1748#define BNX_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) 1749 1750#define BNX_NVM_READ 0x00006410 1751#define BNX_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) 1752#define BNX_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0) 1753#define BNX_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0) 1754#define BNX_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0) 1755#define BNX_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0) 1756#define BNX_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0) 1757#define BNX_NVM_READ_NVM_READ_VALUE_SO (16L<<0) 1758#define BNX_NVM_READ_NVM_READ_VALUE_SI (32L<<0) 1759 1760#define BNX_NVM_CFG1 0x00006414 1761#define BNX_NVM_CFG1_FLASH_MODE (1L<<0) 1762#define BNX_NVM_CFG1_BUFFER_MODE (1L<<1) 1763#define BNX_NVM_CFG1_PASS_MODE (1L<<2) 1764#define BNX_NVM_CFG1_BITBANG_MODE (1L<<3) 1765#define BNX_NVM_CFG1_STATUS_BIT (0x7L<<4) 1766#define BNX_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4) 1767#define BNX_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4) 1768#define BNX_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) 1769#define BNX_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) 1770#define BNX_NVM_CFG1_PROTECT_MODE (1L<<24) 1771#define BNX_NVM_CFG1_FLASH_SIZE (1L<<25) 1772#define BNX_NVM_CFG1_COMPAT_BYPASSS (1L<<31) 1773 1774#define BNX_NVM_CFG2 0x00006418 1775#define BNX_NVM_CFG2_ERASE_CMD (0xffL<<0) 1776#define BNX_NVM_CFG2_DUMMY (0xffL<<8) 1777#define BNX_NVM_CFG2_STATUS_CMD (0xffL<<16) 1778 1779#define BNX_NVM_CFG3 0x0000641c 1780#define BNX_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) 1781#define BNX_NVM_CFG3_WRITE_CMD (0xffL<<8) 1782#define BNX_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16) 1783#define BNX_NVM_CFG3_READ_CMD (0xffL<<24) 1784 1785#define BNX_NVM_SW_ARB 0x00006420 1786#define BNX_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0) 1787#define BNX_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 1788#define BNX_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2) 1789#define BNX_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3) 1790#define BNX_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4) 1791#define BNX_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 1792#define BNX_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6) 1793#define BNX_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7) 1794#define BNX_NVM_SW_ARB_ARB_ARB0 (1L<<8) 1795#define BNX_NVM_SW_ARB_ARB_ARB1 (1L<<9) 1796#define BNX_NVM_SW_ARB_ARB_ARB2 (1L<<10) 1797#define BNX_NVM_SW_ARB_ARB_ARB3 (1L<<11) 1798#define BNX_NVM_SW_ARB_REQ0 (1L<<12) 1799#define BNX_NVM_SW_ARB_REQ1 (1L<<13) 1800#define BNX_NVM_SW_ARB_REQ2 (1L<<14) 1801#define BNX_NVM_SW_ARB_REQ3 (1L<<15) 1802 1803#define BNX_NVM_ACCESS_ENABLE 0x00006424 1804#define BNX_NVM_ACCESS_ENABLE_EN (1L<<0) 1805#define BNX_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 1806 1807#define BNX_NVM_WRITE1 0x00006428 1808#define BNX_NVM_WRITE1_WREN_CMD (0xffL<<0) 1809#define BNX_NVM_WRITE1_WRDI_CMD (0xffL<<8) 1810#define BNX_NVM_WRITE1_SR_DATA (0xffL<<16) 1811 1812 1813 1814/* 1815 * dma_reg definition 1816 * offset: 0xc00 1817 */ 1818#define BNX_DMA_COMMAND 0x00000c00 1819#define BNX_DMA_COMMAND_ENABLE (1L<<0) 1820 1821#define BNX_DMA_STATUS 0x00000c04 1822#define BNX_DMA_STATUS_PAR_ERROR_STATE (1L<<0) 1823#define BNX_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16) 1824#define BNX_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17) 1825#define BNX_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18) 1826#define BNX_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19) 1827#define BNX_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20) 1828#define BNX_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21) 1829#define BNX_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22) 1830#define BNX_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) 1831#define BNX_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) 1832#define BNX_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) 1833 1834#define BNX_DMA_CONFIG 0x00000c08 1835#define BNX_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) 1836#define BNX_DMA_CONFIG_DATA_WORD_SWAP (1L<<1) 1837#define BNX_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4) 1838#define BNX_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5) 1839#define BNX_DMA_CONFIG_ONE_DMA (1L<<6) 1840#define BNX_DMA_CONFIG_CNTL_TWO_DMA (1L<<7) 1841#define BNX_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8) 1842#define BNX_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10) 1843#define BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11) 1844#define BNX_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12) 1845#define BNX_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16) 1846#define BNX_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20) 1847#define BNX_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23) 1848#define BNX_DMA_CONFIG_BIG_SIZE (0xfL<<24) 1849#define BNX_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24) 1850#define BNX_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24) 1851#define BNX_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) 1852#define BNX_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) 1853#define BNX_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) 1854 1855#define BNX_DMA_BLACKOUT 0x00000c0c 1856#define BNX_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) 1857#define BNX_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) 1858#define BNX_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) 1859 1860#define BNX_DMA_RCHAN_STAT 0x00000c30 1861#define BNX_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) 1862#define BNX_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) 1863#define BNX_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) 1864#define BNX_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) 1865#define BNX_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) 1866#define BNX_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) 1867#define BNX_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) 1868#define BNX_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) 1869#define BNX_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) 1870#define BNX_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) 1871#define BNX_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) 1872#define BNX_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) 1873#define BNX_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) 1874#define BNX_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) 1875#define BNX_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) 1876#define BNX_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) 1877 1878#define BNX_DMA_WCHAN_STAT 0x00000c34 1879#define BNX_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) 1880#define BNX_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) 1881#define BNX_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) 1882#define BNX_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) 1883#define BNX_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) 1884#define BNX_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) 1885#define BNX_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) 1886#define BNX_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) 1887#define BNX_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) 1888#define BNX_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) 1889#define BNX_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) 1890#define BNX_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) 1891#define BNX_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) 1892#define BNX_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) 1893#define BNX_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) 1894#define BNX_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) 1895 1896#define BNX_DMA_RCHAN_ASSIGNMENT 0x00000c38 1897#define BNX_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) 1898#define BNX_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) 1899#define BNX_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) 1900#define BNX_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) 1901#define BNX_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) 1902#define BNX_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) 1903#define BNX_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) 1904#define BNX_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) 1905 1906#define BNX_DMA_WCHAN_ASSIGNMENT 0x00000c3c 1907#define BNX_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) 1908#define BNX_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) 1909#define BNX_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) 1910#define BNX_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) 1911#define BNX_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) 1912#define BNX_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) 1913#define BNX_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) 1914#define BNX_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) 1915 1916#define BNX_DMA_RCHAN_STAT_00 0x00000c40 1917#define BNX_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 1918 1919#define BNX_DMA_RCHAN_STAT_01 0x00000c44 1920#define BNX_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 1921 1922#define BNX_DMA_RCHAN_STAT_02 0x00000c48 1923#define BNX_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) 1924#define BNX_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16) 1925#define BNX_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17) 1926#define BNX_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18) 1927 1928#define BNX_DMA_RCHAN_STAT_10 0x00000c4c 1929#define BNX_DMA_RCHAN_STAT_11 0x00000c50 1930#define BNX_DMA_RCHAN_STAT_12 0x00000c54 1931#define BNX_DMA_RCHAN_STAT_20 0x00000c58 1932#define BNX_DMA_RCHAN_STAT_21 0x00000c5c 1933#define BNX_DMA_RCHAN_STAT_22 0x00000c60 1934#define BNX_DMA_RCHAN_STAT_30 0x00000c64 1935#define BNX_DMA_RCHAN_STAT_31 0x00000c68 1936#define BNX_DMA_RCHAN_STAT_32 0x00000c6c 1937#define BNX_DMA_RCHAN_STAT_40 0x00000c70 1938#define BNX_DMA_RCHAN_STAT_41 0x00000c74 1939#define BNX_DMA_RCHAN_STAT_42 0x00000c78 1940#define BNX_DMA_RCHAN_STAT_50 0x00000c7c 1941#define BNX_DMA_RCHAN_STAT_51 0x00000c80 1942#define BNX_DMA_RCHAN_STAT_52 0x00000c84 1943#define BNX_DMA_RCHAN_STAT_60 0x00000c88 1944#define BNX_DMA_RCHAN_STAT_61 0x00000c8c 1945#define BNX_DMA_RCHAN_STAT_62 0x00000c90 1946#define BNX_DMA_RCHAN_STAT_70 0x00000c94 1947#define BNX_DMA_RCHAN_STAT_71 0x00000c98 1948#define BNX_DMA_RCHAN_STAT_72 0x00000c9c 1949#define BNX_DMA_WCHAN_STAT_00 0x00000ca0 1950#define BNX_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 1951 1952#define BNX_DMA_WCHAN_STAT_01 0x00000ca4 1953#define BNX_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 1954 1955#define BNX_DMA_WCHAN_STAT_02 0x00000ca8 1956#define BNX_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0) 1957#define BNX_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16) 1958#define BNX_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17) 1959#define BNX_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18) 1960 1961#define BNX_DMA_WCHAN_STAT_10 0x00000cac 1962#define BNX_DMA_WCHAN_STAT_11 0x00000cb0 1963#define BNX_DMA_WCHAN_STAT_12 0x00000cb4 1964#define BNX_DMA_WCHAN_STAT_20 0x00000cb8 1965#define BNX_DMA_WCHAN_STAT_21 0x00000cbc 1966#define BNX_DMA_WCHAN_STAT_22 0x00000cc0 1967#define BNX_DMA_WCHAN_STAT_30 0x00000cc4 1968#define BNX_DMA_WCHAN_STAT_31 0x00000cc8 1969#define BNX_DMA_WCHAN_STAT_32 0x00000ccc 1970#define BNX_DMA_WCHAN_STAT_40 0x00000cd0 1971#define BNX_DMA_WCHAN_STAT_41 0x00000cd4 1972#define BNX_DMA_WCHAN_STAT_42 0x00000cd8 1973#define BNX_DMA_WCHAN_STAT_50 0x00000cdc 1974#define BNX_DMA_WCHAN_STAT_51 0x00000ce0 1975#define BNX_DMA_WCHAN_STAT_52 0x00000ce4 1976#define BNX_DMA_WCHAN_STAT_60 0x00000ce8 1977#define BNX_DMA_WCHAN_STAT_61 0x00000cec 1978#define BNX_DMA_WCHAN_STAT_62 0x00000cf0 1979#define BNX_DMA_WCHAN_STAT_70 0x00000cf4 1980#define BNX_DMA_WCHAN_STAT_71 0x00000cf8 1981#define BNX_DMA_WCHAN_STAT_72 0x00000cfc 1982#define BNX_DMA_ARB_STAT_00 0x00000d00 1983#define BNX_DMA_ARB_STAT_00_MASTER (0xffffL<<0) 1984#define BNX_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16) 1985#define BNX_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24) 1986 1987#define BNX_DMA_ARB_STAT_01 0x00000d04 1988#define BNX_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0) 1989#define BNX_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4) 1990#define BNX_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8) 1991#define BNX_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12) 1992#define BNX_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16) 1993#define BNX_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20) 1994#define BNX_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24) 1995#define BNX_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28) 1996 1997#define BNX_DMA_FUSE_CTRL0_CMD 0x00000f00 1998#define BNX_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0) 1999#define BNX_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1) 2000#define BNX_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2) 2001#define BNX_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3) 2002#define BNX_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8) 2003 2004#define BNX_DMA_FUSE_CTRL0_DATA 0x00000f04 2005#define BNX_DMA_FUSE_CTRL1_CMD 0x00000f08 2006#define BNX_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0) 2007#define BNX_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1) 2008#define BNX_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2) 2009#define BNX_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3) 2010#define BNX_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8) 2011 2012#define BNX_DMA_FUSE_CTRL1_DATA 0x00000f0c 2013#define BNX_DMA_FUSE_CTRL2_CMD 0x00000f10 2014#define BNX_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0) 2015#define BNX_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1) 2016#define BNX_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2) 2017#define BNX_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3) 2018#define BNX_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8) 2019 2020#define BNX_DMA_FUSE_CTRL2_DATA 0x00000f14 2021 2022 2023/* 2024 * context_reg definition 2025 * offset: 0x1000 2026 */ 2027#define BNX_CTX_COMMAND 0x00001000 2028#define BNX_CTX_COMMAND_ENABLED (1L<<0) 2029 2030#define BNX_CTX_STATUS 0x00001004 2031#define BNX_CTX_STATUS_LOCK_WAIT (1L<<0) 2032#define BNX_CTX_STATUS_READ_STAT (1L<<16) 2033#define BNX_CTX_STATUS_WRITE_STAT (1L<<17) 2034#define BNX_CTX_STATUS_ACC_STALL_STAT (1L<<18) 2035#define BNX_CTX_STATUS_LOCK_STALL_STAT (1L<<19) 2036 2037#define BNX_CTX_VIRT_ADDR 0x00001008 2038#define BNX_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) 2039 2040#define BNX_CTX_PAGE_TBL 0x0000100c 2041#define BNX_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6) 2042 2043#define BNX_CTX_DATA_ADR 0x00001010 2044#define BNX_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2) 2045 2046#define BNX_CTX_DATA 0x00001014 2047#define BNX_CTX_LOCK 0x00001018 2048#define BNX_CTX_LOCK_TYPE (0x7L<<0) 2049#define BNX_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) 2050#define BNX_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0) 2051#define BNX_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) 2052#define BNX_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) 2053#define BNX_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) 2054#define BNX_CTX_LOCK_CID_VALUE (0x3fffL<<7) 2055#define BNX_CTX_LOCK_GRANTED (1L<<26) 2056#define BNX_CTX_LOCK_MODE (0x7L<<27) 2057#define BNX_CTX_LOCK_MODE_UNLOCK (0x0L<<27) 2058#define BNX_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27) 2059#define BNX_CTX_LOCK_MODE_SURE (0x2L<<27) 2060#define BNX_CTX_LOCK_STATUS (1L<<30) 2061#define BNX_CTX_LOCK_REQ (1L<<31) 2062 2063#define BNX_CTX_ACCESS_STATUS 0x00001040 2064#define BNX_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) 2065#define BNX_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) 2066#define BNX_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) 2067#define BNX_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) 2068#define BNX_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) 2069 2070#define BNX_CTX_DBG_LOCK_STATUS 0x00001044 2071#define BNX_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) 2072#define BNX_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) 2073 2074#define BNX_CTX_CHNL_LOCK_STATUS_0 0x00001080 2075#define BNX_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) 2076#define BNX_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) 2077#define BNX_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) 2078 2079#define BNX_CTX_CHNL_LOCK_STATUS_1 0x00001084 2080#define BNX_CTX_CHNL_LOCK_STATUS_2 0x00001088 2081#define BNX_CTX_CHNL_LOCK_STATUS_3 0x0000108c 2082#define BNX_CTX_CHNL_LOCK_STATUS_4 0x00001090 2083#define BNX_CTX_CHNL_LOCK_STATUS_5 0x00001094 2084#define BNX_CTX_CHNL_LOCK_STATUS_6 0x00001098 2085#define BNX_CTX_CHNL_LOCK_STATUS_7 0x0000109c 2086#define BNX_CTX_CHNL_LOCK_STATUS_8 0x000010a0 2087 2088 2089/* 2090 * emac_reg definition 2091 * offset: 0x1400 2092 */ 2093#define BNX_EMAC_MODE 0x00001400 2094#define BNX_EMAC_MODE_RESET (1L<<0) 2095#define BNX_EMAC_MODE_HALF_DUPLEX (1L<<1) 2096#define BNX_EMAC_MODE_PORT (0x3L<<2) 2097#define BNX_EMAC_MODE_PORT_NONE (0L<<2) 2098#define BNX_EMAC_MODE_PORT_MII (1L<<2) 2099#define BNX_EMAC_MODE_PORT_GMII (2L<<2) 2100#define BNX_EMAC_MODE_PORT_MII_10 (3L<<2) 2101#define BNX_EMAC_MODE_MAC_LOOP (1L<<4) 2102#define BNX_EMAC_MODE_25G (1L<<5) 2103#define BNX_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) 2104#define BNX_EMAC_MODE_TX_BURST (1L<<8) 2105#define BNX_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) 2106#define BNX_EMAC_MODE_EXT_LINK_POL (1L<<10) 2107#define BNX_EMAC_MODE_FORCE_LINK (1L<<11) 2108#define BNX_EMAC_MODE_MPKT (1L<<18) 2109#define BNX_EMAC_MODE_MPKT_RCVD (1L<<19) 2110#define BNX_EMAC_MODE_ACPI_RCVD (1L<<20) 2111 2112#define BNX_EMAC_STATUS 0x00001404 2113#define BNX_EMAC_STATUS_LINK (1L<<11) 2114#define BNX_EMAC_STATUS_LINK_CHANGE (1L<<12) 2115#define BNX_EMAC_STATUS_MI_COMPLETE (1L<<22) 2116#define BNX_EMAC_STATUS_MI_INT (1L<<23) 2117#define BNX_EMAC_STATUS_AP_ERROR (1L<<24) 2118#define BNX_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31) 2119 2120#define BNX_EMAC_ATTENTION_ENA 0x00001408 2121#define BNX_EMAC_ATTENTION_ENA_LINK (1L<<11) 2122#define BNX_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) 2123#define BNX_EMAC_ATTENTION_ENA_MI_INT (1L<<23) 2124#define BNX_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) 2125 2126#define BNX_EMAC_LED 0x0000140c 2127#define BNX_EMAC_LED_OVERRIDE (1L<<0) 2128#define BNX_EMAC_LED_1000MB_OVERRIDE (1L<<1) 2129#define BNX_EMAC_LED_100MB_OVERRIDE (1L<<2) 2130#define BNX_EMAC_LED_10MB_OVERRIDE (1L<<3) 2131#define BNX_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4) 2132#define BNX_EMAC_LED_BLNK_TRAFFIC (1L<<5) 2133#define BNX_EMAC_LED_TRAFFIC (1L<<6) 2134#define BNX_EMAC_LED_1000MB (1L<<7) 2135#define BNX_EMAC_LED_100MB (1L<<8) 2136#define BNX_EMAC_LED_10MB (1L<<9) 2137#define BNX_EMAC_LED_TRAFFIC_STAT (1L<<10) 2138#define BNX_EMAC_LED_BLNK_RATE (0xfffL<<19) 2139#define BNX_EMAC_LED_BLNK_RATE_ENA (1L<<31) 2140 2141#define BNX_EMAC_MAC_MATCH0 0x00001410 2142#define BNX_EMAC_MAC_MATCH1 0x00001414 2143#define BNX_EMAC_MAC_MATCH2 0x00001418 2144#define BNX_EMAC_MAC_MATCH3 0x0000141c 2145#define BNX_EMAC_MAC_MATCH4 0x00001420 2146#define BNX_EMAC_MAC_MATCH5 0x00001424 2147#define BNX_EMAC_MAC_MATCH6 0x00001428 2148#define BNX_EMAC_MAC_MATCH7 0x0000142c 2149#define BNX_EMAC_MAC_MATCH8 0x00001430 2150#define BNX_EMAC_MAC_MATCH9 0x00001434 2151#define BNX_EMAC_MAC_MATCH10 0x00001438 2152#define BNX_EMAC_MAC_MATCH11 0x0000143c 2153#define BNX_EMAC_MAC_MATCH12 0x00001440 2154#define BNX_EMAC_MAC_MATCH13 0x00001444 2155#define BNX_EMAC_MAC_MATCH14 0x00001448 2156#define BNX_EMAC_MAC_MATCH15 0x0000144c 2157#define BNX_EMAC_MAC_MATCH16 0x00001450 2158#define BNX_EMAC_MAC_MATCH17 0x00001454 2159#define BNX_EMAC_MAC_MATCH18 0x00001458 2160#define BNX_EMAC_MAC_MATCH19 0x0000145c 2161#define BNX_EMAC_MAC_MATCH20 0x00001460 2162#define BNX_EMAC_MAC_MATCH21 0x00001464 2163#define BNX_EMAC_MAC_MATCH22 0x00001468 2164#define BNX_EMAC_MAC_MATCH23 0x0000146c 2165#define BNX_EMAC_MAC_MATCH24 0x00001470 2166#define BNX_EMAC_MAC_MATCH25 0x00001474 2167#define BNX_EMAC_MAC_MATCH26 0x00001478 2168#define BNX_EMAC_MAC_MATCH27 0x0000147c 2169#define BNX_EMAC_MAC_MATCH28 0x00001480 2170#define BNX_EMAC_MAC_MATCH29 0x00001484 2171#define BNX_EMAC_MAC_MATCH30 0x00001488 2172#define BNX_EMAC_MAC_MATCH31 0x0000148c 2173#define BNX_EMAC_BACKOFF_SEED 0x00001498 2174#define BNX_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0) 2175 2176#define BNX_EMAC_RX_MTU_SIZE 0x0000149c 2177#define BNX_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) 2178#define BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 2179 2180#define BNX_EMAC_SERDES_CNTL 0x000014a4 2181#define BNX_EMAC_SERDES_CNTL_RXR (0x7L<<0) 2182#define BNX_EMAC_SERDES_CNTL_RXG (0x3L<<3) 2183#define BNX_EMAC_SERDES_CNTL_RXCKSEL (1L<<6) 2184#define BNX_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7) 2185#define BNX_EMAC_SERDES_CNTL_BGMAX (1L<<10) 2186#define BNX_EMAC_SERDES_CNTL_BGMIN (1L<<11) 2187#define BNX_EMAC_SERDES_CNTL_TXMODE (1L<<12) 2188#define BNX_EMAC_SERDES_CNTL_TXEDGE (1L<<13) 2189#define BNX_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14) 2190#define BNX_EMAC_SERDES_CNTL_PLLTEST (1L<<15) 2191#define BNX_EMAC_SERDES_CNTL_CDET_EN (1L<<16) 2192#define BNX_EMAC_SERDES_CNTL_TBI_LBK (1L<<17) 2193#define BNX_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18) 2194#define BNX_EMAC_SERDES_CNTL_REV_PHASE (1L<<19) 2195#define BNX_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20) 2196#define BNX_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22) 2197 2198#define BNX_EMAC_SERDES_STATUS 0x000014a8 2199#define BNX_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0) 2200#define BNX_EMAC_SERDES_STATUS_COMMA_DET (1L<<8) 2201 2202#define BNX_EMAC_MDIO_COMM 0x000014ac 2203#define BNX_EMAC_MDIO_COMM_DATA (0xffffL<<0) 2204#define BNX_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16) 2205#define BNX_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) 2206#define BNX_EMAC_MDIO_COMM_COMMAND (0x3L<<26) 2207#define BNX_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) 2208#define BNX_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) 2209#define BNX_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) 2210#define BNX_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) 2211#define BNX_EMAC_MDIO_COMM_FAIL (1L<<28) 2212#define BNX_EMAC_MDIO_COMM_START_BUSY (1L<<29) 2213#define BNX_EMAC_MDIO_COMM_DISEXT (1L<<30) 2214 2215#define BNX_EMAC_MDIO_STATUS 0x000014b0 2216#define BNX_EMAC_MDIO_STATUS_LINK (1L<<0) 2217#define BNX_EMAC_MDIO_STATUS_10MB (1L<<1) 2218 2219#define BNX_EMAC_MDIO_MODE 0x000014b4 2220#define BNX_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1) 2221#define BNX_EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 2222#define BNX_EMAC_MDIO_MODE_BIT_BANG (1L<<8) 2223#define BNX_EMAC_MDIO_MODE_MDIO (1L<<9) 2224#define BNX_EMAC_MDIO_MODE_MDIO_OE (1L<<10) 2225#define BNX_EMAC_MDIO_MODE_MDC (1L<<11) 2226#define BNX_EMAC_MDIO_MODE_MDINT (1L<<12) 2227#define BNX_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) 2228 2229#define BNX_EMAC_MDIO_AUTO_STATUS 0x000014b8 2230#define BNX_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) 2231 2232#define BNX_EMAC_TX_MODE 0x000014bc 2233#define BNX_EMAC_TX_MODE_RESET (1L<<0) 2234#define BNX_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 2235#define BNX_EMAC_TX_MODE_FLOW_EN (1L<<4) 2236#define BNX_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) 2237#define BNX_EMAC_TX_MODE_LONG_PAUSE (1L<<6) 2238#define BNX_EMAC_TX_MODE_LINK_AWARE (1L<<7) 2239 2240#define BNX_EMAC_TX_STATUS 0x000014c0 2241#define BNX_EMAC_TX_STATUS_XOFFED (1L<<0) 2242#define BNX_EMAC_TX_STATUS_XOFF_SENT (1L<<1) 2243#define BNX_EMAC_TX_STATUS_XON_SENT (1L<<2) 2244#define BNX_EMAC_TX_STATUS_LINK_UP (1L<<3) 2245#define BNX_EMAC_TX_STATUS_UNDERRUN (1L<<4) 2246 2247#define BNX_EMAC_TX_LENGTHS 0x000014c4 2248#define BNX_EMAC_TX_LENGTHS_SLOT (0xffL<<0) 2249#define BNX_EMAC_TX_LENGTHS_IPG (0xfL<<8) 2250#define BNX_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12) 2251 2252#define BNX_EMAC_RX_MODE 0x000014c8 2253#define BNX_EMAC_RX_MODE_RESET (1L<<0) 2254#define BNX_EMAC_RX_MODE_FLOW_EN (1L<<2) 2255#define BNX_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 2256#define BNX_EMAC_RX_MODE_KEEP_PAUSE (1L<<4) 2257#define BNX_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5) 2258#define BNX_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6) 2259#define BNX_EMAC_RX_MODE_LLC_CHK (1L<<7) 2260#define BNX_EMAC_RX_MODE_PROMISCUOUS (1L<<8) 2261#define BNX_EMAC_RX_MODE_NO_CRC_CHK (1L<<9) 2262#define BNX_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 2263#define BNX_EMAC_RX_MODE_FILT_BROADCAST (1L<<11) 2264#define BNX_EMAC_RX_MODE_SORT_MODE (1L<<12) 2265 2266#define BNX_EMAC_RX_STATUS 0x000014cc 2267#define BNX_EMAC_RX_STATUS_FFED (1L<<0) 2268#define BNX_EMAC_RX_STATUS_FF_RECEIVED (1L<<1) 2269#define BNX_EMAC_RX_STATUS_N_RECEIVED (1L<<2) 2270 2271#define BNX_EMAC_MULTICAST_HASH0 0x000014d0 2272#define BNX_EMAC_MULTICAST_HASH1 0x000014d4 2273#define BNX_EMAC_MULTICAST_HASH2 0x000014d8 2274#define BNX_EMAC_MULTICAST_HASH3 0x000014dc 2275#define BNX_EMAC_MULTICAST_HASH4 0x000014e0 2276#define BNX_EMAC_MULTICAST_HASH5 0x000014e4 2277#define BNX_EMAC_MULTICAST_HASH6 0x000014e8 2278#define BNX_EMAC_MULTICAST_HASH7 0x000014ec 2279#define BNX_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 2280#define BNX_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 2281#define BNX_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 2282#define BNX_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c 2283#define BNX_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510 2284#define BNX_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514 2285#define BNX_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518 2286#define BNX_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c 2287#define BNX_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520 2288#define BNX_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524 2289#define BNX_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528 2290#define BNX_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c 2291#define BNX_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530 2292#define BNX_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534 2293#define BNX_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538 2294#define BNX_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c 2295#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540 2296#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544 2297#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548 2298#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c 2299#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 2300#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 2301#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558 2302#define BNX_EMAC_RXMAC_DEBUG0 0x0000155c 2303#define BNX_EMAC_RXMAC_DEBUG1 0x00001560 2304#define BNX_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) 2305#define BNX_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1) 2306#define BNX_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2) 2307#define BNX_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3) 2308#define BNX_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4) 2309#define BNX_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5) 2310#define BNX_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6) 2311#define BNX_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7) 2312#define BNX_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23) 2313 2314#define BNX_EMAC_RXMAC_DEBUG2 0x00001564 2315#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0) 2316#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0) 2317#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0) 2318#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0) 2319#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0) 2320#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0) 2321#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0) 2322#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0) 2323#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0) 2324#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3) 2325#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3) 2326#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3) 2327#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3) 2328#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3) 2329#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3) 2330#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3) 2331#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3) 2332#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3) 2333#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3) 2334#define BNX_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7) 2335#define BNX_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15) 2336#define BNX_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16) 2337#define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18) 2338#define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18) 2339#define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18) 2340#define BNX_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19) 2341#define BNX_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23) 2342 2343#define BNX_EMAC_RXMAC_DEBUG3 0x00001568 2344#define BNX_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0) 2345#define BNX_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16) 2346 2347#define BNX_EMAC_RXMAC_DEBUG4 0x0000156c 2348#define BNX_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0) 2349#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16) 2350#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16) 2351#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) 2352#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) 2353#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) 2354#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16) 2355#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) 2356#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) 2357#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) 2358#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) 2359#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) 2360#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16) 2361#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16) 2362#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16) 2363#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16) 2364#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16) 2365#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16) 2366#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16) 2367#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16) 2368#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16) 2369#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16) 2370#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16) 2371#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16) 2372#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16) 2373#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16) 2374#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16) 2375#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16) 2376#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16) 2377#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16) 2378#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16) 2379#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16) 2380#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16) 2381#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16) 2382#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16) 2383#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16) 2384#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16) 2385#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16) 2386#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16) 2387#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16) 2388#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16) 2389#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16) 2390#define BNX_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22) 2391#define BNX_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) 2392#define BNX_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) 2393#define BNX_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) 2394#define BNX_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26) 2395#define BNX_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) 2396#define BNX_EMAC_RXMAC_DEBUG4_START (1L<<28) 2397 2398#define BNX_EMAC_RXMAC_DEBUG5 0x00001570 2399#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0) 2400#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0) 2401#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0) 2402#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0) 2403#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0) 2404#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0) 2405#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0) 2406#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0) 2407#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4) 2408#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4) 2409#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4) 2410#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4) 2411#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4) 2412#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4) 2413#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4) 2414#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4) 2415#define BNX_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7) 2416#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8) 2417#define BNX_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11) 2418#define BNX_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12) 2419#define BNX_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13) 2420#define BNX_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14) 2421#define BNX_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15) 2422#define BNX_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16) 2423#define BNX_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19) 2424#define BNX_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) 2425 2426#define BNX_EMAC_RX_STAT_AC0 0x00001580 2427#define BNX_EMAC_RX_STAT_AC1 0x00001584 2428#define BNX_EMAC_RX_STAT_AC2 0x00001588 2429#define BNX_EMAC_RX_STAT_AC3 0x0000158c 2430#define BNX_EMAC_RX_STAT_AC4 0x00001590 2431#define BNX_EMAC_RX_STAT_AC5 0x00001594 2432#define BNX_EMAC_RX_STAT_AC6 0x00001598 2433#define BNX_EMAC_RX_STAT_AC7 0x0000159c 2434#define BNX_EMAC_RX_STAT_AC8 0x000015a0 2435#define BNX_EMAC_RX_STAT_AC9 0x000015a4 2436#define BNX_EMAC_RX_STAT_AC10 0x000015a8 2437#define BNX_EMAC_RX_STAT_AC11 0x000015ac 2438#define BNX_EMAC_RX_STAT_AC12 0x000015b0 2439#define BNX_EMAC_RX_STAT_AC13 0x000015b4 2440#define BNX_EMAC_RX_STAT_AC14 0x000015b8 2441#define BNX_EMAC_RX_STAT_AC15 0x000015bc 2442#define BNX_EMAC_RX_STAT_AC16 0x000015c0 2443#define BNX_EMAC_RX_STAT_AC17 0x000015c4 2444#define BNX_EMAC_RX_STAT_AC18 0x000015c8 2445#define BNX_EMAC_RX_STAT_AC19 0x000015cc 2446#define BNX_EMAC_RX_STAT_AC20 0x000015d0 2447#define BNX_EMAC_RX_STAT_AC21 0x000015d4 2448#define BNX_EMAC_RX_STAT_AC22 0x000015d8 2449#define BNX_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc 2450#define BNX_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 2451#define BNX_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604 2452#define BNX_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608 2453#define BNX_EMAC_TX_STAT_OUTXONSENT 0x0000160c 2454#define BNX_EMAC_TX_STAT_OUTXOFFSENT 0x00001610 2455#define BNX_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614 2456#define BNX_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618 2457#define BNX_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c 2458#define BNX_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620 2459#define BNX_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624 2460#define BNX_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628 2461#define BNX_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c 2462#define BNX_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630 2463#define BNX_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634 2464#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638 2465#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c 2466#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640 2467#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644 2468#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648 2469#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c 2470#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650 2471#define BNX_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654 2472#define BNX_EMAC_TXMAC_DEBUG0 0x00001658 2473#define BNX_EMAC_TXMAC_DEBUG1 0x0000165c 2474#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0) 2475#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0) 2476#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0) 2477#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0) 2478#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0) 2479#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0) 2480#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0) 2481#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0) 2482#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0) 2483#define BNX_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4) 2484#define BNX_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5) 2485#define BNX_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6) 2486#define BNX_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10) 2487#define BNX_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11) 2488#define BNX_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12) 2489#define BNX_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13) 2490#define BNX_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14) 2491#define BNX_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15) 2492#define BNX_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19) 2493 2494#define BNX_EMAC_TXMAC_DEBUG2 0x00001660 2495#define BNX_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0) 2496#define BNX_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10) 2497#define BNX_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26) 2498#define BNX_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31) 2499 2500#define BNX_EMAC_TXMAC_DEBUG3 0x00001664 2501#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0) 2502#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0) 2503#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0) 2504#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0) 2505#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0) 2506#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0) 2507#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0) 2508#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0) 2509#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0) 2510#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0) 2511#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0) 2512#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0) 2513#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0) 2514#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0) 2515#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0) 2516#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0) 2517#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4) 2518#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4) 2519#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4) 2520#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4) 2521#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4) 2522#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4) 2523#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4) 2524#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4) 2525#define BNX_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7) 2526#define BNX_EMAC_TXMAC_DEBUG3_XOFF (1L<<8) 2527#define BNX_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9) 2528#define BNX_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13) 2529 2530#define BNX_EMAC_TXMAC_DEBUG4 0x00001668 2531#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0) 2532#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16) 2533#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16) 2534#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16) 2535#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16) 2536#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16) 2537#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16) 2538#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16) 2539#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16) 2540#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16) 2541#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16) 2542#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16) 2543#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16) 2544#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16) 2545#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16) 2546#define BNX_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20) 2547#define BNX_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21) 2548#define BNX_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22) 2549#define BNX_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23) 2550#define BNX_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24) 2551#define BNX_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25) 2552#define BNX_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26) 2553#define BNX_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27) 2554#define BNX_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28) 2555#define BNX_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29) 2556#define BNX_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30) 2557#define BNX_EMAC_TXMAC_DEBUG4_GO (1L<<31) 2558 2559#define BNX_EMAC_TX_STAT_AC0 0x00001680 2560#define BNX_EMAC_TX_STAT_AC1 0x00001684 2561#define BNX_EMAC_TX_STAT_AC2 0x00001688 2562#define BNX_EMAC_TX_STAT_AC3 0x0000168c 2563#define BNX_EMAC_TX_STAT_AC4 0x00001690 2564#define BNX_EMAC_TX_STAT_AC5 0x00001694 2565#define BNX_EMAC_TX_STAT_AC6 0x00001698 2566#define BNX_EMAC_TX_STAT_AC7 0x0000169c 2567#define BNX_EMAC_TX_STAT_AC8 0x000016a0 2568#define BNX_EMAC_TX_STAT_AC9 0x000016a4 2569#define BNX_EMAC_TX_STAT_AC10 0x000016a8 2570#define BNX_EMAC_TX_STAT_AC11 0x000016ac 2571#define BNX_EMAC_TX_STAT_AC12 0x000016b0 2572#define BNX_EMAC_TX_STAT_AC13 0x000016b4 2573#define BNX_EMAC_TX_STAT_AC14 0x000016b8 2574#define BNX_EMAC_TX_STAT_AC15 0x000016bc 2575#define BNX_EMAC_TX_STAT_AC16 0x000016c0 2576#define BNX_EMAC_TX_STAT_AC17 0x000016c4 2577#define BNX_EMAC_TX_STAT_AC18 0x000016c8 2578#define BNX_EMAC_TX_STAT_AC19 0x000016cc 2579#define BNX_EMAC_TX_STAT_AC20 0x000016d0 2580#define BNX_EMAC_TX_STAT_AC21 0x000016d4 2581#define BNX_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8 2582 2583 2584/* 2585 * rpm_reg definition 2586 * offset: 0x1800 2587 */ 2588#define BNX_RPM_COMMAND 0x00001800 2589#define BNX_RPM_COMMAND_ENABLED (1L<<0) 2590#define BNX_RPM_COMMAND_OVERRUN_ABORT (1L<<4) 2591 2592#define BNX_RPM_STATUS 0x00001804 2593#define BNX_RPM_STATUS_MBUF_WAIT (1L<<0) 2594#define BNX_RPM_STATUS_FREE_WAIT (1L<<1) 2595 2596#define BNX_RPM_CONFIG 0x00001808 2597#define BNX_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0) 2598#define BNX_RPM_CONFIG_ACPI_ENA (1L<<1) 2599#define BNX_RPM_CONFIG_ACPI_KEEP (1L<<2) 2600#define BNX_RPM_CONFIG_MP_KEEP (1L<<3) 2601#define BNX_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4) 2602#define BNX_RPM_CONFIG_IGNORE_VLAN (1L<<31) 2603 2604#define BNX_RPM_VLAN_MATCH0 0x00001810 2605#define BNX_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0) 2606 2607#define BNX_RPM_VLAN_MATCH1 0x00001814 2608#define BNX_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0) 2609 2610#define BNX_RPM_VLAN_MATCH2 0x00001818 2611#define BNX_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0) 2612 2613#define BNX_RPM_VLAN_MATCH3 0x0000181c 2614#define BNX_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0) 2615 2616#define BNX_RPM_SORT_USER0 0x00001820 2617#define BNX_RPM_SORT_USER0_PM_EN (0xffffL<<0) 2618#define BNX_RPM_SORT_USER0_BC_EN (1L<<16) 2619#define BNX_RPM_SORT_USER0_MC_EN (1L<<17) 2620#define BNX_RPM_SORT_USER0_MC_HSH_EN (1L<<18) 2621#define BNX_RPM_SORT_USER0_PROM_EN (1L<<19) 2622#define BNX_RPM_SORT_USER0_VLAN_EN (0xfL<<20) 2623#define BNX_RPM_SORT_USER0_PROM_VLAN (1L<<24) 2624#define BNX_RPM_SORT_USER0_ENA (1L<<31) 2625 2626#define BNX_RPM_SORT_USER1 0x00001824 2627#define BNX_RPM_SORT_USER1_PM_EN (0xffffL<<0) 2628#define BNX_RPM_SORT_USER1_BC_EN (1L<<16) 2629#define BNX_RPM_SORT_USER1_MC_EN (1L<<17) 2630#define BNX_RPM_SORT_USER1_MC_HSH_EN (1L<<18) 2631#define BNX_RPM_SORT_USER1_PROM_EN (1L<<19) 2632#define BNX_RPM_SORT_USER1_VLAN_EN (0xfL<<20) 2633#define BNX_RPM_SORT_USER1_PROM_VLAN (1L<<24) 2634#define BNX_RPM_SORT_USER1_ENA (1L<<31) 2635 2636#define BNX_RPM_SORT_USER2 0x00001828 2637#define BNX_RPM_SORT_USER2_PM_EN (0xffffL<<0) 2638#define BNX_RPM_SORT_USER2_BC_EN (1L<<16) 2639#define BNX_RPM_SORT_USER2_MC_EN (1L<<17) 2640#define BNX_RPM_SORT_USER2_MC_HSH_EN (1L<<18) 2641#define BNX_RPM_SORT_USER2_PROM_EN (1L<<19) 2642#define BNX_RPM_SORT_USER2_VLAN_EN (0xfL<<20) 2643#define BNX_RPM_SORT_USER2_PROM_VLAN (1L<<24) 2644#define BNX_RPM_SORT_USER2_ENA (1L<<31) 2645 2646#define BNX_RPM_SORT_USER3 0x0000182c 2647#define BNX_RPM_SORT_USER3_PM_EN (0xffffL<<0) 2648#define BNX_RPM_SORT_USER3_BC_EN (1L<<16) 2649#define BNX_RPM_SORT_USER3_MC_EN (1L<<17) 2650#define BNX_RPM_SORT_USER3_MC_HSH_EN (1L<<18) 2651#define BNX_RPM_SORT_USER3_PROM_EN (1L<<19) 2652#define BNX_RPM_SORT_USER3_VLAN_EN (0xfL<<20) 2653#define BNX_RPM_SORT_USER3_PROM_VLAN (1L<<24) 2654#define BNX_RPM_SORT_USER3_ENA (1L<<31) 2655 2656#define BNX_RPM_STAT_L2_FILTER_DISCARDS 0x00001840 2657#define BNX_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844 2658#define BNX_RPM_STAT_IFINFTQDISCARDS 0x00001848 2659#define BNX_RPM_STAT_IFINMBUFDISCARD 0x0000184c 2660#define BNX_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850 2661#define BNX_RPM_STAT_AC0 0x00001880 2662#define BNX_RPM_STAT_AC1 0x00001884 2663#define BNX_RPM_STAT_AC2 0x00001888 2664#define BNX_RPM_STAT_AC3 0x0000188c 2665#define BNX_RPM_STAT_AC4 0x00001890 2666#define BNX_RPM_RC_CNTL_0 0x00001900 2667#define BNX_RPM_RC_CNTL_0_OFFSET (0xffL<<0) 2668#define BNX_RPM_RC_CNTL_0_CLASS (0x7L<<8) 2669#define BNX_RPM_RC_CNTL_0_PRIORITY (1L<<11) 2670#define BNX_RPM_RC_CNTL_0_P4 (1L<<12) 2671#define BNX_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13) 2672#define BNX_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13) 2673#define BNX_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13) 2674#define BNX_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13) 2675#define BNX_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13) 2676#define BNX_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13) 2677#define BNX_RPM_RC_CNTL_0_COMP (0x3L<<16) 2678#define BNX_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16) 2679#define BNX_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16) 2680#define BNX_RPM_RC_CNTL_0_COMP_GREATER (2L<<16) 2681#define BNX_RPM_RC_CNTL_0_COMP_LESS (3L<<16) 2682#define BNX_RPM_RC_CNTL_0_SBIT (1L<<19) 2683#define BNX_RPM_RC_CNTL_0_CMDSEL (0xfL<<20) 2684#define BNX_RPM_RC_CNTL_0_MAP (1L<<24) 2685#define BNX_RPM_RC_CNTL_0_DISCARD (1L<<25) 2686#define BNX_RPM_RC_CNTL_0_MASK (1L<<26) 2687#define BNX_RPM_RC_CNTL_0_P1 (1L<<27) 2688#define BNX_RPM_RC_CNTL_0_P2 (1L<<28) 2689#define BNX_RPM_RC_CNTL_0_P3 (1L<<29) 2690#define BNX_RPM_RC_CNTL_0_NBIT (1L<<30) 2691 2692#define BNX_RPM_RC_VALUE_MASK_0 0x00001904 2693#define BNX_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0) 2694#define BNX_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16) 2695 2696#define BNX_RPM_RC_CNTL_1 0x00001908 2697#define BNX_RPM_RC_CNTL_1_A (0x3ffffL<<0) 2698#define BNX_RPM_RC_CNTL_1_B (0xfffL<<19) 2699 2700#define BNX_RPM_RC_VALUE_MASK_1 0x0000190c 2701#define BNX_RPM_RC_CNTL_2 0x00001910 2702#define BNX_RPM_RC_CNTL_2_A (0x3ffffL<<0) 2703#define BNX_RPM_RC_CNTL_2_B (0xfffL<<19) 2704 2705#define BNX_RPM_RC_VALUE_MASK_2 0x00001914 2706#define BNX_RPM_RC_CNTL_3 0x00001918 2707#define BNX_RPM_RC_CNTL_3_A (0x3ffffL<<0) 2708#define BNX_RPM_RC_CNTL_3_B (0xfffL<<19) 2709 2710#define BNX_RPM_RC_VALUE_MASK_3 0x0000191c 2711#define BNX_RPM_RC_CNTL_4 0x00001920 2712#define BNX_RPM_RC_CNTL_4_A (0x3ffffL<<0) 2713#define BNX_RPM_RC_CNTL_4_B (0xfffL<<19) 2714 2715#define BNX_RPM_RC_VALUE_MASK_4 0x00001924 2716#define BNX_RPM_RC_CNTL_5 0x00001928 2717#define BNX_RPM_RC_CNTL_5_A (0x3ffffL<<0) 2718#define BNX_RPM_RC_CNTL_5_B (0xfffL<<19) 2719 2720#define BNX_RPM_RC_VALUE_MASK_5 0x0000192c 2721#define BNX_RPM_RC_CNTL_6 0x00001930 2722#define BNX_RPM_RC_CNTL_6_A (0x3ffffL<<0) 2723#define BNX_RPM_RC_CNTL_6_B (0xfffL<<19) 2724 2725#define BNX_RPM_RC_VALUE_MASK_6 0x00001934 2726#define BNX_RPM_RC_CNTL_7 0x00001938 2727#define BNX_RPM_RC_CNTL_7_A (0x3ffffL<<0) 2728#define BNX_RPM_RC_CNTL_7_B (0xfffL<<19) 2729 2730#define BNX_RPM_RC_VALUE_MASK_7 0x0000193c 2731#define BNX_RPM_RC_CNTL_8 0x00001940 2732#define BNX_RPM_RC_CNTL_8_A (0x3ffffL<<0) 2733#define BNX_RPM_RC_CNTL_8_B (0xfffL<<19) 2734 2735#define BNX_RPM_RC_VALUE_MASK_8 0x00001944 2736#define BNX_RPM_RC_CNTL_9 0x00001948 2737#define BNX_RPM_RC_CNTL_9_A (0x3ffffL<<0) 2738#define BNX_RPM_RC_CNTL_9_B (0xfffL<<19) 2739 2740#define BNX_RPM_RC_VALUE_MASK_9 0x0000194c 2741#define BNX_RPM_RC_CNTL_10 0x00001950 2742#define BNX_RPM_RC_CNTL_10_A (0x3ffffL<<0) 2743#define BNX_RPM_RC_CNTL_10_B (0xfffL<<19) 2744 2745#define BNX_RPM_RC_VALUE_MASK_10 0x00001954 2746#define BNX_RPM_RC_CNTL_11 0x00001958 2747#define BNX_RPM_RC_CNTL_11_A (0x3ffffL<<0) 2748#define BNX_RPM_RC_CNTL_11_B (0xfffL<<19) 2749 2750#define BNX_RPM_RC_VALUE_MASK_11 0x0000195c 2751#define BNX_RPM_RC_CNTL_12 0x00001960 2752#define BNX_RPM_RC_CNTL_12_A (0x3ffffL<<0) 2753#define BNX_RPM_RC_CNTL_12_B (0xfffL<<19) 2754 2755#define BNX_RPM_RC_VALUE_MASK_12 0x00001964 2756#define BNX_RPM_RC_CNTL_13 0x00001968 2757#define BNX_RPM_RC_CNTL_13_A (0x3ffffL<<0) 2758#define BNX_RPM_RC_CNTL_13_B (0xfffL<<19) 2759 2760#define BNX_RPM_RC_VALUE_MASK_13 0x0000196c 2761#define BNX_RPM_RC_CNTL_14 0x00001970 2762#define BNX_RPM_RC_CNTL_14_A (0x3ffffL<<0) 2763#define BNX_RPM_RC_CNTL_14_B (0xfffL<<19) 2764 2765#define BNX_RPM_RC_VALUE_MASK_14 0x00001974 2766#define BNX_RPM_RC_CNTL_15 0x00001978 2767#define BNX_RPM_RC_CNTL_15_A (0x3ffffL<<0) 2768#define BNX_RPM_RC_CNTL_15_B (0xfffL<<19) 2769 2770#define BNX_RPM_RC_VALUE_MASK_15 0x0000197c 2771#define BNX_RPM_RC_CONFIG 0x00001980 2772#define BNX_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0) 2773#define BNX_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24) 2774 2775#define BNX_RPM_DEBUG0 0x00001984 2776#define BNX_RPM_DEBUG0_FM_BCNT (0xffffL<<0) 2777#define BNX_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16) 2778#define BNX_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17) 2779#define BNX_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18) 2780#define BNX_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19) 2781#define BNX_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20) 2782#define BNX_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21) 2783#define BNX_RPM_DEBUG0_LLC_SNAP (1L<<22) 2784#define BNX_RPM_DEBUG0_FM_STARTED (1L<<23) 2785#define BNX_RPM_DEBUG0_DONE (1L<<24) 2786#define BNX_RPM_DEBUG0_WAIT_4_DONE (1L<<25) 2787#define BNX_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26) 2788#define BNX_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27) 2789#define BNX_RPM_DEBUG0_IGNORE_VLAN (1L<<28) 2790#define BNX_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31) 2791 2792#define BNX_RPM_DEBUG1 0x00001988 2793#define BNX_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0) 2794#define BNX_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0) 2795#define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0) 2796#define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0) 2797#define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0) 2798#define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0) 2799#define BNX_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0) 2800#define BNX_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0) 2801#define BNX_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0) 2802#define BNX_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0) 2803#define BNX_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0) 2804#define BNX_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0) 2805#define BNX_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0) 2806#define BNX_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0) 2807#define BNX_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0) 2808#define BNX_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0) 2809#define BNX_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0) 2810#define BNX_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16) 2811#define BNX_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28) 2812#define BNX_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29) 2813#define BNX_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30) 2814#define BNX_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31) 2815 2816#define BNX_RPM_DEBUG2 0x0000198c 2817#define BNX_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0) 2818#define BNX_RPM_DEBUG2_IP_BCNT (0xffL<<16) 2819#define BNX_RPM_DEBUG2_THIS_CMD_M4 (1L<<24) 2820#define BNX_RPM_DEBUG2_THIS_CMD_M3 (1L<<25) 2821#define BNX_RPM_DEBUG2_THIS_CMD_M2 (1L<<26) 2822#define BNX_RPM_DEBUG2_THIS_CMD_M1 (1L<<27) 2823#define BNX_RPM_DEBUG2_IPIPE_EMPTY (1L<<28) 2824#define BNX_RPM_DEBUG2_FM_DISCARD (1L<<29) 2825#define BNX_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30) 2826#define BNX_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31) 2827 2828#define BNX_RPM_DEBUG3 0x00001990 2829#define BNX_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0) 2830#define BNX_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9) 2831#define BNX_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10) 2832#define BNX_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11) 2833#define BNX_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12) 2834#define BNX_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13) 2835#define BNX_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14) 2836#define BNX_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15) 2837#define BNX_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16) 2838#define BNX_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21) 2839#define BNX_RPM_DEBUG3_DROP_NXT_VLD (1L<<22) 2840#define BNX_RPM_DEBUG3_DROP_NXT (1L<<23) 2841#define BNX_RPM_DEBUG3_FTQ_FSM (0x3L<<24) 2842#define BNX_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24) 2843#define BNX_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24) 2844#define BNX_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24) 2845#define BNX_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26) 2846#define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26) 2847#define BNX_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26) 2848#define BNX_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26) 2849#define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26) 2850#define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26) 2851#define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26) 2852#define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26) 2853#define BNX_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26) 2854#define BNX_RPM_DEBUG3_MBFREE_FSM (1L<<29) 2855#define BNX_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29) 2856#define BNX_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29) 2857#define BNX_RPM_DEBUG3_MBALLOC_FSM (1L<<30) 2858#define BNX_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30) 2859#define BNX_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30) 2860#define BNX_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31) 2861 2862#define BNX_RPM_DEBUG4 0x00001994 2863#define BNX_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0) 2864#define BNX_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25) 2865#define BNX_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28) 2866#define BNX_RPM_DEBUG4_DFIFO_EMPTY (1L<<31) 2867 2868#define BNX_RPM_DEBUG5 0x00001998 2869#define BNX_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0) 2870#define BNX_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5) 2871#define BNX_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10) 2872#define BNX_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15) 2873#define BNX_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20) 2874#define BNX_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21) 2875#define BNX_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22) 2876#define BNX_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23) 2877#define BNX_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24) 2878#define BNX_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25) 2879#define BNX_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26) 2880#define BNX_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27) 2881#define BNX_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28) 2882#define BNX_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29) 2883#define BNX_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30) 2884#define BNX_RPM_DEBUG5_HOLDREG_RD (1L<<31) 2885 2886#define BNX_RPM_DEBUG6 0x0000199c 2887#define BNX_RPM_DEBUG6_ACPI_VEC (0xffffL<<0) 2888#define BNX_RPM_DEBUG6_VEC (0xffffL<<16) 2889 2890#define BNX_RPM_DEBUG7 0x000019a0 2891#define BNX_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0) 2892 2893#define BNX_RPM_DEBUG8 0x000019a4 2894#define BNX_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0) 2895#define BNX_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0) 2896#define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0) 2897#define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0) 2898#define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0) 2899#define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0) 2900#define BNX_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0) 2901#define BNX_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0) 2902#define BNX_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0) 2903#define BNX_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0) 2904#define BNX_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0) 2905#define BNX_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0) 2906#define BNX_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4) 2907#define BNX_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5) 2908#define BNX_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6) 2909#define BNX_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7) 2910#define BNX_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8) 2911#define BNX_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9) 2912#define BNX_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10) 2913#define BNX_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11) 2914#define BNX_RPM_DEBUG8_EOF_DET (1L<<12) 2915#define BNX_RPM_DEBUG8_SOF_DET (1L<<13) 2916#define BNX_RPM_DEBUG8_WAIT_4_SOF (1L<<14) 2917#define BNX_RPM_DEBUG8_ALL_DONE (1L<<15) 2918#define BNX_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16) 2919#define BNX_RPM_DEBUG8_BYTE_CTR (0xffL<<24) 2920 2921#define BNX_RPM_DEBUG9 0x000019a8 2922#define BNX_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0) 2923#define BNX_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3) 2924#define BNX_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4) 2925#define BNX_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28) 2926#define BNX_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29) 2927#define BNX_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30) 2928#define BNX_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31) 2929 2930#define BNX_RPM_ACPI_DBG_BUF_W00 0x000019c0 2931#define BNX_RPM_ACPI_DBG_BUF_W01 0x000019c4 2932#define BNX_RPM_ACPI_DBG_BUF_W02 0x000019c8 2933#define BNX_RPM_ACPI_DBG_BUF_W03 0x000019cc 2934#define BNX_RPM_ACPI_DBG_BUF_W10 0x000019d0 2935#define BNX_RPM_ACPI_DBG_BUF_W11 0x000019d4 2936#define BNX_RPM_ACPI_DBG_BUF_W12 0x000019d8 2937#define BNX_RPM_ACPI_DBG_BUF_W13 0x000019dc 2938#define BNX_RPM_ACPI_DBG_BUF_W20 0x000019e0 2939#define BNX_RPM_ACPI_DBG_BUF_W21 0x000019e4 2940#define BNX_RPM_ACPI_DBG_BUF_W22 0x000019e8 2941#define BNX_RPM_ACPI_DBG_BUF_W23 0x000019ec 2942#define BNX_RPM_ACPI_DBG_BUF_W30 0x000019f0 2943#define BNX_RPM_ACPI_DBG_BUF_W31 0x000019f4 2944#define BNX_RPM_ACPI_DBG_BUF_W32 0x000019f8 2945#define BNX_RPM_ACPI_DBG_BUF_W33 0x000019fc 2946 2947 2948/* 2949 * rbuf_reg definition 2950 * offset: 0x200000 2951 */ 2952#define BNX_RBUF_COMMAND 0x00200000 2953#define BNX_RBUF_COMMAND_ENABLED (1L<<0) 2954#define BNX_RBUF_COMMAND_FREE_INIT (1L<<1) 2955#define BNX_RBUF_COMMAND_RAM_INIT (1L<<2) 2956#define BNX_RBUF_COMMAND_OVER_FREE (1L<<4) 2957#define BNX_RBUF_COMMAND_ALLOC_REQ (1L<<5) 2958 2959#define BNX_RBUF_STATUS1 0x00200004 2960#define BNX_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0) 2961 2962#define BNX_RBUF_STATUS2 0x00200008 2963#define BNX_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0) 2964#define BNX_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16) 2965 2966#define BNX_RBUF_CONFIG 0x0020000c 2967#define BNX_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0) 2968#define BNX_RBUF_CONFIG_XON_TRIP (0x3ffL<<16) 2969 2970#define BNX_RBUF_FW_BUF_ALLOC 0x00200010 2971#define BNX_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7) 2972 2973#define BNX_RBUF_FW_BUF_FREE 0x00200014 2974#define BNX_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0) 2975#define BNX_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7) 2976#define BNX_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16) 2977 2978#define BNX_RBUF_FW_BUF_SEL 0x00200018 2979#define BNX_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0) 2980#define BNX_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7) 2981#define BNX_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16) 2982 2983#define BNX_RBUF_CONFIG2 0x0020001c 2984#define BNX_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0) 2985#define BNX_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16) 2986 2987#define BNX_RBUF_CONFIG3 0x00200020 2988#define BNX_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0) 2989#define BNX_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16) 2990 2991#define BNX_RBUF_PKT_DATA 0x00208000 2992#define BNX_RBUF_CLIST_DATA 0x00210000 2993#define BNX_RBUF_BUF_DATA 0x00220000 2994 2995 2996/* 2997 * rv2p_reg definition 2998 * offset: 0x2800 2999 */ 3000#define BNX_RV2P_COMMAND 0x00002800 3001#define BNX_RV2P_COMMAND_ENABLED (1L<<0) 3002#define BNX_RV2P_COMMAND_PROC1_INTRPT (1L<<1) 3003#define BNX_RV2P_COMMAND_PROC2_INTRPT (1L<<2) 3004#define BNX_RV2P_COMMAND_ABORT0 (1L<<4) 3005#define BNX_RV2P_COMMAND_ABORT1 (1L<<5) 3006#define BNX_RV2P_COMMAND_ABORT2 (1L<<6) 3007#define BNX_RV2P_COMMAND_ABORT3 (1L<<7) 3008#define BNX_RV2P_COMMAND_ABORT4 (1L<<8) 3009#define BNX_RV2P_COMMAND_ABORT5 (1L<<9) 3010#define BNX_RV2P_COMMAND_PROC1_RESET (1L<<16) 3011#define BNX_RV2P_COMMAND_PROC2_RESET (1L<<17) 3012#define BNX_RV2P_COMMAND_CTXIF_RESET (1L<<18) 3013 3014#define BNX_RV2P_STATUS 0x00002804 3015#define BNX_RV2P_STATUS_ALWAYS_0 (1L<<0) 3016#define BNX_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8) 3017#define BNX_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9) 3018#define BNX_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10) 3019#define BNX_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11) 3020#define BNX_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12) 3021#define BNX_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13) 3022 3023#define BNX_RV2P_CONFIG 0x00002808 3024#define BNX_RV2P_CONFIG_STALL_PROC1 (1L<<0) 3025#define BNX_RV2P_CONFIG_STALL_PROC2 (1L<<1) 3026#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8) 3027#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9) 3028#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10) 3029#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11) 3030#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12) 3031#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13) 3032#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16) 3033#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17) 3034#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18) 3035#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19) 3036#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20) 3037#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21) 3038#define BNX_RV2P_CONFIG_PAGE_SIZE (0xfL<<24) 3039#define BNX_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24) 3040#define BNX_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24) 3041#define BNX_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24) 3042#define BNX_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24) 3043#define BNX_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24) 3044#define BNX_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24) 3045#define BNX_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24) 3046#define BNX_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24) 3047#define BNX_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24) 3048#define BNX_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24) 3049#define BNX_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24) 3050#define BNX_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24) 3051#define BNX_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24) 3052 3053#define BNX_RV2P_GEN_BFR_ADDR_0 0x00002810 3054#define BNX_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16) 3055 3056#define BNX_RV2P_GEN_BFR_ADDR_1 0x00002814 3057#define BNX_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16) 3058 3059#define BNX_RV2P_GEN_BFR_ADDR_2 0x00002818 3060#define BNX_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16) 3061 3062#define BNX_RV2P_GEN_BFR_ADDR_3 0x0000281c 3063#define BNX_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16) 3064 3065#define BNX_RV2P_INSTR_HIGH 0x00002830 3066#define BNX_RV2P_INSTR_HIGH_HIGH (0x1fL<<0) 3067 3068#define BNX_RV2P_INSTR_LOW 0x00002834 3069#define BNX_RV2P_PROC1_ADDR_CMD 0x00002838 3070#define BNX_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0) 3071#define BNX_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31) 3072 3073#define BNX_RV2P_PROC2_ADDR_CMD 0x0000283c 3074#define BNX_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0) 3075#define BNX_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31) 3076 3077#define BNX_RV2P_PROC1_GRC_DEBUG 0x00002840 3078#define BNX_RV2P_PROC2_GRC_DEBUG 0x00002844 3079#define BNX_RV2P_GRC_PROC_DEBUG 0x00002848 3080#define BNX_RV2P_DEBUG_VECT_PEEK 0x0000284c 3081#define BNX_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3082#define BNX_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3083#define BNX_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3084#define BNX_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3085#define BNX_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3086#define BNX_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3087 3088#define BNX_RV2P_PFTQ_DATA 0x00002b40 3089#define BNX_RV2P_PFTQ_CMD 0x00002b78 3090#define BNX_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0) 3091#define BNX_RV2P_PFTQ_CMD_WR_TOP (1L<<10) 3092#define BNX_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10) 3093#define BNX_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10) 3094#define BNX_RV2P_PFTQ_CMD_SFT_RESET (1L<<25) 3095#define BNX_RV2P_PFTQ_CMD_RD_DATA (1L<<26) 3096#define BNX_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27) 3097#define BNX_RV2P_PFTQ_CMD_ADD_DATA (1L<<28) 3098#define BNX_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29) 3099#define BNX_RV2P_PFTQ_CMD_POP (1L<<30) 3100#define BNX_RV2P_PFTQ_CMD_BUSY (1L<<31) 3101 3102#define BNX_RV2P_PFTQ_CTL 0x00002b7c 3103#define BNX_RV2P_PFTQ_CTL_INTERVENE (1L<<0) 3104#define BNX_RV2P_PFTQ_CTL_OVERFLOW (1L<<1) 3105#define BNX_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2) 3106#define BNX_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3107#define BNX_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3108 3109#define BNX_RV2P_TFTQ_DATA 0x00002b80 3110#define BNX_RV2P_TFTQ_CMD 0x00002bb8 3111#define BNX_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0) 3112#define BNX_RV2P_TFTQ_CMD_WR_TOP (1L<<10) 3113#define BNX_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10) 3114#define BNX_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10) 3115#define BNX_RV2P_TFTQ_CMD_SFT_RESET (1L<<25) 3116#define BNX_RV2P_TFTQ_CMD_RD_DATA (1L<<26) 3117#define BNX_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27) 3118#define BNX_RV2P_TFTQ_CMD_ADD_DATA (1L<<28) 3119#define BNX_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29) 3120#define BNX_RV2P_TFTQ_CMD_POP (1L<<30) 3121#define BNX_RV2P_TFTQ_CMD_BUSY (1L<<31) 3122 3123#define BNX_RV2P_TFTQ_CTL 0x00002bbc 3124#define BNX_RV2P_TFTQ_CTL_INTERVENE (1L<<0) 3125#define BNX_RV2P_TFTQ_CTL_OVERFLOW (1L<<1) 3126#define BNX_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2) 3127#define BNX_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3128#define BNX_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3129 3130#define BNX_RV2P_MFTQ_DATA 0x00002bc0 3131#define BNX_RV2P_MFTQ_CMD 0x00002bf8 3132#define BNX_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0) 3133#define BNX_RV2P_MFTQ_CMD_WR_TOP (1L<<10) 3134#define BNX_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10) 3135#define BNX_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10) 3136#define BNX_RV2P_MFTQ_CMD_SFT_RESET (1L<<25) 3137#define BNX_RV2P_MFTQ_CMD_RD_DATA (1L<<26) 3138#define BNX_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27) 3139#define BNX_RV2P_MFTQ_CMD_ADD_DATA (1L<<28) 3140#define BNX_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29) 3141#define BNX_RV2P_MFTQ_CMD_POP (1L<<30) 3142#define BNX_RV2P_MFTQ_CMD_BUSY (1L<<31) 3143 3144#define BNX_RV2P_MFTQ_CTL 0x00002bfc 3145#define BNX_RV2P_MFTQ_CTL_INTERVENE (1L<<0) 3146#define BNX_RV2P_MFTQ_CTL_OVERFLOW (1L<<1) 3147#define BNX_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2) 3148#define BNX_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3149#define BNX_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3150 3151 3152 3153/* 3154 * mq_reg definition 3155 * offset: 0x3c00 3156 */ 3157#define BNX_MQ_COMMAND 0x00003c00 3158#define BNX_MQ_COMMAND_ENABLED (1L<<0) 3159#define BNX_MQ_COMMAND_OVERFLOW (1L<<4) 3160#define BNX_MQ_COMMAND_WR_ERROR (1L<<5) 3161#define BNX_MQ_COMMAND_RD_ERROR (1L<<6) 3162 3163#define BNX_MQ_STATUS 0x00003c04 3164#define BNX_MQ_STATUS_CTX_ACCESS_STAT (1L<<16) 3165#define BNX_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17) 3166#define BNX_MQ_STATUS_PCI_STALL_STAT (1L<<18) 3167 3168#define BNX_MQ_CONFIG 0x00003c08 3169#define BNX_MQ_CONFIG_TX_HIGH_PRI (1L<<0) 3170#define BNX_MQ_CONFIG_HALT_DIS (1L<<1) 3171#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4) 3172#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4) 3173#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4) 3174#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4) 3175#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4) 3176#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4) 3177#define BNX_MQ_CONFIG_MAX_DEPTH (0x7fL<<8) 3178#define BNX_MQ_CONFIG_CUR_DEPTH (0x7fL<<20) 3179 3180#define BNX_MQ_ENQUEUE1 0x00003c0c 3181#define BNX_MQ_ENQUEUE1_OFFSET (0x3fL<<2) 3182#define BNX_MQ_ENQUEUE1_CID (0x3fffL<<8) 3183#define BNX_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24) 3184#define BNX_MQ_ENQUEUE1_KNL_MODE (1L<<28) 3185 3186#define BNX_MQ_ENQUEUE2 0x00003c10 3187#define BNX_MQ_BAD_WR_ADDR 0x00003c14 3188#define BNX_MQ_BAD_RD_ADDR 0x00003c18 3189#define BNX_MQ_KNL_BYP_WIND_START 0x00003c1c 3190#define BNX_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12) 3191 3192#define BNX_MQ_KNL_WIND_END 0x00003c20 3193#define BNX_MQ_KNL_WIND_END_VALUE (0xffffffL<<8) 3194 3195#define BNX_MQ_KNL_WRITE_MASK1 0x00003c24 3196#define BNX_MQ_KNL_TX_MASK1 0x00003c28 3197#define BNX_MQ_KNL_CMD_MASK1 0x00003c2c 3198#define BNX_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30 3199#define BNX_MQ_KNL_RX_V2P_MASK1 0x00003c34 3200#define BNX_MQ_KNL_WRITE_MASK2 0x00003c38 3201#define BNX_MQ_KNL_TX_MASK2 0x00003c3c 3202#define BNX_MQ_KNL_CMD_MASK2 0x00003c40 3203#define BNX_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44 3204#define BNX_MQ_KNL_RX_V2P_MASK2 0x00003c48 3205#define BNX_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c 3206#define BNX_MQ_KNL_BYP_TX_MASK1 0x00003c50 3207#define BNX_MQ_KNL_BYP_CMD_MASK1 0x00003c54 3208#define BNX_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58 3209#define BNX_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c 3210#define BNX_MQ_KNL_BYP_WRITE_MASK2 0x00003c60 3211#define BNX_MQ_KNL_BYP_TX_MASK2 0x00003c64 3212#define BNX_MQ_KNL_BYP_CMD_MASK2 0x00003c68 3213#define BNX_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c 3214#define BNX_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70 3215#define BNX_MQ_MEM_WR_ADDR 0x00003c74 3216#define BNX_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0) 3217 3218#define BNX_MQ_MEM_WR_DATA0 0x00003c78 3219#define BNX_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0) 3220 3221#define BNX_MQ_MEM_WR_DATA1 0x00003c7c 3222#define BNX_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0) 3223 3224#define BNX_MQ_MEM_WR_DATA2 0x00003c80 3225#define BNX_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0) 3226 3227#define BNX_MQ_MEM_RD_ADDR 0x00003c84 3228#define BNX_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0) 3229 3230#define BNX_MQ_MEM_RD_DATA0 0x00003c88 3231#define BNX_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0) 3232 3233#define BNX_MQ_MEM_RD_DATA1 0x00003c8c 3234#define BNX_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0) 3235 3236#define BNX_MQ_MEM_RD_DATA2 0x00003c90 3237#define BNX_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0) 3238 3239 3240 3241/* 3242 * tbdr_reg definition 3243 * offset: 0x5000 3244 */ 3245#define BNX_TBDR_COMMAND 0x00005000 3246#define BNX_TBDR_COMMAND_ENABLE (1L<<0) 3247#define BNX_TBDR_COMMAND_SOFT_RST (1L<<1) 3248#define BNX_TBDR_COMMAND_MSTR_ABORT (1L<<4) 3249 3250#define BNX_TBDR_STATUS 0x00005004 3251#define BNX_TBDR_STATUS_DMA_WAIT (1L<<0) 3252#define BNX_TBDR_STATUS_FTQ_WAIT (1L<<1) 3253#define BNX_TBDR_STATUS_FIFO_OVERFLOW (1L<<2) 3254#define BNX_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3) 3255#define BNX_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4) 3256#define BNX_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5) 3257#define BNX_TBDR_STATUS_BURST_CNT (1L<<6) 3258 3259#define BNX_TBDR_CONFIG 0x00005008 3260#define BNX_TBDR_CONFIG_MAX_BDS (0xffL<<0) 3261#define BNX_TBDR_CONFIG_SWAP_MODE (1L<<8) 3262#define BNX_TBDR_CONFIG_PRIORITY (1L<<9) 3263#define BNX_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10) 3264#define BNX_TBDR_CONFIG_PAGE_SIZE (0xfL<<24) 3265#define BNX_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24) 3266#define BNX_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24) 3267#define BNX_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24) 3268#define BNX_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24) 3269#define BNX_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24) 3270#define BNX_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24) 3271#define BNX_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24) 3272#define BNX_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24) 3273#define BNX_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24) 3274#define BNX_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24) 3275#define BNX_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24) 3276#define BNX_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24) 3277#define BNX_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24) 3278 3279#define BNX_TBDR_DEBUG_VECT_PEEK 0x0000500c 3280#define BNX_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3281#define BNX_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3282#define BNX_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3283#define BNX_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3284#define BNX_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3285#define BNX_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3286 3287#define BNX_TBDR_FTQ_DATA 0x000053c0 3288#define BNX_TBDR_FTQ_CMD 0x000053f8 3289#define BNX_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0) 3290#define BNX_TBDR_FTQ_CMD_WR_TOP (1L<<10) 3291#define BNX_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10) 3292#define BNX_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10) 3293#define BNX_TBDR_FTQ_CMD_SFT_RESET (1L<<25) 3294#define BNX_TBDR_FTQ_CMD_RD_DATA (1L<<26) 3295#define BNX_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27) 3296#define BNX_TBDR_FTQ_CMD_ADD_DATA (1L<<28) 3297#define BNX_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29) 3298#define BNX_TBDR_FTQ_CMD_POP (1L<<30) 3299#define BNX_TBDR_FTQ_CMD_BUSY (1L<<31) 3300 3301#define BNX_TBDR_FTQ_CTL 0x000053fc 3302#define BNX_TBDR_FTQ_CTL_INTERVENE (1L<<0) 3303#define BNX_TBDR_FTQ_CTL_OVERFLOW (1L<<1) 3304#define BNX_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3305#define BNX_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3306#define BNX_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3307 3308 3309 3310/* 3311 * tdma_reg definition 3312 * offset: 0x5c00 3313 */ 3314#define BNX_TDMA_COMMAND 0x00005c00 3315#define BNX_TDMA_COMMAND_ENABLED (1L<<0) 3316#define BNX_TDMA_COMMAND_MASTER_ABORT (1L<<4) 3317#define BNX_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7) 3318 3319#define BNX_TDMA_STATUS 0x00005c04 3320#define BNX_TDMA_STATUS_DMA_WAIT (1L<<0) 3321#define BNX_TDMA_STATUS_PAYLOAD_WAIT (1L<<1) 3322#define BNX_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2) 3323#define BNX_TDMA_STATUS_LOCK_WAIT (1L<<3) 3324#define BNX_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16) 3325#define BNX_TDMA_STATUS_BURST_CNT (1L<<17) 3326 3327#define BNX_TDMA_CONFIG 0x00005c08 3328#define BNX_TDMA_CONFIG_ONE_DMA (1L<<0) 3329#define BNX_TDMA_CONFIG_ONE_RECORD (1L<<1) 3330#define BNX_TDMA_CONFIG_LIMIT_SZ (0xfL<<4) 3331#define BNX_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4) 3332#define BNX_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4) 3333#define BNX_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4) 3334#define BNX_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4) 3335#define BNX_TDMA_CONFIG_LINE_SZ (0xfL<<8) 3336#define BNX_TDMA_CONFIG_LINE_SZ_64 (0L<<8) 3337#define BNX_TDMA_CONFIG_LINE_SZ_128 (4L<<8) 3338#define BNX_TDMA_CONFIG_LINE_SZ_256 (6L<<8) 3339#define BNX_TDMA_CONFIG_LINE_SZ_512 (8L<<8) 3340#define BNX_TDMA_CONFIG_ALIGN_ENA (1L<<15) 3341#define BNX_TDMA_CONFIG_CHK_L2_BD (1L<<16) 3342#define BNX_TDMA_CONFIG_FIFO_CMP (0xfL<<20) 3343 3344#define BNX_TDMA_PAYLOAD_PROD 0x00005c0c 3345#define BNX_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3) 3346 3347#define BNX_TDMA_DBG_WATCHDOG 0x00005c10 3348#define BNX_TDMA_DBG_TRIGGER 0x00005c14 3349#define BNX_TDMA_DMAD_FSM 0x00005c80 3350#define BNX_TDMA_DMAD_FSM_BD_INVLD (1L<<0) 3351#define BNX_TDMA_DMAD_FSM_PUSH (0xfL<<4) 3352#define BNX_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8) 3353#define BNX_TDMA_DMAD_FSM_ARB_CTX (1L<<12) 3354#define BNX_TDMA_DMAD_FSM_DR_INTF (1L<<16) 3355#define BNX_TDMA_DMAD_FSM_DMAD (0x7L<<20) 3356#define BNX_TDMA_DMAD_FSM_BD (0xfL<<24) 3357 3358#define BNX_TDMA_DMAD_STATUS 0x00005c84 3359#define BNX_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0) 3360#define BNX_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4) 3361#define BNX_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8) 3362#define BNX_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12) 3363 3364#define BNX_TDMA_DR_INTF_FSM 0x00005c88 3365#define BNX_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0) 3366#define BNX_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4) 3367#define BNX_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8) 3368#define BNX_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12) 3369#define BNX_TDMA_DR_INTF_FSM_DMAD (0x7L<<16) 3370 3371#define BNX_TDMA_DR_INTF_STATUS 0x00005c8c 3372#define BNX_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0) 3373#define BNX_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4) 3374#define BNX_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8) 3375#define BNX_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12) 3376#define BNX_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16) 3377 3378#define BNX_TDMA_FTQ_DATA 0x00005fc0 3379#define BNX_TDMA_FTQ_CMD 0x00005ff8 3380#define BNX_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0) 3381#define BNX_TDMA_FTQ_CMD_WR_TOP (1L<<10) 3382#define BNX_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10) 3383#define BNX_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10) 3384#define BNX_TDMA_FTQ_CMD_SFT_RESET (1L<<25) 3385#define BNX_TDMA_FTQ_CMD_RD_DATA (1L<<26) 3386#define BNX_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27) 3387#define BNX_TDMA_FTQ_CMD_ADD_DATA (1L<<28) 3388#define BNX_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29) 3389#define BNX_TDMA_FTQ_CMD_POP (1L<<30) 3390#define BNX_TDMA_FTQ_CMD_BUSY (1L<<31) 3391 3392#define BNX_TDMA_FTQ_CTL 0x00005ffc 3393#define BNX_TDMA_FTQ_CTL_INTERVENE (1L<<0) 3394#define BNX_TDMA_FTQ_CTL_OVERFLOW (1L<<1) 3395#define BNX_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3396#define BNX_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3397#define BNX_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3398 3399 3400 3401/* 3402 * hc_reg definition 3403 * offset: 0x6800 3404 */ 3405#define BNX_HC_COMMAND 0x00006800 3406#define BNX_HC_COMMAND_ENABLE (1L<<0) 3407#define BNX_HC_COMMAND_SKIP_ABORT (1L<<4) 3408#define BNX_HC_COMMAND_COAL_NOW (1L<<16) 3409#define BNX_HC_COMMAND_COAL_NOW_WO_INT (1L<<17) 3410#define BNX_HC_COMMAND_STATS_NOW (1L<<18) 3411#define BNX_HC_COMMAND_FORCE_INT (0x3L<<19) 3412#define BNX_HC_COMMAND_FORCE_INT_NULL (0L<<19) 3413#define BNX_HC_COMMAND_FORCE_INT_HIGH (1L<<19) 3414#define BNX_HC_COMMAND_FORCE_INT_LOW (2L<<19) 3415#define BNX_HC_COMMAND_FORCE_INT_FREE (3L<<19) 3416#define BNX_HC_COMMAND_CLR_STAT_NOW (1L<<21) 3417 3418#define BNX_HC_STATUS 0x00006804 3419#define BNX_HC_STATUS_MASTER_ABORT (1L<<0) 3420#define BNX_HC_STATUS_PARITY_ERROR_STATE (1L<<1) 3421#define BNX_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16) 3422#define BNX_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17) 3423#define BNX_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18) 3424#define BNX_HC_STATUS_NUM_INT_GEN_STAT (1L<<19) 3425#define BNX_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20) 3426#define BNX_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23) 3427#define BNX_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24) 3428#define BNX_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25) 3429 3430#define BNX_HC_CONFIG 0x00006808 3431#define BNX_HC_CONFIG_COLLECT_STATS (1L<<0) 3432#define BNX_HC_CONFIG_RX_TMR_MODE (1L<<1) 3433#define BNX_HC_CONFIG_TX_TMR_MODE (1L<<2) 3434#define BNX_HC_CONFIG_COM_TMR_MODE (1L<<3) 3435#define BNX_HC_CONFIG_CMD_TMR_MODE (1L<<4) 3436#define BNX_HC_CONFIG_STATISTIC_PRIORITY (1L<<5) 3437#define BNX_HC_CONFIG_STATUS_PRIORITY (1L<<6) 3438#define BNX_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8) 3439 3440#define BNX_HC_ATTN_BITS_ENABLE 0x0000680c 3441#define BNX_HC_STATUS_ADDR_L 0x00006810 3442#define BNX_HC_STATUS_ADDR_H 0x00006814 3443#define BNX_HC_STATISTICS_ADDR_L 0x00006818 3444#define BNX_HC_STATISTICS_ADDR_H 0x0000681c 3445#define BNX_HC_TX_QUICK_CONS_TRIP 0x00006820 3446#define BNX_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 3447#define BNX_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16) 3448 3449#define BNX_HC_COMP_PROD_TRIP 0x00006824 3450#define BNX_HC_COMP_PROD_TRIP_VALUE (0xffL<<0) 3451#define BNX_HC_COMP_PROD_TRIP_INT (0xffL<<16) 3452 3453#define BNX_HC_RX_QUICK_CONS_TRIP 0x00006828 3454#define BNX_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 3455#define BNX_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16) 3456 3457#define BNX_HC_RX_TICKS 0x0000682c 3458#define BNX_HC_RX_TICKS_VALUE (0x3ffL<<0) 3459#define BNX_HC_RX_TICKS_INT (0x3ffL<<16) 3460 3461#define BNX_HC_TX_TICKS 0x00006830 3462#define BNX_HC_TX_TICKS_VALUE (0x3ffL<<0) 3463#define BNX_HC_TX_TICKS_INT (0x3ffL<<16) 3464 3465#define BNX_HC_COM_TICKS 0x00006834 3466#define BNX_HC_COM_TICKS_VALUE (0x3ffL<<0) 3467#define BNX_HC_COM_TICKS_INT (0x3ffL<<16) 3468 3469#define BNX_HC_CMD_TICKS 0x00006838 3470#define BNX_HC_CMD_TICKS_VALUE (0x3ffL<<0) 3471#define BNX_HC_CMD_TICKS_INT (0x3ffL<<16) 3472 3473#define BNX_HC_PERIODIC_TICKS 0x0000683c 3474#define BNX_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0) 3475 3476#define BNX_HC_STAT_COLLECT_TICKS 0x00006840 3477#define BNX_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4) 3478 3479#define BNX_HC_STATS_TICKS 0x00006844 3480#define BNX_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8) 3481 3482#define BNX_HC_STAT_MEM_DATA 0x0000684c 3483#define BNX_HC_STAT_GEN_SEL_0 0x00006850 3484#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0) 3485#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0) 3486#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0) 3487#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0) 3488#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0) 3489#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0) 3490#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0) 3491#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0) 3492#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0) 3493#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0) 3494#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0) 3495#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0) 3496#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0) 3497#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0) 3498#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0) 3499#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0) 3500#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0) 3501#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0) 3502#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0) 3503#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0) 3504#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0) 3505#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0) 3506#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0) 3507#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0) 3508#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0) 3509#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0) 3510#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0) 3511#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0) 3512#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0) 3513#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0) 3514#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0) 3515#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0) 3516#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0) 3517#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0) 3518#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0) 3519#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0) 3520#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0) 3521#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0) 3522#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0) 3523#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0) 3524#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0) 3525#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0) 3526#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0) 3527#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0) 3528#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0) 3529#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0) 3530#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0) 3531#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0) 3532#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0) 3533#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0) 3534#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0) 3535#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0) 3536#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0) 3537#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0) 3538#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0) 3539#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0) 3540#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0) 3541#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0) 3542#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0) 3543#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0) 3544#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0) 3545#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0) 3546#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0) 3547#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0) 3548#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0) 3549#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0) 3550#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0) 3551#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0) 3552#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0) 3553#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0) 3554#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0) 3555#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0) 3556#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0) 3557#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0) 3558#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0) 3559#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0) 3560#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0) 3561#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0) 3562#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0) 3563#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0) 3564#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0) 3565#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0) 3566#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0) 3567#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0) 3568#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0) 3569#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0) 3570#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0) 3571#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0) 3572#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0) 3573#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0) 3574#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0) 3575#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0) 3576#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0) 3577#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0) 3578#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0) 3579#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0) 3580#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0) 3581#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0) 3582#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0) 3583#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0) 3584#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0) 3585#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0) 3586#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0) 3587#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0) 3588#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0) 3589#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0) 3590#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0) 3591#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0) 3592#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0) 3593#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0) 3594#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0) 3595#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0) 3596#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0) 3597#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0) 3598#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0) 3599#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0) 3600#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0) 3601#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0) 3602#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0) 3603#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0) 3604#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0) 3605#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0) 3606#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0) 3607#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8) 3608#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16) 3609#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24) 3610 3611#define BNX_HC_STAT_GEN_SEL_1 0x00006854 3612#define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0) 3613#define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8) 3614#define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16) 3615#define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24) 3616 3617#define BNX_HC_STAT_GEN_SEL_2 0x00006858 3618#define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0) 3619#define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8) 3620#define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16) 3621#define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24) 3622 3623#define BNX_HC_STAT_GEN_SEL_3 0x0000685c 3624#define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0) 3625#define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8) 3626#define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16) 3627#define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24) 3628 3629#define BNX_HC_STAT_GEN_STAT0 0x00006888 3630#define BNX_HC_STAT_GEN_STAT1 0x0000688c 3631#define BNX_HC_STAT_GEN_STAT2 0x00006890 3632#define BNX_HC_STAT_GEN_STAT3 0x00006894 3633#define BNX_HC_STAT_GEN_STAT4 0x00006898 3634#define BNX_HC_STAT_GEN_STAT5 0x0000689c 3635#define BNX_HC_STAT_GEN_STAT6 0x000068a0 3636#define BNX_HC_STAT_GEN_STAT7 0x000068a4 3637#define BNX_HC_STAT_GEN_STAT8 0x000068a8 3638#define BNX_HC_STAT_GEN_STAT9 0x000068ac 3639#define BNX_HC_STAT_GEN_STAT10 0x000068b0 3640#define BNX_HC_STAT_GEN_STAT11 0x000068b4 3641#define BNX_HC_STAT_GEN_STAT12 0x000068b8 3642#define BNX_HC_STAT_GEN_STAT13 0x000068bc 3643#define BNX_HC_STAT_GEN_STAT14 0x000068c0 3644#define BNX_HC_STAT_GEN_STAT15 0x000068c4 3645#define BNX_HC_STAT_GEN_STAT_AC0 0x000068c8 3646#define BNX_HC_STAT_GEN_STAT_AC1 0x000068cc 3647#define BNX_HC_STAT_GEN_STAT_AC2 0x000068d0 3648#define BNX_HC_STAT_GEN_STAT_AC3 0x000068d4 3649#define BNX_HC_STAT_GEN_STAT_AC4 0x000068d8 3650#define BNX_HC_STAT_GEN_STAT_AC5 0x000068dc 3651#define BNX_HC_STAT_GEN_STAT_AC6 0x000068e0 3652#define BNX_HC_STAT_GEN_STAT_AC7 0x000068e4 3653#define BNX_HC_STAT_GEN_STAT_AC8 0x000068e8 3654#define BNX_HC_STAT_GEN_STAT_AC9 0x000068ec 3655#define BNX_HC_STAT_GEN_STAT_AC10 0x000068f0 3656#define BNX_HC_STAT_GEN_STAT_AC11 0x000068f4 3657#define BNX_HC_STAT_GEN_STAT_AC12 0x000068f8 3658#define BNX_HC_STAT_GEN_STAT_AC13 0x000068fc 3659#define BNX_HC_STAT_GEN_STAT_AC14 0x00006900 3660#define BNX_HC_STAT_GEN_STAT_AC15 0x00006904 3661#define BNX_HC_VIS 0x00006908 3662#define BNX_HC_VIS_STAT_BUILD_STATE (0xfL<<0) 3663#define BNX_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0) 3664#define BNX_HC_VIS_STAT_BUILD_STATE_START (1L<<0) 3665#define BNX_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0) 3666#define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0) 3667#define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0) 3668#define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0) 3669#define BNX_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0) 3670#define BNX_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0) 3671#define BNX_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0) 3672#define BNX_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0) 3673#define BNX_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0) 3674#define BNX_HC_VIS_DMA_STAT_STATE (0xfL<<8) 3675#define BNX_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8) 3676#define BNX_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8) 3677#define BNX_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8) 3678#define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8) 3679#define BNX_HC_VIS_DMA_STAT_STATE_COMP (4L<<8) 3680#define BNX_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8) 3681#define BNX_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8) 3682#define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8) 3683#define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8) 3684#define BNX_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8) 3685#define BNX_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8) 3686#define BNX_HC_VIS_DMA_MSI_STATE (0x7L<<12) 3687#define BNX_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15) 3688#define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15) 3689#define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15) 3690#define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15) 3691 3692#define BNX_HC_VIS_1 0x0000690c 3693#define BNX_HC_VIS_1_HW_INTACK_STATE (1L<<4) 3694#define BNX_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4) 3695#define BNX_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4) 3696#define BNX_HC_VIS_1_SW_INTACK_STATE (1L<<5) 3697#define BNX_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5) 3698#define BNX_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5) 3699#define BNX_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6) 3700#define BNX_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6) 3701#define BNX_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6) 3702#define BNX_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7) 3703#define BNX_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7) 3704#define BNX_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7) 3705#define BNX_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17) 3706#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17) 3707#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17) 3708#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17) 3709#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17) 3710#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17) 3711#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17) 3712#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17) 3713#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17) 3714#define BNX_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21) 3715#define BNX_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21) 3716#define BNX_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21) 3717#define BNX_HC_VIS_1_INT_GEN_STATE (1L<<23) 3718#define BNX_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23) 3719#define BNX_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23) 3720#define BNX_HC_VIS_1_STAT_CHAN_ID (0x7L<<24) 3721#define BNX_HC_VIS_1_INT_B (1L<<27) 3722 3723#define BNX_HC_DEBUG_VECT_PEEK 0x00006910 3724#define BNX_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3725#define BNX_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3726#define BNX_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3727#define BNX_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3728#define BNX_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3729#define BNX_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3730 3731 3732 3733/* 3734 * txp_reg definition 3735 * offset: 0x40000 3736 */ 3737#define BNX_TXP_CPU_MODE 0x00045000 3738#define BNX_TXP_CPU_MODE_LOCAL_RST (1L<<0) 3739#define BNX_TXP_CPU_MODE_STEP_ENA (1L<<1) 3740#define BNX_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3741#define BNX_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3742#define BNX_TXP_CPU_MODE_MSG_BIT1 (1L<<6) 3743#define BNX_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 3744#define BNX_TXP_CPU_MODE_SOFT_HALT (1L<<10) 3745#define BNX_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3746#define BNX_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3747#define BNX_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3748#define BNX_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3749 3750#define BNX_TXP_CPU_STATE 0x00045004 3751#define BNX_TXP_CPU_STATE_BREAKPOINT (1L<<0) 3752#define BNX_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 3753#define BNX_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3754#define BNX_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3755#define BNX_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3756#define BNX_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 3757#define BNX_TXP_CPU_STATE_ALIGN_HALTED (1L<<7) 3758#define BNX_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3759#define BNX_TXP_CPU_STATE_SOFT_HALTED (1L<<10) 3760#define BNX_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3761#define BNX_TXP_CPU_STATE_INTERRRUPT (1L<<12) 3762#define BNX_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3763#define BNX_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 3764#define BNX_TXP_CPU_STATE_BLOCKED_READ (1L<<31) 3765 3766#define BNX_TXP_CPU_EVENT_MASK 0x00045008 3767#define BNX_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 3768#define BNX_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 3769#define BNX_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 3770#define BNX_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 3771#define BNX_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 3772#define BNX_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 3773#define BNX_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 3774#define BNX_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 3775#define BNX_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 3776#define BNX_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 3777#define BNX_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 3778 3779#define BNX_TXP_CPU_PROGRAM_COUNTER 0x0004501c 3780#define BNX_TXP_CPU_INSTRUCTION 0x00045020 3781#define BNX_TXP_CPU_DATA_ACCESS 0x00045024 3782#define BNX_TXP_CPU_INTERRUPT_ENABLE 0x00045028 3783#define BNX_TXP_CPU_INTERRUPT_VECTOR 0x0004502c 3784#define BNX_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030 3785#define BNX_TXP_CPU_HW_BREAKPOINT 0x00045034 3786#define BNX_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 3787#define BNX_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 3788 3789#define BNX_TXP_CPU_DEBUG_VECT_PEEK 0x00045038 3790#define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3791#define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3792#define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3793#define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3794#define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3795#define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3796 3797#define BNX_TXP_CPU_LAST_BRANCH_ADDR 0x00045048 3798#define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 3799#define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 3800#define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 3801#define BNX_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 3802 3803#define BNX_TXP_CPU_REG_FILE 0x00045200 3804#define BNX_TXP_FTQ_DATA 0x000453c0 3805#define BNX_TXP_FTQ_CMD 0x000453f8 3806#define BNX_TXP_FTQ_CMD_OFFSET (0x3ffL<<0) 3807#define BNX_TXP_FTQ_CMD_WR_TOP (1L<<10) 3808#define BNX_TXP_FTQ_CMD_WR_TOP_0 (0L<<10) 3809#define BNX_TXP_FTQ_CMD_WR_TOP_1 (1L<<10) 3810#define BNX_TXP_FTQ_CMD_SFT_RESET (1L<<25) 3811#define BNX_TXP_FTQ_CMD_RD_DATA (1L<<26) 3812#define BNX_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 3813#define BNX_TXP_FTQ_CMD_ADD_DATA (1L<<28) 3814#define BNX_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 3815#define BNX_TXP_FTQ_CMD_POP (1L<<30) 3816#define BNX_TXP_FTQ_CMD_BUSY (1L<<31) 3817 3818#define BNX_TXP_FTQ_CTL 0x000453fc 3819#define BNX_TXP_FTQ_CTL_INTERVENE (1L<<0) 3820#define BNX_TXP_FTQ_CTL_OVERFLOW (1L<<1) 3821#define BNX_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3822#define BNX_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3823#define BNX_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3824 3825#define BNX_TXP_SCRATCH 0x00060000 3826 3827 3828/* 3829 * tpat_reg definition 3830 * offset: 0x80000 3831 */ 3832#define BNX_TPAT_CPU_MODE 0x00085000 3833#define BNX_TPAT_CPU_MODE_LOCAL_RST (1L<<0) 3834#define BNX_TPAT_CPU_MODE_STEP_ENA (1L<<1) 3835#define BNX_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3836#define BNX_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3837#define BNX_TPAT_CPU_MODE_MSG_BIT1 (1L<<6) 3838#define BNX_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7) 3839#define BNX_TPAT_CPU_MODE_SOFT_HALT (1L<<10) 3840#define BNX_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3841#define BNX_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3842#define BNX_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3843#define BNX_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3844 3845#define BNX_TPAT_CPU_STATE 0x00085004 3846#define BNX_TPAT_CPU_STATE_BREAKPOINT (1L<<0) 3847#define BNX_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2) 3848#define BNX_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3849#define BNX_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3850#define BNX_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3851#define BNX_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6) 3852#define BNX_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7) 3853#define BNX_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3854#define BNX_TPAT_CPU_STATE_SOFT_HALTED (1L<<10) 3855#define BNX_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3856#define BNX_TPAT_CPU_STATE_INTERRRUPT (1L<<12) 3857#define BNX_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3858#define BNX_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15) 3859#define BNX_TPAT_CPU_STATE_BLOCKED_READ (1L<<31) 3860 3861#define BNX_TPAT_CPU_EVENT_MASK 0x00085008 3862#define BNX_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 3863#define BNX_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 3864#define BNX_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 3865#define BNX_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 3866#define BNX_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 3867#define BNX_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 3868#define BNX_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 3869#define BNX_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 3870#define BNX_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 3871#define BNX_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 3872#define BNX_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 3873 3874#define BNX_TPAT_CPU_PROGRAM_COUNTER 0x0008501c 3875#define BNX_TPAT_CPU_INSTRUCTION 0x00085020 3876#define BNX_TPAT_CPU_DATA_ACCESS 0x00085024 3877#define BNX_TPAT_CPU_INTERRUPT_ENABLE 0x00085028 3878#define BNX_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c 3879#define BNX_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030 3880#define BNX_TPAT_CPU_HW_BREAKPOINT 0x00085034 3881#define BNX_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 3882#define BNX_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 3883 3884#define BNX_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038 3885#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3886#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3887#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3888#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3889#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3890#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3891 3892#define BNX_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048 3893#define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 3894#define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 3895#define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 3896#define BNX_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 3897 3898#define BNX_TPAT_CPU_REG_FILE 0x00085200 3899#define BNX_TPAT_FTQ_DATA 0x000853c0 3900#define BNX_TPAT_FTQ_CMD 0x000853f8 3901#define BNX_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0) 3902#define BNX_TPAT_FTQ_CMD_WR_TOP (1L<<10) 3903#define BNX_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10) 3904#define BNX_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10) 3905#define BNX_TPAT_FTQ_CMD_SFT_RESET (1L<<25) 3906#define BNX_TPAT_FTQ_CMD_RD_DATA (1L<<26) 3907#define BNX_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27) 3908#define BNX_TPAT_FTQ_CMD_ADD_DATA (1L<<28) 3909#define BNX_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29) 3910#define BNX_TPAT_FTQ_CMD_POP (1L<<30) 3911#define BNX_TPAT_FTQ_CMD_BUSY (1L<<31) 3912 3913#define BNX_TPAT_FTQ_CTL 0x000853fc 3914#define BNX_TPAT_FTQ_CTL_INTERVENE (1L<<0) 3915#define BNX_TPAT_FTQ_CTL_OVERFLOW (1L<<1) 3916#define BNX_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3917#define BNX_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3918#define BNX_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3919 3920#define BNX_TPAT_SCRATCH 0x000a0000 3921 3922 3923/* 3924 * rxp_reg definition 3925 * offset: 0xc0000 3926 */ 3927#define BNX_RXP_CPU_MODE 0x000c5000 3928#define BNX_RXP_CPU_MODE_LOCAL_RST (1L<<0) 3929#define BNX_RXP_CPU_MODE_STEP_ENA (1L<<1) 3930#define BNX_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3931#define BNX_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3932#define BNX_RXP_CPU_MODE_MSG_BIT1 (1L<<6) 3933#define BNX_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 3934#define BNX_RXP_CPU_MODE_SOFT_HALT (1L<<10) 3935#define BNX_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3936#define BNX_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3937#define BNX_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3938#define BNX_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3939 3940#define BNX_RXP_CPU_STATE 0x000c5004 3941#define BNX_RXP_CPU_STATE_BREAKPOINT (1L<<0) 3942#define BNX_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 3943#define BNX_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3944#define BNX_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3945#define BNX_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3946#define BNX_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 3947#define BNX_RXP_CPU_STATE_ALIGN_HALTED (1L<<7) 3948#define BNX_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3949#define BNX_RXP_CPU_STATE_SOFT_HALTED (1L<<10) 3950#define BNX_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3951#define BNX_RXP_CPU_STATE_INTERRRUPT (1L<<12) 3952#define BNX_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3953#define BNX_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 3954#define BNX_RXP_CPU_STATE_BLOCKED_READ (1L<<31) 3955 3956#define BNX_RXP_CPU_EVENT_MASK 0x000c5008 3957#define BNX_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 3958#define BNX_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 3959#define BNX_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 3960#define BNX_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 3961#define BNX_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 3962#define BNX_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 3963#define BNX_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 3964#define BNX_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 3965#define BNX_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 3966#define BNX_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 3967#define BNX_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 3968 3969#define BNX_RXP_CPU_PROGRAM_COUNTER 0x000c501c 3970#define BNX_RXP_CPU_INSTRUCTION 0x000c5020 3971#define BNX_RXP_CPU_DATA_ACCESS 0x000c5024 3972#define BNX_RXP_CPU_INTERRUPT_ENABLE 0x000c5028 3973#define BNX_RXP_CPU_INTERRUPT_VECTOR 0x000c502c 3974#define BNX_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030 3975#define BNX_RXP_CPU_HW_BREAKPOINT 0x000c5034 3976#define BNX_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 3977#define BNX_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 3978 3979#define BNX_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038 3980#define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3981#define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3982#define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3983#define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3984#define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3985#define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3986 3987#define BNX_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048 3988#define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 3989#define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 3990#define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 3991#define BNX_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 3992 3993#define BNX_RXP_CPU_REG_FILE 0x000c5200 3994#define BNX_RXP_CFTQ_DATA 0x000c5380 3995#define BNX_RXP_CFTQ_CMD 0x000c53b8 3996#define BNX_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0) 3997#define BNX_RXP_CFTQ_CMD_WR_TOP (1L<<10) 3998#define BNX_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10) 3999#define BNX_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10) 4000#define BNX_RXP_CFTQ_CMD_SFT_RESET (1L<<25) 4001#define BNX_RXP_CFTQ_CMD_RD_DATA (1L<<26) 4002#define BNX_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27) 4003#define BNX_RXP_CFTQ_CMD_ADD_DATA (1L<<28) 4004#define BNX_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29) 4005#define BNX_RXP_CFTQ_CMD_POP (1L<<30) 4006#define BNX_RXP_CFTQ_CMD_BUSY (1L<<31) 4007 4008#define BNX_RXP_CFTQ_CTL 0x000c53bc 4009#define BNX_RXP_CFTQ_CTL_INTERVENE (1L<<0) 4010#define BNX_RXP_CFTQ_CTL_OVERFLOW (1L<<1) 4011#define BNX_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2) 4012#define BNX_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4013#define BNX_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4014 4015#define BNX_RXP_FTQ_DATA 0x000c53c0 4016#define BNX_RXP_FTQ_CMD 0x000c53f8 4017#define BNX_RXP_FTQ_CMD_OFFSET (0x3ffL<<0) 4018#define BNX_RXP_FTQ_CMD_WR_TOP (1L<<10) 4019#define BNX_RXP_FTQ_CMD_WR_TOP_0 (0L<<10) 4020#define BNX_RXP_FTQ_CMD_WR_TOP_1 (1L<<10) 4021#define BNX_RXP_FTQ_CMD_SFT_RESET (1L<<25) 4022#define BNX_RXP_FTQ_CMD_RD_DATA (1L<<26) 4023#define BNX_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 4024#define BNX_RXP_FTQ_CMD_ADD_DATA (1L<<28) 4025#define BNX_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 4026#define BNX_RXP_FTQ_CMD_POP (1L<<30) 4027#define BNX_RXP_FTQ_CMD_BUSY (1L<<31) 4028 4029#define BNX_RXP_FTQ_CTL 0x000c53fc 4030#define BNX_RXP_FTQ_CTL_INTERVENE (1L<<0) 4031#define BNX_RXP_FTQ_CTL_OVERFLOW (1L<<1) 4032#define BNX_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4033#define BNX_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4034#define BNX_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4035 4036#define BNX_RXP_SCRATCH 0x000e0000 4037 4038 4039/* 4040 * com_reg definition 4041 * offset: 0x100000 4042 */ 4043#define BNX_COM_CPU_MODE 0x00105000 4044#define BNX_COM_CPU_MODE_LOCAL_RST (1L<<0) 4045#define BNX_COM_CPU_MODE_STEP_ENA (1L<<1) 4046#define BNX_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4047#define BNX_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4048#define BNX_COM_CPU_MODE_MSG_BIT1 (1L<<6) 4049#define BNX_COM_CPU_MODE_INTERRUPT_ENA (1L<<7) 4050#define BNX_COM_CPU_MODE_SOFT_HALT (1L<<10) 4051#define BNX_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4052#define BNX_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4053#define BNX_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4054#define BNX_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4055 4056#define BNX_COM_CPU_STATE 0x00105004 4057#define BNX_COM_CPU_STATE_BREAKPOINT (1L<<0) 4058#define BNX_COM_CPU_STATE_BAD_INST_HALTED (1L<<2) 4059#define BNX_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4060#define BNX_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4061#define BNX_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4062#define BNX_COM_CPU_STATE_BAD_pc_HALTED (1L<<6) 4063#define BNX_COM_CPU_STATE_ALIGN_HALTED (1L<<7) 4064#define BNX_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4065#define BNX_COM_CPU_STATE_SOFT_HALTED (1L<<10) 4066#define BNX_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4067#define BNX_COM_CPU_STATE_INTERRRUPT (1L<<12) 4068#define BNX_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4069#define BNX_COM_CPU_STATE_INST_FETCH_STALL (1L<<15) 4070#define BNX_COM_CPU_STATE_BLOCKED_READ (1L<<31) 4071 4072#define BNX_COM_CPU_EVENT_MASK 0x00105008 4073#define BNX_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4074#define BNX_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4075#define BNX_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4076#define BNX_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4077#define BNX_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4078#define BNX_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4079#define BNX_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4080#define BNX_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4081#define BNX_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4082#define BNX_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4083#define BNX_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4084 4085#define BNX_COM_CPU_PROGRAM_COUNTER 0x0010501c 4086#define BNX_COM_CPU_INSTRUCTION 0x00105020 4087#define BNX_COM_CPU_DATA_ACCESS 0x00105024 4088#define BNX_COM_CPU_INTERRUPT_ENABLE 0x00105028 4089#define BNX_COM_CPU_INTERRUPT_VECTOR 0x0010502c 4090#define BNX_COM_CPU_INTERRUPT_SAVED_PC 0x00105030 4091#define BNX_COM_CPU_HW_BREAKPOINT 0x00105034 4092#define BNX_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4093#define BNX_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4094 4095#define BNX_COM_CPU_DEBUG_VECT_PEEK 0x00105038 4096#define BNX_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4097#define BNX_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4098#define BNX_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4099#define BNX_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4100#define BNX_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4101#define BNX_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4102 4103#define BNX_COM_CPU_LAST_BRANCH_ADDR 0x00105048 4104#define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4105#define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4106#define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4107#define BNX_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4108 4109#define BNX_COM_CPU_REG_FILE 0x00105200 4110#define BNX_COM_COMXQ_FTQ_DATA 0x00105340 4111#define BNX_COM_COMXQ_FTQ_CMD 0x00105378 4112#define BNX_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4113#define BNX_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10) 4114#define BNX_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4115#define BNX_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4116#define BNX_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25) 4117#define BNX_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26) 4118#define BNX_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4119#define BNX_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28) 4120#define BNX_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4121#define BNX_COM_COMXQ_FTQ_CMD_POP (1L<<30) 4122#define BNX_COM_COMXQ_FTQ_CMD_BUSY (1L<<31) 4123 4124#define BNX_COM_COMXQ_FTQ_CTL 0x0010537c 4125#define BNX_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0) 4126#define BNX_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1) 4127#define BNX_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4128#define BNX_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4129#define BNX_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4130 4131#define BNX_COM_COMTQ_FTQ_DATA 0x00105380 4132#define BNX_COM_COMTQ_FTQ_CMD 0x001053b8 4133#define BNX_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4134#define BNX_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10) 4135#define BNX_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4136#define BNX_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4137#define BNX_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25) 4138#define BNX_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26) 4139#define BNX_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4140#define BNX_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28) 4141#define BNX_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4142#define BNX_COM_COMTQ_FTQ_CMD_POP (1L<<30) 4143#define BNX_COM_COMTQ_FTQ_CMD_BUSY (1L<<31) 4144 4145#define BNX_COM_COMTQ_FTQ_CTL 0x001053bc 4146#define BNX_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0) 4147#define BNX_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1) 4148#define BNX_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4149#define BNX_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4150#define BNX_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4151 4152#define BNX_COM_COMQ_FTQ_DATA 0x001053c0 4153#define BNX_COM_COMQ_FTQ_CMD 0x001053f8 4154#define BNX_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4155#define BNX_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10) 4156#define BNX_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4157#define BNX_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4158#define BNX_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25) 4159#define BNX_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26) 4160#define BNX_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4161#define BNX_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28) 4162#define BNX_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4163#define BNX_COM_COMQ_FTQ_CMD_POP (1L<<30) 4164#define BNX_COM_COMQ_FTQ_CMD_BUSY (1L<<31) 4165 4166#define BNX_COM_COMQ_FTQ_CTL 0x001053fc 4167#define BNX_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0) 4168#define BNX_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1) 4169#define BNX_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4170#define BNX_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4171#define BNX_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4172 4173#define BNX_COM_SCRATCH 0x00120000 4174 4175 4176/* 4177 * cp_reg definition 4178 * offset: 0x180000 4179 */ 4180#define BNX_CP_CPU_MODE 0x00185000 4181#define BNX_CP_CPU_MODE_LOCAL_RST (1L<<0) 4182#define BNX_CP_CPU_MODE_STEP_ENA (1L<<1) 4183#define BNX_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4184#define BNX_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4185#define BNX_CP_CPU_MODE_MSG_BIT1 (1L<<6) 4186#define BNX_CP_CPU_MODE_INTERRUPT_ENA (1L<<7) 4187#define BNX_CP_CPU_MODE_SOFT_HALT (1L<<10) 4188#define BNX_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4189#define BNX_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4190#define BNX_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4191#define BNX_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4192 4193#define BNX_CP_CPU_STATE 0x00185004 4194#define BNX_CP_CPU_STATE_BREAKPOINT (1L<<0) 4195#define BNX_CP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4196#define BNX_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4197#define BNX_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4198#define BNX_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4199#define BNX_CP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4200#define BNX_CP_CPU_STATE_ALIGN_HALTED (1L<<7) 4201#define BNX_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4202#define BNX_CP_CPU_STATE_SOFT_HALTED (1L<<10) 4203#define BNX_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4204#define BNX_CP_CPU_STATE_INTERRRUPT (1L<<12) 4205#define BNX_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4206#define BNX_CP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4207#define BNX_CP_CPU_STATE_BLOCKED_READ (1L<<31) 4208 4209#define BNX_CP_CPU_EVENT_MASK 0x00185008 4210#define BNX_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4211#define BNX_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4212#define BNX_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4213#define BNX_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4214#define BNX_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4215#define BNX_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4216#define BNX_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4217#define BNX_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4218#define BNX_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4219#define BNX_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4220#define BNX_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4221 4222#define BNX_CP_CPU_PROGRAM_COUNTER 0x0018501c 4223#define BNX_CP_CPU_INSTRUCTION 0x00185020 4224#define BNX_CP_CPU_DATA_ACCESS 0x00185024 4225#define BNX_CP_CPU_INTERRUPT_ENABLE 0x00185028 4226#define BNX_CP_CPU_INTERRUPT_VECTOR 0x0018502c 4227#define BNX_CP_CPU_INTERRUPT_SAVED_PC 0x00185030 4228#define BNX_CP_CPU_HW_BREAKPOINT 0x00185034 4229#define BNX_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4230#define BNX_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4231 4232#define BNX_CP_CPU_DEBUG_VECT_PEEK 0x00185038 4233#define BNX_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4234#define BNX_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4235#define BNX_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4236#define BNX_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4237#define BNX_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4238#define BNX_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4239 4240#define BNX_CP_CPU_LAST_BRANCH_ADDR 0x00185048 4241#define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4242#define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4243#define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4244#define BNX_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4245 4246#define BNX_CP_CPU_REG_FILE 0x00185200 4247#define BNX_CP_CPQ_FTQ_DATA 0x001853c0 4248#define BNX_CP_CPQ_FTQ_CMD 0x001853f8 4249#define BNX_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4250#define BNX_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10) 4251#define BNX_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4252#define BNX_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4253#define BNX_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25) 4254#define BNX_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26) 4255#define BNX_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4256#define BNX_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28) 4257#define BNX_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4258#define BNX_CP_CPQ_FTQ_CMD_POP (1L<<30) 4259#define BNX_CP_CPQ_FTQ_CMD_BUSY (1L<<31) 4260 4261#define BNX_CP_CPQ_FTQ_CTL 0x001853fc 4262#define BNX_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0) 4263#define BNX_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1) 4264#define BNX_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4265#define BNX_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4266#define BNX_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4267 4268#define BNX_CP_SCRATCH 0x001a0000 4269 4270 4271/* 4272 * mcp_reg definition 4273 * offset: 0x140000 4274 */ 4275#define BNX_MCP_CPU_MODE 0x00145000 4276#define BNX_MCP_CPU_MODE_LOCAL_RST (1L<<0) 4277#define BNX_MCP_CPU_MODE_STEP_ENA (1L<<1) 4278#define BNX_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4279#define BNX_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4280#define BNX_MCP_CPU_MODE_MSG_BIT1 (1L<<6) 4281#define BNX_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7) 4282#define BNX_MCP_CPU_MODE_SOFT_HALT (1L<<10) 4283#define BNX_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4284#define BNX_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4285#define BNX_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4286#define BNX_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4287 4288#define BNX_MCP_CPU_STATE 0x00145004 4289#define BNX_MCP_CPU_STATE_BREAKPOINT (1L<<0) 4290#define BNX_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4291#define BNX_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4292#define BNX_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4293#define BNX_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4294#define BNX_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4295#define BNX_MCP_CPU_STATE_ALIGN_HALTED (1L<<7) 4296#define BNX_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4297#define BNX_MCP_CPU_STATE_SOFT_HALTED (1L<<10) 4298#define BNX_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4299#define BNX_MCP_CPU_STATE_INTERRRUPT (1L<<12) 4300#define BNX_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4301#define BNX_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4302#define BNX_MCP_CPU_STATE_BLOCKED_READ (1L<<31) 4303 4304#define BNX_MCP_CPU_EVENT_MASK 0x00145008 4305#define BNX_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4306#define BNX_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4307#define BNX_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4308#define BNX_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4309#define BNX_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4310#define BNX_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4311#define BNX_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4312#define BNX_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4313#define BNX_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4314#define BNX_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4315#define BNX_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4316 4317#define BNX_MCP_CPU_PROGRAM_COUNTER 0x0014501c 4318#define BNX_MCP_CPU_INSTRUCTION 0x00145020 4319#define BNX_MCP_CPU_DATA_ACCESS 0x00145024 4320#define BNX_MCP_CPU_INTERRUPT_ENABLE 0x00145028 4321#define BNX_MCP_CPU_INTERRUPT_VECTOR 0x0014502c 4322#define BNX_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030 4323#define BNX_MCP_CPU_HW_BREAKPOINT 0x00145034 4324#define BNX_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4325#define BNX_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4326 4327#define BNX_MCP_CPU_DEBUG_VECT_PEEK 0x00145038 4328#define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4329#define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4330#define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4331#define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4332#define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4333#define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4334 4335#define BNX_MCP_CPU_LAST_BRANCH_ADDR 0x00145048 4336#define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4337#define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4338#define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4339#define BNX_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4340 4341#define BNX_MCP_CPU_REG_FILE 0x00145200 4342#define BNX_MCP_MCPQ_FTQ_DATA 0x001453c0 4343#define BNX_MCP_MCPQ_FTQ_CMD 0x001453f8 4344#define BNX_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4345#define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10) 4346#define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4347#define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4348#define BNX_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25) 4349#define BNX_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26) 4350#define BNX_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4351#define BNX_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28) 4352#define BNX_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4353#define BNX_MCP_MCPQ_FTQ_CMD_POP (1L<<30) 4354#define BNX_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31) 4355 4356#define BNX_MCP_MCPQ_FTQ_CTL 0x001453fc 4357#define BNX_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0) 4358#define BNX_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1) 4359#define BNX_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4360#define BNX_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4361#define BNX_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4362 4363#define BNX_MCP_ROM 0x00150000 4364#define BNX_MCP_SCRATCH 0x00160000 4365 4366#define BNX_SHM_HDR_SIGNATURE BNX_MCP_SCRATCH 4367#define BNX_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000 4368#define BNX_SHM_HDR_SIGNATURE_SIG 0x53530000 4369#define BNX_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff 4370#define BNX_SHM_HDR_SIGNATURE_VER_ONE 0x00000001 4371 4372#define BNX_SHM_HDR_ADDR_0 BNX_MCP_SCRATCH + 4 4373#define BNX_SHM_HDR_ADDR_1 BNX_MCP_SCRATCH + 8 4374 4375/****************************************************************************/ 4376/* End machine generated definitions. */ 4377/****************************************************************************/ 4378 4379#define NUM_MC_HASH_REGISTERS 8 4380 4381 4382/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */ 4383#define PHY_BCM5706_PHY_ID 0x00206160 4384 4385#define PHY_ID(id) ((id) & 0xfffffff0) 4386#define PHY_REV_ID(id) ((id) & 0xf) 4387 4388/* 5708 Serdes PHY registers */ 4389 4390#define BCM5708S_UP1 0xb 4391 4392#define BCM5708S_UP1_2G5 0x1 4393 4394#define BCM5708S_BLK_ADDR 0x1f 4395 4396#define BCM5708S_BLK_ADDR_DIG 0x0000 4397#define BCM5708S_BLK_ADDR_DIG3 0x0002 4398#define BCM5708S_BLK_ADDR_TX_MISC 0x0005 4399 4400/* Digital Block */ 4401#define BCM5708S_1000X_CTL1 0x10 4402 4403#define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001 4404#define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010 4405 4406#define BCM5708S_1000X_CTL2 0x11 4407 4408#define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001 4409 4410#define BCM5708S_1000X_STAT1 0x14 4411 4412#define BCM5708S_1000X_STAT1_SGMII 0x0001 4413#define BCM5708S_1000X_STAT1_LINK 0x0002 4414#define BCM5708S_1000X_STAT1_FD 0x0004 4415#define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018 4416#define BCM5708S_1000X_STAT1_SPEED_10 0x0000 4417#define BCM5708S_1000X_STAT1_SPEED_100 0x0008 4418#define BCM5708S_1000X_STAT1_SPEED_1G 0x0010 4419#define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018 4420#define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020 4421#define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040 4422 4423/* Digital3 Block */ 4424#define BCM5708S_DIG_3_0 0x10 4425 4426#define BCM5708S_DIG_3_0_USE_IEEE 0x0001 4427 4428/* Tx/Misc Block */ 4429#define BCM5708S_TX_ACTL1 0x15 4430 4431#define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30 4432 4433#define BCM5708S_TX_ACTL3 0x17 4434 4435#define RX_COPY_THRESH 92 4436 4437#define DMA_READ_CHANS 5 4438#define DMA_WRITE_CHANS 3 4439 4440/* Use the natural page size of the host CPU. */ 4441/* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */ 4442#define BCM_PAGE_BITS PAGE_SHIFT 4443#define BCM_PAGE_SIZE PAGE_SIZE 4444 4445#define TX_PAGES 2 4446#define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd)) 4447#define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) 4448#define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES) 4449#define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES) 4450#define MAX_TX_BD (TOTAL_TX_BD - 1) 4451#define BNX_TX_SLACK_SPACE 16 4452 4453#define RX_PAGES 2 4454#define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd)) 4455#define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1) 4456#define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES) 4457#define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES) 4458#define MAX_RX_BD (TOTAL_RX_BD - 1) 4459#define BNX_RX_SLACK_SPACE (MAX_RX_BD - 8) 4460 4461#define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \ 4462 (USABLE_TX_BD_PER_PAGE - 1)) ? \ 4463 (x) + 2 : (x) + 1 4464 4465#define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD) 4466 4467#define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8) 4468#define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE) 4469 4470#define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) == \ 4471 (USABLE_RX_BD_PER_PAGE - 1)) ? \ 4472 (x) + 2 : (x) + 1 4473 4474#define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD) 4475 4476#define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> 8) 4477#define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE) 4478 4479/* Context size. */ 4480#define CTX_SHIFT 7 4481#define CTX_SIZE (1 << CTX_SHIFT) 4482#define CTX_MASK (CTX_SIZE - 1) 4483#define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT) 4484#define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) 4485 4486#define PHY_CTX_SHIFT 6 4487#define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT) 4488#define PHY_CTX_MASK (PHY_CTX_SIZE - 1) 4489#define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) 4490#define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) 4491 4492#define MB_KERNEL_CTX_SHIFT 8 4493#define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) 4494#define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) 4495#define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) 4496 4497#define MAX_CID_CNT 0x4000 4498#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) 4499#define INVALID_CID_ADDR 0xffffffff 4500 4501#define TX_CID 16 4502#define RX_CID 0 4503 4504#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID) 4505#define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID) 4506 4507/****************************************************************************/ 4508/* BNX Processor Firmwware Load Definitions */ 4509/****************************************************************************/ 4510 4511struct cpu_reg { 4512 u32 mode; 4513 u32 mode_value_halt; 4514 u32 mode_value_sstep; 4515 4516 u32 state; 4517 u32 state_value_clear; 4518 4519 u32 gpr0; 4520 u32 evmask; 4521 u32 pc; 4522 u32 inst; 4523 u32 bp; 4524 4525 u32 spad_base; 4526 4527 u32 mips_view_base; 4528}; 4529 4530struct fw_info { 4531 u32 ver_major; 4532 u32 ver_minor; 4533 u32 ver_fix; 4534 4535 u32 start_addr; 4536 4537 /* Text section. */ 4538 u32 text_addr; 4539 u32 text_len; 4540 u32 text_index; 4541 u32 *text; 4542 4543 /* Data section. */ 4544 u32 data_addr; 4545 u32 data_len; 4546 u32 data_index; 4547 u32 *data; 4548 4549 /* SBSS section. */ 4550 u32 sbss_addr; 4551 u32 sbss_len; 4552 u32 sbss_index; 4553 u32 *sbss; 4554 4555 /* BSS section. */ 4556 u32 bss_addr; 4557 u32 bss_len; 4558 u32 bss_index; 4559 u32 *bss; 4560 4561 /* Read-only section. */ 4562 u32 rodata_addr; 4563 u32 rodata_len; 4564 u32 rodata_index; 4565 u32 *rodata; 4566}; 4567 4568#define RV2P_PROC1 0 4569#define RV2P_PROC2 1 4570 4571#define BNX_MIREG(x) ((x & 0x1F) << 16) 4572#define BNX_MIPHY(x) ((x & 0x1F) << 21) 4573#define BNX_PHY_TIMEOUT 50 4574 4575#define BNX_NVRAM_SIZE 0x200 4576#define BNX_NVRAM_MAGIC 0x669955aa 4577#define BNX_CRC32_RESIDUAL 0xdebb20e3 4578 4579#define BNX_TX_TIMEOUT 5 4580 4581#define BNX_MAX_SEGMENTS 8 4582#define BNX_DMA_ALIGN 8 4583#define BNX_DMA_BOUNDARY 0 4584 4585#define BNX_MIN_MTU 60 4586#define BNX_MIN_ETHER_MTU 64 4587 4588#define BNX_MAX_STD_MTU 1500 4589#define BNX_MAX_STD_ETHER_MTU 1518 4590#define BNX_MAX_STD_ETHER_MTU_VLAN 1522 4591 4592#define BNX_MAX_JUMBO_MTU 9000 4593#define BNX_MAX_JUMBO_ETHER_MTU 9018 4594#define BNX_MAX_JUMBO_ETHER_MTU_VLAN 9022 4595 4596#if 0 4597#define BNX_MAX_MRU 9216 4598#else 4599#define BNX_MAX_MRU MCLBYTES 4600#endif 4601 4602/****************************************************************************/ 4603/* BNX Device State Data Structure */ 4604/****************************************************************************/ 4605 4606#define BNX_STATUS_BLK_SZ sizeof(struct status_block) 4607#define BNX_STATS_BLK_SZ sizeof(struct statistics_block) 4608#define BNX_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 4609#define BNX_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 4610/* 4611 * Mbuf pointers. We need these to keep track of the virtual addresses 4612 * of our mbuf chains since we can only convert from physical to virtual, 4613 * not the other way around. 4614 */ 4615 4616struct bnx_dmamap_arg { 4617 struct bnx_softc *sc; /* Pointer back to device context */ 4618 bus_addr_t busaddr; /* Physical address of mapped memory */ 4619 u32 tx_flags; /* Flags for frame transmit */ 4620 u16 prod; 4621 u16 chain_prod; 4622 int maxsegs; /* Max segments supported for this mapped memory */ 4623 u32 prod_bseq; 4624 struct tx_bd *tx_chain[TX_PAGES]; 4625}; 4626 4627 4628struct bnx_softc 4629{ 4630 struct device bnx_dev; /* Parent device handle */ 4631 struct arpcom arpcom; 4632 struct pci_attach_args bnx_pa; 4633 4634 struct ifmedia bnx_ifmedia; /* TBI media info */ 4635 4636 bus_space_tag_t bnx_btag; /* Device bus tag */ 4637 bus_space_handle_t bnx_bhandle; /* Device bus handle */ 4638 4639 void *bnx_intrhand; /* Interrupt handler */ 4640 void *bnx_powerhook; 4641 void *bnx_shutdownhook; 4642 4643 /* ASIC Chip ID. */ 4644 u32 bnx_chipid; 4645 4646 /* General controller flags. */ 4647 u32 bnx_flags; 4648#define BNX_PCIX_FLAG 0x01 4649#define BNX_PCI_32BIT_FLAG 0x02 4650#define BNX_ONE_TDMA_FLAG 0x04 /* Deprecated */ 4651#define BNX_NO_WOL_FLAG 0x08 4652#define BNX_USING_DAC_FLAG 0x10 4653#define BNX_USING_MSI_FLAG 0x20 4654#define BNX_MFW_ENABLE_FLAG 0x40 4655 4656 /* PHY specific flags. */ 4657 u32 bnx_phy_flags; 4658#define BNX_PHY_SERDES_FLAG 1 4659#define BNX_PHY_CRC_FIX_FLAG 2 4660#define BNX_PHY_PARALLEL_DETECT_FLAG 4 4661#define BNX_PHY_2_5G_CAPABLE_FLAG 8 4662#define BNX_PHY_INT_MODE_MASK_FLAG 0x300 4663#define BNX_PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 4664#define BNX_PHY_INT_MODE_LINK_READY_FLAG 0x200 4665 4666 int bnx_if_flags; 4667 4668 bus_addr_t max_bus_addr; 4669 u16 bus_speed_mhz; /* PCI bus speed */ 4670 struct flash_spec *bnx_flash_info; /* Flash NVRAM settings */ 4671 u32 bnx_flash_size; /* Flash NVRAM size */ 4672 u32 bnx_shmem_base; /* Shared Memory base address */ 4673 char * bnx_name; /* Name string */ 4674 4675 /* Tracks the version of bootcode firmware. */ 4676 u32 bnx_fw_ver; 4677 4678 /* Tracks the state of the firmware. 0 = Running while any */ 4679 /* other value indicates that the firmware is not responding. */ 4680 u16 bnx_fw_timed_out; 4681 4682 /* An incrementing sequence used to coordinate messages passed */ 4683 /* from the driver to the firmware. */ 4684 u16 bnx_fw_wr_seq; 4685 4686 /* An incrementing sequence used to let the firmware know that */ 4687 /* the driver is still operating. Without the pulse, management */ 4688 /* firmware such as IPMI or UMP will operate in OS absent state. */ 4689 u16 bnx_fw_drv_pulse_wr_seq; 4690 4691 /* Ethernet MAC address. */ 4692 u_char eaddr[6]; 4693 4694 /* These setting are used by the host coalescing (HC) block to */ 4695 /* to control how often the status block, statistics block and */ 4696 /* interrupts are generated. */ 4697 u16 bnx_tx_quick_cons_trip_int; 4698 u16 bnx_tx_quick_cons_trip; 4699 u16 bnx_rx_quick_cons_trip_int; 4700 u16 bnx_rx_quick_cons_trip; 4701 u16 bnx_comp_prod_trip_int; 4702 u16 bnx_comp_prod_trip; 4703 u16 bnx_tx_ticks_int; 4704 u16 bnx_tx_ticks; 4705 u16 bnx_rx_ticks_int; 4706 u16 bnx_rx_ticks; 4707 u16 bnx_com_ticks_int; 4708 u16 bnx_com_ticks; 4709 u16 bnx_cmd_ticks_int; 4710 u16 bnx_cmd_ticks; 4711 u32 bnx_stats_ticks; 4712 4713 /* The address of the integrated PHY on the MII bus. */ 4714 int bnx_phy_addr; 4715 4716 /* The device handle for the MII bus child device. */ 4717 struct mii_data bnx_mii; 4718 4719 /* Driver maintained TX chain pointers and byte counter. */ 4720 u16 rx_prod; 4721 u16 rx_cons; 4722 u32 rx_prod_bseq; /* Counts the bytes used. */ 4723 u16 tx_prod; 4724 u16 tx_cons; 4725 u32 tx_prod_bseq; /* Counts the bytes used. */ 4726 4727 int bnx_link; 4728 struct timeout bnx_timeout; 4729 4730 /* Frame size and mbuf allocation size for RX frames. */ 4731 u32 max_frame_size; 4732 int mbuf_alloc_size; 4733 4734 /* Receive mode settings (i.e promiscuous, multicast, etc.). */ 4735 u32 rx_mode; 4736 4737 /* Bus tag for the bnx controller. */ 4738 bus_dma_tag_t bnx_dmatag; 4739 4740 /* H/W maintained TX buffer descriptor chain structure. */ 4741 bus_dma_segment_t tx_bd_chain_seg[TX_PAGES]; 4742 int tx_bd_chain_rseg[TX_PAGES]; 4743 bus_dmamap_t tx_bd_chain_map[TX_PAGES]; 4744 struct tx_bd *tx_bd_chain[TX_PAGES]; 4745 bus_addr_t tx_bd_chain_paddr[TX_PAGES]; 4746 4747 /* H/W maintained RX buffer descriptor chain structure. */ 4748 bus_dma_segment_t rx_bd_chain_seg[TX_PAGES]; 4749 int rx_bd_chain_rseg[TX_PAGES]; 4750 bus_dmamap_t rx_bd_chain_map[RX_PAGES]; 4751 struct rx_bd *rx_bd_chain[RX_PAGES]; 4752 bus_addr_t rx_bd_chain_paddr[RX_PAGES]; 4753 4754 /* H/W maintained status block. */ 4755 bus_dma_segment_t status_seg; 4756 int status_rseg; 4757 bus_dmamap_t status_map; 4758 struct status_block *status_block; /* virtual address */ 4759 bus_addr_t status_block_paddr; /* Physical address */ 4760 4761 /* Driver maintained status block values. */ 4762 u16 last_status_idx; 4763 u16 hw_rx_cons; 4764 u16 hw_tx_cons; 4765 4766 /* H/W maintained statistics block. */ 4767 bus_dma_segment_t stats_seg; 4768 int stats_rseg; 4769 bus_dmamap_t stats_map; 4770 struct statistics_block *stats_block; /* Virtual address */ 4771 bus_addr_t stats_block_paddr; /* Physical address */ 4772 4773 /* Bus tag for RX/TX mbufs. */ 4774 bus_dma_segment_t rx_mbuf_seg; 4775 int rx_mbuf_rseg; 4776 bus_dma_segment_t tx_mbuf_seg; 4777 int tx_mbuf_rseg; 4778 4779 /* S/W maintained mbuf TX chain structure. */ 4780 bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD]; 4781 struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD]; 4782 4783 /* S/W maintained mbuf RX chain structure. */ 4784 bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD]; 4785 struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD]; 4786 4787 /* Track the number of rx_bd and tx_bd's in use. */ 4788 u16 free_rx_bd; 4789 u16 used_tx_bd; 4790 4791 /* Provides access to hardware statistics through sysctl. */ 4792 u64 stat_IfHCInOctets; 4793 u64 stat_IfHCInBadOctets; 4794 u64 stat_IfHCOutOctets; 4795 u64 stat_IfHCOutBadOctets; 4796 u64 stat_IfHCInUcastPkts; 4797 u64 stat_IfHCInMulticastPkts; 4798 u64 stat_IfHCInBroadcastPkts; 4799 u64 stat_IfHCOutUcastPkts; 4800 u64 stat_IfHCOutMulticastPkts; 4801 u64 stat_IfHCOutBroadcastPkts; 4802 4803 u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 4804 u32 stat_Dot3StatsCarrierSenseErrors; 4805 u32 stat_Dot3StatsFCSErrors; 4806 u32 stat_Dot3StatsAlignmentErrors; 4807 u32 stat_Dot3StatsSingleCollisionFrames; 4808 u32 stat_Dot3StatsMultipleCollisionFrames; 4809 u32 stat_Dot3StatsDeferredTransmissions; 4810 u32 stat_Dot3StatsExcessiveCollisions; 4811 u32 stat_Dot3StatsLateCollisions; 4812 u32 stat_EtherStatsCollisions; 4813 u32 stat_EtherStatsFragments; 4814 u32 stat_EtherStatsJabbers; 4815 u32 stat_EtherStatsUndersizePkts; 4816 u32 stat_EtherStatsOverrsizePkts; 4817 u32 stat_EtherStatsPktsRx64Octets; 4818 u32 stat_EtherStatsPktsRx65Octetsto127Octets; 4819 u32 stat_EtherStatsPktsRx128Octetsto255Octets; 4820 u32 stat_EtherStatsPktsRx256Octetsto511Octets; 4821 u32 stat_EtherStatsPktsRx512Octetsto1023Octets; 4822 u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; 4823 u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; 4824 u32 stat_EtherStatsPktsTx64Octets; 4825 u32 stat_EtherStatsPktsTx65Octetsto127Octets; 4826 u32 stat_EtherStatsPktsTx128Octetsto255Octets; 4827 u32 stat_EtherStatsPktsTx256Octetsto511Octets; 4828 u32 stat_EtherStatsPktsTx512Octetsto1023Octets; 4829 u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; 4830 u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; 4831 u32 stat_XonPauseFramesReceived; 4832 u32 stat_XoffPauseFramesReceived; 4833 u32 stat_OutXonSent; 4834 u32 stat_OutXoffSent; 4835 u32 stat_FlowControlDone; 4836 u32 stat_MacControlFramesReceived; 4837 u32 stat_XoffStateEntered; 4838 u32 stat_IfInFramesL2FilterDiscards; 4839 u32 stat_IfInRuleCheckerDiscards; 4840 u32 stat_IfInFTQDiscards; 4841 u32 stat_IfInMBUFDiscards; 4842 u32 stat_IfInRuleCheckerP4Hit; 4843 u32 stat_CatchupInRuleCheckerDiscards; 4844 u32 stat_CatchupInFTQDiscards; 4845 u32 stat_CatchupInMBUFDiscards; 4846 u32 stat_CatchupInRuleCheckerP4Hit; 4847 4848#ifdef BNX_DEBUG 4849 /* Track the number of enqueued mbufs. */ 4850 int tx_mbuf_alloc; 4851 int rx_mbuf_alloc; 4852 4853 /* Track how many and what type of interrupts are generated. */ 4854 u32 interrupts_generated; 4855 u32 interrupts_handled; 4856 u32 rx_interrupts; 4857 u32 tx_interrupts; 4858 4859 u32 rx_low_watermark; /* Lowest number of rx_bd's free. */ 4860 u32 tx_hi_watermark; /* Greatest number of tx_bd's used. */ 4861 u32 mbuf_alloc_failed; /* Mbuf allocation failure counter. */ 4862 u32 l2fhdr_status_errors; 4863 u32 unexpected_attentions; 4864 u32 lost_status_block_updates; 4865#endif 4866}; 4867 4868#endif /* #ifndef _BNX_H_DEFINED */ 4869