if_bgereg.h revision 1.98
1/* $OpenBSD: if_bgereg.h,v 1.98 2009/07/21 13:09:41 naddy Exp $ */ 2 3/* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bgereg.h,v 1.11 2002/11/14 23:54:50 sam Exp $ 36 */ 37 38/* 39 * BCM570x memory map. The internal memory layout varies somewhat 40 * depending on whether or not we have external SSRAM attached. 41 * The BCM5700 can have up to 16MB of external memory. The BCM5701 42 * is apparently not designed to use external SSRAM. The mappings 43 * up to the first 4 send rings are the same for both internal and 44 * external memory configurations. Note that mini RX ring space is 45 * only available with external SSRAM configurations, which means 46 * the mini RX ring is not supported on the BCM5701. 47 * 48 * The NIC's memory can be accessed by the host in one of 3 ways: 49 * 50 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 51 * registers in PCI config space can be used to read any 32-bit 52 * address within the NIC's memory. 53 * 54 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 55 * space can be used in conjunction with the memory window in the 56 * device register space at offset 0x8000 to read any 32K chunk 57 * of NIC memory. 58 * 59 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 60 * set, the device I/O mapping consumes 32MB of host address space, 61 * allowing all of the registers and internal NIC memory to be 62 * accessed directly. NIC memory addresses are offset by 0x01000000. 63 * Flat mode consumes so much host address space that it is not 64 * recommended. 65 */ 66#define BGE_PAGE_ZERO 0x00000000 67#define BGE_PAGE_ZERO_END 0x000000FF 68#define BGE_SEND_RING_RCB 0x00000100 69#define BGE_SEND_RING_RCB_END 0x000001FF 70#define BGE_RX_RETURN_RING_RCB 0x00000200 71#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 72#define BGE_STATS_BLOCK 0x00000300 73#define BGE_STATS_BLOCK_END 0x00000AFF 74#define BGE_STATUS_BLOCK 0x00000B00 75#define BGE_STATUS_BLOCK_END 0x00000B4F 76#define BGE_SOFTWARE_GENCOMM 0x00000B50 77#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 78#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 79#define BGE_SOFTWARE_GENCOMM_VER 0x00000B5C 80#define BGE_VER_SHIFT 16 81#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 82#define BGE_FW_PAUSE 0x00000002 83#define BGE_SOFTWARE_GENCOMM_NICCFG2 0x00000D38 84#define BGE_SOFTWARE_GENCOMM_NICCFG3 0x00000D3C 85#define BGE_SOFTWARE_GENCOMM_NICCFG4 0x00000D60 86#define BGE_NICCFG4_GMII_MODE 0x00000002 87#define BGE_NICCFG4_RGMII_STD_IBND_DISABLE 0x00000004 88#define BGE_NICCFG4_RGMII_EXT_IBND_RX_EN 0x00000008 89#define BGE_NICCFG4_RGMII_EXT_IBND_TX_EN 0x00000010 90#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 91#define BGE_UNMAPPED 0x00001000 92#define BGE_UNMAPPED_END 0x00001FFF 93#define BGE_DMA_DESCRIPTORS 0x00002000 94#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 95#define BGE_SEND_RING_1_TO_4 0x00004000 96#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 97 98/* Mappings for internal memory configuration */ 99#define BGE_STD_RX_RINGS 0x00006000 100#define BGE_STD_RX_RINGS_END 0x00006FFF 101#define BGE_JUMBO_RX_RINGS 0x00007000 102#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 103#define BGE_BUFFPOOL_1 0x00008000 104#define BGE_BUFFPOOL_1_END 0x0000FFFF 105#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 106#define BGE_BUFFPOOL_2_END 0x00017FFF 107#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 108#define BGE_BUFFPOOL_3_END 0x0001FFFF 109 110/* Mappings for external SSRAM configurations */ 111#define BGE_SEND_RING_5_TO_6 0x00006000 112#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 113#define BGE_SEND_RING_7_TO_8 0x00007000 114#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 115#define BGE_SEND_RING_9_TO_16 0x00008000 116#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 117#define BGE_EXT_STD_RX_RINGS 0x0000C000 118#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 119#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 120#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 121#define BGE_MINI_RX_RINGS 0x0000E000 122#define BGE_MINI_RX_RINGS_END 0x0000FFFF 123#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 124#define BGE_AVAIL_REGION1_END 0x00017FFF 125#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 126#define BGE_AVAIL_REGION2_END 0x0001FFFF 127#define BGE_EXT_SSRAM 0x00020000 128#define BGE_EXT_SSRAM_END 0x000FFFFF 129 130 131/* 132 * BCM570x register offsets. These are memory mapped registers 133 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 134 * Each register must be accessed using 32 bit operations. 135 * 136 * All registers are accessed through a 32K shared memory block. 137 * The first group of registers are actually copies of the PCI 138 * configuration space registers. 139 */ 140 141/* 142 * PCI registers defined in the PCI 2.2 spec. 143 */ 144#define BGE_PCI_VID 0x00 145#define BGE_PCI_DID 0x02 146#define BGE_PCI_CMD 0x04 147#define BGE_PCI_STS 0x06 148#define BGE_PCI_REV 0x08 149#define BGE_PCI_CLASS 0x09 150#define BGE_PCI_CACHESZ 0x0C 151#define BGE_PCI_LATTIMER 0x0D 152#define BGE_PCI_HDRTYPE 0x0E 153#define BGE_PCI_BIST 0x0F 154#define BGE_PCI_BAR0 0x10 155#define BGE_PCI_BAR1 0x14 156#define BGE_PCI_SUBSYS 0x2C 157#define BGE_PCI_SUBVID 0x2E 158#define BGE_PCI_ROMBASE 0x30 159#define BGE_PCI_CAPPTR 0x34 160#define BGE_PCI_INTLINE 0x3C 161#define BGE_PCI_INTPIN 0x3D 162#define BGE_PCI_MINGNT 0x3E 163#define BGE_PCI_MAXLAT 0x3F 164#define BGE_PCI_PCIXCAP 0x40 165#define BGE_PCI_NEXTPTR_PM 0x41 166#define BGE_PCI_PCIX_CMD 0x42 167#define BGE_PCI_PCIX_STS 0x44 168#define BGE_PCI_PWRMGMT_CAPID 0x48 169#define BGE_PCI_NEXTPTR_VPD 0x49 170#define BGE_PCI_PWRMGMT_CAPS 0x4A 171#define BGE_PCI_PWRMGMT_CMD 0x4C 172#define BGE_PCI_PWRMGMT_STS 0x4D 173#define BGE_PCI_PWRMGMT_DATA 0x4F 174#define BGE_PCI_VPD_CAPID 0x50 175#define BGE_PCI_NEXTPTR_MSI 0x51 176#define BGE_PCI_VPD_ADDR 0x52 177#define BGE_PCI_VPD_DATA 0x54 178#define BGE_PCI_MSI_CAPID 0x58 179#define BGE_PCI_NEXTPTR_NONE 0x59 180#define BGE_PCI_MSI_CTL 0x5A 181#define BGE_PCI_MSI_ADDR_HI 0x5C 182#define BGE_PCI_MSI_ADDR_LO 0x60 183#define BGE_PCI_MSI_DATA 0x64 184 185/* PCI MSI. ??? */ 186#define BGE_PCIE_CAPID_REG 0xD0 187#define BGE_PCIE_CAPID 0x10 188 189/* 190 * PCI registers specific to the BCM570x family. 191 */ 192#define BGE_PCI_MISC_CTL 0x68 193#define BGE_PCI_DMA_RW_CTL 0x6C 194#define BGE_PCI_PCISTATE 0x70 195#define BGE_PCI_CLKCTL 0x74 196#define BGE_PCI_REG_BASEADDR 0x78 197#define BGE_PCI_MEMWIN_BASEADDR 0x7C 198#define BGE_PCI_REG_DATA 0x80 199#define BGE_PCI_MEMWIN_DATA 0x84 200#define BGE_PCI_MODECTL 0x88 201#define BGE_PCI_MISC_CFG 0x8C 202#define BGE_PCI_MISC_LOCALCTL 0x90 203#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 204#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 205#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 206#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 207#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 208#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 209#define BGE_PCI_ISR_MBX_HI 0xB0 210#define BGE_PCI_ISR_MBX_LO 0xB4 211#define BGE_PCI_PRODID_ASICREV 0xBC 212 213/* XXX: 214 * Used in PCI-Express code for 575x chips. 215 * Should be replaced with checking for a PCI config-space 216 * capability for PCI-Express, and PCI-Express standard 217 * offsets into that capability block. 218 */ 219#define BGE_PCI_CONF_DEV_CTRL 0xD8 220#define BGE_PCI_CONF_DEV_STUS 0xDA 221 222/* PCI Misc. Host control register */ 223#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 224#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 225#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 226#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 227#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 228#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 229#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 230#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 231#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 232#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 233 234#if BYTE_ORDER == LITTLE_ENDIAN 235#define BGE_DMA_SWAP_OPTIONS \ 236 BGE_MODECTL_WORDSWAP_NONFRAME| \ 237 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 238#else 239#define BGE_DMA_SWAP_OPTIONS \ 240 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 241 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 242#endif 243 244#define BGE_INIT \ 245 (BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 246 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 247 248#define BGE_CHIPID_BCM5700_A0 0x7000 249#define BGE_CHIPID_BCM5700_A1 0x7001 250#define BGE_CHIPID_BCM5700_B0 0x7100 251#define BGE_CHIPID_BCM5700_B1 0x7101 252#define BGE_CHIPID_BCM5700_B2 0x7102 253#define BGE_CHIPID_BCM5700_B3 0x7103 254#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 255#define BGE_CHIPID_BCM5700_C0 0x7200 256#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 257#define BGE_CHIPID_BCM5701_B0 0x0100 258#define BGE_CHIPID_BCM5701_B2 0x0102 259#define BGE_CHIPID_BCM5701_B5 0x0105 260#define BGE_CHIPID_BCM5703_A0 0x1000 261#define BGE_CHIPID_BCM5703_A1 0x1001 262#define BGE_CHIPID_BCM5703_A2 0x1002 263#define BGE_CHIPID_BCM5703_A3 0x1003 264#define BGE_CHIPID_BCM5703_B0 0x1100 265#define BGE_CHIPID_BCM5704_A0 0x2000 266#define BGE_CHIPID_BCM5704_A1 0x2001 267#define BGE_CHIPID_BCM5704_A2 0x2002 268#define BGE_CHIPID_BCM5704_A3 0x2003 269#define BGE_CHIPID_BCM5704_B0 0x2100 270#define BGE_CHIPID_BCM5705_A0 0x3000 271#define BGE_CHIPID_BCM5705_A1 0x3001 272#define BGE_CHIPID_BCM5705_A2 0x3002 273#define BGE_CHIPID_BCM5705_A3 0x3003 274#define BGE_CHIPID_BCM5750_A0 0x4000 275#define BGE_CHIPID_BCM5750_A1 0x4001 276#define BGE_CHIPID_BCM5750_A3 0x4003 277#define BGE_CHIPID_BCM5750_B0 0x4010 278#define BGE_CHIPID_BCM5750_B1 0x4101 279#define BGE_CHIPID_BCM5750_C0 0x4200 280#define BGE_CHIPID_BCM5750_C1 0x4201 281#define BGE_CHIPID_BCM5750_C2 0x4202 282#define BGE_CHIPID_BCM5714_A0 0x5000 283#define BGE_CHIPID_BCM5761_A0 0x5761000 284#define BGE_CHIPID_BCM5761_A1 0x5761100 285#define BGE_CHIPID_BCM5784_A0 0x5784000 286#define BGE_CHIPID_BCM5784_A1 0x5784100 287#define BGE_CHIPID_BCM5752_A0 0x6000 288#define BGE_CHIPID_BCM5752_A1 0x6001 289#define BGE_CHIPID_BCM5752_A2 0x6002 290#define BGE_CHIPID_BCM5714_B0 0x8000 291#define BGE_CHIPID_BCM5714_B3 0x8003 292#define BGE_CHIPID_BCM5715_A0 0x9000 293#define BGE_CHIPID_BCM5715_A1 0x9001 294#define BGE_CHIPID_BCM5715_A3 0x9003 295#define BGE_CHIPID_BCM5755_A0 0xa000 296#define BGE_CHIPID_BCM5755_A1 0xa001 297#define BGE_CHIPID_BCM5755_A2 0xa002 298#define BGE_CHIPID_BCM5755_C0 0xa200 299#define BGE_CHIPID_BCM5787_A0 0xb000 300#define BGE_CHIPID_BCM5787_A1 0xb001 301#define BGE_CHIPID_BCM5787_A2 0xb002 302#define BGE_CHIPID_BCM5906_A1 0xc001 303#define BGE_CHIPID_BCM5906_A2 0xc002 304#define BGE_CHIPID_BCM57780_A0 0x57780000 305#define BGE_CHIPID_BCM57780_A1 0x57780001 306 307/* shorthand one */ 308#define BGE_ASICREV(x) ((x) >> 12) 309#define BGE_ASICREV_BCM5700 0x07 310#define BGE_ASICREV_BCM5701 0x00 311#define BGE_ASICREV_BCM5703 0x01 312#define BGE_ASICREV_BCM5704 0x02 313#define BGE_ASICREV_BCM5705 0x03 314#define BGE_ASICREV_BCM5750 0x04 315#define BGE_ASICREV_BCM5714_A0 0x05 /* 5714, 5715 */ 316#define BGE_ASICREV_BCM5752 0x06 317#define BGE_ASICREV_BCM5780 0x08 318#define BGE_ASICREV_BCM5714 0x09 /* 5714, 5715 */ 319#define BGE_ASICREV_BCM5755 0x0a 320#define BGE_ASICREV_BCM5787 0x0b 321#define BGE_ASICREV_BCM5906 0x0c 322#define BGE_ASICREV_USE_PRODID_REG 0x0f 323#define BGE_ASICREV_BCM5761 0x5761 324#define BGE_ASICREV_BCM5784 0x5784 325#define BGE_ASICREV_BCM5785 0x5785 326#define BGE_ASICREV_BCM57780 0x57780 327 328/* chip revisions */ 329#define BGE_CHIPREV(x) ((x) >> 8) 330#define BGE_CHIPREV_5700_AX 0x70 331#define BGE_CHIPREV_5700_BX 0x71 332#define BGE_CHIPREV_5700_CX 0x72 333#define BGE_CHIPREV_5701_AX 0x00 334#define BGE_CHIPREV_5703_AX 0x10 335#define BGE_CHIPREV_5704_AX 0x20 336#define BGE_CHIPREV_5704_BX 0x21 337#define BGE_CHIPREV_5750_AX 0x40 338#define BGE_CHIPREV_5750_BX 0x41 339#define BGE_CHIPREV_5761_AX 0x57611 340#define BGE_CHIPREV_5784_AX 0x57841 341 342/* PCI DMA Read/Write Control register */ 343#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 344#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 345#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 346#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 347#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 348#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 349#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 350#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 351#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 352#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 353#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 354#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 355 356#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 357#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 358#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 359#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 360 361#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 362#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 363#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 364#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 365#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 366#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 367#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 368#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 369 370#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 371#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 372#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 373#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 374#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 375#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 376#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 377#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 378 379/* 380 * PCI state register -- note, this register is read only 381 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 382 * register is set. 383 */ 384#define BGE_PCISTATE_FORCE_RESET 0x00000001 385#define BGE_PCISTATE_INTR_NOT_ACTIVE 0x00000002 386#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 387#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 388#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 389#define BGE_PCISTATE_WANT_EXPROM 0x00000020 390#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 391#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 392#define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000 393#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 394 395/* 396 * The following bits in PCI state register are reserved. 397 * If we check that the register values reverts on reset, 398 * do not check these bits. On some 5704C (rev A3) and some 399 * Altima chips, these bits do not revert until much later 400 * in the bge driver's bge_reset() chip-reset state machine. 401 */ 402#define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 403 404/* 405 * PCI Clock Control register -- note, this register is read only 406 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 407 * register is set. 408 */ 409#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 410#define BGE_PCICLOCKCTL_M66EN 0x00000080 411#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 412#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 413#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 414#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 415#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 416#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 417#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 418#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 419 420/* 421 * High priority mailbox registers 422 * Each mailbox is 64-bits wide, though we only use the 423 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 424 * first. The NIC will load the mailbox after the lower 32 bit word 425 * has been updated. 426 */ 427#define BGE_MBX_IRQ0_HI 0x0200 428#define BGE_MBX_IRQ0_LO 0x0204 429#define BGE_MBX_IRQ1_HI 0x0208 430#define BGE_MBX_IRQ1_LO 0x020C 431#define BGE_MBX_IRQ2_HI 0x0210 432#define BGE_MBX_IRQ2_LO 0x0214 433#define BGE_MBX_IRQ3_HI 0x0218 434#define BGE_MBX_IRQ3_LO 0x021C 435#define BGE_MBX_GEN0_HI 0x0220 436#define BGE_MBX_GEN0_LO 0x0224 437#define BGE_MBX_GEN1_HI 0x0228 438#define BGE_MBX_GEN1_LO 0x022C 439#define BGE_MBX_GEN2_HI 0x0230 440#define BGE_MBX_GEN2_LO 0x0234 441#define BGE_MBX_GEN3_HI 0x0228 442#define BGE_MBX_GEN3_LO 0x022C 443#define BGE_MBX_GEN4_HI 0x0240 444#define BGE_MBX_GEN4_LO 0x0244 445#define BGE_MBX_GEN5_HI 0x0248 446#define BGE_MBX_GEN5_LO 0x024C 447#define BGE_MBX_GEN6_HI 0x0250 448#define BGE_MBX_GEN6_LO 0x0254 449#define BGE_MBX_GEN7_HI 0x0258 450#define BGE_MBX_GEN7_LO 0x025C 451#define BGE_MBX_RELOAD_STATS_HI 0x0260 452#define BGE_MBX_RELOAD_STATS_LO 0x0264 453#define BGE_MBX_RX_STD_PROD_HI 0x0268 454#define BGE_MBX_RX_STD_PROD_LO 0x026C 455#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 456#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 457#define BGE_MBX_RX_MINI_PROD_HI 0x0278 458#define BGE_MBX_RX_MINI_PROD_LO 0x027C 459#define BGE_MBX_RX_CONS0_HI 0x0280 460#define BGE_MBX_RX_CONS0_LO 0x0284 461#define BGE_MBX_RX_CONS1_HI 0x0288 462#define BGE_MBX_RX_CONS1_LO 0x028C 463#define BGE_MBX_RX_CONS2_HI 0x0290 464#define BGE_MBX_RX_CONS2_LO 0x0294 465#define BGE_MBX_RX_CONS3_HI 0x0298 466#define BGE_MBX_RX_CONS3_LO 0x029C 467#define BGE_MBX_RX_CONS4_HI 0x02A0 468#define BGE_MBX_RX_CONS4_LO 0x02A4 469#define BGE_MBX_RX_CONS5_HI 0x02A8 470#define BGE_MBX_RX_CONS5_LO 0x02AC 471#define BGE_MBX_RX_CONS6_HI 0x02B0 472#define BGE_MBX_RX_CONS6_LO 0x02B4 473#define BGE_MBX_RX_CONS7_HI 0x02B8 474#define BGE_MBX_RX_CONS7_LO 0x02BC 475#define BGE_MBX_RX_CONS8_HI 0x02C0 476#define BGE_MBX_RX_CONS8_LO 0x02C4 477#define BGE_MBX_RX_CONS9_HI 0x02C8 478#define BGE_MBX_RX_CONS9_LO 0x02CC 479#define BGE_MBX_RX_CONS10_HI 0x02D0 480#define BGE_MBX_RX_CONS10_LO 0x02D4 481#define BGE_MBX_RX_CONS11_HI 0x02D8 482#define BGE_MBX_RX_CONS11_LO 0x02DC 483#define BGE_MBX_RX_CONS12_HI 0x02E0 484#define BGE_MBX_RX_CONS12_LO 0x02E4 485#define BGE_MBX_RX_CONS13_HI 0x02E8 486#define BGE_MBX_RX_CONS13_LO 0x02EC 487#define BGE_MBX_RX_CONS14_HI 0x02F0 488#define BGE_MBX_RX_CONS14_LO 0x02F4 489#define BGE_MBX_RX_CONS15_HI 0x02F8 490#define BGE_MBX_RX_CONS15_LO 0x02FC 491#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 492#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 493#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 494#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 495#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 496#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 497#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 498#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 499#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 500#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 501#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 502#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 503#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 504#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 505#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 506#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 507#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 508#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 509#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 510#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 511#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 512#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 513#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 514#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 515#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 516#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 517#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 518#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 519#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 520#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 521#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 522#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 523#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 524#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 525#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 526#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 527#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 528#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 529#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 530#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 531#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 532#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 533#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 534#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 535#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 536#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 537#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 538#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 539#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 540#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 541#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 542#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 543#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 544#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 545#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 546#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 547#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 548#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 549#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 550#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 551#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 552#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 553#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 554#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 555 556#define BGE_TX_RINGS_MAX 4 557#define BGE_TX_RINGS_EXTSSRAM_MAX 16 558#define BGE_RX_RINGS_MAX 16 559 560/* Ethernet MAC control registers */ 561#define BGE_MAC_MODE 0x0400 562#define BGE_MAC_STS 0x0404 563#define BGE_MAC_EVT_ENB 0x0408 564#define BGE_MAC_LED_CTL 0x040C 565#define BGE_MAC_ADDR1_LO 0x0410 566#define BGE_MAC_ADDR1_HI 0x0414 567#define BGE_MAC_ADDR2_LO 0x0418 568#define BGE_MAC_ADDR2_HI 0x041C 569#define BGE_MAC_ADDR3_LO 0x0420 570#define BGE_MAC_ADDR3_HI 0x0424 571#define BGE_MAC_ADDR4_LO 0x0428 572#define BGE_MAC_ADDR4_HI 0x042C 573#define BGE_WOL_PATPTR 0x0430 574#define BGE_WOL_PATCFG 0x0434 575#define BGE_TX_RANDOM_BACKOFF 0x0438 576#define BGE_RX_MTU 0x043C 577#define BGE_GBIT_PCS_TEST 0x0440 578#define BGE_TX_TBI_AUTONEG 0x0444 579#define BGE_RX_TBI_AUTONEG 0x0448 580#define BGE_MI_COMM 0x044C 581#define BGE_MI_STS 0x0450 582#define BGE_MI_MODE 0x0454 583#define BGE_AUTOPOLL_STS 0x0458 584#define BGE_TX_MODE 0x045C 585#define BGE_TX_STS 0x0460 586#define BGE_TX_LENGTHS 0x0464 587#define BGE_RX_MODE 0x0468 588#define BGE_RX_STS 0x046C 589#define BGE_MAR0 0x0470 590#define BGE_MAR1 0x0474 591#define BGE_MAR2 0x0478 592#define BGE_MAR3 0x047C 593#define BGE_RX_BD_RULES_CTL0 0x0480 594#define BGE_RX_BD_RULES_MASKVAL0 0x0484 595#define BGE_RX_BD_RULES_CTL1 0x0488 596#define BGE_RX_BD_RULES_MASKVAL1 0x048C 597#define BGE_RX_BD_RULES_CTL2 0x0490 598#define BGE_RX_BD_RULES_MASKVAL2 0x0494 599#define BGE_RX_BD_RULES_CTL3 0x0498 600#define BGE_RX_BD_RULES_MASKVAL3 0x049C 601#define BGE_RX_BD_RULES_CTL4 0x04A0 602#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 603#define BGE_RX_BD_RULES_CTL5 0x04A8 604#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 605#define BGE_RX_BD_RULES_CTL6 0x04B0 606#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 607#define BGE_RX_BD_RULES_CTL7 0x04B8 608#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 609#define BGE_RX_BD_RULES_CTL8 0x04C0 610#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 611#define BGE_RX_BD_RULES_CTL9 0x04C8 612#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 613#define BGE_RX_BD_RULES_CTL10 0x04D0 614#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 615#define BGE_RX_BD_RULES_CTL11 0x04D8 616#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 617#define BGE_RX_BD_RULES_CTL12 0x04E0 618#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 619#define BGE_RX_BD_RULES_CTL13 0x04E8 620#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 621#define BGE_RX_BD_RULES_CTL14 0x04F0 622#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 623#define BGE_RX_BD_RULES_CTL15 0x04F8 624#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 625#define BGE_RX_RULES_CFG 0x0500 626#define BGE_MAX_RX_FRAME_LOWAT 0x0504 627#define BGE_SERDES_CFG 0x0590 628#define BGE_SERDES_STS 0x0594 629#define BGE_PHYCFG1 0x05A0 630#define BGE_PHYCFG2 0x05A4 631#define BGE_EXT_RGMII_MODE 0x05A8 632#define BGE_SGDIG_CFG 0x05B0 633#define BGE_SGDIG_STS 0x05B4 634#define BGE_MAC_STATS 0x0800 635 636/* Ethernet MAC Mode register */ 637#define BGE_MACMODE_RESET 0x00000001 638#define BGE_MACMODE_HALF_DUPLEX 0x00000002 639#define BGE_MACMODE_PORTMODE 0x0000000C 640#define BGE_MACMODE_LOOPBACK 0x00000010 641#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 642#define BGE_MACMODE_TX_BURST_ENB 0x00000100 643#define BGE_MACMODE_MAX_DEFER 0x00000200 644#define BGE_MACMODE_LINK_POLARITY 0x00000400 645#define BGE_MACMODE_RX_STATS_ENB 0x00000800 646#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 647#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 648#define BGE_MACMODE_TX_STATS_ENB 0x00004000 649#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 650#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 651#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 652#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 653#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 654#define BGE_MACMODE_MIP_ENB 0x00100000 655#define BGE_MACMODE_TXDMA_ENB 0x00200000 656#define BGE_MACMODE_RXDMA_ENB 0x00400000 657#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 658 659#define BGE_PORTMODE_NONE 0x00000000 660#define BGE_PORTMODE_MII 0x00000004 661#define BGE_PORTMODE_GMII 0x00000008 662#define BGE_PORTMODE_TBI 0x0000000C 663 664/* MAC Status register */ 665#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 666#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 667#define BGE_MACSTAT_RX_CFG 0x00000004 668#define BGE_MACSTAT_CFG_CHANGED 0x00000008 669#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 670#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 671#define BGE_MACSTAT_LINK_CHANGED 0x00001000 672#define BGE_MACSTAT_MI_COMPLETE 0x00400000 673#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 674#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 675#define BGE_MACSTAT_ODI_ERROR 0x02000000 676#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 677#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 678 679/* MAC Event Enable Register */ 680#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 681#define BGE_EVTENB_LINK_CHANGED 0x00001000 682#define BGE_EVTENB_MI_COMPLETE 0x00400000 683#define BGE_EVTENB_MI_INTERRUPT 0x00800000 684#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 685#define BGE_EVTENB_ODI_ERROR 0x02000000 686#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 687#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 688 689/* LED Control Register */ 690#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 691#define BGE_LEDCTL_1000MBPS_LED 0x00000002 692#define BGE_LEDCTL_100MBPS_LED 0x00000004 693#define BGE_LEDCTL_10MBPS_LED 0x00000008 694#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 695#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 696#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 697#define BGE_LEDCTL_1000MBPS_STS 0x00000080 698#define BGE_LEDCTL_100MBPS_STS 0x00000100 699#define BGE_LEDCTL_10MBPS_STS 0x00000200 700#define BGE_LEDCTL_TRADLED_STS 0x00000400 701#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 702#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 703 704/* TX backoff seed register */ 705#define BGE_TX_BACKOFF_SEED_MASK 0x3F 706 707/* Autopoll status register */ 708#define BGE_AUTOPOLLSTS_ERROR 0x00000001 709 710/* Transmit MAC mode register */ 711#define BGE_TXMODE_RESET 0x00000001 712#define BGE_TXMODE_ENABLE 0x00000002 713#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 714#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 715#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 716 717/* Transmit MAC status register */ 718#define BGE_TXSTAT_RX_XOFFED 0x00000001 719#define BGE_TXSTAT_SENT_XOFF 0x00000002 720#define BGE_TXSTAT_SENT_XON 0x00000004 721#define BGE_TXSTAT_LINK_UP 0x00000008 722#define BGE_TXSTAT_ODI_UFLOW 0x00000010 723#define BGE_TXSTAT_ODI_OFLOW 0x00000020 724 725/* Transmit MAC lengths register */ 726#define BGE_TXLEN_SLOTTIME 0x000000FF 727#define BGE_TXLEN_IPG 0x00000F00 728#define BGE_TXLEN_CRS 0x00003000 729 730/* Receive MAC mode register */ 731#define BGE_RXMODE_RESET 0x00000001 732#define BGE_RXMODE_ENABLE 0x00000002 733#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 734#define BGE_RXMODE_RX_GIANTS 0x00000020 735#define BGE_RXMODE_RX_RUNTS 0x00000040 736#define BGE_RXMODE_8022_LENCHECK 0x00000080 737#define BGE_RXMODE_RX_PROMISC 0x00000100 738#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 739#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 740#define BGE_RXMODE_RX_IPV6_CSUM_ENABLE 0x01000000 741 742/* Receive MAC status register */ 743#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 744#define BGE_RXSTAT_RCVD_XOFF 0x00000002 745#define BGE_RXSTAT_RCVD_XON 0x00000004 746 747/* Receive Rules Control register */ 748#define BGE_RXRULECTL_OFFSET 0x000000FF 749#define BGE_RXRULECTL_CLASS 0x00001F00 750#define BGE_RXRULECTL_HDRTYPE 0x0000E000 751#define BGE_RXRULECTL_COMPARE_OP 0x00030000 752#define BGE_RXRULECTL_MAP 0x01000000 753#define BGE_RXRULECTL_DISCARD 0x02000000 754#define BGE_RXRULECTL_MASK 0x04000000 755#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 756#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 757#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 758#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 759 760/* Receive Rules Mask register */ 761#define BGE_RXRULEMASK_VALUE 0x0000FFFF 762#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 763 764/* SERDES configuration register */ 765#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 766#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 767#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 768#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 769#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 770#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 771#define BGE_SERDESCFG_TXMODE 0x00001000 772#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 773#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 774#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 775#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 776#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 777#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 778#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125MHz clock */ 779#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 780#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 781 782/* SERDES status register */ 783#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 784#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 785 786/* PHYCFG1 config */ 787#define BGE_PHYCFG1_RGMII_INT 0x00000001 788#define BGE_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000 789#define BGE_PHYCFG1_RGMII_SND_STAT_EN 0x04000000 790#define BGE_PHYCFG1_TXC_DRV 0x20000000 791 792/* PHYCFG2 config */ 793#define BGE_PHYCFG2_INBAND_ENABLE 0x00000001 794#define BGE_PHYCFG2_EMODE_MASK_MASK 0x000001c0 795#define BGE_PHYCFG2_EMODE_MASK_AC131 0x000000c0 796#define BGE_PHYCFG2_EMODE_MASK_50610 0x00000100 797#define BGE_PHYCFG2_EMODE_MASK_RT8211 0x00000000 798#define BGE_PHYCFG2_EMODE_MASK_RT8201 0x000001c0 799#define BGE_PHYCFG2_EMODE_COMP_MASK 0x00000e00 800#define BGE_PHYCFG2_EMODE_COMP_AC131 0x00000600 801#define BGE_PHYCFG2_EMODE_COMP_50610 0x00000400 802#define BGE_PHYCFG2_EMODE_COMP_RT8211 0x00000800 803#define BGE_PHYCFG2_EMODE_COMP_RT8201 0x00000000 804#define BGE_PHYCFG2_FMODE_MASK_MASK 0x00007000 805#define BGE_PHYCFG2_FMODE_MASK_AC131 0x00006000 806#define BGE_PHYCFG2_FMODE_MASK_50610 0x00004000 807#define BGE_PHYCFG2_FMODE_MASK_RT8211 0x00000000 808#define BGE_PHYCFG2_FMODE_MASK_RT8201 0x00007000 809#define BGE_PHYCFG2_FMODE_COMP_MASK 0x00038000 810#define BGE_PHYCFG2_FMODE_COMP_AC131 0x00030000 811#define BGE_PHYCFG2_FMODE_COMP_50610 0x00008000 812#define BGE_PHYCFG2_FMODE_COMP_RT8211 0x00038000 813#define BGE_PHYCFG2_FMODE_COMP_RT8201 0x00000000 814#define BGE_PHYCFG2_GMODE_MASK_MASK 0x001c0000 815#define BGE_PHYCFG2_GMODE_MASK_AC131 0x001c0000 816#define BGE_PHYCFG2_GMODE_MASK_50610 0x00100000 817#define BGE_PHYCFG2_GMODE_MASK_RT8211 0x00000000 818#define BGE_PHYCFG2_GMODE_MASK_RT8201 0x001c0000 819#define BGE_PHYCFG2_GMODE_COMP_MASK 0x00e00000 820#define BGE_PHYCFG2_GMODE_COMP_AC131 0x00e00000 821#define BGE_PHYCFG2_GMODE_COMP_50610 0x00000000 822#define BGE_PHYCFG2_GMODE_COMP_RT8211 0x00200000 823#define BGE_PHYCFG2_GMODE_COMP_RT8201 0x00000000 824#define BGE_PHYCFG2_ACT_MASK_MASK 0x03000000 825#define BGE_PHYCFG2_ACT_MASK_AC131 0x03000000 826#define BGE_PHYCFG2_ACT_MASK_50610 0x01000000 827#define BGE_PHYCFG2_ACT_MASK_RT8211 0x03000000 828#define BGE_PHYCFG2_ACT_MASK_RT8201 0x01000000 829#define BGE_PHYCFG2_ACT_COMP_MASK 0x0c000000 830#define BGE_PHYCFG2_ACT_COMP_AC131 0x00000000 831#define BGE_PHYCFG2_ACT_COMP_50610 0x00000000 832#define BGE_PHYCFG2_ACT_COMP_RT8211 0x00000000 833#define BGE_PHYCFG2_ACT_COMP_RT8201 0x08000000 834#define BGE_PHYCFG2_QUAL_MASK_MASK 0x30000000 835#define BGE_PHYCFG2_QUAL_MASK_AC131 0x30000000 836#define BGE_PHYCFG2_QUAL_MASK_50610 0x30000000 837#define BGE_PHYCFG2_QUAL_MASK_RT8211 0x30000000 838#define BGE_PHYCFG2_QUAL_MASK_RT8201 0x30000000 839#define BGE_PHYCFG2_QUAL_COMP_MASK 0xc0000000 840#define BGE_PHYCFG2_QUAL_COMP_AC131 0x00000000 841#define BGE_PHYCFG2_QUAL_COMP_50610 0x00000000 842#define BGE_PHYCFG2_QUAL_COMP_RT8211 0x00000000 843#define BGE_PHYCFG2_QUAL_COMP_RT8201 0x00000000 844#define BGE_PHYCFG2_50610_LED_MODES \ 845 (BGE_PHYCFG2_EMODE_MASK_50610 | \ 846 BGE_PHYCFG2_EMODE_COMP_50610 | \ 847 BGE_PHYCFG2_FMODE_MASK_50610 | \ 848 BGE_PHYCFG2_FMODE_COMP_50610 | \ 849 BGE_PHYCFG2_GMODE_MASK_50610 | \ 850 BGE_PHYCFG2_GMODE_COMP_50610 | \ 851 BGE_PHYCFG2_ACT_MASK_50610 | \ 852 BGE_PHYCFG2_ACT_COMP_50610 | \ 853 BGE_PHYCFG2_QUAL_MASK_50610 | \ 854 BGE_PHYCFG2_QUAL_COMP_50610) 855#define BGE_PHYCFG2_AC131_LED_MODES \ 856 (BGE_PHYCFG2_EMODE_MASK_AC131 | \ 857 BGE_PHYCFG2_EMODE_COMP_AC131 | \ 858 BGE_PHYCFG2_FMODE_MASK_AC131 | \ 859 BGE_PHYCFG2_FMODE_COMP_AC131 | \ 860 BGE_PHYCFG2_GMODE_MASK_AC131 | \ 861 BGE_PHYCFG2_GMODE_COMP_AC131 | \ 862 BGE_PHYCFG2_ACT_MASK_AC131 | \ 863 BGE_PHYCFG2_ACT_COMP_AC131 | \ 864 BGE_PHYCFG2_QUAL_MASK_AC131 | \ 865 BGE_PHYCFG2_QUAL_COMP_AC131) 866#define BGE_PHYCFG2_RTL8211C_LED_MODES \ 867 (BGE_PHYCFG2_EMODE_MASK_RT8211 | \ 868 BGE_PHYCFG2_EMODE_COMP_RT8211 | \ 869 BGE_PHYCFG2_FMODE_MASK_RT8211 | \ 870 BGE_PHYCFG2_FMODE_COMP_RT8211 | \ 871 BGE_PHYCFG2_GMODE_MASK_RT8211 | \ 872 BGE_PHYCFG2_GMODE_COMP_RT8211 | \ 873 BGE_PHYCFG2_ACT_MASK_RT8211 | \ 874 BGE_PHYCFG2_ACT_COMP_RT8211 | \ 875 BGE_PHYCFG2_QUAL_MASK_RT8211 | \ 876 BGE_PHYCFG2_QUAL_COMP_RT8211) 877#define BGE_PHYCFG2_RTL8201E_LED_MODES \ 878 (BGE_PHYCFG2_EMODE_MASK_RT8201 | \ 879 BGE_PHYCFG2_EMODE_COMP_RT8201 | \ 880 BGE_PHYCFG2_FMODE_MASK_RT8201 | \ 881 BGE_PHYCFG2_FMODE_COMP_RT8201 | \ 882 BGE_PHYCFG2_GMODE_MASK_RT8201 | \ 883 BGE_PHYCFG2_GMODE_COMP_RT8201 | \ 884 BGE_PHYCFG2_ACT_MASK_RT8201 | \ 885 BGE_PHYCFG2_ACT_COMP_RT8201 | \ 886 BGE_PHYCFG2_QUAL_MASK_RT8201 | \ 887 BGE_PHYCFG2_QUAL_COMP_RT8201) 888 889/* EXT_RGMII_MODE config */ 890#define BGE_RGMII_MODE_TX_ENABLE 0x00000001 891#define BGE_RGMII_MODE_TX_LOWPWR 0x00000002 892#define BGE_RGMII_MODE_TX_RESET 0x00000004 893#define BGE_RGMII_MODE_RX_INT_B 0x00000100 894#define BGE_RGMII_MODE_RX_QUALITY 0x00000200 895#define BGE_RGMII_MODE_RX_ACTIVITY 0x00000400 896#define BGE_RGMII_MODE_RX_ENG_DET 0x00000800 897 898/* SGDIG config (not documented) */ 899#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 900#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 901#define BGE_SGDIGCFG_SEND 0x40000000 902#define BGE_SGDIGCFG_AUTO 0x80000000 903 904/* SGDIG status (not documented) */ 905#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 906#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 907#define BGE_SGDIGSTS_DONE 0x00000002 908 909/* MI communication register */ 910#define BGE_MICOMM_DATA 0x0000FFFF 911#define BGE_MICOMM_REG 0x001F0000 912#define BGE_MICOMM_PHY 0x03E00000 913#define BGE_MICOMM_CMD 0x0C000000 914#define BGE_MICOMM_READFAIL 0x10000000 915#define BGE_MICOMM_BUSY 0x20000000 916 917#define BGE_MIREG(x) ((x & 0x1F) << 16) 918#define BGE_MIPHY(x) ((x & 0x1F) << 21) 919#define BGE_MICMD_WRITE 0x04000000 920#define BGE_MICMD_READ 0x08000000 921 922/* MI status register */ 923#define BGE_MISTS_LINK 0x00000001 924#define BGE_MISTS_10MBPS 0x00000002 925 926#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 927#define BGE_MIMODE_AUTOPOLL 0x00000010 928#define BGE_MIMODE_500KHZ_CONST 0x00008000 929#define BGE_MIMODE_CLKCNT 0x001F0000 930#define BGE_MIMODE_BASE 0x000C0000 931 932/* 933 * Send data initiator control registers. 934 */ 935#define BGE_SDI_MODE 0x0C00 936#define BGE_SDI_STATUS 0x0C04 937#define BGE_SDI_STATS_CTL 0x0C08 938#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 939#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 940#define BGE_LOCSTATS_COS0 0x0C80 941#define BGE_LOCSTATS_COS1 0x0C84 942#define BGE_LOCSTATS_COS2 0x0C88 943#define BGE_LOCSTATS_COS3 0x0C8C 944#define BGE_LOCSTATS_COS4 0x0C90 945#define BGE_LOCSTATS_COS5 0x0C84 946#define BGE_LOCSTATS_COS6 0x0C98 947#define BGE_LOCSTATS_COS7 0x0C9C 948#define BGE_LOCSTATS_COS8 0x0CA0 949#define BGE_LOCSTATS_COS9 0x0CA4 950#define BGE_LOCSTATS_COS10 0x0CA8 951#define BGE_LOCSTATS_COS11 0x0CAC 952#define BGE_LOCSTATS_COS12 0x0CB0 953#define BGE_LOCSTATS_COS13 0x0CB4 954#define BGE_LOCSTATS_COS14 0x0CB8 955#define BGE_LOCSTATS_COS15 0x0CBC 956#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 957#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 958#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 959#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 960#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 961#define BGE_LOCSTATS_IRQS 0x0CD4 962#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 963#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 964 965/* Send Data Initiator mode register */ 966#define BGE_SDIMODE_RESET 0x00000001 967#define BGE_SDIMODE_ENABLE 0x00000002 968#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 969 970/* Send Data Initiator stats register */ 971#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 972 973/* Send Data Initiator stats control register */ 974#define BGE_SDISTATSCTL_ENABLE 0x00000001 975#define BGE_SDISTATSCTL_FASTER 0x00000002 976#define BGE_SDISTATSCTL_CLEAR 0x00000004 977#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 978#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 979 980/* 981 * Send Data Completion Control registers 982 */ 983#define BGE_SDC_MODE 0x1000 984#define BGE_SDC_STATUS 0x1004 985 986/* Send Data completion mode register */ 987#define BGE_SDCMODE_RESET 0x00000001 988#define BGE_SDCMODE_ENABLE 0x00000002 989#define BGE_SDCMODE_ATTN 0x00000004 990#define BGE_SDCMODE_CDELAY 0x00000010 991 992/* Send Data completion status register */ 993#define BGE_SDCSTAT_ATTN 0x00000004 994 995/* 996 * Send BD Ring Selector Control registers 997 */ 998#define BGE_SRS_MODE 0x1400 999#define BGE_SRS_STATUS 0x1404 1000#define BGE_SRS_HWDIAG 0x1408 1001#define BGE_SRS_LOC_NIC_CONS0 0x1440 1002#define BGE_SRS_LOC_NIC_CONS1 0x1444 1003#define BGE_SRS_LOC_NIC_CONS2 0x1448 1004#define BGE_SRS_LOC_NIC_CONS3 0x144C 1005#define BGE_SRS_LOC_NIC_CONS4 0x1450 1006#define BGE_SRS_LOC_NIC_CONS5 0x1454 1007#define BGE_SRS_LOC_NIC_CONS6 0x1458 1008#define BGE_SRS_LOC_NIC_CONS7 0x145C 1009#define BGE_SRS_LOC_NIC_CONS8 0x1460 1010#define BGE_SRS_LOC_NIC_CONS9 0x1464 1011#define BGE_SRS_LOC_NIC_CONS10 0x1468 1012#define BGE_SRS_LOC_NIC_CONS11 0x146C 1013#define BGE_SRS_LOC_NIC_CONS12 0x1470 1014#define BGE_SRS_LOC_NIC_CONS13 0x1474 1015#define BGE_SRS_LOC_NIC_CONS14 0x1478 1016#define BGE_SRS_LOC_NIC_CONS15 0x147C 1017 1018/* Send BD Ring Selector Mode register */ 1019#define BGE_SRSMODE_RESET 0x00000001 1020#define BGE_SRSMODE_ENABLE 0x00000002 1021#define BGE_SRSMODE_ATTN 0x00000004 1022 1023/* Send BD Ring Selector Status register */ 1024#define BGE_SRSSTAT_ERROR 0x00000004 1025 1026/* Send BD Ring Selector HW Diagnostics register */ 1027#define BGE_SRSHWDIAG_STATE 0x0000000F 1028#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 1029#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 1030#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 1031 1032/* 1033 * Send BD Initiator Selector Control registers 1034 */ 1035#define BGE_SBDI_MODE 0x1800 1036#define BGE_SBDI_STATUS 0x1804 1037#define BGE_SBDI_LOC_NIC_PROD0 0x1808 1038#define BGE_SBDI_LOC_NIC_PROD1 0x180C 1039#define BGE_SBDI_LOC_NIC_PROD2 0x1810 1040#define BGE_SBDI_LOC_NIC_PROD3 0x1814 1041#define BGE_SBDI_LOC_NIC_PROD4 0x1818 1042#define BGE_SBDI_LOC_NIC_PROD5 0x181C 1043#define BGE_SBDI_LOC_NIC_PROD6 0x1820 1044#define BGE_SBDI_LOC_NIC_PROD7 0x1824 1045#define BGE_SBDI_LOC_NIC_PROD8 0x1828 1046#define BGE_SBDI_LOC_NIC_PROD9 0x182C 1047#define BGE_SBDI_LOC_NIC_PROD10 0x1830 1048#define BGE_SBDI_LOC_NIC_PROD11 0x1834 1049#define BGE_SBDI_LOC_NIC_PROD12 0x1838 1050#define BGE_SBDI_LOC_NIC_PROD13 0x183C 1051#define BGE_SBDI_LOC_NIC_PROD14 0x1840 1052#define BGE_SBDI_LOC_NIC_PROD15 0x1844 1053 1054/* Send BD Initiator Mode register */ 1055#define BGE_SBDIMODE_RESET 0x00000001 1056#define BGE_SBDIMODE_ENABLE 0x00000002 1057#define BGE_SBDIMODE_ATTN 0x00000004 1058 1059/* Send BD Initiator Status register */ 1060#define BGE_SBDISTAT_ERROR 0x00000004 1061 1062/* 1063 * Send BD Completion Control registers 1064 */ 1065#define BGE_SBDC_MODE 0x1C00 1066#define BGE_SBDC_STATUS 0x1C04 1067 1068/* Send BD Completion Control Mode register */ 1069#define BGE_SBDCMODE_RESET 0x00000001 1070#define BGE_SBDCMODE_ENABLE 0x00000002 1071#define BGE_SBDCMODE_ATTN 0x00000004 1072 1073/* Send BD Completion Control Status register */ 1074#define BGE_SBDCSTAT_ATTN 0x00000004 1075 1076/* 1077 * Receive List Placement Control registers 1078 */ 1079#define BGE_RXLP_MODE 0x2000 1080#define BGE_RXLP_STATUS 0x2004 1081#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1082#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1083#define BGE_RXLP_CFG 0x2010 1084#define BGE_RXLP_STATS_CTL 0x2014 1085#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1086#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1087#define BGE_RXLP_HEAD0 0x2100 1088#define BGE_RXLP_TAIL0 0x2104 1089#define BGE_RXLP_COUNT0 0x2108 1090#define BGE_RXLP_HEAD1 0x2110 1091#define BGE_RXLP_TAIL1 0x2114 1092#define BGE_RXLP_COUNT1 0x2118 1093#define BGE_RXLP_HEAD2 0x2120 1094#define BGE_RXLP_TAIL2 0x2124 1095#define BGE_RXLP_COUNT2 0x2128 1096#define BGE_RXLP_HEAD3 0x2130 1097#define BGE_RXLP_TAIL3 0x2134 1098#define BGE_RXLP_COUNT3 0x2138 1099#define BGE_RXLP_HEAD4 0x2140 1100#define BGE_RXLP_TAIL4 0x2144 1101#define BGE_RXLP_COUNT4 0x2148 1102#define BGE_RXLP_HEAD5 0x2150 1103#define BGE_RXLP_TAIL5 0x2154 1104#define BGE_RXLP_COUNT5 0x2158 1105#define BGE_RXLP_HEAD6 0x2160 1106#define BGE_RXLP_TAIL6 0x2164 1107#define BGE_RXLP_COUNT6 0x2168 1108#define BGE_RXLP_HEAD7 0x2170 1109#define BGE_RXLP_TAIL7 0x2174 1110#define BGE_RXLP_COUNT7 0x2178 1111#define BGE_RXLP_HEAD8 0x2180 1112#define BGE_RXLP_TAIL8 0x2184 1113#define BGE_RXLP_COUNT8 0x2188 1114#define BGE_RXLP_HEAD9 0x2190 1115#define BGE_RXLP_TAIL9 0x2194 1116#define BGE_RXLP_COUNT9 0x2198 1117#define BGE_RXLP_HEAD10 0x21A0 1118#define BGE_RXLP_TAIL10 0x21A4 1119#define BGE_RXLP_COUNT10 0x21A8 1120#define BGE_RXLP_HEAD11 0x21B0 1121#define BGE_RXLP_TAIL11 0x21B4 1122#define BGE_RXLP_COUNT11 0x21B8 1123#define BGE_RXLP_HEAD12 0x21C0 1124#define BGE_RXLP_TAIL12 0x21C4 1125#define BGE_RXLP_COUNT12 0x21C8 1126#define BGE_RXLP_HEAD13 0x21D0 1127#define BGE_RXLP_TAIL13 0x21D4 1128#define BGE_RXLP_COUNT13 0x21D8 1129#define BGE_RXLP_HEAD14 0x21E0 1130#define BGE_RXLP_TAIL14 0x21E4 1131#define BGE_RXLP_COUNT14 0x21E8 1132#define BGE_RXLP_HEAD15 0x21F0 1133#define BGE_RXLP_TAIL15 0x21F4 1134#define BGE_RXLP_COUNT15 0x21F8 1135#define BGE_RXLP_LOCSTAT_COS0 0x2200 1136#define BGE_RXLP_LOCSTAT_COS1 0x2204 1137#define BGE_RXLP_LOCSTAT_COS2 0x2208 1138#define BGE_RXLP_LOCSTAT_COS3 0x220C 1139#define BGE_RXLP_LOCSTAT_COS4 0x2210 1140#define BGE_RXLP_LOCSTAT_COS5 0x2214 1141#define BGE_RXLP_LOCSTAT_COS6 0x2218 1142#define BGE_RXLP_LOCSTAT_COS7 0x221C 1143#define BGE_RXLP_LOCSTAT_COS8 0x2220 1144#define BGE_RXLP_LOCSTAT_COS9 0x2224 1145#define BGE_RXLP_LOCSTAT_COS10 0x2228 1146#define BGE_RXLP_LOCSTAT_COS11 0x222C 1147#define BGE_RXLP_LOCSTAT_COS12 0x2230 1148#define BGE_RXLP_LOCSTAT_COS13 0x2234 1149#define BGE_RXLP_LOCSTAT_COS14 0x2238 1150#define BGE_RXLP_LOCSTAT_COS15 0x223C 1151#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1152#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1153#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1154#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1155#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1156#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1157#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1158 1159 1160/* Receive List Placement mode register */ 1161#define BGE_RXLPMODE_RESET 0x00000001 1162#define BGE_RXLPMODE_ENABLE 0x00000002 1163#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1164#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1165#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1166 1167/* Receive List Placement Status register */ 1168#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1169#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1170#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1171 1172/* 1173 * Receive Data and Receive BD Initiator Control Registers 1174 */ 1175#define BGE_RDBDI_MODE 0x2400 1176#define BGE_RDBDI_STATUS 0x2404 1177#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1178#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1179#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1180#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1181#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1182#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1183#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1184#define BGE_RX_STD_RCB_NICADDR 0x245C 1185#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1186#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1187#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1188#define BGE_RX_MINI_RCB_NICADDR 0x246C 1189#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1190#define BGE_RDBDI_STD_RX_CONS 0x2474 1191#define BGE_RDBDI_MINI_RX_CONS 0x2478 1192#define BGE_RDBDI_RETURN_PROD0 0x2480 1193#define BGE_RDBDI_RETURN_PROD1 0x2484 1194#define BGE_RDBDI_RETURN_PROD2 0x2488 1195#define BGE_RDBDI_RETURN_PROD3 0x248C 1196#define BGE_RDBDI_RETURN_PROD4 0x2490 1197#define BGE_RDBDI_RETURN_PROD5 0x2494 1198#define BGE_RDBDI_RETURN_PROD6 0x2498 1199#define BGE_RDBDI_RETURN_PROD7 0x249C 1200#define BGE_RDBDI_RETURN_PROD8 0x24A0 1201#define BGE_RDBDI_RETURN_PROD9 0x24A4 1202#define BGE_RDBDI_RETURN_PROD10 0x24A8 1203#define BGE_RDBDI_RETURN_PROD11 0x24AC 1204#define BGE_RDBDI_RETURN_PROD12 0x24B0 1205#define BGE_RDBDI_RETURN_PROD13 0x24B4 1206#define BGE_RDBDI_RETURN_PROD14 0x24B8 1207#define BGE_RDBDI_RETURN_PROD15 0x24BC 1208#define BGE_RDBDI_HWDIAG 0x24C0 1209 1210 1211/* Receive Data and Receive BD Initiator Mode register */ 1212#define BGE_RDBDIMODE_RESET 0x00000001 1213#define BGE_RDBDIMODE_ENABLE 0x00000002 1214#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1215#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1216#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1217 1218/* Receive Data and Receive BD Initiator Status register */ 1219#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1220#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1221#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1222 1223 1224/* 1225 * Receive Data Completion Control registers 1226 */ 1227#define BGE_RDC_MODE 0x2800 1228 1229/* Receive Data Completion Mode register */ 1230#define BGE_RDCMODE_RESET 0x00000001 1231#define BGE_RDCMODE_ENABLE 0x00000002 1232#define BGE_RDCMODE_ATTN 0x00000004 1233 1234/* 1235 * Receive BD Initiator Control registers 1236 */ 1237#define BGE_RBDI_MODE 0x2C00 1238#define BGE_RBDI_STATUS 0x2C04 1239#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1240#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1241#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1242#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1243#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1244#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1245 1246/* Receive BD Initiator Mode register */ 1247#define BGE_RBDIMODE_RESET 0x00000001 1248#define BGE_RBDIMODE_ENABLE 0x00000002 1249#define BGE_RBDIMODE_ATTN 0x00000004 1250 1251/* Receive BD Initiator Status register */ 1252#define BGE_RBDISTAT_ATTN 0x00000004 1253 1254/* 1255 * Receive BD Completion Control registers 1256 */ 1257#define BGE_RBDC_MODE 0x3000 1258#define BGE_RBDC_STATUS 0x3004 1259#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1260#define BGE_RBDC_STD_BD_PROD 0x300C 1261#define BGE_RBDC_MINI_BD_PROD 0x3010 1262 1263/* Receive BD completion mode register */ 1264#define BGE_RBDCMODE_RESET 0x00000001 1265#define BGE_RBDCMODE_ENABLE 0x00000002 1266#define BGE_RBDCMODE_ATTN 0x00000004 1267 1268/* Receive BD completion status register */ 1269#define BGE_RBDCSTAT_ERROR 0x00000004 1270 1271/* 1272 * Receive List Selector Control registers 1273 */ 1274#define BGE_RXLS_MODE 0x3400 1275#define BGE_RXLS_STATUS 0x3404 1276 1277/* Receive List Selector Mode register */ 1278#define BGE_RXLSMODE_RESET 0x00000001 1279#define BGE_RXLSMODE_ENABLE 0x00000002 1280#define BGE_RXLSMODE_ATTN 0x00000004 1281 1282/* Receive List Selector Status register */ 1283#define BGE_RXLSSTAT_ERROR 0x00000004 1284 1285/* 1286 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1287 */ 1288#define BGE_MBCF_MODE 0x3800 1289#define BGE_MBCF_STATUS 0x3804 1290 1291/* Mbuf Cluster Free mode register */ 1292#define BGE_MBCFMODE_RESET 0x00000001 1293#define BGE_MBCFMODE_ENABLE 0x00000002 1294#define BGE_MBCFMODE_ATTN 0x00000004 1295 1296/* Mbuf Cluster Free status register */ 1297#define BGE_MBCFSTAT_ERROR 0x00000004 1298 1299/* 1300 * Host Coalescing Control registers 1301 */ 1302#define BGE_HCC_MODE 0x3C00 1303#define BGE_HCC_STATUS 0x3C04 1304#define BGE_HCC_RX_COAL_TICKS 0x3C08 1305#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1306#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1307#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1308#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1309#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1310#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1311#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1312#define BGE_HCC_STATS_TICKS 0x3C28 1313#define BGE_HCC_STATS_ADDR_HI 0x3C30 1314#define BGE_HCC_STATS_ADDR_LO 0x3C34 1315#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1316#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1317#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1318#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1319#define BGE_FLOW_ATTN 0x3C48 1320#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1321#define BGE_HCC_STD_BD_CONS 0x3C54 1322#define BGE_HCC_MINI_BD_CONS 0x3C58 1323#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1324#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1325#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1326#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1327#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1328#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1329#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1330#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1331#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1332#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1333#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1334#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1335#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1336#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1337#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1338#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1339#define BGE_HCC_TX_BD_CONS0 0x3CC0 1340#define BGE_HCC_TX_BD_CONS1 0x3CC4 1341#define BGE_HCC_TX_BD_CONS2 0x3CC8 1342#define BGE_HCC_TX_BD_CONS3 0x3CCC 1343#define BGE_HCC_TX_BD_CONS4 0x3CD0 1344#define BGE_HCC_TX_BD_CONS5 0x3CD4 1345#define BGE_HCC_TX_BD_CONS6 0x3CD8 1346#define BGE_HCC_TX_BD_CONS7 0x3CDC 1347#define BGE_HCC_TX_BD_CONS8 0x3CE0 1348#define BGE_HCC_TX_BD_CONS9 0x3CE4 1349#define BGE_HCC_TX_BD_CONS10 0x3CE8 1350#define BGE_HCC_TX_BD_CONS11 0x3CEC 1351#define BGE_HCC_TX_BD_CONS12 0x3CF0 1352#define BGE_HCC_TX_BD_CONS13 0x3CF4 1353#define BGE_HCC_TX_BD_CONS14 0x3CF8 1354#define BGE_HCC_TX_BD_CONS15 0x3CFC 1355 1356 1357/* Host coalescing mode register */ 1358#define BGE_HCCMODE_RESET 0x00000001 1359#define BGE_HCCMODE_ENABLE 0x00000002 1360#define BGE_HCCMODE_ATTN 0x00000004 1361#define BGE_HCCMODE_COAL_NOW 0x00000008 1362#define BGE_HCCMODE_MSI_BITS 0x00000070 1363#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1364 1365#define BGE_STATBLKSZ_FULL 0x00000000 1366#define BGE_STATBLKSZ_64BYTE 0x00000080 1367#define BGE_STATBLKSZ_32BYTE 0x00000100 1368 1369/* Host coalescing status register */ 1370#define BGE_HCCSTAT_ERROR 0x00000004 1371 1372/* Flow attention register */ 1373#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1374#define BGE_FLOWATTN_MEMARB 0x00000080 1375#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1376#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1377#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1378#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1379#define BGE_FLOWATTN_RDBDI 0x00080000 1380#define BGE_FLOWATTN_RXLS 0x00100000 1381#define BGE_FLOWATTN_RXLP 0x00200000 1382#define BGE_FLOWATTN_RBDC 0x00400000 1383#define BGE_FLOWATTN_RBDI 0x00800000 1384#define BGE_FLOWATTN_SDC 0x08000000 1385#define BGE_FLOWATTN_SDI 0x10000000 1386#define BGE_FLOWATTN_SRS 0x20000000 1387#define BGE_FLOWATTN_SBDC 0x40000000 1388#define BGE_FLOWATTN_SBDI 0x80000000 1389 1390/* 1391 * Memory arbiter registers 1392 */ 1393#define BGE_MARB_MODE 0x4000 1394#define BGE_MARB_STATUS 0x4004 1395#define BGE_MARB_TRAPADDR_HI 0x4008 1396#define BGE_MARB_TRAPADDR_LO 0x400C 1397 1398/* Memory arbiter mode register */ 1399#define BGE_MARBMODE_RESET 0x00000001 1400#define BGE_MARBMODE_ENABLE 0x00000002 1401#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1402#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1403#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1404#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1405#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1406#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1407#define BGE_MARBMODE_PCI_TRAP 0x00000100 1408#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1409#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1410#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1411#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1412#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1413#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1414#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1415#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1416#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1417#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1418#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1419#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1420#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1421#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1422#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1423#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1424#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1425 1426/* Memory arbiter status register */ 1427#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1428#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1429#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1430#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1431#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1432#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1433#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1434#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1435#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1436#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1437#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1438#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1439#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1440#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1441#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1442#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1443#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1444#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1445#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1446#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1447#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1448#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1449#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1450#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1451 1452/* 1453 * Buffer manager control registers 1454 */ 1455#define BGE_BMAN_MODE 0x4400 1456#define BGE_BMAN_STATUS 0x4404 1457#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1458#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1459#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1460#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1461#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1462#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1463#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1464#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1465#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1466#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1467#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1468#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1469#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1470#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1471#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1472#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1473#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1474#define BGE_BMAN_HWDIAG_1 0x444C 1475#define BGE_BMAN_HWDIAG_2 0x4450 1476#define BGE_BMAN_HWDIAG_3 0x4454 1477 1478/* Buffer manager mode register */ 1479#define BGE_BMANMODE_RESET 0x00000001 1480#define BGE_BMANMODE_ENABLE 0x00000002 1481#define BGE_BMANMODE_ATTN 0x00000004 1482#define BGE_BMANMODE_TESTMODE 0x00000008 1483#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1484 1485/* Buffer manager status register */ 1486#define BGE_BMANSTAT_ERRO 0x00000004 1487#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1488 1489 1490/* 1491 * Read DMA Control registers 1492 */ 1493#define BGE_RDMA_MODE 0x4800 1494#define BGE_RDMA_STATUS 0x4804 1495 1496/* Read DMA mode register */ 1497#define BGE_RDMAMODE_RESET 0x00000001 1498#define BGE_RDMAMODE_ENABLE 0x00000002 1499#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1500#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1501#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1502#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1503#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1504#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1505#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1506#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1507#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1508#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1509#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1510#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1511#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1512#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1513 1514/* Read DMA status register */ 1515#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1516#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1517#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1518#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1519#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1520#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1521#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1522#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1523 1524/* 1525 * Write DMA control registers 1526 */ 1527#define BGE_WDMA_MODE 0x4C00 1528#define BGE_WDMA_STATUS 0x4C04 1529 1530/* Write DMA mode register */ 1531#define BGE_WDMAMODE_RESET 0x00000001 1532#define BGE_WDMAMODE_ENABLE 0x00000002 1533#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1534#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1535#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1536#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1537#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1538#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1539#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1540#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1541#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1542#define BGE_WDMAMODE_RX_ACCEL 0x00000400 1543#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1544 1545/* Write DMA status register */ 1546#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1547#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1548#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1549#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1550#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1551#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1552#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1553#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1554 1555 1556/* 1557 * RX CPU registers 1558 */ 1559#define BGE_RXCPU_MODE 0x5000 1560#define BGE_RXCPU_STATUS 0x5004 1561#define BGE_RXCPU_PC 0x501C 1562 1563/* RX CPU mode register */ 1564#define BGE_RXCPUMODE_RESET 0x00000001 1565#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1566#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1567#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1568#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1569#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1570#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1571#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1572#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1573#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1574#define BGE_RXCPUMODE_HALTCPU 0x00000400 1575#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1576#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1577#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1578 1579/* RX CPU status register */ 1580#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1581#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1582#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1583#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1584#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1585#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1586#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1587#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1588#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1589#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1590#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1591#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1592#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1593#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1594#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1595#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1596#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1597 1598 1599/* 1600 * V? CPU registers 1601 */ 1602#define BGE_VCPU_STATUS 0x5100 1603#define BGE_VCPU_EXT_CTRL 0x6890 1604 1605#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1606#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1607 1608#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1609#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1610 1611 1612/* 1613 * TX CPU registers 1614 */ 1615#define BGE_TXCPU_MODE 0x5400 1616#define BGE_TXCPU_STATUS 0x5404 1617#define BGE_TXCPU_PC 0x541C 1618 1619/* TX CPU mode register */ 1620#define BGE_TXCPUMODE_RESET 0x00000001 1621#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1622#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1623#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1624#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1625#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1626#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1627#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1628#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1629#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1630#define BGE_TXCPUMODE_HALTCPU 0x00000400 1631#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1632#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1633 1634/* TX CPU status register */ 1635#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1636#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1637#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1638#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1639#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1640#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1641#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1642#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1643#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1644#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1645#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1646#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1647#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1648#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1649#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1650#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1651#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1652 1653 1654/* 1655 * Low priority mailbox registers 1656 */ 1657#define BGE_LPMBX_IRQ0_HI 0x5800 1658#define BGE_LPMBX_IRQ0_LO 0x5804 1659#define BGE_LPMBX_IRQ1_HI 0x5808 1660#define BGE_LPMBX_IRQ1_LO 0x580C 1661#define BGE_LPMBX_IRQ2_HI 0x5810 1662#define BGE_LPMBX_IRQ2_LO 0x5814 1663#define BGE_LPMBX_IRQ3_HI 0x5818 1664#define BGE_LPMBX_IRQ3_LO 0x581C 1665#define BGE_LPMBX_GEN0_HI 0x5820 1666#define BGE_LPMBX_GEN0_LO 0x5824 1667#define BGE_LPMBX_GEN1_HI 0x5828 1668#define BGE_LPMBX_GEN1_LO 0x582C 1669#define BGE_LPMBX_GEN2_HI 0x5830 1670#define BGE_LPMBX_GEN2_LO 0x5834 1671#define BGE_LPMBX_GEN3_HI 0x5828 1672#define BGE_LPMBX_GEN3_LO 0x582C 1673#define BGE_LPMBX_GEN4_HI 0x5840 1674#define BGE_LPMBX_GEN4_LO 0x5844 1675#define BGE_LPMBX_GEN5_HI 0x5848 1676#define BGE_LPMBX_GEN5_LO 0x584C 1677#define BGE_LPMBX_GEN6_HI 0x5850 1678#define BGE_LPMBX_GEN6_LO 0x5854 1679#define BGE_LPMBX_GEN7_HI 0x5858 1680#define BGE_LPMBX_GEN7_LO 0x585C 1681#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1682#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1683#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1684#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1685#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1686#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1687#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1688#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1689#define BGE_LPMBX_RX_CONS0_HI 0x5880 1690#define BGE_LPMBX_RX_CONS0_LO 0x5884 1691#define BGE_LPMBX_RX_CONS1_HI 0x5888 1692#define BGE_LPMBX_RX_CONS1_LO 0x588C 1693#define BGE_LPMBX_RX_CONS2_HI 0x5890 1694#define BGE_LPMBX_RX_CONS2_LO 0x5894 1695#define BGE_LPMBX_RX_CONS3_HI 0x5898 1696#define BGE_LPMBX_RX_CONS3_LO 0x589C 1697#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1698#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1699#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1700#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1701#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1702#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1703#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1704#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1705#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1706#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1707#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1708#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1709#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1710#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1711#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1712#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1713#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1714#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1715#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1716#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1717#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1718#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1719#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1720#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1721#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1722#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1723#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1724#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1725#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1726#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1727#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1728#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1729#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1730#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1731#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1732#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1733#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1734#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1735#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1736#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1737#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1738#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1739#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1740#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1741#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1742#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1743#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1744#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1745#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1746#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1747#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1748#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1749#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1750#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1751#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1752#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1753#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1754#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1755#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1756#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1757#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1758#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1759#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1760#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1761#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1762#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1763#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1764#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1765#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1766#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1767#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1768#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1769#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1770#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1771#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1772#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1773#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1774#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1775#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1776#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1777#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1778#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1779#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1780#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1781#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1782#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1783#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1784#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1785 1786/* 1787 * Flow throw Queue reset register 1788 */ 1789#define BGE_FTQ_RESET 0x5C00 1790 1791#define BGE_FTQRESET_DMAREAD 0x00000002 1792#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1793#define BGE_FTQRESET_DMADONE 0x00000010 1794#define BGE_FTQRESET_SBDC 0x00000020 1795#define BGE_FTQRESET_SDI 0x00000040 1796#define BGE_FTQRESET_WDMA 0x00000080 1797#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1798#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1799#define BGE_FTQRESET_SDC 0x00000400 1800#define BGE_FTQRESET_HCC 0x00000800 1801#define BGE_FTQRESET_TXFIFO 0x00001000 1802#define BGE_FTQRESET_MBC 0x00002000 1803#define BGE_FTQRESET_RBDC 0x00004000 1804#define BGE_FTQRESET_RXLP 0x00008000 1805#define BGE_FTQRESET_RDBDI 0x00010000 1806#define BGE_FTQRESET_RDC 0x00020000 1807#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1808 1809/* 1810 * Message Signaled Interrupt registers 1811 */ 1812#define BGE_MSI_MODE 0x6000 1813#define BGE_MSI_STATUS 0x6004 1814#define BGE_MSI_FIFOACCESS 0x6008 1815 1816/* MSI mode register */ 1817#define BGE_MSIMODE_RESET 0x00000001 1818#define BGE_MSIMODE_ENABLE 0x00000002 1819#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1820#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1821#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1822#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1823#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1824 1825/* MSI status register */ 1826#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1827#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1828#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1829#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1830#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1831 1832 1833/* 1834 * DMA Completion registers 1835 */ 1836#define BGE_DMAC_MODE 0x6400 1837 1838/* DMA Completion mode register */ 1839#define BGE_DMACMODE_RESET 0x00000001 1840#define BGE_DMACMODE_ENABLE 0x00000002 1841 1842 1843/* 1844 * General control registers. 1845 */ 1846#define BGE_MODE_CTL 0x6800 1847#define BGE_MISC_CFG 0x6804 1848#define BGE_MISC_LOCAL_CTL 0x6808 1849#define BGE_CPU_EVENT 0x6810 1850#define BGE_EE_ADDR 0x6838 1851#define BGE_EE_DATA 0x683C 1852#define BGE_EE_CTL 0x6840 1853#define BGE_MDI_CTL 0x6844 1854#define BGE_EE_DELAY 0x6848 1855 1856#define BGE_FASTBOOT_PC 0x6894 1857 1858/* 1859 * NVRAM Control registers 1860 */ 1861 1862#define BGE_NVRAM_CMD 0x7000 1863#define BGE_NVRAM_STAT 0x7004 1864#define BGE_NVRAM_WRDATA 0x7008 1865#define BGE_NVRAM_ADDR 0x700c 1866#define BGE_NVRAM_RDDATA 0x7010 1867#define BGE_NVRAM_CFG1 0x7014 1868#define BGE_NVRAM_CFG2 0x7018 1869#define BGE_NVRAM_CFG3 0x701c 1870#define BGE_NVRAM_SWARB 0x7020 1871#define BGE_NVRAM_ACCESS 0x7024 1872#define BGE_NVRAM_WRITE1 0x7028 1873 1874 1875#define BGE_NVRAMCMD_RESET 0x00000001 1876#define BGE_NVRAMCMD_DONE 0x00000008 1877#define BGE_NVRAMCMD_START 0x00000010 1878#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1879#define BGE_NVRAMCMD_ERASE 0x00000040 1880#define BGE_NVRAMCMD_FIRST 0x00000080 1881#define BGE_NVRAMCMD_LAST 0x00000100 1882 1883#define BGE_NVRAM_READCMD \ 1884 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1885 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1886#define BGE_NVRAM_WRITECMD \ 1887 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1888 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1889 1890#define BGE_NVRAMSWARB_SET0 0x00000001 1891#define BGE_NVRAMSWARB_SET1 0x00000002 1892#define BGE_NVRAMSWARB_SET2 0x00000003 1893#define BGE_NVRAMSWARB_SET3 0x00000004 1894#define BGE_NVRAMSWARB_CLR0 0x00000010 1895#define BGE_NVRAMSWARB_CLR1 0x00000020 1896#define BGE_NVRAMSWARB_CLR2 0x00000040 1897#define BGE_NVRAMSWARB_CLR3 0x00000080 1898#define BGE_NVRAMSWARB_GNT0 0x00000100 1899#define BGE_NVRAMSWARB_GNT1 0x00000200 1900#define BGE_NVRAMSWARB_GNT2 0x00000400 1901#define BGE_NVRAMSWARB_GNT3 0x00000800 1902#define BGE_NVRAMSWARB_REQ0 0x00001000 1903#define BGE_NVRAMSWARB_REQ1 0x00002000 1904#define BGE_NVRAMSWARB_REQ2 0x00004000 1905#define BGE_NVRAMSWARB_REQ3 0x00008000 1906 1907#define BGE_NVRAMACC_ENABLE 0x00000001 1908#define BGE_NVRAMACC_WRENABLE 0x00000002 1909 1910/* 1911 * TLP Control Register 1912 * Applicable to BCM5721 and BCM5751 only 1913 */ 1914#define BGE_TLP_CONTROL_REG 0x7c00 1915#define BGE_TLP_DATA_FIFO_PROTECT 0x02000000 1916 1917/* 1918 * PHY Test Control Register 1919 * Applicable to BCM5721 and BCM5751 only 1920 */ 1921#define BGE_PHY_TEST_CTRL_REG 0x7e2c 1922#define BGE_PHY_PCIE_SCRAM_MODE 0x0020 1923#define BGE_PHY_PCIE_LTASS_MODE 0x0040 1924 1925/* Mode control register */ 1926#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1927#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1928#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1929#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1930#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1931#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1932#define BGE_MODECTL_NO_RX_CRC 0x00000400 1933#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1934#define BGE_MODECTL_NO_TX_INTR 0x00002000 1935#define BGE_MODECTL_NO_RX_INTR 0x00004000 1936#define BGE_MODECTL_FORCE_PCI32 0x00008000 1937#define BGE_MODECTL_STACKUP 0x00010000 1938#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1939#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1940#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1941#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1942#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1943#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1944#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1945#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1946#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1947#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1948 1949/* Misc. config register */ 1950#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1951#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1952#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1953#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1954#define BGE_MISCCFG_BOARD_ID_MASK 0x0001e000 1955#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1956#define BGE_MISCCFG_KEEP_GPHY_POWER 0x04000000 1957 1958#define BGE_32BITTIME_66MHZ (0x41 << 1) 1959 1960/* Misc. Local Control */ 1961#define BGE_MLC_INTR_STATE 0x00000001 1962#define BGE_MLC_INTR_CLR 0x00000002 1963#define BGE_MLC_INTR_SET 0x00000004 1964#define BGE_MLC_INTR_ONATTN 0x00000008 1965#define BGE_MLC_MISCIO_IN0 0x00000100 1966#define BGE_MLC_MISCIO_IN1 0x00000200 1967#define BGE_MLC_MISCIO_IN2 0x00000400 1968#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1969#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1970#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1971#define BGE_MLC_MISCIO_OUT0 0x00004000 1972#define BGE_MLC_MISCIO_OUT1 0x00008000 1973#define BGE_MLC_MISCIO_OUT2 0x00010000 1974#define BGE_MLC_EXTRAM_ENB 0x00020000 1975#define BGE_MLC_SRAM_SIZE 0x001C0000 1976#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1977#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1978#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1979#define BGE_MLC_AUTO_EEPROM 0x01000000 1980 1981#define BGE_SSRAMSIZE_256KB 0x00000000 1982#define BGE_SSRAMSIZE_512KB 0x00040000 1983#define BGE_SSRAMSIZE_1MB 0x00080000 1984#define BGE_SSRAMSIZE_2MB 0x000C0000 1985#define BGE_SSRAMSIZE_4MB 0x00100000 1986#define BGE_SSRAMSIZE_8MB 0x00140000 1987#define BGE_SSRAMSIZE_16M 0x00180000 1988 1989/* EEPROM address register */ 1990#define BGE_EEADDR_ADDRESS 0x0000FFFC 1991#define BGE_EEADDR_HALFCLK 0x01FF0000 1992#define BGE_EEADDR_START 0x02000000 1993#define BGE_EEADDR_DEVID 0x1C000000 1994#define BGE_EEADDR_RESET 0x20000000 1995#define BGE_EEADDR_DONE 0x40000000 1996#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1997 1998#define BGE_EEDEVID(x) ((x & 7) << 26) 1999#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2000#define BGE_HALFCLK_384SCL 0x60 2001#define BGE_EE_READCMD \ 2002 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2003 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 2004#define BGE_EE_WRCMD \ 2005 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2006 BGE_EEADDR_START|BGE_EEADDR_DONE) 2007 2008/* EEPROM Control register */ 2009#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2010#define BGE_EECTL_CLKOUT 0x00000002 2011#define BGE_EECTL_CLKIN 0x00000004 2012#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2013#define BGE_EECTL_DATAOUT 0x00000010 2014#define BGE_EECTL_DATAIN 0x00000020 2015 2016/* MDI (MII/GMII) access register */ 2017#define BGE_MDI_DATA 0x00000001 2018#define BGE_MDI_DIR 0x00000002 2019#define BGE_MDI_SEL 0x00000004 2020#define BGE_MDI_CLK 0x00000008 2021 2022#define BGE_MEMWIN_START 0x00008000 2023#define BGE_MEMWIN_END 0x0000FFFF 2024 2025 2026#define BGE_MEMWIN_READ(pc, tag, x, val) \ 2027 do { \ 2028 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 2029 (0xFFFF0000 & x)); \ 2030 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 2031 } while(0) 2032 2033#define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 2034 do { \ 2035 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 2036 (0xFFFF0000 & x)); \ 2037 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 2038 } while(0) 2039 2040/* 2041 * This magic number is written to the firmware mailbox at 0xb50 2042 * before a software reset is issued. After the internal firmware 2043 * has completed its initialization it will write the opposite of 2044 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 2045 * driver to synchronize with the firmware. 2046 */ 2047#define BGE_MAGIC_NUMBER 0x4B657654 2048 2049typedef struct { 2050 u_int32_t bge_addr_hi; 2051 u_int32_t bge_addr_lo; 2052} bge_hostaddr; 2053#define BGE_HOSTADDR(x,y) \ 2054 do { \ 2055 (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 2056 if (sizeof(bus_addr_t) == 8) \ 2057 (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 2058 else \ 2059 (x).bge_addr_hi = 0; \ 2060 } while(0) 2061 2062/* Ring control block structure */ 2063struct bge_rcb { 2064 bge_hostaddr bge_hostaddr; 2065 u_int32_t bge_maxlen_flags; 2066 u_int32_t bge_nicaddr; 2067}; 2068 2069#define RCB_WRITE_4(sc, rcb, offset, val) \ 2070 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 2071 rcb + offsetof(struct bge_rcb, offset), val) 2072 2073#define RCB_WRITE_2(sc, rcb, offset, val) \ 2074 bus_space_write_2(sc->bge_btag, sc->bge_bhandle, \ 2075 rcb + offsetof(struct bge_rcb, offset), val) 2076 2077#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 2078 2079#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2080#define BGE_RCB_FLAG_RING_DISABLED 0x0002 2081 2082struct bge_tx_bd { 2083 bge_hostaddr bge_addr; 2084#if BYTE_ORDER == LITTLE_ENDIAN 2085 u_int16_t bge_flags; 2086 u_int16_t bge_len; 2087 u_int16_t bge_vlan_tag; 2088 u_int16_t bge_rsvd; 2089#else 2090 u_int16_t bge_len; 2091 u_int16_t bge_flags; 2092 u_int16_t bge_rsvd; 2093 u_int16_t bge_vlan_tag; 2094#endif 2095}; 2096 2097#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2098#define BGE_TXBDFLAG_IP_CSUM 0x0002 2099#define BGE_TXBDFLAG_END 0x0004 2100#define BGE_TXBDFLAG_IP_FRAG 0x0008 2101#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2102#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2103#define BGE_TXBDFLAG_COAL_NOW 0x0080 2104#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2105#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2106#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2107#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2108#define BGE_TXBDFLAG_NO_CRC 0x8000 2109 2110#define BGE_NIC_TXRING_ADDR(ringno, size) \ 2111 BGE_SEND_RING_1_TO_4 + \ 2112 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2113 2114struct bge_rx_bd { 2115 bge_hostaddr bge_addr; 2116#if BYTE_ORDER == LITTLE_ENDIAN 2117 u_int16_t bge_len; 2118 u_int16_t bge_idx; 2119 u_int16_t bge_flags; 2120 u_int16_t bge_type; 2121 u_int16_t bge_tcp_udp_csum; 2122 u_int16_t bge_ip_csum; 2123 u_int16_t bge_vlan_tag; 2124 u_int16_t bge_error_flag; 2125#else 2126 u_int16_t bge_idx; 2127 u_int16_t bge_len; 2128 u_int16_t bge_type; 2129 u_int16_t bge_flags; 2130 u_int16_t bge_ip_csum; 2131 u_int16_t bge_tcp_udp_csum; 2132 u_int16_t bge_error_flag; 2133 u_int16_t bge_vlan_tag; 2134#endif 2135 u_int32_t bge_rsvd; 2136 u_int32_t bge_opaque; 2137}; 2138 2139struct bge_ext_rx_bd { 2140 bge_hostaddr bge_addr1; 2141 bge_hostaddr bge_addr2; 2142 bge_hostaddr bge_addr3; 2143#if BYTE_ORDER == LITTLE_ENDIAN 2144 u_int16_t bge_len2; 2145 u_int16_t bge_len1; 2146 u_int16_t bge_rsvd; 2147 u_int16_t bge_len3; 2148#else 2149 u_int16_t bge_len1; 2150 u_int16_t bge_len2; 2151 u_int16_t bge_len3; 2152 u_int16_t bge_rsvd; 2153#endif 2154 struct bge_rx_bd bge_bd; 2155}; 2156 2157#define BGE_RXBDFLAG_END 0x0004 2158#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2159#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2160#define BGE_RXBDFLAG_ERROR 0x0400 2161#define BGE_RXBDFLAG_MINI_RING 0x0800 2162#define BGE_RXBDFLAG_IP_CSUM 0x1000 2163#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2164#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2165 2166#define BGE_RXERRFLAG_BAD_CRC 0x0001 2167#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2168#define BGE_RXERRFLAG_LINK_LOST 0x0004 2169#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2170#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2171#define BGE_RXERRFLAG_RUNT 0x0020 2172#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2173#define BGE_RXERRFLAG_GIANT 0x0080 2174 2175struct bge_sts_idx { 2176#if BYTE_ORDER == LITTLE_ENDIAN 2177 u_int16_t bge_rx_prod_idx; 2178 u_int16_t bge_tx_cons_idx; 2179#else 2180 u_int16_t bge_tx_cons_idx; 2181 u_int16_t bge_rx_prod_idx; 2182#endif 2183}; 2184 2185struct bge_status_block { 2186 u_int32_t bge_status; 2187 u_int32_t bge_rsvd0; 2188#if BYTE_ORDER == LITTLE_ENDIAN 2189 u_int16_t bge_rx_jumbo_cons_idx; 2190 u_int16_t bge_rx_std_cons_idx; 2191 u_int16_t bge_rx_mini_cons_idx; 2192 u_int16_t bge_rsvd1; 2193#else 2194 u_int16_t bge_rx_std_cons_idx; 2195 u_int16_t bge_rx_jumbo_cons_idx; 2196 u_int16_t bge_rsvd1; 2197 u_int16_t bge_rx_mini_cons_idx; 2198#endif 2199 struct bge_sts_idx bge_idx[16]; 2200}; 2201 2202#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 2203#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 2204 2205#define BGE_STATFLAG_UPDATED 0x00000001 2206#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2207#define BGE_STATFLAG_ERROR 0x00000004 2208 2209/* 2210 * SysKonnect Subsystem IDs 2211 */ 2212#define SK_SUBSYSID_9D41 0x4441 2213 2214/* 2215 * Dell PCI vendor ID 2216 */ 2217#define DELL_VENDORID 0x1028 2218 2219/* 2220 * Offset of MAC address inside EEPROM. 2221 */ 2222#define BGE_EE_MAC_OFFSET 0x7C 2223#define BGE_EE_MAC_OFFSET_5906 0x10 2224#define BGE_EE_HWCFG_OFFSET 0xC8 2225 2226#define BGE_HWCFG_VOLTAGE 0x00000003 2227#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2228#define BGE_HWCFG_MEDIA 0x00000030 2229#define BGE_HWCFG_ASF 0x00000080 2230 2231#define BGE_VOLTAGE_1POINT3 0x00000000 2232#define BGE_VOLTAGE_1POINT8 0x00000001 2233 2234#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2235#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2236#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2237 2238#define BGE_MEDIA_UNSPEC 0x00000000 2239#define BGE_MEDIA_COPPER 0x00000010 2240#define BGE_MEDIA_FIBER 0x00000020 2241 2242#define BGE_TICKS_PER_SEC 1000000 2243 2244/* 2245 * Ring size constants. 2246 */ 2247#define BGE_EVENT_RING_CNT 256 2248#define BGE_CMD_RING_CNT 64 2249#define BGE_STD_RX_RING_CNT 512 2250#define BGE_JUMBO_RX_RING_CNT 256 2251#define BGE_MINI_RX_RING_CNT 1024 2252#define BGE_RETURN_RING_CNT 1024 2253 2254/* 5705 has smaller return ring size */ 2255#define BGE_RETURN_RING_CNT_5705 512 2256 2257/* 2258 * Possible TX ring sizes. 2259 */ 2260#define BGE_TX_RING_CNT_128 128 2261#define BGE_TX_RING_BASE_128 0x3800 2262 2263#define BGE_TX_RING_CNT_256 256 2264#define BGE_TX_RING_BASE_256 0x3000 2265 2266#define BGE_TX_RING_CNT_512 512 2267#define BGE_TX_RING_BASE_512 0x2000 2268 2269#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2270#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2271 2272/* 2273 * Tigon III statistics counters. 2274 */ 2275/* Statistics maintained MAC Receive block. */ 2276struct bge_rx_mac_stats { 2277 bge_hostaddr ifHCInOctets; 2278 bge_hostaddr Reserved1; 2279 bge_hostaddr etherStatsFragments; 2280 bge_hostaddr ifHCInUcastPkts; 2281 bge_hostaddr ifHCInMulticastPkts; 2282 bge_hostaddr ifHCInBroadcastPkts; 2283 bge_hostaddr dot3StatsFCSErrors; 2284 bge_hostaddr dot3StatsAlignmentErrors; 2285 bge_hostaddr xonPauseFramesReceived; 2286 bge_hostaddr xoffPauseFramesReceived; 2287 bge_hostaddr macControlFramesReceived; 2288 bge_hostaddr xoffStateEntered; 2289 bge_hostaddr dot3StatsFramesTooLong; 2290 bge_hostaddr etherStatsJabbers; 2291 bge_hostaddr etherStatsUndersizePkts; 2292 bge_hostaddr inRangeLengthError; 2293 bge_hostaddr outRangeLengthError; 2294 bge_hostaddr etherStatsPkts64Octets; 2295 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2296 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2297 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2298 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2299 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2300 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2301 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2302 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2303 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2304}; 2305 2306/* Statistics maintained MAC Transmit block. */ 2307struct bge_tx_mac_stats { 2308 bge_hostaddr ifHCOutOctets; 2309 bge_hostaddr Reserved2; 2310 bge_hostaddr etherStatsCollisions; 2311 bge_hostaddr outXonSent; 2312 bge_hostaddr outXoffSent; 2313 bge_hostaddr flowControlDone; 2314 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2315 bge_hostaddr dot3StatsSingleCollisionFrames; 2316 bge_hostaddr dot3StatsMultipleCollisionFrames; 2317 bge_hostaddr dot3StatsDeferredTransmissions; 2318 bge_hostaddr Reserved3; 2319 bge_hostaddr dot3StatsExcessiveCollisions; 2320 bge_hostaddr dot3StatsLateCollisions; 2321 bge_hostaddr dot3Collided2Times; 2322 bge_hostaddr dot3Collided3Times; 2323 bge_hostaddr dot3Collided4Times; 2324 bge_hostaddr dot3Collided5Times; 2325 bge_hostaddr dot3Collided6Times; 2326 bge_hostaddr dot3Collided7Times; 2327 bge_hostaddr dot3Collided8Times; 2328 bge_hostaddr dot3Collided9Times; 2329 bge_hostaddr dot3Collided10Times; 2330 bge_hostaddr dot3Collided11Times; 2331 bge_hostaddr dot3Collided12Times; 2332 bge_hostaddr dot3Collided13Times; 2333 bge_hostaddr dot3Collided14Times; 2334 bge_hostaddr dot3Collided15Times; 2335 bge_hostaddr ifHCOutUcastPkts; 2336 bge_hostaddr ifHCOutMulticastPkts; 2337 bge_hostaddr ifHCOutBroadcastPkts; 2338 bge_hostaddr dot3StatsCarrierSenseErrors; 2339 bge_hostaddr ifOutDiscards; 2340 bge_hostaddr ifOutErrors; 2341}; 2342 2343/* Stats counters access through registers */ 2344struct bge_mac_stats_regs { 2345 u_int32_t ifHCOutOctets; 2346 u_int32_t Reserved0; 2347 u_int32_t etherStatsCollisions; 2348 u_int32_t outXonSent; 2349 u_int32_t outXoffSent; 2350 u_int32_t Reserved1; 2351 u_int32_t dot3StatsInternalMacTransmitErrors; 2352 u_int32_t dot3StatsSingleCollisionFrames; 2353 u_int32_t dot3StatsMultipleCollisionFrames; 2354 u_int32_t dot3StatsDeferredTransmissions; 2355 u_int32_t Reserved2; 2356 u_int32_t dot3StatsExcessiveCollisions; 2357 u_int32_t dot3StatsLateCollisions; 2358 u_int32_t Reserved3[14]; 2359 u_int32_t ifHCOutUcastPkts; 2360 u_int32_t ifHCOutMulticastPkts; 2361 u_int32_t ifHCOutBroadcastPkts; 2362 u_int32_t Reserved4[2]; 2363 u_int32_t ifHCInOctets; 2364 u_int32_t Reserved5; 2365 u_int32_t etherStatsFragments; 2366 u_int32_t ifHCInUcastPkts; 2367 u_int32_t ifHCInMulticastPkts; 2368 u_int32_t ifHCInBroadcastPkts; 2369 u_int32_t dot3StatsFCSErrors; 2370 u_int32_t dot3StatsAlignmentErrors; 2371 u_int32_t xonPauseFramesReceived; 2372 u_int32_t xoffPauseFramesReceived; 2373 u_int32_t macControlFramesReceived; 2374 u_int32_t xoffStateEntered; 2375 u_int32_t dot3StatsFramesTooLong; 2376 u_int32_t etherStatsJabbers; 2377 u_int32_t etherStatsUndersizePkts; 2378}; 2379 2380struct bge_stats { 2381 u_int8_t Reserved0[256]; 2382 2383 /* Statistics maintained by Receive MAC. */ 2384 struct bge_rx_mac_stats rxstats; 2385 2386 bge_hostaddr Unused1[37]; 2387 2388 /* Statistics maintained by Transmit MAC. */ 2389 struct bge_tx_mac_stats txstats; 2390 2391 bge_hostaddr Unused2[31]; 2392 2393 /* Statistics maintained by Receive List Placement. */ 2394 bge_hostaddr COSIfHCInPkts[16]; 2395 bge_hostaddr COSFramesDroppedDueToFilters; 2396 bge_hostaddr nicDmaWriteQueueFull; 2397 bge_hostaddr nicDmaWriteHighPriQueueFull; 2398 bge_hostaddr nicNoMoreRxBDs; 2399 bge_hostaddr ifInDiscards; 2400 bge_hostaddr ifInErrors; 2401 bge_hostaddr nicRecvThresholdHit; 2402 2403 bge_hostaddr Unused3[9]; 2404 2405 /* Statistics maintained by Send Data Initiator. */ 2406 bge_hostaddr COSIfHCOutPkts[16]; 2407 bge_hostaddr nicDmaReadQueueFull; 2408 bge_hostaddr nicDmaReadHighPriQueueFull; 2409 bge_hostaddr nicSendDataCompQueueFull; 2410 2411 /* Statistics maintained by Host Coalescing. */ 2412 bge_hostaddr nicRingSetSendProdIndex; 2413 bge_hostaddr nicRingStatusUpdate; 2414 bge_hostaddr nicInterrupts; 2415 bge_hostaddr nicAvoidedInterrupts; 2416 bge_hostaddr nicSendThresholdHit; 2417 2418 u_int8_t Reserved4[320]; 2419}; 2420 2421/* 2422 * Tigon general information block. This resides in host memory 2423 * and contains the status counters, ring control blocks and 2424 * producer pointers. 2425 */ 2426 2427struct bge_gib { 2428 struct bge_stats bge_stats; 2429 struct bge_rcb bge_tx_rcb[16]; 2430 struct bge_rcb bge_std_rx_rcb; 2431 struct bge_rcb bge_jumbo_rx_rcb; 2432 struct bge_rcb bge_mini_rx_rcb; 2433 struct bge_rcb bge_return_rcb; 2434}; 2435 2436/* 2437 * NOTE! On the Alpha, we have an alignment constraint. 2438 * The first thing in the packet is a 14-byte Ethernet header. 2439 * This means that the packet is misaligned. To compensate, 2440 * we actually offset the data 2 bytes into the cluster. This 2441 * alignes the packet after the Ethernet header at a 32-bit 2442 * boundary. 2443 */ 2444 2445#define BGE_JUMBO_FRAMELEN 9022 2446#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 2447#define BGE_PAGE_SIZE PAGE_SIZE 2448 2449/* 2450 * Other utility macros. 2451 */ 2452#define BGE_INC(x, y) (x) = (x + 1) % y 2453 2454/* 2455 * Vital product data and structures. 2456 */ 2457#define BGE_VPD_FLAG 0x8000 2458 2459#define VPD_RES_ID 0x82 /* ID string */ 2460#define VPD_RES_READ 0x90 /* start of read only area */ 2461#define VPD_RES_WRITE 0x81 /* start of read/write area */ 2462#define VPD_RES_END 0x78 /* end tag */ 2463 2464/* 2465 * Register access macros. The Tigon always uses memory mapped register 2466 * accesses and all registers must be accessed with 32 bit operations. 2467 */ 2468 2469#define CSR_WRITE_4(sc, reg, val) \ 2470 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2471 2472#define CSR_READ_4(sc, reg) \ 2473 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2474 2475#define BGE_SETBIT(sc, reg, x) \ 2476 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2477#define BGE_CLRBIT(sc, reg, x) \ 2478 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2479 2480#define PCI_SETBIT(pc, tag, reg, x) \ 2481 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 2482#define PCI_CLRBIT(pc, tag, reg, x) \ 2483 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 2484 2485/* 2486 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2487 * values are tuneable. They control the actual amount of buffers 2488 * allocated for the standard, mini and jumbo receive rings. 2489 */ 2490 2491#define BGE_SSLOTS 256 2492#define BGE_MSLOTS 256 2493#define BGE_JSLOTS 384 2494 2495#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2496#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2497 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2498 2499/* 2500 * Ring structures. Most of these reside in host memory and we tell 2501 * the NIC where they are via the ring control blocks. The exceptions 2502 * are the tx and command rings, which live in NIC memory and which 2503 * we access via the shared memory window. 2504 */ 2505struct bge_ring_data { 2506 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2507 struct bge_ext_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2508 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2509 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2510 struct bge_status_block bge_status_block; 2511 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2512 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2513 struct bge_gib bge_info; 2514}; 2515 2516#define BGE_RING_DMA_ADDR(sc, offset) \ 2517 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2518 offsetof(struct bge_ring_data, offset)) 2519 2520/* 2521 * Number of DMA segments in a TxCB. Note that this is carefully 2522 * chosen to make the total struct size an even power of two. It's 2523 * critical that no TxCB be split across a page boundary since 2524 * no attempt is made to allocate physically contiguous memory. 2525 * 2526 */ 2527#ifdef __LP64__ 2528#define BGE_NTXSEG 30 2529#else 2530#define BGE_NTXSEG 31 2531#endif 2532 2533/* 2534 * Mbuf pointers. We need these to keep track of the virtual addresses 2535 * of our mbuf chains since we can only convert from physical to virtual, 2536 * not the other way around. 2537 */ 2538struct bge_chain_data { 2539 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2540 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2541 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2542 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2543 bus_dmamap_t bge_tx_map[BGE_TX_RING_CNT]; 2544 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2545 bus_dmamap_t bge_rx_jumbo_map[BGE_JUMBO_RX_RING_CNT]; 2546}; 2547 2548struct bge_type { 2549 u_int16_t bge_vid; 2550 u_int16_t bge_did; 2551 char *bge_name; 2552}; 2553 2554#define BGE_TIMEOUT 100000 2555#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2556 2557struct txdmamap_pool_entry { 2558 bus_dmamap_t dmamap; 2559 SLIST_ENTRY(txdmamap_pool_entry) link; 2560}; 2561 2562#define ASF_ENABLE 1 2563#define ASF_NEW_HANDSHAKE 2 2564#define ASF_STACKUP 4 2565 2566struct bge_softc { 2567 struct device bge_dev; 2568 struct arpcom arpcom; /* interface info */ 2569 bus_space_handle_t bge_bhandle; 2570 bus_space_tag_t bge_btag; 2571 void *bge_intrhand; 2572 struct pci_attach_args bge_pa; 2573 struct mii_data bge_mii; 2574 struct ifmedia bge_ifmedia; /* media info */ 2575 u_int32_t bge_flags; 2576#define BGE_TXRING_VALID 0x00000001 2577#define BGE_RXRING_VALID 0x00000002 2578#define BGE_JUMBO_RXRING_VALID 0x00000004 2579#define BGE_RX_ALIGNBUG 0x00000008 2580#define BGE_NO_3LED 0x00000010 2581#define BGE_PCIX 0x00000020 2582#define BGE_PCIE 0x00000040 2583#define BGE_ASF_MODE 0x00000080 2584#define BGE_NO_EEPROM 0x00000100 2585#define BGE_JUMBO_CAPABLE 0x00000200 2586#define BGE_10_100_ONLY 0x00000400 2587#define BGE_PHY_FIBER_TBI 0x00000800 2588#define BGE_PHY_FIBER_MII 0x00001000 2589#define BGE_PHY_CRC_BUG 0x00002000 2590#define BGE_PHY_ADC_BUG 0x00004000 2591#define BGE_PHY_5704_A0_BUG 0x00008000 2592#define BGE_PHY_JITTER_BUG 0x00010000 2593#define BGE_PHY_BER_BUG 0x00020000 2594#define BGE_PHY_ADJUST_TRIM 0x00040000 2595#define BGE_NO_ETH_WIRE_SPEED 0x00080000 2596#define BGE_IS_5788 0x00100000 2597#define BGE_5705_PLUS 0x00200000 2598#define BGE_5750_PLUS 0x00400000 2599#define BGE_5755_PLUS 0x00800000 2600#define BGE_5714_FAMILY 0x01000000 2601#define BGE_5700_FAMILY 0x02000000 2602 2603 bus_dma_tag_t bge_dmatag; 2604 u_int32_t bge_chipid; 2605 struct bge_ring_data *bge_rdata; /* rings */ 2606 struct bge_chain_data bge_cdata; /* mbufs */ 2607 bus_dmamap_t bge_ring_map; 2608 u_int16_t bge_tx_saved_considx; 2609 u_int16_t bge_rx_saved_considx; 2610 u_int16_t bge_ev_saved_considx; 2611 u_int16_t bge_return_ring_cnt; 2612 u_int32_t bge_tx_prodidx; 2613 u_int16_t bge_std; /* current std ring head */ 2614 int bge_std_cnt; 2615 u_int16_t bge_jumbo; /* current jumo ring head */ 2616 int bge_jumbo_cnt; 2617 u_int32_t bge_stat_ticks; 2618 u_int32_t bge_rx_coal_ticks; 2619 u_int32_t bge_tx_coal_ticks; 2620 u_int32_t bge_rx_max_coal_bds; 2621 u_int32_t bge_tx_max_coal_bds; 2622 u_int32_t bge_tx_buf_ratio; 2623 u_int32_t bge_sts; 2624#define BGE_STS_LINK 0x00000001 /* MAC link status */ 2625#define BGE_STS_LINK_EVT 0x00000002 /* pending link event */ 2626#define BGE_STS_AUTOPOLL 0x00000004 /* PHY auto-polling */ 2627#define BGE_STS_BIT(sc, x) ((sc)->bge_sts & (x)) 2628#define BGE_STS_SETBIT(sc, x) ((sc)->bge_sts |= (x)) 2629#define BGE_STS_CLRBIT(sc, x) ((sc)->bge_sts &= ~(x)) 2630 int bge_flowflags; 2631 int bge_txcnt; 2632 struct timeout bge_timeout; 2633 struct timeout bge_rxtimeout; 2634 void *sc_powerhook; 2635 void *sc_shutdownhook; 2636 u_int32_t bge_rx_discards; 2637 u_int32_t bge_tx_discards; 2638 u_int32_t bge_rx_inerrors; 2639 u_int32_t bge_rx_overruns; 2640 u_int32_t bge_tx_collisions; 2641 SLIST_HEAD(, txdmamap_pool_entry) txdma_list; 2642 struct txdmamap_pool_entry *txdma[BGE_TX_RING_CNT]; 2643}; 2644