if_bgereg.h revision 1.93
1/* $OpenBSD: if_bgereg.h,v 1.93 2009/06/02 03:58:17 naddy Exp $ */ 2 3/* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bgereg.h,v 1.11 2002/11/14 23:54:50 sam Exp $ 36 */ 37 38/* 39 * BCM570x memory map. The internal memory layout varies somewhat 40 * depending on whether or not we have external SSRAM attached. 41 * The BCM5700 can have up to 16MB of external memory. The BCM5701 42 * is apparently not designed to use external SSRAM. The mappings 43 * up to the first 4 send rings are the same for both internal and 44 * external memory configurations. Note that mini RX ring space is 45 * only available with external SSRAM configurations, which means 46 * the mini RX ring is not supported on the BCM5701. 47 * 48 * The NIC's memory can be accessed by the host in one of 3 ways: 49 * 50 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 51 * registers in PCI config space can be used to read any 32-bit 52 * address within the NIC's memory. 53 * 54 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 55 * space can be used in conjunction with the memory window in the 56 * device register space at offset 0x8000 to read any 32K chunk 57 * of NIC memory. 58 * 59 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 60 * set, the device I/O mapping consumes 32MB of host address space, 61 * allowing all of the registers and internal NIC memory to be 62 * accessed directly. NIC memory addresses are offset by 0x01000000. 63 * Flat mode consumes so much host address space that it is not 64 * recommended. 65 */ 66#define BGE_PAGE_ZERO 0x00000000 67#define BGE_PAGE_ZERO_END 0x000000FF 68#define BGE_SEND_RING_RCB 0x00000100 69#define BGE_SEND_RING_RCB_END 0x000001FF 70#define BGE_RX_RETURN_RING_RCB 0x00000200 71#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 72#define BGE_STATS_BLOCK 0x00000300 73#define BGE_STATS_BLOCK_END 0x00000AFF 74#define BGE_STATUS_BLOCK 0x00000B00 75#define BGE_STATUS_BLOCK_END 0x00000B4F 76#define BGE_SOFTWARE_GENCOMM 0x00000B50 77#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 78#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 79#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 80#define BGE_FW_PAUSE 0x00000002 81#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 82#define BGE_UNMAPPED 0x00001000 83#define BGE_UNMAPPED_END 0x00001FFF 84#define BGE_DMA_DESCRIPTORS 0x00002000 85#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 86#define BGE_SEND_RING_1_TO_4 0x00004000 87#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 88 89/* Mappings for internal memory configuration */ 90#define BGE_STD_RX_RINGS 0x00006000 91#define BGE_STD_RX_RINGS_END 0x00006FFF 92#define BGE_JUMBO_RX_RINGS 0x00007000 93#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 94#define BGE_BUFFPOOL_1 0x00008000 95#define BGE_BUFFPOOL_1_END 0x0000FFFF 96#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 97#define BGE_BUFFPOOL_2_END 0x00017FFF 98#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 99#define BGE_BUFFPOOL_3_END 0x0001FFFF 100 101/* Mappings for external SSRAM configurations */ 102#define BGE_SEND_RING_5_TO_6 0x00006000 103#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 104#define BGE_SEND_RING_7_TO_8 0x00007000 105#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 106#define BGE_SEND_RING_9_TO_16 0x00008000 107#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 108#define BGE_EXT_STD_RX_RINGS 0x0000C000 109#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 110#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 111#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 112#define BGE_MINI_RX_RINGS 0x0000E000 113#define BGE_MINI_RX_RINGS_END 0x0000FFFF 114#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 115#define BGE_AVAIL_REGION1_END 0x00017FFF 116#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 117#define BGE_AVAIL_REGION2_END 0x0001FFFF 118#define BGE_EXT_SSRAM 0x00020000 119#define BGE_EXT_SSRAM_END 0x000FFFFF 120 121 122/* 123 * BCM570x register offsets. These are memory mapped registers 124 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 125 * Each register must be accessed using 32 bit operations. 126 * 127 * All registers are accessed through a 32K shared memory block. 128 * The first group of registers are actually copies of the PCI 129 * configuration space registers. 130 */ 131 132/* 133 * PCI registers defined in the PCI 2.2 spec. 134 */ 135#define BGE_PCI_VID 0x00 136#define BGE_PCI_DID 0x02 137#define BGE_PCI_CMD 0x04 138#define BGE_PCI_STS 0x06 139#define BGE_PCI_REV 0x08 140#define BGE_PCI_CLASS 0x09 141#define BGE_PCI_CACHESZ 0x0C 142#define BGE_PCI_LATTIMER 0x0D 143#define BGE_PCI_HDRTYPE 0x0E 144#define BGE_PCI_BIST 0x0F 145#define BGE_PCI_BAR0 0x10 146#define BGE_PCI_BAR1 0x14 147#define BGE_PCI_SUBSYS 0x2C 148#define BGE_PCI_SUBVID 0x2E 149#define BGE_PCI_ROMBASE 0x30 150#define BGE_PCI_CAPPTR 0x34 151#define BGE_PCI_INTLINE 0x3C 152#define BGE_PCI_INTPIN 0x3D 153#define BGE_PCI_MINGNT 0x3E 154#define BGE_PCI_MAXLAT 0x3F 155#define BGE_PCI_PCIXCAP 0x40 156#define BGE_PCI_NEXTPTR_PM 0x41 157#define BGE_PCI_PCIX_CMD 0x42 158#define BGE_PCI_PCIX_STS 0x44 159#define BGE_PCI_PWRMGMT_CAPID 0x48 160#define BGE_PCI_NEXTPTR_VPD 0x49 161#define BGE_PCI_PWRMGMT_CAPS 0x4A 162#define BGE_PCI_PWRMGMT_CMD 0x4C 163#define BGE_PCI_PWRMGMT_STS 0x4D 164#define BGE_PCI_PWRMGMT_DATA 0x4F 165#define BGE_PCI_VPD_CAPID 0x50 166#define BGE_PCI_NEXTPTR_MSI 0x51 167#define BGE_PCI_VPD_ADDR 0x52 168#define BGE_PCI_VPD_DATA 0x54 169#define BGE_PCI_MSI_CAPID 0x58 170#define BGE_PCI_NEXTPTR_NONE 0x59 171#define BGE_PCI_MSI_CTL 0x5A 172#define BGE_PCI_MSI_ADDR_HI 0x5C 173#define BGE_PCI_MSI_ADDR_LO 0x60 174#define BGE_PCI_MSI_DATA 0x64 175 176/* PCI MSI. ??? */ 177#define BGE_PCIE_CAPID_REG 0xD0 178#define BGE_PCIE_CAPID 0x10 179 180/* 181 * PCI registers specific to the BCM570x family. 182 */ 183#define BGE_PCI_MISC_CTL 0x68 184#define BGE_PCI_DMA_RW_CTL 0x6C 185#define BGE_PCI_PCISTATE 0x70 186#define BGE_PCI_CLKCTL 0x74 187#define BGE_PCI_REG_BASEADDR 0x78 188#define BGE_PCI_MEMWIN_BASEADDR 0x7C 189#define BGE_PCI_REG_DATA 0x80 190#define BGE_PCI_MEMWIN_DATA 0x84 191#define BGE_PCI_MODECTL 0x88 192#define BGE_PCI_MISC_CFG 0x8C 193#define BGE_PCI_MISC_LOCALCTL 0x90 194#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 195#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 196#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 197#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 198#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 199#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 200#define BGE_PCI_ISR_MBX_HI 0xB0 201#define BGE_PCI_ISR_MBX_LO 0xB4 202#define BGE_PCI_PRODID_ASICREV 0xBC 203 204/* XXX: 205 * Used in PCI-Express code for 575x chips. 206 * Should be replaced with checking for a PCI config-space 207 * capability for PCI-Express, and PCI-Express standard 208 * offsets into that capability block. 209 */ 210#define BGE_PCI_CONF_DEV_CTRL 0xD8 211#define BGE_PCI_CONF_DEV_STUS 0xDA 212 213/* PCI Misc. Host control register */ 214#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 215#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 216#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 217#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 218#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 219#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 220#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 221#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 222#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 223#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 224 225#if BYTE_ORDER == LITTLE_ENDIAN 226#define BGE_DMA_SWAP_OPTIONS \ 227 BGE_MODECTL_WORDSWAP_NONFRAME| \ 228 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 229#else 230#define BGE_DMA_SWAP_OPTIONS \ 231 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 232 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 233#endif 234 235#define BGE_INIT \ 236 (BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 237 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 238 239#define BGE_CHIPID_BCM5700_A0 0x7000 240#define BGE_CHIPID_BCM5700_A1 0x7001 241#define BGE_CHIPID_BCM5700_B0 0x7100 242#define BGE_CHIPID_BCM5700_B1 0x7101 243#define BGE_CHIPID_BCM5700_B2 0x7102 244#define BGE_CHIPID_BCM5700_B3 0x7103 245#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 246#define BGE_CHIPID_BCM5700_C0 0x7200 247#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 248#define BGE_CHIPID_BCM5701_B0 0x0100 249#define BGE_CHIPID_BCM5701_B2 0x0102 250#define BGE_CHIPID_BCM5701_B5 0x0105 251#define BGE_CHIPID_BCM5703_A0 0x1000 252#define BGE_CHIPID_BCM5703_A1 0x1001 253#define BGE_CHIPID_BCM5703_A2 0x1002 254#define BGE_CHIPID_BCM5703_A3 0x1003 255#define BGE_CHIPID_BCM5703_B0 0x1100 256#define BGE_CHIPID_BCM5704_A0 0x2000 257#define BGE_CHIPID_BCM5704_A1 0x2001 258#define BGE_CHIPID_BCM5704_A2 0x2002 259#define BGE_CHIPID_BCM5704_A3 0x2003 260#define BGE_CHIPID_BCM5704_B0 0x2100 261#define BGE_CHIPID_BCM5705_A0 0x3000 262#define BGE_CHIPID_BCM5705_A1 0x3001 263#define BGE_CHIPID_BCM5705_A2 0x3002 264#define BGE_CHIPID_BCM5705_A3 0x3003 265#define BGE_CHIPID_BCM5750_A0 0x4000 266#define BGE_CHIPID_BCM5750_A1 0x4001 267#define BGE_CHIPID_BCM5750_A3 0x4003 268#define BGE_CHIPID_BCM5750_B0 0x4010 269#define BGE_CHIPID_BCM5750_B1 0x4101 270#define BGE_CHIPID_BCM5750_C0 0x4200 271#define BGE_CHIPID_BCM5750_C1 0x4201 272#define BGE_CHIPID_BCM5750_C2 0x4202 273#define BGE_CHIPID_BCM5714_A0 0x5000 274#define BGE_CHIPID_BCM5761_A0 0x5761000 275#define BGE_CHIPID_BCM5761_A1 0x5761100 276#define BGE_CHIPID_BCM5784_A0 0x5784000 277#define BGE_CHIPID_BCM5784_A1 0x5784100 278#define BGE_CHIPID_BCM5752_A0 0x6000 279#define BGE_CHIPID_BCM5752_A1 0x6001 280#define BGE_CHIPID_BCM5752_A2 0x6002 281#define BGE_CHIPID_BCM5714_B0 0x8000 282#define BGE_CHIPID_BCM5714_B3 0x8003 283#define BGE_CHIPID_BCM5715_A0 0x9000 284#define BGE_CHIPID_BCM5715_A1 0x9001 285#define BGE_CHIPID_BCM5715_A3 0x9003 286#define BGE_CHIPID_BCM5755_A0 0xa000 287#define BGE_CHIPID_BCM5755_A1 0xa001 288#define BGE_CHIPID_BCM5755_A2 0xa002 289#define BGE_CHIPID_BCM5755_C0 0xa200 290#define BGE_CHIPID_BCM5787_A0 0xb000 291#define BGE_CHIPID_BCM5787_A1 0xb001 292#define BGE_CHIPID_BCM5787_A2 0xb002 293#define BGE_CHIPID_BCM5906_A1 0xc001 294#define BGE_CHIPID_BCM5906_A2 0xc002 295 296/* shorthand one */ 297#define BGE_ASICREV(x) ((x) >> 12) 298#define BGE_ASICREV_BCM5700 0x07 299#define BGE_ASICREV_BCM5701 0x00 300#define BGE_ASICREV_BCM5703 0x01 301#define BGE_ASICREV_BCM5704 0x02 302#define BGE_ASICREV_BCM5705 0x03 303#define BGE_ASICREV_BCM5750 0x04 304#define BGE_ASICREV_BCM5714_A0 0x05 /* 5714, 5715 */ 305#define BGE_ASICREV_BCM5752 0x06 306#define BGE_ASICREV_BCM5780 0x08 307#define BGE_ASICREV_BCM5714 0x09 /* 5714, 5715 */ 308#define BGE_ASICREV_BCM5755 0x0a 309#define BGE_ASICREV_BCM5787 0x0b 310#define BGE_ASICREV_BCM5906 0x0c 311#define BGE_ASICREV_USE_PRODID_REG 0x0f 312#define BGE_ASICREV_BCM5761 0x5761 313#define BGE_ASICREV_BCM5784 0x5784 314#define BGE_ASICREV_BCM5785 0x5785 315#define BGE_ASICREV_BCM57780 0x57780 316 317/* chip revisions */ 318#define BGE_CHIPREV(x) ((x) >> 8) 319#define BGE_CHIPREV_5700_AX 0x70 320#define BGE_CHIPREV_5700_BX 0x71 321#define BGE_CHIPREV_5700_CX 0x72 322#define BGE_CHIPREV_5701_AX 0x00 323#define BGE_CHIPREV_5703_AX 0x10 324#define BGE_CHIPREV_5704_AX 0x20 325#define BGE_CHIPREV_5704_BX 0x21 326#define BGE_CHIPREV_5750_AX 0x40 327#define BGE_CHIPREV_5750_BX 0x41 328#define BGE_CHIPREV_5761_AX 0x57611 329#define BGE_CHIPREV_5784_AX 0x57841 330 331/* PCI DMA Read/Write Control register */ 332#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 333#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 334#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 335#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 336#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 337#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 338#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 339#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 340#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 341#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 342#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 343#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 344 345#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 346#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 347#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 348#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 349 350#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 351#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 352#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 353#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 354#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 355#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 356#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 357#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 358 359#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 360#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 361#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 362#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 363#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 364#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 365#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 366#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 367 368/* 369 * PCI state register -- note, this register is read only 370 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 371 * register is set. 372 */ 373#define BGE_PCISTATE_FORCE_RESET 0x00000001 374#define BGE_PCISTATE_INTR_NOT_ACTIVE 0x00000002 375#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 376#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 377#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 378#define BGE_PCISTATE_WANT_EXPROM 0x00000020 379#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 380#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 381#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 382 383/* 384 * The following bits in PCI state register are reserved. 385 * If we check that the register values reverts on reset, 386 * do not check these bits. On some 5704C (rev A3) and some 387 * Altima chips, these bits do not revert until much later 388 * in the bge driver's bge_reset() chip-reset state machine. 389 */ 390#define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 391 392/* 393 * PCI Clock Control register -- note, this register is read only 394 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 395 * register is set. 396 */ 397#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 398#define BGE_PCICLOCKCTL_M66EN 0x00000080 399#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 400#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 401#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 402#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 403#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 404#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 405#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 406#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 407 408/* 409 * High priority mailbox registers 410 * Each mailbox is 64-bits wide, though we only use the 411 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 412 * first. The NIC will load the mailbox after the lower 32 bit word 413 * has been updated. 414 */ 415#define BGE_MBX_IRQ0_HI 0x0200 416#define BGE_MBX_IRQ0_LO 0x0204 417#define BGE_MBX_IRQ1_HI 0x0208 418#define BGE_MBX_IRQ1_LO 0x020C 419#define BGE_MBX_IRQ2_HI 0x0210 420#define BGE_MBX_IRQ2_LO 0x0214 421#define BGE_MBX_IRQ3_HI 0x0218 422#define BGE_MBX_IRQ3_LO 0x021C 423#define BGE_MBX_GEN0_HI 0x0220 424#define BGE_MBX_GEN0_LO 0x0224 425#define BGE_MBX_GEN1_HI 0x0228 426#define BGE_MBX_GEN1_LO 0x022C 427#define BGE_MBX_GEN2_HI 0x0230 428#define BGE_MBX_GEN2_LO 0x0234 429#define BGE_MBX_GEN3_HI 0x0228 430#define BGE_MBX_GEN3_LO 0x022C 431#define BGE_MBX_GEN4_HI 0x0240 432#define BGE_MBX_GEN4_LO 0x0244 433#define BGE_MBX_GEN5_HI 0x0248 434#define BGE_MBX_GEN5_LO 0x024C 435#define BGE_MBX_GEN6_HI 0x0250 436#define BGE_MBX_GEN6_LO 0x0254 437#define BGE_MBX_GEN7_HI 0x0258 438#define BGE_MBX_GEN7_LO 0x025C 439#define BGE_MBX_RELOAD_STATS_HI 0x0260 440#define BGE_MBX_RELOAD_STATS_LO 0x0264 441#define BGE_MBX_RX_STD_PROD_HI 0x0268 442#define BGE_MBX_RX_STD_PROD_LO 0x026C 443#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 444#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 445#define BGE_MBX_RX_MINI_PROD_HI 0x0278 446#define BGE_MBX_RX_MINI_PROD_LO 0x027C 447#define BGE_MBX_RX_CONS0_HI 0x0280 448#define BGE_MBX_RX_CONS0_LO 0x0284 449#define BGE_MBX_RX_CONS1_HI 0x0288 450#define BGE_MBX_RX_CONS1_LO 0x028C 451#define BGE_MBX_RX_CONS2_HI 0x0290 452#define BGE_MBX_RX_CONS2_LO 0x0294 453#define BGE_MBX_RX_CONS3_HI 0x0298 454#define BGE_MBX_RX_CONS3_LO 0x029C 455#define BGE_MBX_RX_CONS4_HI 0x02A0 456#define BGE_MBX_RX_CONS4_LO 0x02A4 457#define BGE_MBX_RX_CONS5_HI 0x02A8 458#define BGE_MBX_RX_CONS5_LO 0x02AC 459#define BGE_MBX_RX_CONS6_HI 0x02B0 460#define BGE_MBX_RX_CONS6_LO 0x02B4 461#define BGE_MBX_RX_CONS7_HI 0x02B8 462#define BGE_MBX_RX_CONS7_LO 0x02BC 463#define BGE_MBX_RX_CONS8_HI 0x02C0 464#define BGE_MBX_RX_CONS8_LO 0x02C4 465#define BGE_MBX_RX_CONS9_HI 0x02C8 466#define BGE_MBX_RX_CONS9_LO 0x02CC 467#define BGE_MBX_RX_CONS10_HI 0x02D0 468#define BGE_MBX_RX_CONS10_LO 0x02D4 469#define BGE_MBX_RX_CONS11_HI 0x02D8 470#define BGE_MBX_RX_CONS11_LO 0x02DC 471#define BGE_MBX_RX_CONS12_HI 0x02E0 472#define BGE_MBX_RX_CONS12_LO 0x02E4 473#define BGE_MBX_RX_CONS13_HI 0x02E8 474#define BGE_MBX_RX_CONS13_LO 0x02EC 475#define BGE_MBX_RX_CONS14_HI 0x02F0 476#define BGE_MBX_RX_CONS14_LO 0x02F4 477#define BGE_MBX_RX_CONS15_HI 0x02F8 478#define BGE_MBX_RX_CONS15_LO 0x02FC 479#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 480#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 481#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 482#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 483#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 484#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 485#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 486#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 487#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 488#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 489#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 490#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 491#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 492#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 493#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 494#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 495#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 496#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 497#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 498#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 499#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 500#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 501#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 502#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 503#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 504#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 505#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 506#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 507#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 508#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 509#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 510#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 511#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 512#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 513#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 514#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 515#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 516#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 517#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 518#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 519#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 520#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 521#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 522#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 523#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 524#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 525#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 526#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 527#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 528#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 529#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 530#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 531#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 532#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 533#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 534#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 535#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 536#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 537#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 538#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 539#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 540#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 541#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 542#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 543 544#define BGE_TX_RINGS_MAX 4 545#define BGE_TX_RINGS_EXTSSRAM_MAX 16 546#define BGE_RX_RINGS_MAX 16 547 548/* Ethernet MAC control registers */ 549#define BGE_MAC_MODE 0x0400 550#define BGE_MAC_STS 0x0404 551#define BGE_MAC_EVT_ENB 0x0408 552#define BGE_MAC_LED_CTL 0x040C 553#define BGE_MAC_ADDR1_LO 0x0410 554#define BGE_MAC_ADDR1_HI 0x0414 555#define BGE_MAC_ADDR2_LO 0x0418 556#define BGE_MAC_ADDR2_HI 0x041C 557#define BGE_MAC_ADDR3_LO 0x0420 558#define BGE_MAC_ADDR3_HI 0x0424 559#define BGE_MAC_ADDR4_LO 0x0428 560#define BGE_MAC_ADDR4_HI 0x042C 561#define BGE_WOL_PATPTR 0x0430 562#define BGE_WOL_PATCFG 0x0434 563#define BGE_TX_RANDOM_BACKOFF 0x0438 564#define BGE_RX_MTU 0x043C 565#define BGE_GBIT_PCS_TEST 0x0440 566#define BGE_TX_TBI_AUTONEG 0x0444 567#define BGE_RX_TBI_AUTONEG 0x0448 568#define BGE_MI_COMM 0x044C 569#define BGE_MI_STS 0x0450 570#define BGE_MI_MODE 0x0454 571#define BGE_AUTOPOLL_STS 0x0458 572#define BGE_TX_MODE 0x045C 573#define BGE_TX_STS 0x0460 574#define BGE_TX_LENGTHS 0x0464 575#define BGE_RX_MODE 0x0468 576#define BGE_RX_STS 0x046C 577#define BGE_MAR0 0x0470 578#define BGE_MAR1 0x0474 579#define BGE_MAR2 0x0478 580#define BGE_MAR3 0x047C 581#define BGE_RX_BD_RULES_CTL0 0x0480 582#define BGE_RX_BD_RULES_MASKVAL0 0x0484 583#define BGE_RX_BD_RULES_CTL1 0x0488 584#define BGE_RX_BD_RULES_MASKVAL1 0x048C 585#define BGE_RX_BD_RULES_CTL2 0x0490 586#define BGE_RX_BD_RULES_MASKVAL2 0x0494 587#define BGE_RX_BD_RULES_CTL3 0x0498 588#define BGE_RX_BD_RULES_MASKVAL3 0x049C 589#define BGE_RX_BD_RULES_CTL4 0x04A0 590#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 591#define BGE_RX_BD_RULES_CTL5 0x04A8 592#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 593#define BGE_RX_BD_RULES_CTL6 0x04B0 594#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 595#define BGE_RX_BD_RULES_CTL7 0x04B8 596#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 597#define BGE_RX_BD_RULES_CTL8 0x04C0 598#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 599#define BGE_RX_BD_RULES_CTL9 0x04C8 600#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 601#define BGE_RX_BD_RULES_CTL10 0x04D0 602#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 603#define BGE_RX_BD_RULES_CTL11 0x04D8 604#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 605#define BGE_RX_BD_RULES_CTL12 0x04E0 606#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 607#define BGE_RX_BD_RULES_CTL13 0x04E8 608#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 609#define BGE_RX_BD_RULES_CTL14 0x04F0 610#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 611#define BGE_RX_BD_RULES_CTL15 0x04F8 612#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 613#define BGE_RX_RULES_CFG 0x0500 614#define BGE_MAX_RX_FRAME_LOWAT 0x0504 615#define BGE_SERDES_CFG 0x0590 616#define BGE_SERDES_STS 0x0594 617#define BGE_SGDIG_CFG 0x05B0 618#define BGE_SGDIG_STS 0x05B4 619#define BGE_MAC_STATS 0x0800 620 621/* Ethernet MAC Mode register */ 622#define BGE_MACMODE_RESET 0x00000001 623#define BGE_MACMODE_HALF_DUPLEX 0x00000002 624#define BGE_MACMODE_PORTMODE 0x0000000C 625#define BGE_MACMODE_LOOPBACK 0x00000010 626#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 627#define BGE_MACMODE_TX_BURST_ENB 0x00000100 628#define BGE_MACMODE_MAX_DEFER 0x00000200 629#define BGE_MACMODE_LINK_POLARITY 0x00000400 630#define BGE_MACMODE_RX_STATS_ENB 0x00000800 631#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 632#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 633#define BGE_MACMODE_TX_STATS_ENB 0x00004000 634#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 635#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 636#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 637#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 638#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 639#define BGE_MACMODE_MIP_ENB 0x00100000 640#define BGE_MACMODE_TXDMA_ENB 0x00200000 641#define BGE_MACMODE_RXDMA_ENB 0x00400000 642#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 643 644#define BGE_PORTMODE_NONE 0x00000000 645#define BGE_PORTMODE_MII 0x00000004 646#define BGE_PORTMODE_GMII 0x00000008 647#define BGE_PORTMODE_TBI 0x0000000C 648 649/* MAC Status register */ 650#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 651#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 652#define BGE_MACSTAT_RX_CFG 0x00000004 653#define BGE_MACSTAT_CFG_CHANGED 0x00000008 654#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 655#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 656#define BGE_MACSTAT_LINK_CHANGED 0x00001000 657#define BGE_MACSTAT_MI_COMPLETE 0x00400000 658#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 659#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 660#define BGE_MACSTAT_ODI_ERROR 0x02000000 661#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 662#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 663 664/* MAC Event Enable Register */ 665#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 666#define BGE_EVTENB_LINK_CHANGED 0x00001000 667#define BGE_EVTENB_MI_COMPLETE 0x00400000 668#define BGE_EVTENB_MI_INTERRUPT 0x00800000 669#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 670#define BGE_EVTENB_ODI_ERROR 0x02000000 671#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 672#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 673 674/* LED Control Register */ 675#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 676#define BGE_LEDCTL_1000MBPS_LED 0x00000002 677#define BGE_LEDCTL_100MBPS_LED 0x00000004 678#define BGE_LEDCTL_10MBPS_LED 0x00000008 679#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 680#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 681#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 682#define BGE_LEDCTL_1000MBPS_STS 0x00000080 683#define BGE_LEDCTL_100MBPS_STS 0x00000100 684#define BGE_LEDCTL_10MBPS_STS 0x00000200 685#define BGE_LEDCTL_TRADLED_STS 0x00000400 686#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 687#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 688 689/* TX backoff seed register */ 690#define BGE_TX_BACKOFF_SEED_MASK 0x3F 691 692/* Autopoll status register */ 693#define BGE_AUTOPOLLSTS_ERROR 0x00000001 694 695/* Transmit MAC mode register */ 696#define BGE_TXMODE_RESET 0x00000001 697#define BGE_TXMODE_ENABLE 0x00000002 698#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 699#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 700#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 701 702/* Transmit MAC status register */ 703#define BGE_TXSTAT_RX_XOFFED 0x00000001 704#define BGE_TXSTAT_SENT_XOFF 0x00000002 705#define BGE_TXSTAT_SENT_XON 0x00000004 706#define BGE_TXSTAT_LINK_UP 0x00000008 707#define BGE_TXSTAT_ODI_UFLOW 0x00000010 708#define BGE_TXSTAT_ODI_OFLOW 0x00000020 709 710/* Transmit MAC lengths register */ 711#define BGE_TXLEN_SLOTTIME 0x000000FF 712#define BGE_TXLEN_IPG 0x00000F00 713#define BGE_TXLEN_CRS 0x00003000 714 715/* Receive MAC mode register */ 716#define BGE_RXMODE_RESET 0x00000001 717#define BGE_RXMODE_ENABLE 0x00000002 718#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 719#define BGE_RXMODE_RX_GIANTS 0x00000020 720#define BGE_RXMODE_RX_RUNTS 0x00000040 721#define BGE_RXMODE_8022_LENCHECK 0x00000080 722#define BGE_RXMODE_RX_PROMISC 0x00000100 723#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 724#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 725 726/* Receive MAC status register */ 727#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 728#define BGE_RXSTAT_RCVD_XOFF 0x00000002 729#define BGE_RXSTAT_RCVD_XON 0x00000004 730 731/* Receive Rules Control register */ 732#define BGE_RXRULECTL_OFFSET 0x000000FF 733#define BGE_RXRULECTL_CLASS 0x00001F00 734#define BGE_RXRULECTL_HDRTYPE 0x0000E000 735#define BGE_RXRULECTL_COMPARE_OP 0x00030000 736#define BGE_RXRULECTL_MAP 0x01000000 737#define BGE_RXRULECTL_DISCARD 0x02000000 738#define BGE_RXRULECTL_MASK 0x04000000 739#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 740#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 741#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 742#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 743 744/* Receive Rules Mask register */ 745#define BGE_RXRULEMASK_VALUE 0x0000FFFF 746#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 747 748/* SERDES configuration register */ 749#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 750#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 751#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 752#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 753#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 754#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 755#define BGE_SERDESCFG_TXMODE 0x00001000 756#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 757#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 758#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 759#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 760#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 761#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 762#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125MHz clock */ 763#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 764#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 765 766/* SERDES status register */ 767#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 768#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 769 770/* SGDIG config (not documented) */ 771#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 772#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 773#define BGE_SGDIGCFG_SEND 0x40000000 774#define BGE_SGDIGCFG_AUTO 0x80000000 775 776/* SGDIG status (not documented) */ 777#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 778#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 779#define BGE_SGDIGSTS_DONE 0x00000002 780 781/* MI communication register */ 782#define BGE_MICOMM_DATA 0x0000FFFF 783#define BGE_MICOMM_REG 0x001F0000 784#define BGE_MICOMM_PHY 0x03E00000 785#define BGE_MICOMM_CMD 0x0C000000 786#define BGE_MICOMM_READFAIL 0x10000000 787#define BGE_MICOMM_BUSY 0x20000000 788 789#define BGE_MIREG(x) ((x & 0x1F) << 16) 790#define BGE_MIPHY(x) ((x & 0x1F) << 21) 791#define BGE_MICMD_WRITE 0x04000000 792#define BGE_MICMD_READ 0x08000000 793 794/* MI status register */ 795#define BGE_MISTS_LINK 0x00000001 796#define BGE_MISTS_10MBPS 0x00000002 797 798#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 799#define BGE_MIMODE_AUTOPOLL 0x00000010 800#define BGE_MIMODE_500KHZ_CONST 0x00008000 801#define BGE_MIMODE_CLKCNT 0x001F0000 802#define BGE_MIMODE_BASE 0x000C0000 803 804/* 805 * Send data initiator control registers. 806 */ 807#define BGE_SDI_MODE 0x0C00 808#define BGE_SDI_STATUS 0x0C04 809#define BGE_SDI_STATS_CTL 0x0C08 810#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 811#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 812#define BGE_LOCSTATS_COS0 0x0C80 813#define BGE_LOCSTATS_COS1 0x0C84 814#define BGE_LOCSTATS_COS2 0x0C88 815#define BGE_LOCSTATS_COS3 0x0C8C 816#define BGE_LOCSTATS_COS4 0x0C90 817#define BGE_LOCSTATS_COS5 0x0C84 818#define BGE_LOCSTATS_COS6 0x0C98 819#define BGE_LOCSTATS_COS7 0x0C9C 820#define BGE_LOCSTATS_COS8 0x0CA0 821#define BGE_LOCSTATS_COS9 0x0CA4 822#define BGE_LOCSTATS_COS10 0x0CA8 823#define BGE_LOCSTATS_COS11 0x0CAC 824#define BGE_LOCSTATS_COS12 0x0CB0 825#define BGE_LOCSTATS_COS13 0x0CB4 826#define BGE_LOCSTATS_COS14 0x0CB8 827#define BGE_LOCSTATS_COS15 0x0CBC 828#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 829#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 830#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 831#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 832#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 833#define BGE_LOCSTATS_IRQS 0x0CD4 834#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 835#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 836 837/* Send Data Initiator mode register */ 838#define BGE_SDIMODE_RESET 0x00000001 839#define BGE_SDIMODE_ENABLE 0x00000002 840#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 841 842/* Send Data Initiator stats register */ 843#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 844 845/* Send Data Initiator stats control register */ 846#define BGE_SDISTATSCTL_ENABLE 0x00000001 847#define BGE_SDISTATSCTL_FASTER 0x00000002 848#define BGE_SDISTATSCTL_CLEAR 0x00000004 849#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 850#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 851 852/* 853 * Send Data Completion Control registers 854 */ 855#define BGE_SDC_MODE 0x1000 856#define BGE_SDC_STATUS 0x1004 857 858/* Send Data completion mode register */ 859#define BGE_SDCMODE_RESET 0x00000001 860#define BGE_SDCMODE_ENABLE 0x00000002 861#define BGE_SDCMODE_ATTN 0x00000004 862#define BGE_SDCMODE_CDELAY 0x00000010 863 864/* Send Data completion status register */ 865#define BGE_SDCSTAT_ATTN 0x00000004 866 867/* 868 * Send BD Ring Selector Control registers 869 */ 870#define BGE_SRS_MODE 0x1400 871#define BGE_SRS_STATUS 0x1404 872#define BGE_SRS_HWDIAG 0x1408 873#define BGE_SRS_LOC_NIC_CONS0 0x1440 874#define BGE_SRS_LOC_NIC_CONS1 0x1444 875#define BGE_SRS_LOC_NIC_CONS2 0x1448 876#define BGE_SRS_LOC_NIC_CONS3 0x144C 877#define BGE_SRS_LOC_NIC_CONS4 0x1450 878#define BGE_SRS_LOC_NIC_CONS5 0x1454 879#define BGE_SRS_LOC_NIC_CONS6 0x1458 880#define BGE_SRS_LOC_NIC_CONS7 0x145C 881#define BGE_SRS_LOC_NIC_CONS8 0x1460 882#define BGE_SRS_LOC_NIC_CONS9 0x1464 883#define BGE_SRS_LOC_NIC_CONS10 0x1468 884#define BGE_SRS_LOC_NIC_CONS11 0x146C 885#define BGE_SRS_LOC_NIC_CONS12 0x1470 886#define BGE_SRS_LOC_NIC_CONS13 0x1474 887#define BGE_SRS_LOC_NIC_CONS14 0x1478 888#define BGE_SRS_LOC_NIC_CONS15 0x147C 889 890/* Send BD Ring Selector Mode register */ 891#define BGE_SRSMODE_RESET 0x00000001 892#define BGE_SRSMODE_ENABLE 0x00000002 893#define BGE_SRSMODE_ATTN 0x00000004 894 895/* Send BD Ring Selector Status register */ 896#define BGE_SRSSTAT_ERROR 0x00000004 897 898/* Send BD Ring Selector HW Diagnostics register */ 899#define BGE_SRSHWDIAG_STATE 0x0000000F 900#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 901#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 902#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 903 904/* 905 * Send BD Initiator Selector Control registers 906 */ 907#define BGE_SBDI_MODE 0x1800 908#define BGE_SBDI_STATUS 0x1804 909#define BGE_SBDI_LOC_NIC_PROD0 0x1808 910#define BGE_SBDI_LOC_NIC_PROD1 0x180C 911#define BGE_SBDI_LOC_NIC_PROD2 0x1810 912#define BGE_SBDI_LOC_NIC_PROD3 0x1814 913#define BGE_SBDI_LOC_NIC_PROD4 0x1818 914#define BGE_SBDI_LOC_NIC_PROD5 0x181C 915#define BGE_SBDI_LOC_NIC_PROD6 0x1820 916#define BGE_SBDI_LOC_NIC_PROD7 0x1824 917#define BGE_SBDI_LOC_NIC_PROD8 0x1828 918#define BGE_SBDI_LOC_NIC_PROD9 0x182C 919#define BGE_SBDI_LOC_NIC_PROD10 0x1830 920#define BGE_SBDI_LOC_NIC_PROD11 0x1834 921#define BGE_SBDI_LOC_NIC_PROD12 0x1838 922#define BGE_SBDI_LOC_NIC_PROD13 0x183C 923#define BGE_SBDI_LOC_NIC_PROD14 0x1840 924#define BGE_SBDI_LOC_NIC_PROD15 0x1844 925 926/* Send BD Initiator Mode register */ 927#define BGE_SBDIMODE_RESET 0x00000001 928#define BGE_SBDIMODE_ENABLE 0x00000002 929#define BGE_SBDIMODE_ATTN 0x00000004 930 931/* Send BD Initiator Status register */ 932#define BGE_SBDISTAT_ERROR 0x00000004 933 934/* 935 * Send BD Completion Control registers 936 */ 937#define BGE_SBDC_MODE 0x1C00 938#define BGE_SBDC_STATUS 0x1C04 939 940/* Send BD Completion Control Mode register */ 941#define BGE_SBDCMODE_RESET 0x00000001 942#define BGE_SBDCMODE_ENABLE 0x00000002 943#define BGE_SBDCMODE_ATTN 0x00000004 944 945/* Send BD Completion Control Status register */ 946#define BGE_SBDCSTAT_ATTN 0x00000004 947 948/* 949 * Receive List Placement Control registers 950 */ 951#define BGE_RXLP_MODE 0x2000 952#define BGE_RXLP_STATUS 0x2004 953#define BGE_RXLP_SEL_LIST_LOCK 0x2008 954#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 955#define BGE_RXLP_CFG 0x2010 956#define BGE_RXLP_STATS_CTL 0x2014 957#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 958#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 959#define BGE_RXLP_HEAD0 0x2100 960#define BGE_RXLP_TAIL0 0x2104 961#define BGE_RXLP_COUNT0 0x2108 962#define BGE_RXLP_HEAD1 0x2110 963#define BGE_RXLP_TAIL1 0x2114 964#define BGE_RXLP_COUNT1 0x2118 965#define BGE_RXLP_HEAD2 0x2120 966#define BGE_RXLP_TAIL2 0x2124 967#define BGE_RXLP_COUNT2 0x2128 968#define BGE_RXLP_HEAD3 0x2130 969#define BGE_RXLP_TAIL3 0x2134 970#define BGE_RXLP_COUNT3 0x2138 971#define BGE_RXLP_HEAD4 0x2140 972#define BGE_RXLP_TAIL4 0x2144 973#define BGE_RXLP_COUNT4 0x2148 974#define BGE_RXLP_HEAD5 0x2150 975#define BGE_RXLP_TAIL5 0x2154 976#define BGE_RXLP_COUNT5 0x2158 977#define BGE_RXLP_HEAD6 0x2160 978#define BGE_RXLP_TAIL6 0x2164 979#define BGE_RXLP_COUNT6 0x2168 980#define BGE_RXLP_HEAD7 0x2170 981#define BGE_RXLP_TAIL7 0x2174 982#define BGE_RXLP_COUNT7 0x2178 983#define BGE_RXLP_HEAD8 0x2180 984#define BGE_RXLP_TAIL8 0x2184 985#define BGE_RXLP_COUNT8 0x2188 986#define BGE_RXLP_HEAD9 0x2190 987#define BGE_RXLP_TAIL9 0x2194 988#define BGE_RXLP_COUNT9 0x2198 989#define BGE_RXLP_HEAD10 0x21A0 990#define BGE_RXLP_TAIL10 0x21A4 991#define BGE_RXLP_COUNT10 0x21A8 992#define BGE_RXLP_HEAD11 0x21B0 993#define BGE_RXLP_TAIL11 0x21B4 994#define BGE_RXLP_COUNT11 0x21B8 995#define BGE_RXLP_HEAD12 0x21C0 996#define BGE_RXLP_TAIL12 0x21C4 997#define BGE_RXLP_COUNT12 0x21C8 998#define BGE_RXLP_HEAD13 0x21D0 999#define BGE_RXLP_TAIL13 0x21D4 1000#define BGE_RXLP_COUNT13 0x21D8 1001#define BGE_RXLP_HEAD14 0x21E0 1002#define BGE_RXLP_TAIL14 0x21E4 1003#define BGE_RXLP_COUNT14 0x21E8 1004#define BGE_RXLP_HEAD15 0x21F0 1005#define BGE_RXLP_TAIL15 0x21F4 1006#define BGE_RXLP_COUNT15 0x21F8 1007#define BGE_RXLP_LOCSTAT_COS0 0x2200 1008#define BGE_RXLP_LOCSTAT_COS1 0x2204 1009#define BGE_RXLP_LOCSTAT_COS2 0x2208 1010#define BGE_RXLP_LOCSTAT_COS3 0x220C 1011#define BGE_RXLP_LOCSTAT_COS4 0x2210 1012#define BGE_RXLP_LOCSTAT_COS5 0x2214 1013#define BGE_RXLP_LOCSTAT_COS6 0x2218 1014#define BGE_RXLP_LOCSTAT_COS7 0x221C 1015#define BGE_RXLP_LOCSTAT_COS8 0x2220 1016#define BGE_RXLP_LOCSTAT_COS9 0x2224 1017#define BGE_RXLP_LOCSTAT_COS10 0x2228 1018#define BGE_RXLP_LOCSTAT_COS11 0x222C 1019#define BGE_RXLP_LOCSTAT_COS12 0x2230 1020#define BGE_RXLP_LOCSTAT_COS13 0x2234 1021#define BGE_RXLP_LOCSTAT_COS14 0x2238 1022#define BGE_RXLP_LOCSTAT_COS15 0x223C 1023#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1024#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1025#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1026#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1027#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1028#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1029#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1030 1031 1032/* Receive List Placement mode register */ 1033#define BGE_RXLPMODE_RESET 0x00000001 1034#define BGE_RXLPMODE_ENABLE 0x00000002 1035#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1036#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1037#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1038 1039/* Receive List Placement Status register */ 1040#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1041#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1042#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1043 1044/* 1045 * Receive Data and Receive BD Initiator Control Registers 1046 */ 1047#define BGE_RDBDI_MODE 0x2400 1048#define BGE_RDBDI_STATUS 0x2404 1049#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1050#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1051#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1052#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1053#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1054#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1055#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1056#define BGE_RX_STD_RCB_NICADDR 0x245C 1057#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1058#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1059#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1060#define BGE_RX_MINI_RCB_NICADDR 0x246C 1061#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1062#define BGE_RDBDI_STD_RX_CONS 0x2474 1063#define BGE_RDBDI_MINI_RX_CONS 0x2478 1064#define BGE_RDBDI_RETURN_PROD0 0x2480 1065#define BGE_RDBDI_RETURN_PROD1 0x2484 1066#define BGE_RDBDI_RETURN_PROD2 0x2488 1067#define BGE_RDBDI_RETURN_PROD3 0x248C 1068#define BGE_RDBDI_RETURN_PROD4 0x2490 1069#define BGE_RDBDI_RETURN_PROD5 0x2494 1070#define BGE_RDBDI_RETURN_PROD6 0x2498 1071#define BGE_RDBDI_RETURN_PROD7 0x249C 1072#define BGE_RDBDI_RETURN_PROD8 0x24A0 1073#define BGE_RDBDI_RETURN_PROD9 0x24A4 1074#define BGE_RDBDI_RETURN_PROD10 0x24A8 1075#define BGE_RDBDI_RETURN_PROD11 0x24AC 1076#define BGE_RDBDI_RETURN_PROD12 0x24B0 1077#define BGE_RDBDI_RETURN_PROD13 0x24B4 1078#define BGE_RDBDI_RETURN_PROD14 0x24B8 1079#define BGE_RDBDI_RETURN_PROD15 0x24BC 1080#define BGE_RDBDI_HWDIAG 0x24C0 1081 1082 1083/* Receive Data and Receive BD Initiator Mode register */ 1084#define BGE_RDBDIMODE_RESET 0x00000001 1085#define BGE_RDBDIMODE_ENABLE 0x00000002 1086#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1087#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1088#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1089 1090/* Receive Data and Receive BD Initiator Status register */ 1091#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1092#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1093#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1094 1095 1096/* 1097 * Receive Data Completion Control registers 1098 */ 1099#define BGE_RDC_MODE 0x2800 1100 1101/* Receive Data Completion Mode register */ 1102#define BGE_RDCMODE_RESET 0x00000001 1103#define BGE_RDCMODE_ENABLE 0x00000002 1104#define BGE_RDCMODE_ATTN 0x00000004 1105 1106/* 1107 * Receive BD Initiator Control registers 1108 */ 1109#define BGE_RBDI_MODE 0x2C00 1110#define BGE_RBDI_STATUS 0x2C04 1111#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1112#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1113#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1114#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1115#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1116#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1117 1118/* Receive BD Initiator Mode register */ 1119#define BGE_RBDIMODE_RESET 0x00000001 1120#define BGE_RBDIMODE_ENABLE 0x00000002 1121#define BGE_RBDIMODE_ATTN 0x00000004 1122 1123/* Receive BD Initiator Status register */ 1124#define BGE_RBDISTAT_ATTN 0x00000004 1125 1126/* 1127 * Receive BD Completion Control registers 1128 */ 1129#define BGE_RBDC_MODE 0x3000 1130#define BGE_RBDC_STATUS 0x3004 1131#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1132#define BGE_RBDC_STD_BD_PROD 0x300C 1133#define BGE_RBDC_MINI_BD_PROD 0x3010 1134 1135/* Receive BD completion mode register */ 1136#define BGE_RBDCMODE_RESET 0x00000001 1137#define BGE_RBDCMODE_ENABLE 0x00000002 1138#define BGE_RBDCMODE_ATTN 0x00000004 1139 1140/* Receive BD completion status register */ 1141#define BGE_RBDCSTAT_ERROR 0x00000004 1142 1143/* 1144 * Receive List Selector Control registers 1145 */ 1146#define BGE_RXLS_MODE 0x3400 1147#define BGE_RXLS_STATUS 0x3404 1148 1149/* Receive List Selector Mode register */ 1150#define BGE_RXLSMODE_RESET 0x00000001 1151#define BGE_RXLSMODE_ENABLE 0x00000002 1152#define BGE_RXLSMODE_ATTN 0x00000004 1153 1154/* Receive List Selector Status register */ 1155#define BGE_RXLSSTAT_ERROR 0x00000004 1156 1157/* 1158 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1159 */ 1160#define BGE_MBCF_MODE 0x3800 1161#define BGE_MBCF_STATUS 0x3804 1162 1163/* Mbuf Cluster Free mode register */ 1164#define BGE_MBCFMODE_RESET 0x00000001 1165#define BGE_MBCFMODE_ENABLE 0x00000002 1166#define BGE_MBCFMODE_ATTN 0x00000004 1167 1168/* Mbuf Cluster Free status register */ 1169#define BGE_MBCFSTAT_ERROR 0x00000004 1170 1171/* 1172 * Host Coalescing Control registers 1173 */ 1174#define BGE_HCC_MODE 0x3C00 1175#define BGE_HCC_STATUS 0x3C04 1176#define BGE_HCC_RX_COAL_TICKS 0x3C08 1177#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1178#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1179#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1180#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1181#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1182#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1183#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1184#define BGE_HCC_STATS_TICKS 0x3C28 1185#define BGE_HCC_STATS_ADDR_HI 0x3C30 1186#define BGE_HCC_STATS_ADDR_LO 0x3C34 1187#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1188#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1189#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1190#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1191#define BGE_FLOW_ATTN 0x3C48 1192#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1193#define BGE_HCC_STD_BD_CONS 0x3C54 1194#define BGE_HCC_MINI_BD_CONS 0x3C58 1195#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1196#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1197#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1198#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1199#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1200#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1201#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1202#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1203#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1204#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1205#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1206#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1207#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1208#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1209#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1210#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1211#define BGE_HCC_TX_BD_CONS0 0x3CC0 1212#define BGE_HCC_TX_BD_CONS1 0x3CC4 1213#define BGE_HCC_TX_BD_CONS2 0x3CC8 1214#define BGE_HCC_TX_BD_CONS3 0x3CCC 1215#define BGE_HCC_TX_BD_CONS4 0x3CD0 1216#define BGE_HCC_TX_BD_CONS5 0x3CD4 1217#define BGE_HCC_TX_BD_CONS6 0x3CD8 1218#define BGE_HCC_TX_BD_CONS7 0x3CDC 1219#define BGE_HCC_TX_BD_CONS8 0x3CE0 1220#define BGE_HCC_TX_BD_CONS9 0x3CE4 1221#define BGE_HCC_TX_BD_CONS10 0x3CE8 1222#define BGE_HCC_TX_BD_CONS11 0x3CEC 1223#define BGE_HCC_TX_BD_CONS12 0x3CF0 1224#define BGE_HCC_TX_BD_CONS13 0x3CF4 1225#define BGE_HCC_TX_BD_CONS14 0x3CF8 1226#define BGE_HCC_TX_BD_CONS15 0x3CFC 1227 1228 1229/* Host coalescing mode register */ 1230#define BGE_HCCMODE_RESET 0x00000001 1231#define BGE_HCCMODE_ENABLE 0x00000002 1232#define BGE_HCCMODE_ATTN 0x00000004 1233#define BGE_HCCMODE_COAL_NOW 0x00000008 1234#define BGE_HCCMODE_MSI_BITS 0x00000070 1235#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1236 1237#define BGE_STATBLKSZ_FULL 0x00000000 1238#define BGE_STATBLKSZ_64BYTE 0x00000080 1239#define BGE_STATBLKSZ_32BYTE 0x00000100 1240 1241/* Host coalescing status register */ 1242#define BGE_HCCSTAT_ERROR 0x00000004 1243 1244/* Flow attention register */ 1245#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1246#define BGE_FLOWATTN_MEMARB 0x00000080 1247#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1248#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1249#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1250#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1251#define BGE_FLOWATTN_RDBDI 0x00080000 1252#define BGE_FLOWATTN_RXLS 0x00100000 1253#define BGE_FLOWATTN_RXLP 0x00200000 1254#define BGE_FLOWATTN_RBDC 0x00400000 1255#define BGE_FLOWATTN_RBDI 0x00800000 1256#define BGE_FLOWATTN_SDC 0x08000000 1257#define BGE_FLOWATTN_SDI 0x10000000 1258#define BGE_FLOWATTN_SRS 0x20000000 1259#define BGE_FLOWATTN_SBDC 0x40000000 1260#define BGE_FLOWATTN_SBDI 0x80000000 1261 1262/* 1263 * Memory arbiter registers 1264 */ 1265#define BGE_MARB_MODE 0x4000 1266#define BGE_MARB_STATUS 0x4004 1267#define BGE_MARB_TRAPADDR_HI 0x4008 1268#define BGE_MARB_TRAPADDR_LO 0x400C 1269 1270/* Memory arbiter mode register */ 1271#define BGE_MARBMODE_RESET 0x00000001 1272#define BGE_MARBMODE_ENABLE 0x00000002 1273#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1274#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1275#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1276#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1277#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1278#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1279#define BGE_MARBMODE_PCI_TRAP 0x00000100 1280#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1281#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1282#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1283#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1284#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1285#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1286#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1287#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1288#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1289#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1290#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1291#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1292#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1293#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1294#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1295#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1296#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1297 1298/* Memory arbiter status register */ 1299#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1300#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1301#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1302#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1303#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1304#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1305#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1306#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1307#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1308#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1309#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1310#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1311#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1312#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1313#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1314#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1315#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1316#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1317#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1318#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1319#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1320#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1321#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1322#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1323 1324/* 1325 * Buffer manager control registers 1326 */ 1327#define BGE_BMAN_MODE 0x4400 1328#define BGE_BMAN_STATUS 0x4404 1329#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1330#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1331#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1332#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1333#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1334#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1335#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1336#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1337#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1338#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1339#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1340#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1341#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1342#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1343#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1344#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1345#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1346#define BGE_BMAN_HWDIAG_1 0x444C 1347#define BGE_BMAN_HWDIAG_2 0x4450 1348#define BGE_BMAN_HWDIAG_3 0x4454 1349 1350/* Buffer manager mode register */ 1351#define BGE_BMANMODE_RESET 0x00000001 1352#define BGE_BMANMODE_ENABLE 0x00000002 1353#define BGE_BMANMODE_ATTN 0x00000004 1354#define BGE_BMANMODE_TESTMODE 0x00000008 1355#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1356 1357/* Buffer manager status register */ 1358#define BGE_BMANSTAT_ERRO 0x00000004 1359#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1360 1361 1362/* 1363 * Read DMA Control registers 1364 */ 1365#define BGE_RDMA_MODE 0x4800 1366#define BGE_RDMA_STATUS 0x4804 1367 1368/* Read DMA mode register */ 1369#define BGE_RDMAMODE_RESET 0x00000001 1370#define BGE_RDMAMODE_ENABLE 0x00000002 1371#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1372#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1373#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1374#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1375#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1376#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1377#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1378#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1379#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1380#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1381#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1382#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1383#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1384#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1385 1386/* Read DMA status register */ 1387#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1388#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1389#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1390#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1391#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1392#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1393#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1394#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1395 1396/* 1397 * Write DMA control registers 1398 */ 1399#define BGE_WDMA_MODE 0x4C00 1400#define BGE_WDMA_STATUS 0x4C04 1401 1402/* Write DMA mode register */ 1403#define BGE_WDMAMODE_RESET 0x00000001 1404#define BGE_WDMAMODE_ENABLE 0x00000002 1405#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1406#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1407#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1408#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1409#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1410#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1411#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1412#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1413#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1414#define BGE_WDMAMODE_RX_ACCEL 0x00000400 1415 1416/* Write DMA status register */ 1417#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1418#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1419#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1420#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1421#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1422#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1423#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1424#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1425 1426 1427/* 1428 * RX CPU registers 1429 */ 1430#define BGE_RXCPU_MODE 0x5000 1431#define BGE_RXCPU_STATUS 0x5004 1432#define BGE_RXCPU_PC 0x501C 1433 1434/* RX CPU mode register */ 1435#define BGE_RXCPUMODE_RESET 0x00000001 1436#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1437#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1438#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1439#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1440#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1441#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1442#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1443#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1444#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1445#define BGE_RXCPUMODE_HALTCPU 0x00000400 1446#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1447#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1448#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1449 1450/* RX CPU status register */ 1451#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1452#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1453#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1454#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1455#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1456#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1457#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1458#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1459#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1460#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1461#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1462#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1463#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1464#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1465#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1466#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1467#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1468 1469 1470/* 1471 * V? CPU registers 1472 */ 1473#define BGE_VCPU_STATUS 0x5100 1474#define BGE_VCPU_EXT_CTRL 0x6890 1475 1476#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1477#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1478 1479#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1480#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1481 1482 1483/* 1484 * TX CPU registers 1485 */ 1486#define BGE_TXCPU_MODE 0x5400 1487#define BGE_TXCPU_STATUS 0x5404 1488#define BGE_TXCPU_PC 0x541C 1489 1490/* TX CPU mode register */ 1491#define BGE_TXCPUMODE_RESET 0x00000001 1492#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1493#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1494#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1495#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1496#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1497#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1498#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1499#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1500#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1501#define BGE_TXCPUMODE_HALTCPU 0x00000400 1502#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1503#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1504 1505/* TX CPU status register */ 1506#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1507#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1508#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1509#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1510#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1511#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1512#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1513#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1514#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1515#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1516#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1517#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1518#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1519#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1520#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1521#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1522#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1523 1524 1525/* 1526 * Low priority mailbox registers 1527 */ 1528#define BGE_LPMBX_IRQ0_HI 0x5800 1529#define BGE_LPMBX_IRQ0_LO 0x5804 1530#define BGE_LPMBX_IRQ1_HI 0x5808 1531#define BGE_LPMBX_IRQ1_LO 0x580C 1532#define BGE_LPMBX_IRQ2_HI 0x5810 1533#define BGE_LPMBX_IRQ2_LO 0x5814 1534#define BGE_LPMBX_IRQ3_HI 0x5818 1535#define BGE_LPMBX_IRQ3_LO 0x581C 1536#define BGE_LPMBX_GEN0_HI 0x5820 1537#define BGE_LPMBX_GEN0_LO 0x5824 1538#define BGE_LPMBX_GEN1_HI 0x5828 1539#define BGE_LPMBX_GEN1_LO 0x582C 1540#define BGE_LPMBX_GEN2_HI 0x5830 1541#define BGE_LPMBX_GEN2_LO 0x5834 1542#define BGE_LPMBX_GEN3_HI 0x5828 1543#define BGE_LPMBX_GEN3_LO 0x582C 1544#define BGE_LPMBX_GEN4_HI 0x5840 1545#define BGE_LPMBX_GEN4_LO 0x5844 1546#define BGE_LPMBX_GEN5_HI 0x5848 1547#define BGE_LPMBX_GEN5_LO 0x584C 1548#define BGE_LPMBX_GEN6_HI 0x5850 1549#define BGE_LPMBX_GEN6_LO 0x5854 1550#define BGE_LPMBX_GEN7_HI 0x5858 1551#define BGE_LPMBX_GEN7_LO 0x585C 1552#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1553#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1554#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1555#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1556#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1557#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1558#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1559#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1560#define BGE_LPMBX_RX_CONS0_HI 0x5880 1561#define BGE_LPMBX_RX_CONS0_LO 0x5884 1562#define BGE_LPMBX_RX_CONS1_HI 0x5888 1563#define BGE_LPMBX_RX_CONS1_LO 0x588C 1564#define BGE_LPMBX_RX_CONS2_HI 0x5890 1565#define BGE_LPMBX_RX_CONS2_LO 0x5894 1566#define BGE_LPMBX_RX_CONS3_HI 0x5898 1567#define BGE_LPMBX_RX_CONS3_LO 0x589C 1568#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1569#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1570#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1571#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1572#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1573#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1574#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1575#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1576#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1577#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1578#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1579#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1580#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1581#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1582#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1583#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1584#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1585#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1586#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1587#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1588#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1589#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1590#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1591#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1592#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1593#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1594#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1595#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1596#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1597#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1598#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1599#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1600#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1601#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1602#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1603#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1604#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1605#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1606#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1607#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1608#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1609#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1610#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1611#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1612#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1613#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1614#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1615#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1616#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1617#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1618#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1619#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1620#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1621#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1622#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1623#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1624#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1625#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1626#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1627#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1628#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1629#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1630#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1631#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1632#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1633#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1634#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1635#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1636#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1637#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1638#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1639#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1640#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1641#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1642#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1643#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1644#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1645#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1646#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1647#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1648#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1649#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1650#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1651#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1652#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1653#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1654#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1655#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1656 1657/* 1658 * Flow throw Queue reset register 1659 */ 1660#define BGE_FTQ_RESET 0x5C00 1661 1662#define BGE_FTQRESET_DMAREAD 0x00000002 1663#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1664#define BGE_FTQRESET_DMADONE 0x00000010 1665#define BGE_FTQRESET_SBDC 0x00000020 1666#define BGE_FTQRESET_SDI 0x00000040 1667#define BGE_FTQRESET_WDMA 0x00000080 1668#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1669#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1670#define BGE_FTQRESET_SDC 0x00000400 1671#define BGE_FTQRESET_HCC 0x00000800 1672#define BGE_FTQRESET_TXFIFO 0x00001000 1673#define BGE_FTQRESET_MBC 0x00002000 1674#define BGE_FTQRESET_RBDC 0x00004000 1675#define BGE_FTQRESET_RXLP 0x00008000 1676#define BGE_FTQRESET_RDBDI 0x00010000 1677#define BGE_FTQRESET_RDC 0x00020000 1678#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1679 1680/* 1681 * Message Signaled Interrupt registers 1682 */ 1683#define BGE_MSI_MODE 0x6000 1684#define BGE_MSI_STATUS 0x6004 1685#define BGE_MSI_FIFOACCESS 0x6008 1686 1687/* MSI mode register */ 1688#define BGE_MSIMODE_RESET 0x00000001 1689#define BGE_MSIMODE_ENABLE 0x00000002 1690#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1691#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1692#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1693#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1694#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1695 1696/* MSI status register */ 1697#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1698#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1699#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1700#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1701#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1702 1703 1704/* 1705 * DMA Completion registers 1706 */ 1707#define BGE_DMAC_MODE 0x6400 1708 1709/* DMA Completion mode register */ 1710#define BGE_DMACMODE_RESET 0x00000001 1711#define BGE_DMACMODE_ENABLE 0x00000002 1712 1713 1714/* 1715 * General control registers. 1716 */ 1717#define BGE_MODE_CTL 0x6800 1718#define BGE_MISC_CFG 0x6804 1719#define BGE_MISC_LOCAL_CTL 0x6808 1720#define BGE_CPU_EVENT 0x6810 1721#define BGE_EE_ADDR 0x6838 1722#define BGE_EE_DATA 0x683C 1723#define BGE_EE_CTL 0x6840 1724#define BGE_MDI_CTL 0x6844 1725#define BGE_EE_DELAY 0x6848 1726 1727#define BGE_FASTBOOT_PC 0x6894 1728 1729/* 1730 * NVRAM Control registers 1731 */ 1732 1733#define BGE_NVRAM_CMD 0x7000 1734#define BGE_NVRAM_STAT 0x7004 1735#define BGE_NVRAM_WRDATA 0x7008 1736#define BGE_NVRAM_ADDR 0x700c 1737#define BGE_NVRAM_RDDATA 0x7010 1738#define BGE_NVRAM_CFG1 0x7014 1739#define BGE_NVRAM_CFG2 0x7018 1740#define BGE_NVRAM_CFG3 0x701c 1741#define BGE_NVRAM_SWARB 0x7020 1742#define BGE_NVRAM_ACCESS 0x7024 1743#define BGE_NVRAM_WRITE1 0x7028 1744 1745 1746#define BGE_NVRAMCMD_RESET 0x00000001 1747#define BGE_NVRAMCMD_DONE 0x00000008 1748#define BGE_NVRAMCMD_START 0x00000010 1749#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1750#define BGE_NVRAMCMD_ERASE 0x00000040 1751#define BGE_NVRAMCMD_FIRST 0x00000080 1752#define BGE_NVRAMCMD_LAST 0x00000100 1753 1754#define BGE_NVRAM_READCMD \ 1755 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1756 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1757#define BGE_NVRAM_WRITECMD \ 1758 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1759 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1760 1761#define BGE_NVRAMSWARB_SET0 0x00000001 1762#define BGE_NVRAMSWARB_SET1 0x00000002 1763#define BGE_NVRAMSWARB_SET2 0x00000003 1764#define BGE_NVRAMSWARB_SET3 0x00000004 1765#define BGE_NVRAMSWARB_CLR0 0x00000010 1766#define BGE_NVRAMSWARB_CLR1 0x00000020 1767#define BGE_NVRAMSWARB_CLR2 0x00000040 1768#define BGE_NVRAMSWARB_CLR3 0x00000080 1769#define BGE_NVRAMSWARB_GNT0 0x00000100 1770#define BGE_NVRAMSWARB_GNT1 0x00000200 1771#define BGE_NVRAMSWARB_GNT2 0x00000400 1772#define BGE_NVRAMSWARB_GNT3 0x00000800 1773#define BGE_NVRAMSWARB_REQ0 0x00001000 1774#define BGE_NVRAMSWARB_REQ1 0x00002000 1775#define BGE_NVRAMSWARB_REQ2 0x00004000 1776#define BGE_NVRAMSWARB_REQ3 0x00008000 1777 1778#define BGE_NVRAMACC_ENABLE 0x00000001 1779#define BGE_NVRAMACC_WRENABLE 0x00000002 1780 1781/* 1782 * TLP Control Register 1783 * Applicable to BCM5721 and BCM5751 only 1784 */ 1785#define BGE_TLP_CONTROL_REG 0x7c00 1786#define BGE_TLP_DATA_FIFO_PROTECT 0x02000000 1787 1788/* 1789 * PHY Test Control Register 1790 * Applicable to BCM5721 and BCM5751 only 1791 */ 1792#define BGE_PHY_TEST_CTRL_REG 0x7e2c 1793#define BGE_PHY_PCIE_SCRAM_MODE 0x0020 1794#define BGE_PHY_PCIE_LTASS_MODE 0x0040 1795 1796/* Mode control register */ 1797#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1798#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1799#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1800#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1801#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1802#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1803#define BGE_MODECTL_NO_RX_CRC 0x00000400 1804#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1805#define BGE_MODECTL_NO_TX_INTR 0x00002000 1806#define BGE_MODECTL_NO_RX_INTR 0x00004000 1807#define BGE_MODECTL_FORCE_PCI32 0x00008000 1808#define BGE_MODECTL_STACKUP 0x00010000 1809#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1810#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1811#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1812#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1813#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1814#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1815#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1816#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1817#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1818#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1819 1820/* Misc. config register */ 1821#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1822#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1823#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1824#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1825#define BGE_MISCCFG_BOARD_ID_MASK 0x0001e000 1826#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1827#define BGE_MISCCFG_KEEP_GPHY_POWER 0x04000000 1828 1829#define BGE_32BITTIME_66MHZ (0x41 << 1) 1830 1831/* Misc. Local Control */ 1832#define BGE_MLC_INTR_STATE 0x00000001 1833#define BGE_MLC_INTR_CLR 0x00000002 1834#define BGE_MLC_INTR_SET 0x00000004 1835#define BGE_MLC_INTR_ONATTN 0x00000008 1836#define BGE_MLC_MISCIO_IN0 0x00000100 1837#define BGE_MLC_MISCIO_IN1 0x00000200 1838#define BGE_MLC_MISCIO_IN2 0x00000400 1839#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1840#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1841#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1842#define BGE_MLC_MISCIO_OUT0 0x00004000 1843#define BGE_MLC_MISCIO_OUT1 0x00008000 1844#define BGE_MLC_MISCIO_OUT2 0x00010000 1845#define BGE_MLC_EXTRAM_ENB 0x00020000 1846#define BGE_MLC_SRAM_SIZE 0x001C0000 1847#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1848#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1849#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1850#define BGE_MLC_AUTO_EEPROM 0x01000000 1851 1852#define BGE_SSRAMSIZE_256KB 0x00000000 1853#define BGE_SSRAMSIZE_512KB 0x00040000 1854#define BGE_SSRAMSIZE_1MB 0x00080000 1855#define BGE_SSRAMSIZE_2MB 0x000C0000 1856#define BGE_SSRAMSIZE_4MB 0x00100000 1857#define BGE_SSRAMSIZE_8MB 0x00140000 1858#define BGE_SSRAMSIZE_16M 0x00180000 1859 1860/* EEPROM address register */ 1861#define BGE_EEADDR_ADDRESS 0x0000FFFC 1862#define BGE_EEADDR_HALFCLK 0x01FF0000 1863#define BGE_EEADDR_START 0x02000000 1864#define BGE_EEADDR_DEVID 0x1C000000 1865#define BGE_EEADDR_RESET 0x20000000 1866#define BGE_EEADDR_DONE 0x40000000 1867#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1868 1869#define BGE_EEDEVID(x) ((x & 7) << 26) 1870#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1871#define BGE_HALFCLK_384SCL 0x60 1872#define BGE_EE_READCMD \ 1873 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1874 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1875#define BGE_EE_WRCMD \ 1876 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1877 BGE_EEADDR_START|BGE_EEADDR_DONE) 1878 1879/* EEPROM Control register */ 1880#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1881#define BGE_EECTL_CLKOUT 0x00000002 1882#define BGE_EECTL_CLKIN 0x00000004 1883#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1884#define BGE_EECTL_DATAOUT 0x00000010 1885#define BGE_EECTL_DATAIN 0x00000020 1886 1887/* MDI (MII/GMII) access register */ 1888#define BGE_MDI_DATA 0x00000001 1889#define BGE_MDI_DIR 0x00000002 1890#define BGE_MDI_SEL 0x00000004 1891#define BGE_MDI_CLK 0x00000008 1892 1893#define BGE_MEMWIN_START 0x00008000 1894#define BGE_MEMWIN_END 0x0000FFFF 1895 1896 1897#define BGE_MEMWIN_READ(pc, tag, x, val) \ 1898 do { \ 1899 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1900 (0xFFFF0000 & x)); \ 1901 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1902 } while(0) 1903 1904#define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 1905 do { \ 1906 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1907 (0xFFFF0000 & x)); \ 1908 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1909 } while(0) 1910 1911/* 1912 * This magic number is written to the firmware mailbox at 0xb50 1913 * before a software reset is issued. After the internal firmware 1914 * has completed its initialization it will write the opposite of 1915 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 1916 * driver to synchronize with the firmware. 1917 */ 1918#define BGE_MAGIC_NUMBER 0x4B657654 1919 1920typedef struct { 1921 u_int32_t bge_addr_hi; 1922 u_int32_t bge_addr_lo; 1923} bge_hostaddr; 1924#define BGE_HOSTADDR(x,y) \ 1925 do { \ 1926 (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 1927 if (sizeof(bus_addr_t) == 8) \ 1928 (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 1929 else \ 1930 (x).bge_addr_hi = 0; \ 1931 } while(0) 1932 1933/* Ring control block structure */ 1934struct bge_rcb { 1935 bge_hostaddr bge_hostaddr; 1936 u_int32_t bge_maxlen_flags; 1937 u_int32_t bge_nicaddr; 1938}; 1939 1940#define RCB_WRITE_4(sc, rcb, offset, val) \ 1941 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1942 rcb + offsetof(struct bge_rcb, offset), val) 1943 1944#define RCB_WRITE_2(sc, rcb, offset, val) \ 1945 bus_space_write_2(sc->bge_btag, sc->bge_bhandle, \ 1946 rcb + offsetof(struct bge_rcb, offset), val) 1947 1948#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1949 1950#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1951#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1952 1953struct bge_tx_bd { 1954 bge_hostaddr bge_addr; 1955#if BYTE_ORDER == LITTLE_ENDIAN 1956 u_int16_t bge_flags; 1957 u_int16_t bge_len; 1958 u_int16_t bge_vlan_tag; 1959 u_int16_t bge_rsvd; 1960#else 1961 u_int16_t bge_len; 1962 u_int16_t bge_flags; 1963 u_int16_t bge_rsvd; 1964 u_int16_t bge_vlan_tag; 1965#endif 1966}; 1967 1968#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1969#define BGE_TXBDFLAG_IP_CSUM 0x0002 1970#define BGE_TXBDFLAG_END 0x0004 1971#define BGE_TXBDFLAG_IP_FRAG 0x0008 1972#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1973#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1974#define BGE_TXBDFLAG_COAL_NOW 0x0080 1975#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1976#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1977#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1978#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1979#define BGE_TXBDFLAG_NO_CRC 0x8000 1980 1981#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1982 BGE_SEND_RING_1_TO_4 + \ 1983 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1984 1985struct bge_rx_bd { 1986 bge_hostaddr bge_addr; 1987#if BYTE_ORDER == LITTLE_ENDIAN 1988 u_int16_t bge_len; 1989 u_int16_t bge_idx; 1990 u_int16_t bge_flags; 1991 u_int16_t bge_type; 1992 u_int16_t bge_tcp_udp_csum; 1993 u_int16_t bge_ip_csum; 1994 u_int16_t bge_vlan_tag; 1995 u_int16_t bge_error_flag; 1996#else 1997 u_int16_t bge_idx; 1998 u_int16_t bge_len; 1999 u_int16_t bge_type; 2000 u_int16_t bge_flags; 2001 u_int16_t bge_ip_csum; 2002 u_int16_t bge_tcp_udp_csum; 2003 u_int16_t bge_error_flag; 2004 u_int16_t bge_vlan_tag; 2005#endif 2006 u_int32_t bge_rsvd; 2007 u_int32_t bge_opaque; 2008}; 2009 2010struct bge_ext_rx_bd { 2011 bge_hostaddr bge_addr1; 2012 bge_hostaddr bge_addr2; 2013 bge_hostaddr bge_addr3; 2014#if BYTE_ORDER == LITTLE_ENDIAN 2015 u_int16_t bge_len2; 2016 u_int16_t bge_len1; 2017 u_int16_t bge_rsvd; 2018 u_int16_t bge_len3; 2019#else 2020 u_int16_t bge_len1; 2021 u_int16_t bge_len2; 2022 u_int16_t bge_len3; 2023 u_int16_t bge_rsvd; 2024#endif 2025 struct bge_rx_bd bge_bd; 2026}; 2027 2028#define BGE_RXBDFLAG_END 0x0004 2029#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2030#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2031#define BGE_RXBDFLAG_ERROR 0x0400 2032#define BGE_RXBDFLAG_MINI_RING 0x0800 2033#define BGE_RXBDFLAG_IP_CSUM 0x1000 2034#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2035#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2036 2037#define BGE_RXERRFLAG_BAD_CRC 0x0001 2038#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2039#define BGE_RXERRFLAG_LINK_LOST 0x0004 2040#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2041#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2042#define BGE_RXERRFLAG_RUNT 0x0020 2043#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2044#define BGE_RXERRFLAG_GIANT 0x0080 2045 2046struct bge_sts_idx { 2047#if BYTE_ORDER == LITTLE_ENDIAN 2048 u_int16_t bge_rx_prod_idx; 2049 u_int16_t bge_tx_cons_idx; 2050#else 2051 u_int16_t bge_tx_cons_idx; 2052 u_int16_t bge_rx_prod_idx; 2053#endif 2054}; 2055 2056struct bge_status_block { 2057 u_int32_t bge_status; 2058 u_int32_t bge_rsvd0; 2059#if BYTE_ORDER == LITTLE_ENDIAN 2060 u_int16_t bge_rx_jumbo_cons_idx; 2061 u_int16_t bge_rx_std_cons_idx; 2062 u_int16_t bge_rx_mini_cons_idx; 2063 u_int16_t bge_rsvd1; 2064#else 2065 u_int16_t bge_rx_std_cons_idx; 2066 u_int16_t bge_rx_jumbo_cons_idx; 2067 u_int16_t bge_rsvd1; 2068 u_int16_t bge_rx_mini_cons_idx; 2069#endif 2070 struct bge_sts_idx bge_idx[16]; 2071}; 2072 2073#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 2074#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 2075 2076#define BGE_STATFLAG_UPDATED 0x00000001 2077#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2078#define BGE_STATFLAG_ERROR 0x00000004 2079 2080/* 2081 * SysKonnect Subsystem IDs 2082 */ 2083#define SK_SUBSYSID_9D41 0x4441 2084 2085/* 2086 * Dell PCI vendor ID 2087 */ 2088#define DELL_VENDORID 0x1028 2089 2090/* 2091 * Offset of MAC address inside EEPROM. 2092 */ 2093#define BGE_EE_MAC_OFFSET 0x7C 2094#define BGE_EE_MAC_OFFSET_5906 0x10 2095#define BGE_EE_HWCFG_OFFSET 0xC8 2096 2097#define BGE_HWCFG_VOLTAGE 0x00000003 2098#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2099#define BGE_HWCFG_MEDIA 0x00000030 2100#define BGE_HWCFG_ASF 0x00000080 2101 2102#define BGE_VOLTAGE_1POINT3 0x00000000 2103#define BGE_VOLTAGE_1POINT8 0x00000001 2104 2105#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2106#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2107#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2108 2109#define BGE_MEDIA_UNSPEC 0x00000000 2110#define BGE_MEDIA_COPPER 0x00000010 2111#define BGE_MEDIA_FIBER 0x00000020 2112 2113#define BGE_TICKS_PER_SEC 1000000 2114 2115/* 2116 * Ring size constants. 2117 */ 2118#define BGE_EVENT_RING_CNT 256 2119#define BGE_CMD_RING_CNT 64 2120#define BGE_STD_RX_RING_CNT 512 2121#define BGE_JUMBO_RX_RING_CNT 256 2122#define BGE_MINI_RX_RING_CNT 1024 2123#define BGE_RETURN_RING_CNT 1024 2124 2125/* 5705 has smaller return ring size */ 2126#define BGE_RETURN_RING_CNT_5705 512 2127 2128/* 2129 * Possible TX ring sizes. 2130 */ 2131#define BGE_TX_RING_CNT_128 128 2132#define BGE_TX_RING_BASE_128 0x3800 2133 2134#define BGE_TX_RING_CNT_256 256 2135#define BGE_TX_RING_BASE_256 0x3000 2136 2137#define BGE_TX_RING_CNT_512 512 2138#define BGE_TX_RING_BASE_512 0x2000 2139 2140#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2141#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2142 2143/* 2144 * Tigon III statistics counters. 2145 */ 2146/* Statistics maintained MAC Receive block. */ 2147struct bge_rx_mac_stats { 2148 bge_hostaddr ifHCInOctets; 2149 bge_hostaddr Reserved1; 2150 bge_hostaddr etherStatsFragments; 2151 bge_hostaddr ifHCInUcastPkts; 2152 bge_hostaddr ifHCInMulticastPkts; 2153 bge_hostaddr ifHCInBroadcastPkts; 2154 bge_hostaddr dot3StatsFCSErrors; 2155 bge_hostaddr dot3StatsAlignmentErrors; 2156 bge_hostaddr xonPauseFramesReceived; 2157 bge_hostaddr xoffPauseFramesReceived; 2158 bge_hostaddr macControlFramesReceived; 2159 bge_hostaddr xoffStateEntered; 2160 bge_hostaddr dot3StatsFramesTooLong; 2161 bge_hostaddr etherStatsJabbers; 2162 bge_hostaddr etherStatsUndersizePkts; 2163 bge_hostaddr inRangeLengthError; 2164 bge_hostaddr outRangeLengthError; 2165 bge_hostaddr etherStatsPkts64Octets; 2166 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2167 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2168 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2169 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2170 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2171 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2172 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2173 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2174 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2175}; 2176 2177/* Statistics maintained MAC Transmit block. */ 2178struct bge_tx_mac_stats { 2179 bge_hostaddr ifHCOutOctets; 2180 bge_hostaddr Reserved2; 2181 bge_hostaddr etherStatsCollisions; 2182 bge_hostaddr outXonSent; 2183 bge_hostaddr outXoffSent; 2184 bge_hostaddr flowControlDone; 2185 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2186 bge_hostaddr dot3StatsSingleCollisionFrames; 2187 bge_hostaddr dot3StatsMultipleCollisionFrames; 2188 bge_hostaddr dot3StatsDeferredTransmissions; 2189 bge_hostaddr Reserved3; 2190 bge_hostaddr dot3StatsExcessiveCollisions; 2191 bge_hostaddr dot3StatsLateCollisions; 2192 bge_hostaddr dot3Collided2Times; 2193 bge_hostaddr dot3Collided3Times; 2194 bge_hostaddr dot3Collided4Times; 2195 bge_hostaddr dot3Collided5Times; 2196 bge_hostaddr dot3Collided6Times; 2197 bge_hostaddr dot3Collided7Times; 2198 bge_hostaddr dot3Collided8Times; 2199 bge_hostaddr dot3Collided9Times; 2200 bge_hostaddr dot3Collided10Times; 2201 bge_hostaddr dot3Collided11Times; 2202 bge_hostaddr dot3Collided12Times; 2203 bge_hostaddr dot3Collided13Times; 2204 bge_hostaddr dot3Collided14Times; 2205 bge_hostaddr dot3Collided15Times; 2206 bge_hostaddr ifHCOutUcastPkts; 2207 bge_hostaddr ifHCOutMulticastPkts; 2208 bge_hostaddr ifHCOutBroadcastPkts; 2209 bge_hostaddr dot3StatsCarrierSenseErrors; 2210 bge_hostaddr ifOutDiscards; 2211 bge_hostaddr ifOutErrors; 2212}; 2213 2214/* Stats counters access through registers */ 2215struct bge_mac_stats_regs { 2216 u_int32_t ifHCOutOctets; 2217 u_int32_t Reserved0; 2218 u_int32_t etherStatsCollisions; 2219 u_int32_t outXonSent; 2220 u_int32_t outXoffSent; 2221 u_int32_t Reserved1; 2222 u_int32_t dot3StatsInternalMacTransmitErrors; 2223 u_int32_t dot3StatsSingleCollisionFrames; 2224 u_int32_t dot3StatsMultipleCollisionFrames; 2225 u_int32_t dot3StatsDeferredTransmissions; 2226 u_int32_t Reserved2; 2227 u_int32_t dot3StatsExcessiveCollisions; 2228 u_int32_t dot3StatsLateCollisions; 2229 u_int32_t Reserved3[14]; 2230 u_int32_t ifHCOutUcastPkts; 2231 u_int32_t ifHCOutMulticastPkts; 2232 u_int32_t ifHCOutBroadcastPkts; 2233 u_int32_t Reserved4[2]; 2234 u_int32_t ifHCInOctets; 2235 u_int32_t Reserved5; 2236 u_int32_t etherStatsFragments; 2237 u_int32_t ifHCInUcastPkts; 2238 u_int32_t ifHCInMulticastPkts; 2239 u_int32_t ifHCInBroadcastPkts; 2240 u_int32_t dot3StatsFCSErrors; 2241 u_int32_t dot3StatsAlignmentErrors; 2242 u_int32_t xonPauseFramesReceived; 2243 u_int32_t xoffPauseFramesReceived; 2244 u_int32_t macControlFramesReceived; 2245 u_int32_t xoffStateEntered; 2246 u_int32_t dot3StatsFramesTooLong; 2247 u_int32_t etherStatsJabbers; 2248 u_int32_t etherStatsUndersizePkts; 2249}; 2250 2251struct bge_stats { 2252 u_int8_t Reserved0[256]; 2253 2254 /* Statistics maintained by Receive MAC. */ 2255 struct bge_rx_mac_stats rxstats; 2256 2257 bge_hostaddr Unused1[37]; 2258 2259 /* Statistics maintained by Transmit MAC. */ 2260 struct bge_tx_mac_stats txstats; 2261 2262 bge_hostaddr Unused2[31]; 2263 2264 /* Statistics maintained by Receive List Placement. */ 2265 bge_hostaddr COSIfHCInPkts[16]; 2266 bge_hostaddr COSFramesDroppedDueToFilters; 2267 bge_hostaddr nicDmaWriteQueueFull; 2268 bge_hostaddr nicDmaWriteHighPriQueueFull; 2269 bge_hostaddr nicNoMoreRxBDs; 2270 bge_hostaddr ifInDiscards; 2271 bge_hostaddr ifInErrors; 2272 bge_hostaddr nicRecvThresholdHit; 2273 2274 bge_hostaddr Unused3[9]; 2275 2276 /* Statistics maintained by Send Data Initiator. */ 2277 bge_hostaddr COSIfHCOutPkts[16]; 2278 bge_hostaddr nicDmaReadQueueFull; 2279 bge_hostaddr nicDmaReadHighPriQueueFull; 2280 bge_hostaddr nicSendDataCompQueueFull; 2281 2282 /* Statistics maintained by Host Coalescing. */ 2283 bge_hostaddr nicRingSetSendProdIndex; 2284 bge_hostaddr nicRingStatusUpdate; 2285 bge_hostaddr nicInterrupts; 2286 bge_hostaddr nicAvoidedInterrupts; 2287 bge_hostaddr nicSendThresholdHit; 2288 2289 u_int8_t Reserved4[320]; 2290}; 2291 2292/* 2293 * Tigon general information block. This resides in host memory 2294 * and contains the status counters, ring control blocks and 2295 * producer pointers. 2296 */ 2297 2298struct bge_gib { 2299 struct bge_stats bge_stats; 2300 struct bge_rcb bge_tx_rcb[16]; 2301 struct bge_rcb bge_std_rx_rcb; 2302 struct bge_rcb bge_jumbo_rx_rcb; 2303 struct bge_rcb bge_mini_rx_rcb; 2304 struct bge_rcb bge_return_rcb; 2305}; 2306 2307/* 2308 * NOTE! On the Alpha, we have an alignment constraint. 2309 * The first thing in the packet is a 14-byte Ethernet header. 2310 * This means that the packet is misaligned. To compensate, 2311 * we actually offset the data 2 bytes into the cluster. This 2312 * alignes the packet after the Ethernet header at a 32-bit 2313 * boundary. 2314 */ 2315 2316#define BGE_JUMBO_FRAMELEN 9022 2317#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 2318#define BGE_PAGE_SIZE PAGE_SIZE 2319 2320/* 2321 * Other utility macros. 2322 */ 2323#define BGE_INC(x, y) (x) = (x + 1) % y 2324 2325/* 2326 * Vital product data and structures. 2327 */ 2328#define BGE_VPD_FLAG 0x8000 2329 2330#define VPD_RES_ID 0x82 /* ID string */ 2331#define VPD_RES_READ 0x90 /* start of read only area */ 2332#define VPD_RES_WRITE 0x81 /* start of read/write area */ 2333#define VPD_RES_END 0x78 /* end tag */ 2334 2335/* 2336 * Register access macros. The Tigon always uses memory mapped register 2337 * accesses and all registers must be accessed with 32 bit operations. 2338 */ 2339 2340#define CSR_WRITE_4(sc, reg, val) \ 2341 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2342 2343#define CSR_READ_4(sc, reg) \ 2344 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2345 2346#define BGE_SETBIT(sc, reg, x) \ 2347 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2348#define BGE_CLRBIT(sc, reg, x) \ 2349 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2350 2351#define PCI_SETBIT(pc, tag, reg, x) \ 2352 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 2353#define PCI_CLRBIT(pc, tag, reg, x) \ 2354 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 2355 2356/* 2357 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2358 * values are tuneable. They control the actual amount of buffers 2359 * allocated for the standard, mini and jumbo receive rings. 2360 */ 2361 2362#define BGE_SSLOTS 256 2363#define BGE_MSLOTS 256 2364#define BGE_JSLOTS 384 2365 2366#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2367#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2368 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2369 2370/* 2371 * Ring structures. Most of these reside in host memory and we tell 2372 * the NIC where they are via the ring control blocks. The exceptions 2373 * are the tx and command rings, which live in NIC memory and which 2374 * we access via the shared memory window. 2375 */ 2376struct bge_ring_data { 2377 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2378 struct bge_ext_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2379 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2380 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2381 struct bge_status_block bge_status_block; 2382 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2383 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2384 struct bge_gib bge_info; 2385}; 2386 2387#define BGE_RING_DMA_ADDR(sc, offset) \ 2388 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2389 offsetof(struct bge_ring_data, offset)) 2390 2391/* 2392 * Number of DMA segments in a TxCB. Note that this is carefully 2393 * chosen to make the total struct size an even power of two. It's 2394 * critical that no TxCB be split across a page boundary since 2395 * no attempt is made to allocate physically contiguous memory. 2396 * 2397 */ 2398#ifdef __LP64__ 2399#define BGE_NTXSEG 30 2400#else 2401#define BGE_NTXSEG 31 2402#endif 2403 2404/* 2405 * Mbuf pointers. We need these to keep track of the virtual addresses 2406 * of our mbuf chains since we can only convert from physical to virtual, 2407 * not the other way around. 2408 */ 2409struct bge_chain_data { 2410 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2411 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2412 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2413 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2414 bus_dmamap_t bge_tx_map[BGE_TX_RING_CNT]; 2415 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2416 bus_dmamap_t bge_rx_jumbo_map[BGE_JUMBO_RX_RING_CNT]; 2417}; 2418 2419struct bge_type { 2420 u_int16_t bge_vid; 2421 u_int16_t bge_did; 2422 char *bge_name; 2423}; 2424 2425#define BGE_TIMEOUT 100000 2426#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2427 2428struct txdmamap_pool_entry { 2429 bus_dmamap_t dmamap; 2430 SLIST_ENTRY(txdmamap_pool_entry) link; 2431}; 2432 2433#define ASF_ENABLE 1 2434#define ASF_NEW_HANDSHAKE 2 2435#define ASF_STACKUP 4 2436 2437struct bge_softc { 2438 struct device bge_dev; 2439 struct arpcom arpcom; /* interface info */ 2440 bus_space_handle_t bge_bhandle; 2441 bus_space_tag_t bge_btag; 2442 void *bge_intrhand; 2443 struct pci_attach_args bge_pa; 2444 struct mii_data bge_mii; 2445 struct ifmedia bge_ifmedia; /* media info */ 2446 u_int32_t bge_flags; 2447#define BGE_TXRING_VALID 0x00000001 2448#define BGE_RXRING_VALID 0x00000002 2449#define BGE_JUMBO_RXRING_VALID 0x00000004 2450#define BGE_RX_ALIGNBUG 0x00000008 2451#define BGE_NO_3LED 0x00000010 2452#define BGE_PCIX 0x00000020 2453#define BGE_PCIE 0x00000040 2454#define BGE_ASF_MODE 0x00000080 2455#define BGE_NO_EEPROM 0x00000100 2456#define BGE_JUMBO_CAP 0x00000200 2457#define BGE_10_100_ONLY 0x00000400 2458#define BGE_PHY_FIBER_TBI 0x00000800 2459#define BGE_PHY_FIBER_MII 0x00001000 2460#define BGE_PHY_CRC_BUG 0x00002000 2461#define BGE_PHY_ADC_BUG 0x00004000 2462#define BGE_PHY_5704_A0_BUG 0x00008000 2463#define BGE_PHY_JITTER_BUG 0x00010000 2464#define BGE_PHY_BER_BUG 0x00020000 2465#define BGE_PHY_ADJUST_TRIM 0x00040000 2466#define BGE_NO_ETH_WIRE_SPEED 0x00080000 2467#define BGE_IS_5788 0x00100000 2468 2469 bus_dma_tag_t bge_dmatag; 2470 u_int32_t bge_chipid; 2471 struct bge_ring_data *bge_rdata; /* rings */ 2472 struct bge_chain_data bge_cdata; /* mbufs */ 2473 bus_dmamap_t bge_ring_map; 2474 u_int16_t bge_tx_saved_considx; 2475 u_int16_t bge_rx_saved_considx; 2476 u_int16_t bge_ev_saved_considx; 2477 u_int16_t bge_return_ring_cnt; 2478 u_int32_t bge_tx_prodidx; 2479 u_int16_t bge_std; /* current std ring head */ 2480 int bge_std_cnt; 2481 u_int16_t bge_jumbo; /* current jumo ring head */ 2482 int bge_jumbo_cnt; 2483 u_int32_t bge_stat_ticks; 2484 u_int32_t bge_rx_coal_ticks; 2485 u_int32_t bge_tx_coal_ticks; 2486 u_int32_t bge_rx_max_coal_bds; 2487 u_int32_t bge_tx_max_coal_bds; 2488 u_int32_t bge_tx_buf_ratio; 2489 u_int32_t bge_sts; 2490#define BGE_STS_LINK 0x00000001 /* MAC link status */ 2491#define BGE_STS_LINK_EVT 0x00000002 /* pending link event */ 2492#define BGE_STS_AUTOPOLL 0x00000004 /* PHY auto-polling */ 2493#define BGE_STS_BIT(sc, x) ((sc)->bge_sts & (x)) 2494#define BGE_STS_SETBIT(sc, x) ((sc)->bge_sts |= (x)) 2495#define BGE_STS_CLRBIT(sc, x) ((sc)->bge_sts &= ~(x)) 2496 int bge_flowflags; 2497 int bge_txcnt; 2498 struct timeout bge_timeout; 2499 struct timeout bge_rxtimeout; 2500 void *sc_powerhook; 2501 void *sc_shutdownhook; 2502 u_int32_t bge_rx_discards; 2503 u_int32_t bge_tx_discards; 2504 u_int32_t bge_rx_inerrors; 2505 u_int32_t bge_rx_overruns; 2506 u_int32_t bge_tx_collisions; 2507 SLIST_HEAD(, txdmamap_pool_entry) txdma_list; 2508 struct txdmamap_pool_entry *txdma[BGE_TX_RING_CNT]; 2509}; 2510