if_bgereg.h revision 1.8
1/* $OpenBSD: if_bgereg.h,v 1.8 2004/03/19 21:57:36 miod Exp $ */ 2/* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bgereg.h,v 1.11 2002/11/14 23:54:50 sam Exp $ 35 */ 36 37/* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65#define BGE_PAGE_ZERO 0x00000000 66#define BGE_PAGE_ZERO_END 0x000000FF 67#define BGE_SEND_RING_RCB 0x00000100 68#define BGE_SEND_RING_RCB_END 0x000001FF 69#define BGE_RX_RETURN_RING_RCB 0x00000200 70#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 71#define BGE_STATS_BLOCK 0x00000300 72#define BGE_STATS_BLOCK_END 0x00000AFF 73#define BGE_STATUS_BLOCK 0x00000B00 74#define BGE_STATUS_BLOCK_END 0x00000B4F 75#define BGE_SOFTWARE_GENCOMM 0x00000B50 76#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 77#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 78#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 79#define BGE_UNMAPPED 0x00001000 80#define BGE_UNMAPPED_END 0x00001FFF 81#define BGE_DMA_DESCRIPTORS 0x00002000 82#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 83#define BGE_SEND_RING_1_TO_4 0x00004000 84#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 85 86/* Mappings for internal memory configuration */ 87#define BGE_STD_RX_RINGS 0x00006000 88#define BGE_STD_RX_RINGS_END 0x00006FFF 89#define BGE_JUMBO_RX_RINGS 0x00007000 90#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 91#define BGE_BUFFPOOL_1 0x00008000 92#define BGE_BUFFPOOL_1_END 0x0000FFFF 93#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 94#define BGE_BUFFPOOL_2_END 0x00017FFF 95#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 96#define BGE_BUFFPOOL_3_END 0x0001FFFF 97 98/* Mappings for external SSRAM configurations */ 99#define BGE_SEND_RING_5_TO_6 0x00006000 100#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 101#define BGE_SEND_RING_7_TO_8 0x00007000 102#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 103#define BGE_SEND_RING_9_TO_16 0x00008000 104#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 105#define BGE_EXT_STD_RX_RINGS 0x0000C000 106#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 107#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 108#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 109#define BGE_MINI_RX_RINGS 0x0000E000 110#define BGE_MINI_RX_RINGS_END 0x0000FFFF 111#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 112#define BGE_AVAIL_REGION1_END 0x00017FFF 113#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 114#define BGE_AVAIL_REGION2_END 0x0001FFFF 115#define BGE_EXT_SSRAM 0x00020000 116#define BGE_EXT_SSRAM_END 0x000FFFFF 117 118 119/* 120 * BCM570x register offsets. These are memory mapped registers 121 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 122 * Each register must be accessed using 32 bit operations. 123 * 124 * All registers are accessed through a 32K shared memory block. 125 * The first group of registers are actually copies of the PCI 126 * configuration space registers. 127 */ 128 129/* 130 * PCI registers defined in the PCI 2.2 spec. 131 */ 132#define BGE_PCI_VID 0x00 133#define BGE_PCI_DID 0x02 134#define BGE_PCI_CMD 0x04 135#define BGE_PCI_STS 0x06 136#define BGE_PCI_REV 0x08 137#define BGE_PCI_CLASS 0x09 138#define BGE_PCI_CACHESZ 0x0C 139#define BGE_PCI_LATTIMER 0x0D 140#define BGE_PCI_HDRTYPE 0x0E 141#define BGE_PCI_BIST 0x0F 142#define BGE_PCI_BAR0 0x10 143#define BGE_PCI_BAR1 0x14 144#define BGE_PCI_SUBSYS 0x2C 145#define BGE_PCI_SUBVID 0x2E 146#define BGE_PCI_ROMBASE 0x30 147#define BGE_PCI_CAPPTR 0x34 148#define BGE_PCI_INTLINE 0x3C 149#define BGE_PCI_INTPIN 0x3D 150#define BGE_PCI_MINGNT 0x3E 151#define BGE_PCI_MAXLAT 0x3F 152#define BGE_PCI_PCIXCAP 0x40 153#define BGE_PCI_NEXTPTR_PM 0x41 154#define BGE_PCI_PCIX_CMD 0x42 155#define BGE_PCI_PCIX_STS 0x44 156#define BGE_PCI_PWRMGMT_CAPID 0x48 157#define BGE_PCI_NEXTPTR_VPD 0x49 158#define BGE_PCI_PWRMGMT_CAPS 0x4A 159#define BGE_PCI_PWRMGMT_CMD 0x4C 160#define BGE_PCI_PWRMGMT_STS 0x4D 161#define BGE_PCI_PWRMGMT_DATA 0x4F 162#define BGE_PCI_VPD_CAPID 0x50 163#define BGE_PCI_NEXTPTR_MSI 0x51 164#define BGE_PCI_VPD_ADDR 0x52 165#define BGE_PCI_VPD_DATA 0x54 166#define BGE_PCI_MSI_CAPID 0x58 167#define BGE_PCI_NEXTPTR_NONE 0x59 168#define BGE_PCI_MSI_CTL 0x5A 169#define BGE_PCI_MSI_ADDR_HI 0x5C 170#define BGE_PCI_MSI_ADDR_LO 0x60 171#define BGE_PCI_MSI_DATA 0x64 172 173/* 174 * PCI registers specific to the BCM570x family. 175 */ 176#define BGE_PCI_MISC_CTL 0x68 177#define BGE_PCI_DMA_RW_CTL 0x6C 178#define BGE_PCI_PCISTATE 0x70 179#define BGE_PCI_CLKCTL 0x74 180#define BGE_PCI_REG_BASEADDR 0x78 181#define BGE_PCI_MEMWIN_BASEADDR 0x7C 182#define BGE_PCI_REG_DATA 0x80 183#define BGE_PCI_MEMWIN_DATA 0x84 184#define BGE_PCI_MODECTL 0x88 185#define BGE_PCI_MISC_CFG 0x8C 186#define BGE_PCI_MISC_LOCALCTL 0x90 187#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 188#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 189#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 190#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 191#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 192#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 193#define BGE_PCI_ISR_MBX_HI 0xB0 194#define BGE_PCI_ISR_MBX_LO 0xB4 195 196/* PCI Misc. Host control register */ 197#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 198#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 199#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 200#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 201#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 202#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 203#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 204#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 205#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 206 207#define BGE_BIGENDIAN_INIT \ 208 (BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \ 209 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 210 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR) 211 212#define BGE_LITTLEENDIAN_INIT \ 213 (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \ 214 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS) 215 216#define BGE_CHIPID_TIGON_I 0x40000000 217#define BGE_CHIPID_TIGON_II 0x60000000 218#define BGE_CHIPID_BCM5700_B0 0x71000000 219#define BGE_CHIPID_BCM5700_B1 0x71020000 220#define BGE_CHIPID_BCM5700_B2 0x71030000 221#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 222#define BGE_CHIPID_BCM5700_C0 0x72000000 223#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 224#define BGE_CHIPID_BCM5701_B0 0x01000000 225#define BGE_CHIPID_BCM5701_B2 0x01020000 226#define BGE_CHIPID_BCM5701_B5 0x01050000 227#define BGE_CHIPID_BCM5703_A0 0x10000000 228#define BGE_CHIPID_BCM5703_A1 0x10010000 229#define BGE_CHIPID_BCM5703_A2 0x10020000 230#define BGE_CHIPID_BCM5704_A0 0x20000000 231#define BGE_CHIPID_BCM5704_A1 0x20010000 232#define BGE_CHIPID_BCM5704_A2 0x20020000 233#define BGE_CHIPID_BCM5704_A3 0x20030000 234#define BGE_CHIPID_BCM5705_A0 0x30000000 235#define BGE_CHIPID_BCM5705_A1 0x30010000 236#define BGE_CHIPID_BCM5705_A2 0x30020000 237#define BGE_CHIPID_BCM5705_A3 0x30030000 238 239/* shorthand one */ 240#define BGE_ASICREV(x) ((x) >> 28) 241#define BGE_ASICREV_BCM5700 0x07 242#define BGE_ASICREV_BCM5701 0x00 243#define BGE_ASICREV_BCM5703 0x01 244#define BGE_ASICREV_BCM5704 0x02 245#define BGE_ASICREV_BCM5705 0x03 246 247/* chip revisions */ 248#define BGE_CHIPREV(x) ((x) >> 24) 249#define BGE_CHIPREV_5700_AX 0x70 250#define BGE_CHIPREV_5700_BX 0x71 251#define BGE_CHIPREV_5700_CX 0x72 252#define BGE_CHIPREV_5701_AX 0x00 253 254/* PCI DMA Read/Write Control register */ 255#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 256#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 257#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 258#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 259#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 260#define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 261#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 262#define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 263#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 264#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 265#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 266#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD_SHIFT 24 267#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 268#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD_SHIFT 28 269 270#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 271#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 272#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 273#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 274#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 275#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 276#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 277#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 278 279#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 280#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 281#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 282#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 283#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 284#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 285#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 286#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 287 288/* 289 * PCI state register -- note, this register is read only 290 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 291 * register is set. 292 */ 293#define BGE_PCISTATE_FORCE_RESET 0x00000001 294#define BGE_PCISTATE_INTR_STATE 0x00000002 295#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 296#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 297#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 298#define BGE_PCISTATE_WANT_EXPROM 0x00000020 299#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 300#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 301#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 302 303/* 304 * PCI Clock Control register -- note, this register is read only 305 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 306 * register is set. 307 */ 308#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 309#define BGE_PCICLOCKCTL_M66EN 0x00000080 310#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 311#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 312#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 313#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 314#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 315#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 316#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 317#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 318 319/* 320 * High priority mailbox registers 321 * Each mailbox is 64-bits wide, though we only use the 322 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 323 * first. The NIC will load the mailbox after the lower 32 bit word 324 * has been updated. 325 */ 326#define BGE_MBX_IRQ0_HI 0x0200 327#define BGE_MBX_IRQ0_LO 0x0204 328#define BGE_MBX_IRQ1_HI 0x0208 329#define BGE_MBX_IRQ1_LO 0x020C 330#define BGE_MBX_IRQ2_HI 0x0210 331#define BGE_MBX_IRQ2_LO 0x0214 332#define BGE_MBX_IRQ3_HI 0x0218 333#define BGE_MBX_IRQ3_LO 0x021C 334#define BGE_MBX_GEN0_HI 0x0220 335#define BGE_MBX_GEN0_LO 0x0224 336#define BGE_MBX_GEN1_HI 0x0228 337#define BGE_MBX_GEN1_LO 0x022C 338#define BGE_MBX_GEN2_HI 0x0230 339#define BGE_MBX_GEN2_LO 0x0234 340#define BGE_MBX_GEN3_HI 0x0228 341#define BGE_MBX_GEN3_LO 0x022C 342#define BGE_MBX_GEN4_HI 0x0240 343#define BGE_MBX_GEN4_LO 0x0244 344#define BGE_MBX_GEN5_HI 0x0248 345#define BGE_MBX_GEN5_LO 0x024C 346#define BGE_MBX_GEN6_HI 0x0250 347#define BGE_MBX_GEN6_LO 0x0254 348#define BGE_MBX_GEN7_HI 0x0258 349#define BGE_MBX_GEN7_LO 0x025C 350#define BGE_MBX_RELOAD_STATS_HI 0x0260 351#define BGE_MBX_RELOAD_STATS_LO 0x0264 352#define BGE_MBX_RX_STD_PROD_HI 0x0268 353#define BGE_MBX_RX_STD_PROD_LO 0x026C 354#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 355#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 356#define BGE_MBX_RX_MINI_PROD_HI 0x0278 357#define BGE_MBX_RX_MINI_PROD_LO 0x027C 358#define BGE_MBX_RX_CONS0_HI 0x0280 359#define BGE_MBX_RX_CONS0_LO 0x0284 360#define BGE_MBX_RX_CONS1_HI 0x0288 361#define BGE_MBX_RX_CONS1_LO 0x028C 362#define BGE_MBX_RX_CONS2_HI 0x0290 363#define BGE_MBX_RX_CONS2_LO 0x0294 364#define BGE_MBX_RX_CONS3_HI 0x0298 365#define BGE_MBX_RX_CONS3_LO 0x029C 366#define BGE_MBX_RX_CONS4_HI 0x02A0 367#define BGE_MBX_RX_CONS4_LO 0x02A4 368#define BGE_MBX_RX_CONS5_HI 0x02A8 369#define BGE_MBX_RX_CONS5_LO 0x02AC 370#define BGE_MBX_RX_CONS6_HI 0x02B0 371#define BGE_MBX_RX_CONS6_LO 0x02B4 372#define BGE_MBX_RX_CONS7_HI 0x02B8 373#define BGE_MBX_RX_CONS7_LO 0x02BC 374#define BGE_MBX_RX_CONS8_HI 0x02C0 375#define BGE_MBX_RX_CONS8_LO 0x02C4 376#define BGE_MBX_RX_CONS9_HI 0x02C8 377#define BGE_MBX_RX_CONS9_LO 0x02CC 378#define BGE_MBX_RX_CONS10_HI 0x02D0 379#define BGE_MBX_RX_CONS10_LO 0x02D4 380#define BGE_MBX_RX_CONS11_HI 0x02D8 381#define BGE_MBX_RX_CONS11_LO 0x02DC 382#define BGE_MBX_RX_CONS12_HI 0x02E0 383#define BGE_MBX_RX_CONS12_LO 0x02E4 384#define BGE_MBX_RX_CONS13_HI 0x02E8 385#define BGE_MBX_RX_CONS13_LO 0x02EC 386#define BGE_MBX_RX_CONS14_HI 0x02F0 387#define BGE_MBX_RX_CONS14_LO 0x02F4 388#define BGE_MBX_RX_CONS15_HI 0x02F8 389#define BGE_MBX_RX_CONS15_LO 0x02FC 390#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 391#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 392#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 393#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 394#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 395#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 396#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 397#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 398#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 399#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 400#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 401#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 402#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 403#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 404#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 405#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 406#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 407#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 408#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 409#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 410#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 411#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 412#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 413#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 414#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 415#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 416#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 417#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 418#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 419#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 420#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 421#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 422#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 423#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 424#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 425#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 426#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 427#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 428#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 429#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 430#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 431#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 432#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 433#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 434#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 435#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 436#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 437#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 438#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 439#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 440#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 441#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 442#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 443#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 444#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 445#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 446#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 447#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 448#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 449#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 450#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 451#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 452#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 453#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 454 455#define BGE_TX_RINGS_MAX 4 456#define BGE_TX_RINGS_EXTSSRAM_MAX 16 457#define BGE_RX_RINGS_MAX 16 458 459/* Ethernet MAC control registers */ 460#define BGE_MAC_MODE 0x0400 461#define BGE_MAC_STS 0x0404 462#define BGE_MAC_EVT_ENB 0x0408 463#define BGE_MAC_LED_CTL 0x040C 464#define BGE_MAC_ADDR1_LO 0x0410 465#define BGE_MAC_ADDR1_HI 0x0414 466#define BGE_MAC_ADDR2_LO 0x0418 467#define BGE_MAC_ADDR2_HI 0x041C 468#define BGE_MAC_ADDR3_LO 0x0420 469#define BGE_MAC_ADDR3_HI 0x0424 470#define BGE_MAC_ADDR4_LO 0x0428 471#define BGE_MAC_ADDR4_HI 0x042C 472#define BGE_WOL_PATPTR 0x0430 473#define BGE_WOL_PATCFG 0x0434 474#define BGE_TX_RANDOM_BACKOFF 0x0438 475#define BGE_RX_MTU 0x043C 476#define BGE_GBIT_PCS_TEST 0x0440 477#define BGE_TX_TBI_AUTONEG 0x0444 478#define BGE_RX_TBI_AUTONEG 0x0448 479#define BGE_MI_COMM 0x044C 480#define BGE_MI_STS 0x0450 481#define BGE_MI_MODE 0x0454 482#define BGE_AUTOPOLL_STS 0x0458 483#define BGE_TX_MODE 0x045C 484#define BGE_TX_STS 0x0460 485#define BGE_TX_LENGTHS 0x0464 486#define BGE_RX_MODE 0x0468 487#define BGE_RX_STS 0x046C 488#define BGE_MAR0 0x0470 489#define BGE_MAR1 0x0474 490#define BGE_MAR2 0x0478 491#define BGE_MAR3 0x047C 492#define BGE_RX_BD_RULES_CTL0 0x0480 493#define BGE_RX_BD_RULES_MASKVAL0 0x0484 494#define BGE_RX_BD_RULES_CTL1 0x0488 495#define BGE_RX_BD_RULES_MASKVAL1 0x048C 496#define BGE_RX_BD_RULES_CTL2 0x0490 497#define BGE_RX_BD_RULES_MASKVAL2 0x0494 498#define BGE_RX_BD_RULES_CTL3 0x0498 499#define BGE_RX_BD_RULES_MASKVAL3 0x049C 500#define BGE_RX_BD_RULES_CTL4 0x04A0 501#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 502#define BGE_RX_BD_RULES_CTL5 0x04A8 503#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 504#define BGE_RX_BD_RULES_CTL6 0x04B0 505#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 506#define BGE_RX_BD_RULES_CTL7 0x04B8 507#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 508#define BGE_RX_BD_RULES_CTL8 0x04C0 509#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 510#define BGE_RX_BD_RULES_CTL9 0x04C8 511#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 512#define BGE_RX_BD_RULES_CTL10 0x04D0 513#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 514#define BGE_RX_BD_RULES_CTL11 0x04D8 515#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 516#define BGE_RX_BD_RULES_CTL12 0x04E0 517#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 518#define BGE_RX_BD_RULES_CTL13 0x04E8 519#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 520#define BGE_RX_BD_RULES_CTL14 0x04F0 521#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 522#define BGE_RX_BD_RULES_CTL15 0x04F8 523#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 524#define BGE_RX_RULES_CFG 0x0500 525#define BGE_RX_STATS 0x0800 526#define BGE_TX_STATS 0x0880 527 528/* Ethernet MAC Mode register */ 529#define BGE_MACMODE_RESET 0x00000001 530#define BGE_MACMODE_HALF_DUPLEX 0x00000002 531#define BGE_MACMODE_PORTMODE 0x0000000C 532#define BGE_MACMODE_LOOPBACK 0x00000010 533#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 534#define BGE_MACMODE_TX_BURST_ENB 0x00000100 535#define BGE_MACMODE_MAX_DEFER 0x00000200 536#define BGE_MACMODE_LINK_POLARITY 0x00000400 537#define BGE_MACMODE_RX_STATS_ENB 0x00000800 538#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 539#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 540#define BGE_MACMODE_TX_STATS_ENB 0x00004000 541#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 542#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 543#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 544#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 545#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 546#define BGE_MACMODE_MIP_ENB 0x00100000 547#define BGE_MACMODE_TXDMA_ENB 0x00200000 548#define BGE_MACMODE_RXDMA_ENB 0x00400000 549#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 550 551#define BGE_PORTMODE_NONE 0x00000000 552#define BGE_PORTMODE_MII 0x00000004 553#define BGE_PORTMODE_GMII 0x00000008 554#define BGE_PORTMODE_TBI 0x0000000C 555 556/* MAC Status register */ 557#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 558#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 559#define BGE_MACSTAT_RX_CFG 0x00000004 560#define BGE_MACSTAT_CFG_CHANGED 0x00000008 561#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 562#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 563#define BGE_MACSTAT_LINK_CHANGED 0x00001000 564#define BGE_MACSTAT_MI_COMPLETE 0x00400000 565#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 566#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 567#define BGE_MACSTAT_ODI_ERROR 0x02000000 568#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 569#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 570 571/* MAC Event Enable Register */ 572#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 573#define BGE_EVTENB_LINK_CHANGED 0x00001000 574#define BGE_EVTENB_MI_COMPLETE 0x00400000 575#define BGE_EVTENB_MI_INTERRUPT 0x00800000 576#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 577#define BGE_EVTENB_ODI_ERROR 0x02000000 578#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 579#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 580 581/* LED Control Register */ 582#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 583#define BGE_LEDCTL_1000MBPS_LED 0x00000002 584#define BGE_LEDCTL_100MBPS_LED 0x00000004 585#define BGE_LEDCTL_10MBPS_LED 0x00000008 586#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 587#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 588#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 589#define BGE_LEDCTL_1000MBPS_STS 0x00000080 590#define BGE_LEDCTL_100MBPS_STS 0x00000100 591#define BGE_LEDCTL_10MBPS_STS 0x00000200 592#define BGE_LEDCTL_TRADLED_STS 0x00000400 593#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 594#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 595 596/* TX backoff seed register */ 597#define BGE_TX_BACKOFF_SEED_MASK 0x3F 598 599/* Autopoll status register */ 600#define BGE_AUTOPOLLSTS_ERROR 0x00000001 601 602/* Transmit MAC mode register */ 603#define BGE_TXMODE_RESET 0x00000001 604#define BGE_TXMODE_ENABLE 0x00000002 605#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 606#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 607#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 608 609/* Transmit MAC status register */ 610#define BGE_TXSTAT_RX_XOFFED 0x00000001 611#define BGE_TXSTAT_SENT_XOFF 0x00000002 612#define BGE_TXSTAT_SENT_XON 0x00000004 613#define BGE_TXSTAT_LINK_UP 0x00000008 614#define BGE_TXSTAT_ODI_UFLOW 0x00000010 615#define BGE_TXSTAT_ODI_OFLOW 0x00000020 616 617/* Transmit MAC lengths register */ 618#define BGE_TXLEN_SLOTTIME 0x000000FF 619#define BGE_TXLEN_IPG 0x00000F00 620#define BGE_TXLEN_CRS 0x00003000 621 622/* Receive MAC mode register */ 623#define BGE_RXMODE_RESET 0x00000001 624#define BGE_RXMODE_ENABLE 0x00000002 625#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 626#define BGE_RXMODE_RX_GIANTS 0x00000020 627#define BGE_RXMODE_RX_RUNTS 0x00000040 628#define BGE_RXMODE_8022_LENCHECK 0x00000080 629#define BGE_RXMODE_RX_PROMISC 0x00000100 630#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 631#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 632 633/* Receive MAC status register */ 634#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 635#define BGE_RXSTAT_RCVD_XOFF 0x00000002 636#define BGE_RXSTAT_RCVD_XON 0x00000004 637 638/* Receive Rules Control register */ 639#define BGE_RXRULECTL_OFFSET 0x000000FF 640#define BGE_RXRULECTL_CLASS 0x00001F00 641#define BGE_RXRULECTL_HDRTYPE 0x0000E000 642#define BGE_RXRULECTL_COMPARE_OP 0x00030000 643#define BGE_RXRULECTL_MAP 0x01000000 644#define BGE_RXRULECTL_DISCARD 0x02000000 645#define BGE_RXRULECTL_MASK 0x04000000 646#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 647#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 648#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 649#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 650 651/* Receive Rules Mask register */ 652#define BGE_RXRULEMASK_VALUE 0x0000FFFF 653#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 654 655/* MI communication register */ 656#define BGE_MICOMM_DATA 0x0000FFFF 657#define BGE_MICOMM_REG 0x001F0000 658#define BGE_MICOMM_PHY 0x03E00000 659#define BGE_MICOMM_CMD 0x0C000000 660#define BGE_MICOMM_READFAIL 0x10000000 661#define BGE_MICOMM_BUSY 0x20000000 662 663#define BGE_MIREG(x) ((x & 0x1F) << 16) 664#define BGE_MIPHY(x) ((x & 0x1F) << 21) 665#define BGE_MICMD_WRITE 0x04000000 666#define BGE_MICMD_READ 0x08000000 667 668/* MI status register */ 669#define BGE_MISTS_LINK 0x00000001 670#define BGE_MISTS_10MBPS 0x00000002 671 672#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 673#define BGE_MIMODE_AUTOPOLL 0x00000010 674#define BGE_MIMODE_CLKCNT 0x001F0000 675 676 677/* 678 * Send data initiator control registers. 679 */ 680#define BGE_SDI_MODE 0x0C00 681#define BGE_SDI_STATUS 0x0C04 682#define BGE_SDI_STATS_CTL 0x0C08 683#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 684#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 685#define BGE_LOCSTATS_COS0 0x0C80 686#define BGE_LOCSTATS_COS1 0x0C84 687#define BGE_LOCSTATS_COS2 0x0C88 688#define BGE_LOCSTATS_COS3 0x0C8C 689#define BGE_LOCSTATS_COS4 0x0C90 690#define BGE_LOCSTATS_COS5 0x0C84 691#define BGE_LOCSTATS_COS6 0x0C98 692#define BGE_LOCSTATS_COS7 0x0C9C 693#define BGE_LOCSTATS_COS8 0x0CA0 694#define BGE_LOCSTATS_COS9 0x0CA4 695#define BGE_LOCSTATS_COS10 0x0CA8 696#define BGE_LOCSTATS_COS11 0x0CAC 697#define BGE_LOCSTATS_COS12 0x0CB0 698#define BGE_LOCSTATS_COS13 0x0CB4 699#define BGE_LOCSTATS_COS14 0x0CB8 700#define BGE_LOCSTATS_COS15 0x0CBC 701#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 702#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 703#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 704#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 705#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 706#define BGE_LOCSTATS_IRQS 0x0CD4 707#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 708#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 709 710/* Send Data Initiator mode register */ 711#define BGE_SDIMODE_RESET 0x00000001 712#define BGE_SDIMODE_ENABLE 0x00000002 713#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 714 715/* Send Data Initiator stats register */ 716#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 717 718/* Send Data Initiator stats control register */ 719#define BGE_SDISTATSCTL_ENABLE 0x00000001 720#define BGE_SDISTATSCTL_FASTER 0x00000002 721#define BGE_SDISTATSCTL_CLEAR 0x00000004 722#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 723#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 724 725/* 726 * Send Data Completion Control registers 727 */ 728#define BGE_SDC_MODE 0x1000 729#define BGE_SDC_STATUS 0x1004 730 731/* Send Data completion mode register */ 732#define BGE_SDCMODE_RESET 0x00000001 733#define BGE_SDCMODE_ENABLE 0x00000002 734#define BGE_SDCMODE_ATTN 0x00000004 735 736/* Send Data completion status register */ 737#define BGE_SDCSTAT_ATTN 0x00000004 738 739/* 740 * Send BD Ring Selector Control registers 741 */ 742#define BGE_SRS_MODE 0x1400 743#define BGE_SRS_STATUS 0x1404 744#define BGE_SRS_HWDIAG 0x1408 745#define BGE_SRS_LOC_NIC_CONS0 0x1440 746#define BGE_SRS_LOC_NIC_CONS1 0x1444 747#define BGE_SRS_LOC_NIC_CONS2 0x1448 748#define BGE_SRS_LOC_NIC_CONS3 0x144C 749#define BGE_SRS_LOC_NIC_CONS4 0x1450 750#define BGE_SRS_LOC_NIC_CONS5 0x1454 751#define BGE_SRS_LOC_NIC_CONS6 0x1458 752#define BGE_SRS_LOC_NIC_CONS7 0x145C 753#define BGE_SRS_LOC_NIC_CONS8 0x1460 754#define BGE_SRS_LOC_NIC_CONS9 0x1464 755#define BGE_SRS_LOC_NIC_CONS10 0x1468 756#define BGE_SRS_LOC_NIC_CONS11 0x146C 757#define BGE_SRS_LOC_NIC_CONS12 0x1470 758#define BGE_SRS_LOC_NIC_CONS13 0x1474 759#define BGE_SRS_LOC_NIC_CONS14 0x1478 760#define BGE_SRS_LOC_NIC_CONS15 0x147C 761 762/* Send BD Ring Selector Mode register */ 763#define BGE_SRSMODE_RESET 0x00000001 764#define BGE_SRSMODE_ENABLE 0x00000002 765#define BGE_SRSMODE_ATTN 0x00000004 766 767/* Send BD Ring Selector Status register */ 768#define BGE_SRSSTAT_ERROR 0x00000004 769 770/* Send BD Ring Selector HW Diagnostics register */ 771#define BGE_SRSHWDIAG_STATE 0x0000000F 772#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 773#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 774#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 775 776/* 777 * Send BD Initiator Selector Control registers 778 */ 779#define BGE_SBDI_MODE 0x1800 780#define BGE_SBDI_STATUS 0x1804 781#define BGE_SBDI_LOC_NIC_PROD0 0x1808 782#define BGE_SBDI_LOC_NIC_PROD1 0x180C 783#define BGE_SBDI_LOC_NIC_PROD2 0x1810 784#define BGE_SBDI_LOC_NIC_PROD3 0x1814 785#define BGE_SBDI_LOC_NIC_PROD4 0x1818 786#define BGE_SBDI_LOC_NIC_PROD5 0x181C 787#define BGE_SBDI_LOC_NIC_PROD6 0x1820 788#define BGE_SBDI_LOC_NIC_PROD7 0x1824 789#define BGE_SBDI_LOC_NIC_PROD8 0x1828 790#define BGE_SBDI_LOC_NIC_PROD9 0x182C 791#define BGE_SBDI_LOC_NIC_PROD10 0x1830 792#define BGE_SBDI_LOC_NIC_PROD11 0x1834 793#define BGE_SBDI_LOC_NIC_PROD12 0x1838 794#define BGE_SBDI_LOC_NIC_PROD13 0x183C 795#define BGE_SBDI_LOC_NIC_PROD14 0x1840 796#define BGE_SBDI_LOC_NIC_PROD15 0x1844 797 798/* Send BD Initiator Mode register */ 799#define BGE_SBDIMODE_RESET 0x00000001 800#define BGE_SBDIMODE_ENABLE 0x00000002 801#define BGE_SBDIMODE_ATTN 0x00000004 802 803/* Send BD Initiator Status register */ 804#define BGE_SBDISTAT_ERROR 0x00000004 805 806/* 807 * Send BD Completion Control registers 808 */ 809#define BGE_SBDC_MODE 0x1C00 810#define BGE_SBDC_STATUS 0x1C04 811 812/* Send BD Completion Control Mode register */ 813#define BGE_SBDCMODE_RESET 0x00000001 814#define BGE_SBDCMODE_ENABLE 0x00000002 815#define BGE_SBDCMODE_ATTN 0x00000004 816 817/* Send BD Completion Control Status register */ 818#define BGE_SBDCSTAT_ATTN 0x00000004 819 820/* 821 * Receive List Placement Control registers 822 */ 823#define BGE_RXLP_MODE 0x2000 824#define BGE_RXLP_STATUS 0x2004 825#define BGE_RXLP_SEL_LIST_LOCK 0x2008 826#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 827#define BGE_RXLP_CFG 0x2010 828#define BGE_RXLP_STATS_CTL 0x2014 829#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 830#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 831#define BGE_RXLP_HEAD0 0x2100 832#define BGE_RXLP_TAIL0 0x2104 833#define BGE_RXLP_COUNT0 0x2108 834#define BGE_RXLP_HEAD1 0x2110 835#define BGE_RXLP_TAIL1 0x2114 836#define BGE_RXLP_COUNT1 0x2118 837#define BGE_RXLP_HEAD2 0x2120 838#define BGE_RXLP_TAIL2 0x2124 839#define BGE_RXLP_COUNT2 0x2128 840#define BGE_RXLP_HEAD3 0x2130 841#define BGE_RXLP_TAIL3 0x2134 842#define BGE_RXLP_COUNT3 0x2138 843#define BGE_RXLP_HEAD4 0x2140 844#define BGE_RXLP_TAIL4 0x2144 845#define BGE_RXLP_COUNT4 0x2148 846#define BGE_RXLP_HEAD5 0x2150 847#define BGE_RXLP_TAIL5 0x2154 848#define BGE_RXLP_COUNT5 0x2158 849#define BGE_RXLP_HEAD6 0x2160 850#define BGE_RXLP_TAIL6 0x2164 851#define BGE_RXLP_COUNT6 0x2168 852#define BGE_RXLP_HEAD7 0x2170 853#define BGE_RXLP_TAIL7 0x2174 854#define BGE_RXLP_COUNT7 0x2178 855#define BGE_RXLP_HEAD8 0x2180 856#define BGE_RXLP_TAIL8 0x2184 857#define BGE_RXLP_COUNT8 0x2188 858#define BGE_RXLP_HEAD9 0x2190 859#define BGE_RXLP_TAIL9 0x2194 860#define BGE_RXLP_COUNT9 0x2198 861#define BGE_RXLP_HEAD10 0x21A0 862#define BGE_RXLP_TAIL10 0x21A4 863#define BGE_RXLP_COUNT10 0x21A8 864#define BGE_RXLP_HEAD11 0x21B0 865#define BGE_RXLP_TAIL11 0x21B4 866#define BGE_RXLP_COUNT11 0x21B8 867#define BGE_RXLP_HEAD12 0x21C0 868#define BGE_RXLP_TAIL12 0x21C4 869#define BGE_RXLP_COUNT12 0x21C8 870#define BGE_RXLP_HEAD13 0x21D0 871#define BGE_RXLP_TAIL13 0x21D4 872#define BGE_RXLP_COUNT13 0x21D8 873#define BGE_RXLP_HEAD14 0x21E0 874#define BGE_RXLP_TAIL14 0x21E4 875#define BGE_RXLP_COUNT14 0x21E8 876#define BGE_RXLP_HEAD15 0x21F0 877#define BGE_RXLP_TAIL15 0x21F4 878#define BGE_RXLP_COUNT15 0x21F8 879#define BGE_RXLP_LOCSTAT_COS0 0x2200 880#define BGE_RXLP_LOCSTAT_COS1 0x2204 881#define BGE_RXLP_LOCSTAT_COS2 0x2208 882#define BGE_RXLP_LOCSTAT_COS3 0x220C 883#define BGE_RXLP_LOCSTAT_COS4 0x2210 884#define BGE_RXLP_LOCSTAT_COS5 0x2214 885#define BGE_RXLP_LOCSTAT_COS6 0x2218 886#define BGE_RXLP_LOCSTAT_COS7 0x221C 887#define BGE_RXLP_LOCSTAT_COS8 0x2220 888#define BGE_RXLP_LOCSTAT_COS9 0x2224 889#define BGE_RXLP_LOCSTAT_COS10 0x2228 890#define BGE_RXLP_LOCSTAT_COS11 0x222C 891#define BGE_RXLP_LOCSTAT_COS12 0x2230 892#define BGE_RXLP_LOCSTAT_COS13 0x2234 893#define BGE_RXLP_LOCSTAT_COS14 0x2238 894#define BGE_RXLP_LOCSTAT_COS15 0x223C 895#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 896#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 897#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 898#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 899#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 900#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 901#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 902 903 904/* Receive List Placement mode register */ 905#define BGE_RXLPMODE_RESET 0x00000001 906#define BGE_RXLPMODE_ENABLE 0x00000002 907#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 908#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 909#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 910 911/* Receive List Placement Status register */ 912#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 913#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 914#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 915 916/* 917 * Receive Data and Receive BD Initiator Control Registers 918 */ 919#define BGE_RDBDI_MODE 0x2400 920#define BGE_RDBDI_STATUS 0x2404 921#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 922#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 923#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 924#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 925#define BGE_RX_STD_RCB_HADDR_HI 0x2450 926#define BGE_RX_STD_RCB_HADDR_LO 0x2454 927#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 928#define BGE_RX_STD_RCB_NICADDR 0x245C 929#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 930#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 931#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 932#define BGE_RX_MINI_RCB_NICADDR 0x246C 933#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 934#define BGE_RDBDI_STD_RX_CONS 0x2474 935#define BGE_RDBDI_MINI_RX_CONS 0x2478 936#define BGE_RDBDI_RETURN_PROD0 0x2480 937#define BGE_RDBDI_RETURN_PROD1 0x2484 938#define BGE_RDBDI_RETURN_PROD2 0x2488 939#define BGE_RDBDI_RETURN_PROD3 0x248C 940#define BGE_RDBDI_RETURN_PROD4 0x2490 941#define BGE_RDBDI_RETURN_PROD5 0x2494 942#define BGE_RDBDI_RETURN_PROD6 0x2498 943#define BGE_RDBDI_RETURN_PROD7 0x249C 944#define BGE_RDBDI_RETURN_PROD8 0x24A0 945#define BGE_RDBDI_RETURN_PROD9 0x24A4 946#define BGE_RDBDI_RETURN_PROD10 0x24A8 947#define BGE_RDBDI_RETURN_PROD11 0x24AC 948#define BGE_RDBDI_RETURN_PROD12 0x24B0 949#define BGE_RDBDI_RETURN_PROD13 0x24B4 950#define BGE_RDBDI_RETURN_PROD14 0x24B8 951#define BGE_RDBDI_RETURN_PROD15 0x24BC 952#define BGE_RDBDI_HWDIAG 0x24C0 953 954 955/* Receive Data and Receive BD Initiator Mode register */ 956#define BGE_RDBDIMODE_RESET 0x00000001 957#define BGE_RDBDIMODE_ENABLE 0x00000002 958#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 959#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 960#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 961 962/* Receive Data and Receive BD Initiator Status register */ 963#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 964#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 965#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 966 967 968/* 969 * Receive Data Completion Control registers 970 */ 971#define BGE_RDC_MODE 0x2800 972 973/* Receive Data Completion Mode register */ 974#define BGE_RDCMODE_RESET 0x00000001 975#define BGE_RDCMODE_ENABLE 0x00000002 976#define BGE_RDCMODE_ATTN 0x00000004 977 978/* 979 * Receive BD Initiator Control registers 980 */ 981#define BGE_RBDI_MODE 0x2C00 982#define BGE_RBDI_STATUS 0x2C04 983#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 984#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 985#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 986#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 987#define BGE_RBDI_STD_REPL_THRESH 0x2C18 988#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 989 990/* Receive BD Initiator Mode register */ 991#define BGE_RBDIMODE_RESET 0x00000001 992#define BGE_RBDIMODE_ENABLE 0x00000002 993#define BGE_RBDIMODE_ATTN 0x00000004 994 995/* Receive BD Initiator Status register */ 996#define BGE_RBDISTAT_ATTN 0x00000004 997 998/* 999 * Receive BD Completion Control registers 1000 */ 1001#define BGE_RBDC_MODE 0x3000 1002#define BGE_RBDC_STATUS 0x3004 1003#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1004#define BGE_RBDC_STD_BD_PROD 0x300C 1005#define BGE_RBDC_MINI_BD_PROD 0x3010 1006 1007/* Receive BD completion mode register */ 1008#define BGE_RBDCMODE_RESET 0x00000001 1009#define BGE_RBDCMODE_ENABLE 0x00000002 1010#define BGE_RBDCMODE_ATTN 0x00000004 1011 1012/* Receive BD completion status register */ 1013#define BGE_RBDCSTAT_ERROR 0x00000004 1014 1015/* 1016 * Receive List Selector Control registers 1017 */ 1018#define BGE_RXLS_MODE 0x3400 1019#define BGE_RXLS_STATUS 0x3404 1020 1021/* Receive List Selector Mode register */ 1022#define BGE_RXLSMODE_RESET 0x00000001 1023#define BGE_RXLSMODE_ENABLE 0x00000002 1024#define BGE_RXLSMODE_ATTN 0x00000004 1025 1026/* Receive List Selector Status register */ 1027#define BGE_RXLSSTAT_ERROR 0x00000004 1028 1029/* 1030 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1031 */ 1032#define BGE_MBCF_MODE 0x3800 1033#define BGE_MBCF_STATUS 0x3804 1034 1035/* Mbuf Cluster Free mode register */ 1036#define BGE_MBCFMODE_RESET 0x00000001 1037#define BGE_MBCFMODE_ENABLE 0x00000002 1038#define BGE_MBCFMODE_ATTN 0x00000004 1039 1040/* Mbuf Cluster Free status register */ 1041#define BGE_MBCFSTAT_ERROR 0x00000004 1042 1043/* 1044 * Host Coalescing Control registers 1045 */ 1046#define BGE_HCC_MODE 0x3C00 1047#define BGE_HCC_STATUS 0x3C04 1048#define BGE_HCC_RX_COAL_TICKS 0x3C08 1049#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1050#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1051#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1052#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1053#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1054#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1055#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1056#define BGE_HCC_STATS_TICKS 0x3C28 1057#define BGE_HCC_STATS_ADDR_HI 0x3C30 1058#define BGE_HCC_STATS_ADDR_LO 0x3C34 1059#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1060#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1061#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1062#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1063#define BGE_FLOW_ATTN 0x3C48 1064#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1065#define BGE_HCC_STD_BD_CONS 0x3C54 1066#define BGE_HCC_MINI_BD_CONS 0x3C58 1067#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1068#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1069#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1070#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1071#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1072#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1073#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1074#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1075#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1076#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1077#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1078#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1079#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1080#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1081#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1082#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1083#define BGE_HCC_TX_BD_CONS0 0x3CC0 1084#define BGE_HCC_TX_BD_CONS1 0x3CC4 1085#define BGE_HCC_TX_BD_CONS2 0x3CC8 1086#define BGE_HCC_TX_BD_CONS3 0x3CCC 1087#define BGE_HCC_TX_BD_CONS4 0x3CD0 1088#define BGE_HCC_TX_BD_CONS5 0x3CD4 1089#define BGE_HCC_TX_BD_CONS6 0x3CD8 1090#define BGE_HCC_TX_BD_CONS7 0x3CDC 1091#define BGE_HCC_TX_BD_CONS8 0x3CE0 1092#define BGE_HCC_TX_BD_CONS9 0x3CE4 1093#define BGE_HCC_TX_BD_CONS10 0x3CE8 1094#define BGE_HCC_TX_BD_CONS11 0x3CEC 1095#define BGE_HCC_TX_BD_CONS12 0x3CF0 1096#define BGE_HCC_TX_BD_CONS13 0x3CF4 1097#define BGE_HCC_TX_BD_CONS14 0x3CF8 1098#define BGE_HCC_TX_BD_CONS15 0x3CFC 1099 1100 1101/* Host coalescing mode register */ 1102#define BGE_HCCMODE_RESET 0x00000001 1103#define BGE_HCCMODE_ENABLE 0x00000002 1104#define BGE_HCCMODE_ATTN 0x00000004 1105#define BGE_HCCMODE_COAL_NOW 0x00000008 1106#define BGE_HCCMODE_MSI_BITS 0x0x000070 1107#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1108 1109#define BGE_STATBLKSZ_FULL 0x00000000 1110#define BGE_STATBLKSZ_64BYTE 0x00000080 1111#define BGE_STATBLKSZ_32BYTE 0x00000100 1112 1113/* Host coalescing status register */ 1114#define BGE_HCCSTAT_ERROR 0x00000004 1115 1116/* Flow attention register */ 1117#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1118#define BGE_FLOWATTN_MEMARB 0x00000080 1119#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1120#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1121#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1122#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1123#define BGE_FLOWATTN_RDBDI 0x00080000 1124#define BGE_FLOWATTN_RXLS 0x00100000 1125#define BGE_FLOWATTN_RXLP 0x00200000 1126#define BGE_FLOWATTN_RBDC 0x00400000 1127#define BGE_FLOWATTN_RBDI 0x00800000 1128#define BGE_FLOWATTN_SDC 0x08000000 1129#define BGE_FLOWATTN_SDI 0x10000000 1130#define BGE_FLOWATTN_SRS 0x20000000 1131#define BGE_FLOWATTN_SBDC 0x40000000 1132#define BGE_FLOWATTN_SBDI 0x80000000 1133 1134/* 1135 * Memory arbiter registers 1136 */ 1137#define BGE_MARB_MODE 0x4000 1138#define BGE_MARB_STATUS 0x4004 1139#define BGE_MARB_TRAPADDR_HI 0x4008 1140#define BGE_MARB_TRAPADDR_LO 0x400C 1141 1142/* Memory arbiter mode register */ 1143#define BGE_MARBMODE_RESET 0x00000001 1144#define BGE_MARBMODE_ENABLE 0x00000002 1145#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1146#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1147#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1148#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1149#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1150#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1151#define BGE_MARBMODE_PCI_TRAP 0x00000100 1152#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1153#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1154#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1155#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1156#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1157#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1158#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1159#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1160#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1161#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1162#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1163#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1164#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1165#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1166#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1167#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1168#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1169 1170/* Memory arbiter status register */ 1171#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1172#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1173#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1174#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1175#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1176#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1177#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1178#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1179#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1180#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1181#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1182#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1183#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1184#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1185#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1186#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1187#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1188#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1189#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1190#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1191#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1192#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1193#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1194#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1195 1196/* 1197 * Buffer manager control registers 1198 */ 1199#define BGE_BMAN_MODE 0x4400 1200#define BGE_BMAN_STATUS 0x4404 1201#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1202#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1203#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1204#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1205#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1206#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1207#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1208#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1209#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1210#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1211#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1212#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1213#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1214#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1215#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1216#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1217#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1218#define BGE_BMAN_HWDIAG_1 0x444C 1219#define BGE_BMAN_HWDIAG_2 0x4450 1220#define BGE_BMAN_HWDIAG_3 0x4454 1221 1222/* Buffer manager mode register */ 1223#define BGE_BMANMODE_RESET 0x00000001 1224#define BGE_BMANMODE_ENABLE 0x00000002 1225#define BGE_BMANMODE_ATTN 0x00000004 1226#define BGE_BMANMODE_TESTMODE 0x00000008 1227#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1228 1229/* Buffer manager status register */ 1230#define BGE_BMANSTAT_ERRO 0x00000004 1231#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1232 1233 1234/* 1235 * Read DMA Control registers 1236 */ 1237#define BGE_RDMA_MODE 0x4800 1238#define BGE_RDMA_STATUS 0x4804 1239 1240/* Read DMA mode register */ 1241#define BGE_RDMAMODE_RESET 0x00000001 1242#define BGE_RDMAMODE_ENABLE 0x00000002 1243#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1244#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1245#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1246#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1247#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1248#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1249#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1250#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1251#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1252 1253/* Read DMA status register */ 1254#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1255#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1256#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1257#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1258#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1259#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1260#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1261#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1262 1263/* 1264 * Write DMA control registers 1265 */ 1266#define BGE_WDMA_MODE 0x4C00 1267#define BGE_WDMA_STATUS 0x4C04 1268 1269/* Write DMA mode register */ 1270#define BGE_WDMAMODE_RESET 0x00000001 1271#define BGE_WDMAMODE_ENABLE 0x00000002 1272#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1273#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1274#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1275#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1276#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1277#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1278#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1279#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1280#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1281 1282/* Write DMA status register */ 1283#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1284#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1285#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1286#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1287#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1288#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1289#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1290#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1291 1292 1293/* 1294 * RX CPU registers 1295 */ 1296#define BGE_RXCPU_MODE 0x5000 1297#define BGE_RXCPU_STATUS 0x5004 1298#define BGE_RXCPU_PC 0x501C 1299 1300/* RX CPU mode register */ 1301#define BGE_RXCPUMODE_RESET 0x00000001 1302#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1303#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1304#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1305#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1306#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1307#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1308#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1309#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1310#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1311#define BGE_RXCPUMODE_HALTCPU 0x00000400 1312#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1313#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1314#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1315 1316/* RX CPU status register */ 1317#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1318#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1319#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1320#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1321#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1322#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1323#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1324#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1325#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1326#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1327#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1328#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1329#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1330#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1331#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1332#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1333#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1334 1335 1336/* 1337 * TX CPU registers 1338 */ 1339#define BGE_TXCPU_MODE 0x5400 1340#define BGE_TXCPU_STATUS 0x5404 1341#define BGE_TXCPU_PC 0x541C 1342 1343/* TX CPU mode register */ 1344#define BGE_TXCPUMODE_RESET 0x00000001 1345#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1346#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1347#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1348#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1349#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1350#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1351#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1352#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1353#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1354#define BGE_TXCPUMODE_HALTCPU 0x00000400 1355#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1356#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1357 1358/* TX CPU status register */ 1359#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1360#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1361#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1362#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1363#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1364#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1365#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1366#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1367#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1368#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1369#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1370#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1371#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1372#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1373#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1374#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1375#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1376 1377 1378/* 1379 * Low priority mailbox registers 1380 */ 1381#define BGE_LPMBX_IRQ0_HI 0x5800 1382#define BGE_LPMBX_IRQ0_LO 0x5804 1383#define BGE_LPMBX_IRQ1_HI 0x5808 1384#define BGE_LPMBX_IRQ1_LO 0x580C 1385#define BGE_LPMBX_IRQ2_HI 0x5810 1386#define BGE_LPMBX_IRQ2_LO 0x5814 1387#define BGE_LPMBX_IRQ3_HI 0x5818 1388#define BGE_LPMBX_IRQ3_LO 0x581C 1389#define BGE_LPMBX_GEN0_HI 0x5820 1390#define BGE_LPMBX_GEN0_LO 0x5824 1391#define BGE_LPMBX_GEN1_HI 0x5828 1392#define BGE_LPMBX_GEN1_LO 0x582C 1393#define BGE_LPMBX_GEN2_HI 0x5830 1394#define BGE_LPMBX_GEN2_LO 0x5834 1395#define BGE_LPMBX_GEN3_HI 0x5828 1396#define BGE_LPMBX_GEN3_LO 0x582C 1397#define BGE_LPMBX_GEN4_HI 0x5840 1398#define BGE_LPMBX_GEN4_LO 0x5844 1399#define BGE_LPMBX_GEN5_HI 0x5848 1400#define BGE_LPMBX_GEN5_LO 0x584C 1401#define BGE_LPMBX_GEN6_HI 0x5850 1402#define BGE_LPMBX_GEN6_LO 0x5854 1403#define BGE_LPMBX_GEN7_HI 0x5858 1404#define BGE_LPMBX_GEN7_LO 0x585C 1405#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1406#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1407#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1408#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1409#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1410#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1411#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1412#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1413#define BGE_LPMBX_RX_CONS0_HI 0x5880 1414#define BGE_LPMBX_RX_CONS0_LO 0x5884 1415#define BGE_LPMBX_RX_CONS1_HI 0x5888 1416#define BGE_LPMBX_RX_CONS1_LO 0x588C 1417#define BGE_LPMBX_RX_CONS2_HI 0x5890 1418#define BGE_LPMBX_RX_CONS2_LO 0x5894 1419#define BGE_LPMBX_RX_CONS3_HI 0x5898 1420#define BGE_LPMBX_RX_CONS3_LO 0x589C 1421#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1422#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1423#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1424#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1425#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1426#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1427#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1428#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1429#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1430#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1431#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1432#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1433#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1434#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1435#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1436#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1437#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1438#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1439#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1440#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1441#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1442#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1443#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1444#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1445#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1446#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1447#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1448#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1449#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1450#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1451#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1452#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1453#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1454#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1455#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1456#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1457#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1458#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1459#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1460#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1461#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1462#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1463#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1464#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1465#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1466#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1467#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1468#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1469#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1470#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1471#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1472#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1473#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1474#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1475#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1476#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1477#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1478#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1479#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1480#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1481#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1482#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1483#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1484#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1485#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1486#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1487#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1488#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1489#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1490#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1491#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1492#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1493#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1494#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1495#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1496#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1497#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1498#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1499#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1500#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1501#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1502#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1503#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1504#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1505#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1506#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1507#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1508#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1509 1510/* 1511 * Flow throw Queue reset register 1512 */ 1513#define BGE_FTQ_RESET 0x5C00 1514 1515#define BGE_FTQRESET_DMAREAD 0x00000002 1516#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1517#define BGE_FTQRESET_DMADONE 0x00000010 1518#define BGE_FTQRESET_SBDC 0x00000020 1519#define BGE_FTQRESET_SDI 0x00000040 1520#define BGE_FTQRESET_WDMA 0x00000080 1521#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1522#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1523#define BGE_FTQRESET_SDC 0x00000400 1524#define BGE_FTQRESET_HCC 0x00000800 1525#define BGE_FTQRESET_TXFIFO 0x00001000 1526#define BGE_FTQRESET_MBC 0x00002000 1527#define BGE_FTQRESET_RBDC 0x00004000 1528#define BGE_FTQRESET_RXLP 0x00008000 1529#define BGE_FTQRESET_RDBDI 0x00010000 1530#define BGE_FTQRESET_RDC 0x00020000 1531#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1532 1533/* 1534 * Message Signaled Interrupt registers 1535 */ 1536#define BGE_MSI_MODE 0x6000 1537#define BGE_MSI_STATUS 0x6004 1538#define BGE_MSI_FIFOACCESS 0x6008 1539 1540/* MSI mode register */ 1541#define BGE_MSIMODE_RESET 0x00000001 1542#define BGE_MSIMODE_ENABLE 0x00000002 1543#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1544#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1545#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1546#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1547#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1548 1549/* MSI status register */ 1550#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1551#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1552#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1553#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1554#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1555 1556 1557/* 1558 * DMA Completion registers 1559 */ 1560#define BGE_DMAC_MODE 0x6400 1561 1562/* DMA Completion mode register */ 1563#define BGE_DMACMODE_RESET 0x00000001 1564#define BGE_DMACMODE_ENABLE 0x00000002 1565 1566 1567/* 1568 * General control registers. 1569 */ 1570#define BGE_MODE_CTL 0x6800 1571#define BGE_MISC_CFG 0x6804 1572#define BGE_MISC_LOCAL_CTL 0x6808 1573#define BGE_EE_ADDR 0x6838 1574#define BGE_EE_DATA 0x683C 1575#define BGE_EE_CTL 0x6840 1576#define BGE_MDI_CTL 0x6844 1577#define BGE_EE_DELAY 0x6848 1578 1579/* Mode control register */ 1580#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1581#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1582#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1583#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1584#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1585#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1586#define BGE_MODECTL_NO_RX_CRC 0x00000400 1587#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1588#define BGE_MODECTL_NO_TX_INTR 0x00002000 1589#define BGE_MODECTL_NO_RX_INTR 0x00004000 1590#define BGE_MODECTL_FORCE_PCI32 0x00008000 1591#define BGE_MODECTL_STACKUP 0x00010000 1592#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1593#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1594#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1595#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1596#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1597#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1598#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1599#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1600#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1601#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1602 1603/* Misc. config register */ 1604#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1605#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1606 1607#define BGE_32BITTIME_66MHZ (0x41 << 1) 1608 1609/* Misc. Local Control */ 1610#define BGE_MLC_INTR_STATE 0x00000001 1611#define BGE_MLC_INTR_CLR 0x00000002 1612#define BGE_MLC_INTR_SET 0x00000004 1613#define BGE_MLC_INTR_ONATTN 0x00000008 1614#define BGE_MLC_MISCIO_IN0 0x00000100 1615#define BGE_MLC_MISCIO_IN1 0x00000200 1616#define BGE_MLC_MISCIO_IN2 0x00000400 1617#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1618#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1619#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1620#define BGE_MLC_MISCIO_OUT0 0x00004000 1621#define BGE_MLC_MISCIO_OUT1 0x00008000 1622#define BGE_MLC_MISCIO_OUT2 0x00010000 1623#define BGE_MLC_EXTRAM_ENB 0x00020000 1624#define BGE_MLC_SRAM_SIZE 0x001C0000 1625#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1626#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1627#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1628#define BGE_MLC_AUTO_EEPROM 0x01000000 1629 1630#define BGE_SSRAMSIZE_256KB 0x00000000 1631#define BGE_SSRAMSIZE_512KB 0x00040000 1632#define BGE_SSRAMSIZE_1MB 0x00080000 1633#define BGE_SSRAMSIZE_2MB 0x000C0000 1634#define BGE_SSRAMSIZE_4MB 0x00100000 1635#define BGE_SSRAMSIZE_8MB 0x00140000 1636#define BGE_SSRAMSIZE_16M 0x00180000 1637 1638/* EEPROM address register */ 1639#define BGE_EEADDR_ADDRESS 0x0000FFFC 1640#define BGE_EEADDR_HALFCLK 0x01FF0000 1641#define BGE_EEADDR_START 0x02000000 1642#define BGE_EEADDR_DEVID 0x1C000000 1643#define BGE_EEADDR_RESET 0x20000000 1644#define BGE_EEADDR_DONE 0x40000000 1645#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1646 1647#define BGE_EEDEVID(x) ((x & 7) << 26) 1648#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1649#define BGE_HALFCLK_384SCL 0x60 1650#define BGE_EE_READCMD \ 1651 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1652 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1653#define BGE_EE_WRCMD \ 1654 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1655 BGE_EEADDR_START|BGE_EEADDR_DONE) 1656 1657/* EEPROM Control register */ 1658#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1659#define BGE_EECTL_CLKOUT 0x00000002 1660#define BGE_EECTL_CLKIN 0x00000004 1661#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1662#define BGE_EECTL_DATAOUT 0x00000010 1663#define BGE_EECTL_DATAIN 0x00000020 1664 1665/* MDI (MII/GMII) access register */ 1666#define BGE_MDI_DATA 0x00000001 1667#define BGE_MDI_DIR 0x00000002 1668#define BGE_MDI_SEL 0x00000004 1669#define BGE_MDI_CLK 0x00000008 1670 1671#define BGE_MEMWIN_START 0x00008000 1672#define BGE_MEMWIN_END 0x0000FFFF 1673 1674 1675#define BGE_MEMWIN_READ(pc, tag, x, val) \ 1676 do { \ 1677 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1678 (0xFFFF0000 & x)); \ 1679 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1680 } while(0) 1681 1682#define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 1683 do { \ 1684 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1685 (0xFFFF0000 & x)); \ 1686 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1687 } while(0) 1688 1689/* 1690 * This magic number is used to prevent PXE restart when we 1691 * issue a software reset. We write this magic number to the 1692 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1693 * code from running. 1694 */ 1695#define BGE_MAGIC_NUMBER 0x4B657654 1696 1697typedef struct { 1698 u_int32_t bge_addr_hi; 1699 u_int32_t bge_addr_lo; 1700} bge_hostaddr; 1701#define BGE_HOSTADDR(x,y) \ 1702 do { \ 1703 (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 1704 (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 1705 } while(0) 1706 1707/* Ring control block structure */ 1708struct bge_rcb { 1709 bge_hostaddr bge_hostaddr; 1710 u_int32_t bge_maxlen_flags; 1711 u_int32_t bge_nicaddr; 1712}; 1713 1714#define RCB_WRITE_4(sc, rcb, offset, val) \ 1715 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1716 rcb + offsetof(struct bge_rcb, offset), val) 1717 1718#define RCB_WRITE_2(sc, rcb, offset, val) \ 1719 bus_space_write_2(sc->bge_btag, sc->bge_bhandle, \ 1720 rcb + offsetof(struct bge_rcb, offset), val) 1721 1722#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen << 16) | (flags)) 1723 1724#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1725#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1726 1727struct bge_tx_bd { 1728 bge_hostaddr bge_addr; 1729 u_int16_t bge_flags; 1730 u_int16_t bge_len; 1731 u_int16_t bge_vlan_tag; 1732 u_int16_t bge_rsvd; 1733}; 1734 1735#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1736#define BGE_TXBDFLAG_IP_CSUM 0x0002 1737#define BGE_TXBDFLAG_END 0x0004 1738#define BGE_TXBDFLAG_IP_FRAG 0x0008 1739#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1740#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1741#define BGE_TXBDFLAG_COAL_NOW 0x0080 1742#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1743#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1744#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1745#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1746#define BGE_TXBDFLAG_NO_CRC 0x8000 1747 1748#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1749 BGE_SEND_RING_1_TO_4 + \ 1750 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1751 1752struct bge_rx_bd { 1753 bge_hostaddr bge_addr; 1754 u_int16_t bge_len; 1755 u_int16_t bge_idx; 1756 u_int16_t bge_flags; 1757 u_int16_t bge_type; 1758 u_int16_t bge_tcp_udp_csum; 1759 u_int16_t bge_ip_csum; 1760 u_int16_t bge_vlan_tag; 1761 u_int16_t bge_error_flag; 1762 u_int32_t bge_rsvd; 1763 u_int32_t bge_opaque; 1764}; 1765 1766#define BGE_RXBDFLAG_END 0x0004 1767#define BGE_RXBDFLAG_JUMBO_RING 0x0020 1768#define BGE_RXBDFLAG_VLAN_TAG 0x0040 1769#define BGE_RXBDFLAG_ERROR 0x0400 1770#define BGE_RXBDFLAG_MINI_RING 0x0800 1771#define BGE_RXBDFLAG_IP_CSUM 0x1000 1772#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1773#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1774 1775#define BGE_RXERRFLAG_BAD_CRC 0x0001 1776#define BGE_RXERRFLAG_COLL_DETECT 0x0002 1777#define BGE_RXERRFLAG_LINK_LOST 0x0004 1778#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1779#define BGE_RXERRFLAG_MAC_ABORT 0x0010 1780#define BGE_RXERRFLAG_RUNT 0x0020 1781#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1782#define BGE_RXERRFLAG_GIANT 0x0080 1783 1784struct bge_sts_idx { 1785 u_int16_t bge_rx_prod_idx; 1786 u_int16_t bge_tx_cons_idx; 1787}; 1788 1789struct bge_status_block { 1790 u_int32_t bge_status; 1791 u_int32_t bge_rsvd0; 1792 u_int16_t bge_rx_jumbo_cons_idx; 1793 u_int16_t bge_rx_std_cons_idx; 1794 u_int16_t bge_rx_mini_cons_idx; 1795 u_int16_t bge_rsvd1; 1796 struct bge_sts_idx bge_idx[16]; 1797}; 1798 1799#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1800#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1801 1802#define BGE_STATFLAG_UPDATED 0x00000001 1803#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1804#define BGE_STATFLAG_ERROR 0x00000004 1805 1806/* 1807 * SysKonnect Subsystem IDs 1808 */ 1809#define SK_SUBSYSID_9D21 0x4421 1810#define SK_SUBSYSID_9D41 0x4441 1811 1812/* 1813 * Offset of MAC address inside EEPROM. 1814 */ 1815#define BGE_EE_MAC_OFFSET 0x7C 1816#define BGE_EE_HWCFG_OFFSET 0xC8 1817 1818#define BGE_HWCFG_VOLTAGE 0x00000003 1819#define BGE_HWCFG_PHYLED_MODE 0x0000000C 1820#define BGE_HWCFG_MEDIA 0x00000030 1821 1822#define BGE_VOLTAGE_1POINT3 0x00000000 1823#define BGE_VOLTAGE_1POINT8 0x00000001 1824 1825#define BGE_PHYLEDMODE_UNSPEC 0x00000000 1826#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 1827#define BGE_PHYLEDMODE_SINGLELED 0x00000008 1828 1829#define BGE_MEDIA_UNSPEC 0x00000000 1830#define BGE_MEDIA_COPPER 0x00000010 1831#define BGE_MEDIA_FIBER 0x00000020 1832 1833#define BGE_PCI_READ_CMD 0x06000000 1834#define BGE_PCI_WRITE_CMD 0x70000000 1835 1836#define BGE_TICKS_PER_SEC 1000000 1837 1838/* 1839 * Ring size constants. 1840 */ 1841#define BGE_EVENT_RING_CNT 256 1842#define BGE_CMD_RING_CNT 64 1843#define BGE_STD_RX_RING_CNT 512 1844#define BGE_JUMBO_RX_RING_CNT 256 1845#define BGE_MINI_RX_RING_CNT 1024 1846#define BGE_RETURN_RING_CNT 1024 1847 1848/* 5705 has smaller return ring size */ 1849#define BGE_RETURN_RING_CNT_5705 512 1850 1851/* 1852 * Possible TX ring sizes. 1853 */ 1854#define BGE_TX_RING_CNT_128 128 1855#define BGE_TX_RING_BASE_128 0x3800 1856 1857#define BGE_TX_RING_CNT_256 256 1858#define BGE_TX_RING_BASE_256 0x3000 1859 1860#define BGE_TX_RING_CNT_512 512 1861#define BGE_TX_RING_BASE_512 0x2000 1862 1863#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 1864#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 1865 1866/* 1867 * Tigon III statistics counters. 1868 */ 1869/* Statistics maintained MAC Receive block. */ 1870struct bge_rx_mac_stats { 1871 bge_hostaddr ifHCInOctets; 1872 bge_hostaddr Reserved1; 1873 bge_hostaddr etherStatsFragments; 1874 bge_hostaddr ifHCInUcastPkts; 1875 bge_hostaddr ifHCInMulticastPkts; 1876 bge_hostaddr ifHCInBroadcastPkts; 1877 bge_hostaddr dot3StatsFCSErrors; 1878 bge_hostaddr dot3StatsAlignmentErrors; 1879 bge_hostaddr xonPauseFramesReceived; 1880 bge_hostaddr xoffPauseFramesReceived; 1881 bge_hostaddr macControlFramesReceived; 1882 bge_hostaddr xoffStateEntered; 1883 bge_hostaddr dot3StatsFramesTooLong; 1884 bge_hostaddr etherStatsJabbers; 1885 bge_hostaddr etherStatsUndersizePkts; 1886 bge_hostaddr inRangeLengthError; 1887 bge_hostaddr outRangeLengthError; 1888 bge_hostaddr etherStatsPkts64Octets; 1889 bge_hostaddr etherStatsPkts65Octetsto127Octets; 1890 bge_hostaddr etherStatsPkts128Octetsto255Octets; 1891 bge_hostaddr etherStatsPkts256Octetsto511Octets; 1892 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 1893 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 1894 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 1895 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 1896 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 1897 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 1898}; 1899 1900/* Statistics maintained MAC Transmit block. */ 1901struct bge_tx_mac_stats { 1902 bge_hostaddr ifHCOutOctets; 1903 bge_hostaddr Reserved2; 1904 bge_hostaddr etherStatsCollisions; 1905 bge_hostaddr outXonSent; 1906 bge_hostaddr outXoffSent; 1907 bge_hostaddr flowControlDone; 1908 bge_hostaddr dot3StatsInternalMacTransmitErrors; 1909 bge_hostaddr dot3StatsSingleCollisionFrames; 1910 bge_hostaddr dot3StatsMultipleCollisionFrames; 1911 bge_hostaddr dot3StatsDeferredTransmissions; 1912 bge_hostaddr Reserved3; 1913 bge_hostaddr dot3StatsExcessiveCollisions; 1914 bge_hostaddr dot3StatsLateCollisions; 1915 bge_hostaddr dot3Collided2Times; 1916 bge_hostaddr dot3Collided3Times; 1917 bge_hostaddr dot3Collided4Times; 1918 bge_hostaddr dot3Collided5Times; 1919 bge_hostaddr dot3Collided6Times; 1920 bge_hostaddr dot3Collided7Times; 1921 bge_hostaddr dot3Collided8Times; 1922 bge_hostaddr dot3Collided9Times; 1923 bge_hostaddr dot3Collided10Times; 1924 bge_hostaddr dot3Collided11Times; 1925 bge_hostaddr dot3Collided12Times; 1926 bge_hostaddr dot3Collided13Times; 1927 bge_hostaddr dot3Collided14Times; 1928 bge_hostaddr dot3Collided15Times; 1929 bge_hostaddr ifHCOutUcastPkts; 1930 bge_hostaddr ifHCOutMulticastPkts; 1931 bge_hostaddr ifHCOutBroadcastPkts; 1932 bge_hostaddr dot3StatsCarrierSenseErrors; 1933 bge_hostaddr ifOutDiscards; 1934 bge_hostaddr ifOutErrors; 1935}; 1936 1937/* Stats counters access through registers */ 1938struct bge_mac_stats_regs { 1939 u_int32_t ifHCOutOctets; 1940 u_int32_t Reserved0; 1941 u_int32_t etherStatsCollisions; 1942 u_int32_t outXonSent; 1943 u_int32_t outXoffSent; 1944 u_int32_t Reserved1; 1945 u_int32_t dot3StatsInternalMacTransmitErrors; 1946 u_int32_t dot3StatsSingleCollisionFrames; 1947 u_int32_t dot3StatsMultipleCollisionFrames; 1948 u_int32_t dot3StatsDeferredTransmissions; 1949 u_int32_t Reserved2; 1950 u_int32_t dot3StatsExcessiveCollisions; 1951 u_int32_t dot3StatsLateCollisions; 1952 u_int32_t Reserved3[14]; 1953 u_int32_t ifHCOutUcastPkts; 1954 u_int32_t ifHCOutMulticastPkts; 1955 u_int32_t ifHCOutBroadcastPkts; 1956 u_int32_t Reserved4[2]; 1957 u_int32_t ifHCInOctets; 1958 u_int32_t Reserved5; 1959 u_int32_t etherStatsFragments; 1960 u_int32_t ifHCInUcastPkts; 1961 u_int32_t ifHCInMulticastPkts; 1962 u_int32_t ifHCInBroadcastPkts; 1963 u_int32_t dot3StatsFCSErrors; 1964 u_int32_t dot3StatsAlignmentErrors; 1965 u_int32_t xonPauseFramesReceived; 1966 u_int32_t xoffPauseFramesReceived; 1967 u_int32_t macControlFramesReceived; 1968 u_int32_t xoffStateEntered; 1969 u_int32_t dot3StatsFramesTooLong; 1970 u_int32_t etherStatsJabbers; 1971 u_int32_t etherStatsUndersizePkts; 1972}; 1973 1974struct bge_stats { 1975 u_int8_t Reserved0[256]; 1976 1977 /* Statistics maintained by Receive MAC. */ 1978 struct bge_rx_mac_stats rxstats; 1979 1980 bge_hostaddr Unused1[37]; 1981 1982 /* Statistics maintained by Transmit MAC. */ 1983 struct bge_tx_mac_stats txstats; 1984 1985 bge_hostaddr Unused2[31]; 1986 1987 /* Statistics maintained by Receive List Placement. */ 1988 bge_hostaddr COSIfHCInPkts[16]; 1989 bge_hostaddr COSFramesDroppedDueToFilters; 1990 bge_hostaddr nicDmaWriteQueueFull; 1991 bge_hostaddr nicDmaWriteHighPriQueueFull; 1992 bge_hostaddr nicNoMoreRxBDs; 1993 bge_hostaddr ifInDiscards; 1994 bge_hostaddr ifInErrors; 1995 bge_hostaddr nicRecvThresholdHit; 1996 1997 bge_hostaddr Unused3[9]; 1998 1999 /* Statistics maintained by Send Data Initiator. */ 2000 bge_hostaddr COSIfHCOutPkts[16]; 2001 bge_hostaddr nicDmaReadQueueFull; 2002 bge_hostaddr nicDmaReadHighPriQueueFull; 2003 bge_hostaddr nicSendDataCompQueueFull; 2004 2005 /* Statistics maintained by Host Coalescing. */ 2006 bge_hostaddr nicRingSetSendProdIndex; 2007 bge_hostaddr nicRingStatusUpdate; 2008 bge_hostaddr nicInterrupts; 2009 bge_hostaddr nicAvoidedInterrupts; 2010 bge_hostaddr nicSendThresholdHit; 2011 2012 u_int8_t Reserved4[320]; 2013}; 2014 2015/* 2016 * Tigon general information block. This resides in host memory 2017 * and contains the status counters, ring control blocks and 2018 * producer pointers. 2019 */ 2020 2021struct bge_gib { 2022 struct bge_stats bge_stats; 2023 struct bge_rcb bge_tx_rcb[16]; 2024 struct bge_rcb bge_std_rx_rcb; 2025 struct bge_rcb bge_jumbo_rx_rcb; 2026 struct bge_rcb bge_mini_rx_rcb; 2027 struct bge_rcb bge_return_rcb; 2028}; 2029 2030/* 2031 * NOTE! On the Alpha, we have an alignment constraint. 2032 * The first thing in the packet is a 14-byte Ethernet header. 2033 * This means that the packet is misaligned. To compensate, 2034 * we actually offset the data 2 bytes into the cluster. This 2035 * alignes the packet after the Ethernet header at a 32-bit 2036 * boundary. 2037 */ 2038 2039#define ETHER_ALIGN 2 2040 2041#define BGE_FRAMELEN 1518 2042#define BGE_MAX_FRAMELEN 1536 2043#define BGE_JUMBO_FRAMELEN 9018 2044#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2045#define BGE_PAGE_SIZE PAGE_SIZE 2046#define BGE_MIN_FRAMELEN 60 2047 2048/* 2049 * Other utility macros. 2050 */ 2051#define BGE_INC(x, y) (x) = (x + 1) % y 2052 2053/* 2054 * Vital product data and structures. 2055 */ 2056#define BGE_VPD_FLAG 0x8000 2057 2058/* VPD structures */ 2059struct vpd_res { 2060 u_int8_t vr_id; 2061 u_int8_t vr_len; 2062 u_int8_t vr_pad; 2063}; 2064 2065struct vpd_key { 2066 char vk_key[2]; 2067 u_int8_t vk_len; 2068}; 2069 2070#define VPD_RES_ID 0x82 /* ID string */ 2071#define VPD_RES_READ 0x90 /* start of read only area */ 2072#define VPD_RES_WRITE 0x81 /* start of read/write area */ 2073#define VPD_RES_END 0x78 /* end tag */ 2074 2075 2076/* 2077 * Register access macros. The Tigon always uses memory mapped register 2078 * accesses and all registers must be accessed with 32 bit operations. 2079 */ 2080 2081#define CSR_WRITE_4(sc, reg, val) \ 2082 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2083 2084#define CSR_READ_4(sc, reg) \ 2085 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2086 2087#define BGE_SETBIT(sc, reg, x) \ 2088 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2089#define BGE_CLRBIT(sc, reg, x) \ 2090 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2091 2092#define PCI_SETBIT(pc, tag, reg, x) \ 2093 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 2094#define PCI_CLRBIT(pc, tag, reg, x) \ 2095 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 2096 2097/* 2098 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2099 * values are tuneable. They control the actual amount of buffers 2100 * allocated for the standard, mini and jumbo receive rings. 2101 */ 2102 2103#define BGE_SSLOTS 256 2104#define BGE_MSLOTS 256 2105#define BGE_JSLOTS 384 2106 2107#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2108#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2109 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2110#define BGE_JPAGESZ PAGE_SIZE 2111#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2112#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2113 2114/* 2115 * Ring structures. Most of these reside in host memory and we tell 2116 * the NIC where they are via the ring control blocks. The exceptions 2117 * are the tx and command rings, which live in NIC memory and which 2118 * we access via the shared memory window. 2119 */ 2120struct bge_ring_data { 2121 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2122 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2123 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2124 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2125 struct bge_status_block bge_status_block; 2126 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2127 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2128 struct bge_gib bge_info; 2129}; 2130 2131#define BGE_RING_DMA_ADDR(sc, offset) \ 2132 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2133 offsetof(struct bge_ring_data, offset)) 2134 2135/* 2136 * Number of DMA segments in a TxCB. Note that this is carefully 2137 * chosen to make the total struct size an even power of two. It's 2138 * critical that no TxCB be split across a page boundry since 2139 * no attempt is made to allocate physically contiguous memory. 2140 * 2141 */ 2142#ifdef __LP64__ 2143#define BGE_NTXSEG 30 2144#else 2145#define BGE_NTXSEG 31 2146#endif 2147 2148/* 2149 * Mbuf pointers. We need these to keep track of the virtual addresses 2150 * of our mbuf chains since we can only convert from physical to virtual, 2151 * not the other way around. 2152 */ 2153struct bge_chain_data { 2154 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2155 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2156 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2157 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2158 bus_dmamap_t bge_tx_map[BGE_TX_RING_CNT]; 2159 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2160 bus_dmamap_t bge_rx_jumbo_map; 2161 /* Stick the jumbo mem management stuff here too. */ 2162 caddr_t bge_jslots[BGE_JSLOTS]; 2163 void *bge_jumbo_buf; 2164}; 2165 2166#define BGE_JUMBO_DMA_ADDR(sc, m) \ 2167 ((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \ 2168 (mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf)) 2169 2170struct bge_type { 2171 u_int16_t bge_vid; 2172 u_int16_t bge_did; 2173 char *bge_name; 2174}; 2175 2176#define BGE_HWREV_TIGON 0x01 2177#define BGE_HWREV_TIGON_II 0x02 2178#define BGE_TIMEOUT 100000 2179#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2180 2181struct bge_jpool_entry { 2182 int slot; 2183 LIST_ENTRY(bge_jpool_entry) jpool_entries; 2184}; 2185 2186struct bge_bcom_hack { 2187 int reg; 2188 int val; 2189}; 2190 2191struct bge_softc { 2192 struct device bge_dev; 2193 struct arpcom arpcom; /* interface info */ 2194 bus_space_handle_t bge_bhandle; 2195 bus_space_tag_t bge_btag; 2196 void *bge_intrhand; 2197 struct pci_attach_args bge_pa; 2198 struct mii_data bge_mii; 2199 struct ifmedia bge_ifmedia; /* media info */ 2200 u_int8_t bge_extram; /* has external SSRAM */ 2201 u_int8_t bge_tbi; 2202 u_int8_t bge_rx_alignment_bug; 2203 bus_dma_tag_t bge_dmatag; 2204 u_int32_t bge_chipid; 2205 u_int8_t bge_asicrev; 2206 u_int8_t bge_chiprev; 2207 u_int8_t bge_no_3_led; 2208 struct bge_ring_data *bge_rdata; /* rings */ 2209 struct bge_chain_data bge_cdata; /* mbufs */ 2210 bus_dmamap_t bge_ring_map; 2211 u_int16_t bge_tx_saved_considx; 2212 u_int16_t bge_rx_saved_considx; 2213 u_int16_t bge_ev_saved_considx; 2214 u_int16_t bge_return_ring_cnt; 2215 u_int16_t bge_std; /* current std ring head */ 2216 u_int16_t bge_jumbo; /* current jumo ring head */ 2217 LIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2218 LIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2219 u_int32_t bge_stat_ticks; 2220 u_int32_t bge_rx_coal_ticks; 2221 u_int32_t bge_tx_coal_ticks; 2222 u_int32_t bge_rx_max_coal_bds; 2223 u_int32_t bge_tx_max_coal_bds; 2224 u_int32_t bge_tx_buf_ratio; 2225 int bge_if_flags; 2226 int bge_txcnt; 2227 int bge_link; 2228 struct timeout bge_timeout; 2229 char *bge_vpd_prodname; 2230 char *bge_vpd_readonly; 2231}; 2232