if_bgereg.h revision 1.5
1/* $OpenBSD: if_bgereg.h,v 1.5 2002/11/26 04:38:40 nate Exp $ */ 2/* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bgereg.h,v 1.11 2002/11/14 23:54:50 sam Exp $ 35 */ 36 37/* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65#define BGE_PAGE_ZERO 0x00000000 66#define BGE_PAGE_ZERO_END 0x000000FF 67#define BGE_SEND_RING_RCB 0x00000100 68#define BGE_SEND_RING_RCB_END 0x000001FF 69#define BGE_RX_RETURN_RING_RCB 0x00000200 70#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 71#define BGE_STATS_BLOCK 0x00000300 72#define BGE_STATS_BLOCK_END 0x00000AFF 73#define BGE_STATUS_BLOCK 0x00000B00 74#define BGE_STATUS_BLOCK_END 0x00000B4F 75#define BGE_SOFTWARE_GENCOMM 0x00000B50 76#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 77#define BGE_UNMAPPED 0x00001000 78#define BGE_UNMAPPED_END 0x00001FFF 79#define BGE_DMA_DESCRIPTORS 0x00002000 80#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 81#define BGE_SEND_RING_1_TO_4 0x00004000 82#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 83 84/* Mappings for internal memory configuration */ 85#define BGE_STD_RX_RINGS 0x00006000 86#define BGE_STD_RX_RINGS_END 0x00006FFF 87#define BGE_JUMBO_RX_RINGS 0x00007000 88#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 89#define BGE_BUFFPOOL_1 0x00008000 90#define BGE_BUFFPOOL_1_END 0x0000FFFF 91#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 92#define BGE_BUFFPOOL_2_END 0x00017FFF 93#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 94#define BGE_BUFFPOOL_3_END 0x0001FFFF 95 96/* Mappings for external SSRAM configurations */ 97#define BGE_SEND_RING_5_TO_6 0x00006000 98#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 99#define BGE_SEND_RING_7_TO_8 0x00007000 100#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 101#define BGE_SEND_RING_9_TO_16 0x00008000 102#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 103#define BGE_EXT_STD_RX_RINGS 0x0000C000 104#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 105#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 106#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 107#define BGE_MINI_RX_RINGS 0x0000E000 108#define BGE_MINI_RX_RINGS_END 0x0000FFFF 109#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 110#define BGE_AVAIL_REGION1_END 0x00017FFF 111#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 112#define BGE_AVAIL_REGION2_END 0x0001FFFF 113#define BGE_EXT_SSRAM 0x00020000 114#define BGE_EXT_SSRAM_END 0x000FFFFF 115 116 117/* 118 * BCM570x register offsets. These are memory mapped registers 119 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 120 * Each register must be accessed using 32 bit operations. 121 * 122 * All registers are accessed through a 32K shared memory block. 123 * The first group of registers are actually copies of the PCI 124 * configuration space registers. 125 */ 126 127/* 128 * PCI registers defined in the PCI 2.2 spec. 129 */ 130#define BGE_PCI_VID 0x00 131#define BGE_PCI_DID 0x02 132#define BGE_PCI_CMD 0x04 133#define BGE_PCI_STS 0x06 134#define BGE_PCI_REV 0x08 135#define BGE_PCI_CLASS 0x09 136#define BGE_PCI_CACHESZ 0x0C 137#define BGE_PCI_LATTIMER 0x0D 138#define BGE_PCI_HDRTYPE 0x0E 139#define BGE_PCI_BIST 0x0F 140#define BGE_PCI_BAR0 0x10 141#define BGE_PCI_BAR1 0x14 142#define BGE_PCI_SUBSYS 0x2C 143#define BGE_PCI_SUBVID 0x2E 144#define BGE_PCI_ROMBASE 0x30 145#define BGE_PCI_CAPPTR 0x34 146#define BGE_PCI_INTLINE 0x3C 147#define BGE_PCI_INTPIN 0x3D 148#define BGE_PCI_MINGNT 0x3E 149#define BGE_PCI_MAXLAT 0x3F 150#define BGE_PCI_PCIXCAP 0x40 151#define BGE_PCI_NEXTPTR_PM 0x41 152#define BGE_PCI_PCIX_CMD 0x42 153#define BGE_PCI_PCIX_STS 0x44 154#define BGE_PCI_PWRMGMT_CAPID 0x48 155#define BGE_PCI_NEXTPTR_VPD 0x49 156#define BGE_PCI_PWRMGMT_CAPS 0x4A 157#define BGE_PCI_PWRMGMT_CMD 0x4C 158#define BGE_PCI_PWRMGMT_STS 0x4D 159#define BGE_PCI_PWRMGMT_DATA 0x4F 160#define BGE_PCI_VPD_CAPID 0x50 161#define BGE_PCI_NEXTPTR_MSI 0x51 162#define BGE_PCI_VPD_ADDR 0x52 163#define BGE_PCI_VPD_DATA 0x54 164#define BGE_PCI_MSI_CAPID 0x58 165#define BGE_PCI_NEXTPTR_NONE 0x59 166#define BGE_PCI_MSI_CTL 0x5A 167#define BGE_PCI_MSI_ADDR_HI 0x5C 168#define BGE_PCI_MSI_ADDR_LO 0x60 169#define BGE_PCI_MSI_DATA 0x64 170 171/* 172 * PCI registers specific to the BCM570x family. 173 */ 174#define BGE_PCI_MISC_CTL 0x68 175#define BGE_PCI_DMA_RW_CTL 0x6C 176#define BGE_PCI_PCISTATE 0x70 177#define BGE_PCI_CLKCTL 0x74 178#define BGE_PCI_REG_BASEADDR 0x78 179#define BGE_PCI_MEMWIN_BASEADDR 0x7C 180#define BGE_PCI_REG_DATA 0x80 181#define BGE_PCI_MEMWIN_DATA 0x84 182#define BGE_PCI_MODECTL 0x88 183#define BGE_PCI_MISC_CFG 0x8C 184#define BGE_PCI_MISC_LOCALCTL 0x90 185#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 186#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 187#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 188#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 189#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 190#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 191#define BGE_PCI_ISR_MBX_HI 0xB0 192#define BGE_PCI_ISR_MBX_LO 0xB4 193 194/* PCI Misc. Host control register */ 195#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 196#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 197#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 198#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 199#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 200#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 201#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 202#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 203#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 204 205#define BGE_BIGENDIAN_INIT \ 206 (BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \ 207 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 208 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR) 209 210#define BGE_LITTLEENDIAN_INIT \ 211 (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \ 212 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS) 213 214#define BGE_ASICREV_TIGON_I 0x40000000 215#define BGE_ASICREV_TIGON_II 0x60000000 216#define BGE_ASICREV_BCM5700_B0 0x71000000 217#define BGE_ASICREV_BCM5700_B1 0x71020000 218#define BGE_ASICREV_BCM5700_B2 0x71030000 219#define BGE_ASICREV_BCM5700_ALTIMA 0x71040000 220#define BGE_ASICREV_BCM5700_C0 0x72000000 221#define BGE_ASICREV_BCM5701_A0 0x00000000 /* grrrr */ 222#define BGE_ASICREV_BCM5701_B0 0x01000000 223#define BGE_ASICREV_BCM5701_B2 0x01020000 224#define BGE_ASICREV_BCM5701_B5 0x01050000 225#define BGE_ASICREV_BCM5703_A0 0x10000000 226#define BGE_ASICREV_BCM5703_A1 0x10010000 227#define BGE_ASICREV_BCM5703_A2 0x10020000 228 229/* shorthand one */ 230#define BGE_ASICREV_BCM5700 0x71000000 231 232/* PCI DMA Read/Write Control register */ 233#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 234#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 235#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 236#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 237#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 238#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 239#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 240#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 241#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 242#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 243 244#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 245#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 246#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 247#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 248#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 249#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 250#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 251#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 252 253#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 254#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 255#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 256#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 257#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 258#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 259#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 260#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 261 262/* 263 * PCI state register -- note, this register is read only 264 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 265 * register is set. 266 */ 267#define BGE_PCISTATE_FORCE_RESET 0x00000001 268#define BGE_PCISTATE_INTR_STATE 0x00000002 269#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 270#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 271#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 272#define BGE_PCISTATE_WANT_EXPROM 0x00000020 273#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 274#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 275#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 276 277/* 278 * PCI Clock Control register -- note, this register is read only 279 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 280 * register is set. 281 */ 282#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 283#define BGE_PCICLOCKCTL_M66EN 0x00000080 284#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 285#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 286#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 287#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 288#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 289#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 290#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 291#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 292 293/* 294 * High priority mailbox registers 295 * Each mailbox is 64-bits wide, though we only use the 296 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 297 * first. The NIC will load the mailbox after the lower 32 bit word 298 * has been updated. 299 */ 300#define BGE_MBX_IRQ0_HI 0x0200 301#define BGE_MBX_IRQ0_LO 0x0204 302#define BGE_MBX_IRQ1_HI 0x0208 303#define BGE_MBX_IRQ1_LO 0x020C 304#define BGE_MBX_IRQ2_HI 0x0210 305#define BGE_MBX_IRQ2_LO 0x0214 306#define BGE_MBX_IRQ3_HI 0x0218 307#define BGE_MBX_IRQ3_LO 0x021C 308#define BGE_MBX_GEN0_HI 0x0220 309#define BGE_MBX_GEN0_LO 0x0224 310#define BGE_MBX_GEN1_HI 0x0228 311#define BGE_MBX_GEN1_LO 0x022C 312#define BGE_MBX_GEN2_HI 0x0230 313#define BGE_MBX_GEN2_LO 0x0234 314#define BGE_MBX_GEN3_HI 0x0228 315#define BGE_MBX_GEN3_LO 0x022C 316#define BGE_MBX_GEN4_HI 0x0240 317#define BGE_MBX_GEN4_LO 0x0244 318#define BGE_MBX_GEN5_HI 0x0248 319#define BGE_MBX_GEN5_LO 0x024C 320#define BGE_MBX_GEN6_HI 0x0250 321#define BGE_MBX_GEN6_LO 0x0254 322#define BGE_MBX_GEN7_HI 0x0258 323#define BGE_MBX_GEN7_LO 0x025C 324#define BGE_MBX_RELOAD_STATS_HI 0x0260 325#define BGE_MBX_RELOAD_STATS_LO 0x0264 326#define BGE_MBX_RX_STD_PROD_HI 0x0268 327#define BGE_MBX_RX_STD_PROD_LO 0x026C 328#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 329#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 330#define BGE_MBX_RX_MINI_PROD_HI 0x0278 331#define BGE_MBX_RX_MINI_PROD_LO 0x027C 332#define BGE_MBX_RX_CONS0_HI 0x0280 333#define BGE_MBX_RX_CONS0_LO 0x0284 334#define BGE_MBX_RX_CONS1_HI 0x0288 335#define BGE_MBX_RX_CONS1_LO 0x028C 336#define BGE_MBX_RX_CONS2_HI 0x0290 337#define BGE_MBX_RX_CONS2_LO 0x0294 338#define BGE_MBX_RX_CONS3_HI 0x0298 339#define BGE_MBX_RX_CONS3_LO 0x029C 340#define BGE_MBX_RX_CONS4_HI 0x02A0 341#define BGE_MBX_RX_CONS4_LO 0x02A4 342#define BGE_MBX_RX_CONS5_HI 0x02A8 343#define BGE_MBX_RX_CONS5_LO 0x02AC 344#define BGE_MBX_RX_CONS6_HI 0x02B0 345#define BGE_MBX_RX_CONS6_LO 0x02B4 346#define BGE_MBX_RX_CONS7_HI 0x02B8 347#define BGE_MBX_RX_CONS7_LO 0x02BC 348#define BGE_MBX_RX_CONS8_HI 0x02C0 349#define BGE_MBX_RX_CONS8_LO 0x02C4 350#define BGE_MBX_RX_CONS9_HI 0x02C8 351#define BGE_MBX_RX_CONS9_LO 0x02CC 352#define BGE_MBX_RX_CONS10_HI 0x02D0 353#define BGE_MBX_RX_CONS10_LO 0x02D4 354#define BGE_MBX_RX_CONS11_HI 0x02D8 355#define BGE_MBX_RX_CONS11_LO 0x02DC 356#define BGE_MBX_RX_CONS12_HI 0x02E0 357#define BGE_MBX_RX_CONS12_LO 0x02E4 358#define BGE_MBX_RX_CONS13_HI 0x02E8 359#define BGE_MBX_RX_CONS13_LO 0x02EC 360#define BGE_MBX_RX_CONS14_HI 0x02F0 361#define BGE_MBX_RX_CONS14_LO 0x02F4 362#define BGE_MBX_RX_CONS15_HI 0x02F8 363#define BGE_MBX_RX_CONS15_LO 0x02FC 364#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 365#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 366#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 367#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 368#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 369#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 370#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 371#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 372#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 373#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 374#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 375#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 376#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 377#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 378#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 379#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 380#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 381#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 382#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 383#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 384#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 385#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 386#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 387#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 388#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 389#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 390#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 391#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 392#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 393#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 394#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 395#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 396#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 397#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 398#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 399#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 400#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 401#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 402#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 403#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 404#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 405#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 406#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 407#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 408#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 409#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 410#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 411#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 412#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 413#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 414#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 415#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 416#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 417#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 418#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 419#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 420#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 421#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 422#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 423#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 424#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 425#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 426#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 427#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 428 429#define BGE_TX_RINGS_MAX 4 430#define BGE_TX_RINGS_EXTSSRAM_MAX 16 431#define BGE_RX_RINGS_MAX 16 432 433/* Ethernet MAC control registers */ 434#define BGE_MAC_MODE 0x0400 435#define BGE_MAC_STS 0x0404 436#define BGE_MAC_EVT_ENB 0x0408 437#define BGE_MAC_LED_CTL 0x040C 438#define BGE_MAC_ADDR1_LO 0x0410 439#define BGE_MAC_ADDR1_HI 0x0414 440#define BGE_MAC_ADDR2_LO 0x0418 441#define BGE_MAC_ADDR2_HI 0x041C 442#define BGE_MAC_ADDR3_LO 0x0420 443#define BGE_MAC_ADDR3_HI 0x0424 444#define BGE_MAC_ADDR4_LO 0x0428 445#define BGE_MAC_ADDR4_HI 0x042C 446#define BGE_WOL_PATPTR 0x0430 447#define BGE_WOL_PATCFG 0x0434 448#define BGE_TX_RANDOM_BACKOFF 0x0438 449#define BGE_RX_MTU 0x043C 450#define BGE_GBIT_PCS_TEST 0x0440 451#define BGE_TX_TBI_AUTONEG 0x0444 452#define BGE_RX_TBI_AUTONEG 0x0448 453#define BGE_MI_COMM 0x044C 454#define BGE_MI_STS 0x0450 455#define BGE_MI_MODE 0x0454 456#define BGE_AUTOPOLL_STS 0x0458 457#define BGE_TX_MODE 0x045C 458#define BGE_TX_STS 0x0460 459#define BGE_TX_LENGTHS 0x0464 460#define BGE_RX_MODE 0x0468 461#define BGE_RX_STS 0x046C 462#define BGE_MAR0 0x0470 463#define BGE_MAR1 0x0474 464#define BGE_MAR2 0x0478 465#define BGE_MAR3 0x047C 466#define BGE_RX_BD_RULES_CTL0 0x0480 467#define BGE_RX_BD_RULES_MASKVAL0 0x0484 468#define BGE_RX_BD_RULES_CTL1 0x0488 469#define BGE_RX_BD_RULES_MASKVAL1 0x048C 470#define BGE_RX_BD_RULES_CTL2 0x0490 471#define BGE_RX_BD_RULES_MASKVAL2 0x0494 472#define BGE_RX_BD_RULES_CTL3 0x0498 473#define BGE_RX_BD_RULES_MASKVAL3 0x049C 474#define BGE_RX_BD_RULES_CTL4 0x04A0 475#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 476#define BGE_RX_BD_RULES_CTL5 0x04A8 477#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 478#define BGE_RX_BD_RULES_CTL6 0x04B0 479#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 480#define BGE_RX_BD_RULES_CTL7 0x04B8 481#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 482#define BGE_RX_BD_RULES_CTL8 0x04C0 483#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 484#define BGE_RX_BD_RULES_CTL9 0x04C8 485#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 486#define BGE_RX_BD_RULES_CTL10 0x04D0 487#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 488#define BGE_RX_BD_RULES_CTL11 0x04D8 489#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 490#define BGE_RX_BD_RULES_CTL12 0x04E0 491#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 492#define BGE_RX_BD_RULES_CTL13 0x04E8 493#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 494#define BGE_RX_BD_RULES_CTL14 0x04F0 495#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 496#define BGE_RX_BD_RULES_CTL15 0x04F8 497#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 498#define BGE_RX_RULES_CFG 0x0500 499#define BGE_RX_STATS 0x0800 500#define BGE_TX_STATS 0x0880 501 502/* Ethernet MAC Mode register */ 503#define BGE_MACMODE_RESET 0x00000001 504#define BGE_MACMODE_HALF_DUPLEX 0x00000002 505#define BGE_MACMODE_PORTMODE 0x0000000C 506#define BGE_MACMODE_LOOPBACK 0x00000010 507#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 508#define BGE_MACMODE_TX_BURST_ENB 0x00000100 509#define BGE_MACMODE_MAX_DEFER 0x00000200 510#define BGE_MACMODE_LINK_POLARITY 0x00000400 511#define BGE_MACMODE_RX_STATS_ENB 0x00000800 512#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 513#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 514#define BGE_MACMODE_TX_STATS_ENB 0x00004000 515#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 516#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 517#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 518#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 519#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 520#define BGE_MACMODE_MIP_ENB 0x00100000 521#define BGE_MACMODE_TXDMA_ENB 0x00200000 522#define BGE_MACMODE_RXDMA_ENB 0x00400000 523#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 524 525#define BGE_PORTMODE_NONE 0x00000000 526#define BGE_PORTMODE_MII 0x00000004 527#define BGE_PORTMODE_GMII 0x00000008 528#define BGE_PORTMODE_TBI 0x0000000C 529 530/* MAC Status register */ 531#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 532#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 533#define BGE_MACSTAT_RX_CFG 0x00000004 534#define BGE_MACSTAT_CFG_CHANGED 0x00000008 535#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 536#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 537#define BGE_MACSTAT_LINK_CHANGED 0x00001000 538#define BGE_MACSTAT_MI_COMPLETE 0x00400000 539#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 540#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 541#define BGE_MACSTAT_ODI_ERROR 0x02000000 542#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 543#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 544 545/* MAC Event Enable Register */ 546#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 547#define BGE_EVTENB_LINK_CHANGED 0x00001000 548#define BGE_EVTENB_MI_COMPLETE 0x00400000 549#define BGE_EVTENB_MI_INTERRUPT 0x00800000 550#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 551#define BGE_EVTENB_ODI_ERROR 0x02000000 552#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 553#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 554 555/* LED Control Register */ 556#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 557#define BGE_LEDCTL_1000MBPS_LED 0x00000002 558#define BGE_LEDCTL_100MBPS_LED 0x00000004 559#define BGE_LEDCTL_10MBPS_LED 0x00000008 560#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 561#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 562#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 563#define BGE_LEDCTL_1000MBPS_STS 0x00000080 564#define BGE_LEDCTL_100MBPS_STS 0x00000100 565#define BGE_LEDCTL_10MBPS_STS 0x00000200 566#define BGE_LEDCTL_TRADLED_STS 0x00000400 567#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 568#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 569 570/* TX backoff seed register */ 571#define BGE_TX_BACKOFF_SEED_MASK 0x3F 572 573/* Autopoll status register */ 574#define BGE_AUTOPOLLSTS_ERROR 0x00000001 575 576/* Transmit MAC mode register */ 577#define BGE_TXMODE_RESET 0x00000001 578#define BGE_TXMODE_ENABLE 0x00000002 579#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 580#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 581#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 582 583/* Transmit MAC status register */ 584#define BGE_TXSTAT_RX_XOFFED 0x00000001 585#define BGE_TXSTAT_SENT_XOFF 0x00000002 586#define BGE_TXSTAT_SENT_XON 0x00000004 587#define BGE_TXSTAT_LINK_UP 0x00000008 588#define BGE_TXSTAT_ODI_UFLOW 0x00000010 589#define BGE_TXSTAT_ODI_OFLOW 0x00000020 590 591/* Transmit MAC lengths register */ 592#define BGE_TXLEN_SLOTTIME 0x000000FF 593#define BGE_TXLEN_IPG 0x00000F00 594#define BGE_TXLEN_CRS 0x00003000 595 596/* Receive MAC mode register */ 597#define BGE_RXMODE_RESET 0x00000001 598#define BGE_RXMODE_ENABLE 0x00000002 599#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 600#define BGE_RXMODE_RX_GIANTS 0x00000020 601#define BGE_RXMODE_RX_RUNTS 0x00000040 602#define BGE_RXMODE_8022_LENCHECK 0x00000080 603#define BGE_RXMODE_RX_PROMISC 0x00000100 604#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 605#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 606 607/* Receive MAC status register */ 608#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 609#define BGE_RXSTAT_RCVD_XOFF 0x00000002 610#define BGE_RXSTAT_RCVD_XON 0x00000004 611 612/* Receive Rules Control register */ 613#define BGE_RXRULECTL_OFFSET 0x000000FF 614#define BGE_RXRULECTL_CLASS 0x00001F00 615#define BGE_RXRULECTL_HDRTYPE 0x0000E000 616#define BGE_RXRULECTL_COMPARE_OP 0x00030000 617#define BGE_RXRULECTL_MAP 0x01000000 618#define BGE_RXRULECTL_DISCARD 0x02000000 619#define BGE_RXRULECTL_MASK 0x04000000 620#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 621#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 622#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 623#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 624 625/* Receive Rules Mask register */ 626#define BGE_RXRULEMASK_VALUE 0x0000FFFF 627#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 628 629/* MI communication register */ 630#define BGE_MICOMM_DATA 0x0000FFFF 631#define BGE_MICOMM_REG 0x001F0000 632#define BGE_MICOMM_PHY 0x03E00000 633#define BGE_MICOMM_CMD 0x0C000000 634#define BGE_MICOMM_READFAIL 0x10000000 635#define BGE_MICOMM_BUSY 0x20000000 636 637#define BGE_MIREG(x) ((x & 0x1F) << 16) 638#define BGE_MIPHY(x) ((x & 0x1F) << 21) 639#define BGE_MICMD_WRITE 0x04000000 640#define BGE_MICMD_READ 0x08000000 641 642/* MI status register */ 643#define BGE_MISTS_LINK 0x00000001 644#define BGE_MISTS_10MBPS 0x00000002 645 646#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 647#define BGE_MIMODE_AUTOPOLL 0x00000010 648#define BGE_MIMODE_CLKCNT 0x001F0000 649 650 651/* 652 * Send data initiator control registers. 653 */ 654#define BGE_SDI_MODE 0x0C00 655#define BGE_SDI_STATUS 0x0C04 656#define BGE_SDI_STATS_CTL 0x0C08 657#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 658#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 659#define BGE_LOCSTATS_COS0 0x0C80 660#define BGE_LOCSTATS_COS1 0x0C84 661#define BGE_LOCSTATS_COS2 0x0C88 662#define BGE_LOCSTATS_COS3 0x0C8C 663#define BGE_LOCSTATS_COS4 0x0C90 664#define BGE_LOCSTATS_COS5 0x0C84 665#define BGE_LOCSTATS_COS6 0x0C98 666#define BGE_LOCSTATS_COS7 0x0C9C 667#define BGE_LOCSTATS_COS8 0x0CA0 668#define BGE_LOCSTATS_COS9 0x0CA4 669#define BGE_LOCSTATS_COS10 0x0CA8 670#define BGE_LOCSTATS_COS11 0x0CAC 671#define BGE_LOCSTATS_COS12 0x0CB0 672#define BGE_LOCSTATS_COS13 0x0CB4 673#define BGE_LOCSTATS_COS14 0x0CB8 674#define BGE_LOCSTATS_COS15 0x0CBC 675#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 676#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 677#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 678#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 679#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 680#define BGE_LOCSTATS_IRQS 0x0CD4 681#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 682#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 683 684/* Send Data Initiator mode register */ 685#define BGE_SDIMODE_RESET 0x00000001 686#define BGE_SDIMODE_ENABLE 0x00000002 687#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 688 689/* Send Data Initiator stats register */ 690#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 691 692/* Send Data Initiator stats control register */ 693#define BGE_SDISTATSCTL_ENABLE 0x00000001 694#define BGE_SDISTATSCTL_FASTER 0x00000002 695#define BGE_SDISTATSCTL_CLEAR 0x00000004 696#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 697#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 698 699/* 700 * Send Data Completion Control registers 701 */ 702#define BGE_SDC_MODE 0x1000 703#define BGE_SDC_STATUS 0x1004 704 705/* Send Data completion mode register */ 706#define BGE_SDCMODE_RESET 0x00000001 707#define BGE_SDCMODE_ENABLE 0x00000002 708#define BGE_SDCMODE_ATTN 0x00000004 709 710/* Send Data completion status register */ 711#define BGE_SDCSTAT_ATTN 0x00000004 712 713/* 714 * Send BD Ring Selector Control registers 715 */ 716#define BGE_SRS_MODE 0x1400 717#define BGE_SRS_STATUS 0x1404 718#define BGE_SRS_HWDIAG 0x1408 719#define BGE_SRS_LOC_NIC_CONS0 0x1440 720#define BGE_SRS_LOC_NIC_CONS1 0x1444 721#define BGE_SRS_LOC_NIC_CONS2 0x1448 722#define BGE_SRS_LOC_NIC_CONS3 0x144C 723#define BGE_SRS_LOC_NIC_CONS4 0x1450 724#define BGE_SRS_LOC_NIC_CONS5 0x1454 725#define BGE_SRS_LOC_NIC_CONS6 0x1458 726#define BGE_SRS_LOC_NIC_CONS7 0x145C 727#define BGE_SRS_LOC_NIC_CONS8 0x1460 728#define BGE_SRS_LOC_NIC_CONS9 0x1464 729#define BGE_SRS_LOC_NIC_CONS10 0x1468 730#define BGE_SRS_LOC_NIC_CONS11 0x146C 731#define BGE_SRS_LOC_NIC_CONS12 0x1470 732#define BGE_SRS_LOC_NIC_CONS13 0x1474 733#define BGE_SRS_LOC_NIC_CONS14 0x1478 734#define BGE_SRS_LOC_NIC_CONS15 0x147C 735 736/* Send BD Ring Selector Mode register */ 737#define BGE_SRSMODE_RESET 0x00000001 738#define BGE_SRSMODE_ENABLE 0x00000002 739#define BGE_SRSMODE_ATTN 0x00000004 740 741/* Send BD Ring Selector Status register */ 742#define BGE_SRSSTAT_ERROR 0x00000004 743 744/* Send BD Ring Selector HW Diagnostics register */ 745#define BGE_SRSHWDIAG_STATE 0x0000000F 746#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 747#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 748#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 749 750/* 751 * Send BD Initiator Selector Control registers 752 */ 753#define BGE_SBDI_MODE 0x1800 754#define BGE_SBDI_STATUS 0x1804 755#define BGE_SBDI_LOC_NIC_PROD0 0x1808 756#define BGE_SBDI_LOC_NIC_PROD1 0x180C 757#define BGE_SBDI_LOC_NIC_PROD2 0x1810 758#define BGE_SBDI_LOC_NIC_PROD3 0x1814 759#define BGE_SBDI_LOC_NIC_PROD4 0x1818 760#define BGE_SBDI_LOC_NIC_PROD5 0x181C 761#define BGE_SBDI_LOC_NIC_PROD6 0x1820 762#define BGE_SBDI_LOC_NIC_PROD7 0x1824 763#define BGE_SBDI_LOC_NIC_PROD8 0x1828 764#define BGE_SBDI_LOC_NIC_PROD9 0x182C 765#define BGE_SBDI_LOC_NIC_PROD10 0x1830 766#define BGE_SBDI_LOC_NIC_PROD11 0x1834 767#define BGE_SBDI_LOC_NIC_PROD12 0x1838 768#define BGE_SBDI_LOC_NIC_PROD13 0x183C 769#define BGE_SBDI_LOC_NIC_PROD14 0x1840 770#define BGE_SBDI_LOC_NIC_PROD15 0x1844 771 772/* Send BD Initiator Mode register */ 773#define BGE_SBDIMODE_RESET 0x00000001 774#define BGE_SBDIMODE_ENABLE 0x00000002 775#define BGE_SBDIMODE_ATTN 0x00000004 776 777/* Send BD Initiator Status register */ 778#define BGE_SBDISTAT_ERROR 0x00000004 779 780/* 781 * Send BD Completion Control registers 782 */ 783#define BGE_SBDC_MODE 0x1C00 784#define BGE_SBDC_STATUS 0x1C04 785 786/* Send BD Completion Control Mode register */ 787#define BGE_SBDCMODE_RESET 0x00000001 788#define BGE_SBDCMODE_ENABLE 0x00000002 789#define BGE_SBDCMODE_ATTN 0x00000004 790 791/* Send BD Completion Control Status register */ 792#define BGE_SBDCSTAT_ATTN 0x00000004 793 794/* 795 * Receive List Placement Control registers 796 */ 797#define BGE_RXLP_MODE 0x2000 798#define BGE_RXLP_STATUS 0x2004 799#define BGE_RXLP_SEL_LIST_LOCK 0x2008 800#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 801#define BGE_RXLP_CFG 0x2010 802#define BGE_RXLP_STATS_CTL 0x2014 803#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 804#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 805#define BGE_RXLP_HEAD0 0x2100 806#define BGE_RXLP_TAIL0 0x2104 807#define BGE_RXLP_COUNT0 0x2108 808#define BGE_RXLP_HEAD1 0x2110 809#define BGE_RXLP_TAIL1 0x2114 810#define BGE_RXLP_COUNT1 0x2118 811#define BGE_RXLP_HEAD2 0x2120 812#define BGE_RXLP_TAIL2 0x2124 813#define BGE_RXLP_COUNT2 0x2128 814#define BGE_RXLP_HEAD3 0x2130 815#define BGE_RXLP_TAIL3 0x2134 816#define BGE_RXLP_COUNT3 0x2138 817#define BGE_RXLP_HEAD4 0x2140 818#define BGE_RXLP_TAIL4 0x2144 819#define BGE_RXLP_COUNT4 0x2148 820#define BGE_RXLP_HEAD5 0x2150 821#define BGE_RXLP_TAIL5 0x2154 822#define BGE_RXLP_COUNT5 0x2158 823#define BGE_RXLP_HEAD6 0x2160 824#define BGE_RXLP_TAIL6 0x2164 825#define BGE_RXLP_COUNT6 0x2168 826#define BGE_RXLP_HEAD7 0x2170 827#define BGE_RXLP_TAIL7 0x2174 828#define BGE_RXLP_COUNT7 0x2178 829#define BGE_RXLP_HEAD8 0x2180 830#define BGE_RXLP_TAIL8 0x2184 831#define BGE_RXLP_COUNT8 0x2188 832#define BGE_RXLP_HEAD9 0x2190 833#define BGE_RXLP_TAIL9 0x2194 834#define BGE_RXLP_COUNT9 0x2198 835#define BGE_RXLP_HEAD10 0x21A0 836#define BGE_RXLP_TAIL10 0x21A4 837#define BGE_RXLP_COUNT10 0x21A8 838#define BGE_RXLP_HEAD11 0x21B0 839#define BGE_RXLP_TAIL11 0x21B4 840#define BGE_RXLP_COUNT11 0x21B8 841#define BGE_RXLP_HEAD12 0x21C0 842#define BGE_RXLP_TAIL12 0x21C4 843#define BGE_RXLP_COUNT12 0x21C8 844#define BGE_RXLP_HEAD13 0x21D0 845#define BGE_RXLP_TAIL13 0x21D4 846#define BGE_RXLP_COUNT13 0x21D8 847#define BGE_RXLP_HEAD14 0x21E0 848#define BGE_RXLP_TAIL14 0x21E4 849#define BGE_RXLP_COUNT14 0x21E8 850#define BGE_RXLP_HEAD15 0x21F0 851#define BGE_RXLP_TAIL15 0x21F4 852#define BGE_RXLP_COUNT15 0x21F8 853#define BGE_RXLP_LOCSTAT_COS0 0x2200 854#define BGE_RXLP_LOCSTAT_COS1 0x2204 855#define BGE_RXLP_LOCSTAT_COS2 0x2208 856#define BGE_RXLP_LOCSTAT_COS3 0x220C 857#define BGE_RXLP_LOCSTAT_COS4 0x2210 858#define BGE_RXLP_LOCSTAT_COS5 0x2214 859#define BGE_RXLP_LOCSTAT_COS6 0x2218 860#define BGE_RXLP_LOCSTAT_COS7 0x221C 861#define BGE_RXLP_LOCSTAT_COS8 0x2220 862#define BGE_RXLP_LOCSTAT_COS9 0x2224 863#define BGE_RXLP_LOCSTAT_COS10 0x2228 864#define BGE_RXLP_LOCSTAT_COS11 0x222C 865#define BGE_RXLP_LOCSTAT_COS12 0x2230 866#define BGE_RXLP_LOCSTAT_COS13 0x2234 867#define BGE_RXLP_LOCSTAT_COS14 0x2238 868#define BGE_RXLP_LOCSTAT_COS15 0x223C 869#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 870#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 871#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 872#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 873#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 874#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 875#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 876 877 878/* Receive List Placement mode register */ 879#define BGE_RXLPMODE_RESET 0x00000001 880#define BGE_RXLPMODE_ENABLE 0x00000002 881#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 882#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 883#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 884 885/* Receive List Placement Status register */ 886#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 887#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 888#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 889 890/* 891 * Receive Data and Receive BD Initiator Control Registers 892 */ 893#define BGE_RDBDI_MODE 0x2400 894#define BGE_RDBDI_STATUS 0x2404 895#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 896#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 897#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 898#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 899#define BGE_RX_STD_RCB_HADDR_HI 0x2450 900#define BGE_RX_STD_RCB_HADDR_LO 0x2454 901#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 902#define BGE_RX_STD_RCB_NICADDR 0x245C 903#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 904#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 905#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 906#define BGE_RX_MINI_RCB_NICADDR 0x246C 907#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 908#define BGE_RDBDI_STD_RX_CONS 0x2474 909#define BGE_RDBDI_MINI_RX_CONS 0x2478 910#define BGE_RDBDI_RETURN_PROD0 0x2480 911#define BGE_RDBDI_RETURN_PROD1 0x2484 912#define BGE_RDBDI_RETURN_PROD2 0x2488 913#define BGE_RDBDI_RETURN_PROD3 0x248C 914#define BGE_RDBDI_RETURN_PROD4 0x2490 915#define BGE_RDBDI_RETURN_PROD5 0x2494 916#define BGE_RDBDI_RETURN_PROD6 0x2498 917#define BGE_RDBDI_RETURN_PROD7 0x249C 918#define BGE_RDBDI_RETURN_PROD8 0x24A0 919#define BGE_RDBDI_RETURN_PROD9 0x24A4 920#define BGE_RDBDI_RETURN_PROD10 0x24A8 921#define BGE_RDBDI_RETURN_PROD11 0x24AC 922#define BGE_RDBDI_RETURN_PROD12 0x24B0 923#define BGE_RDBDI_RETURN_PROD13 0x24B4 924#define BGE_RDBDI_RETURN_PROD14 0x24B8 925#define BGE_RDBDI_RETURN_PROD15 0x24BC 926#define BGE_RDBDI_HWDIAG 0x24C0 927 928 929/* Receive Data and Receive BD Initiator Mode register */ 930#define BGE_RDBDIMODE_RESET 0x00000001 931#define BGE_RDBDIMODE_ENABLE 0x00000002 932#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 933#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 934#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 935 936/* Receive Data and Receive BD Initiator Status register */ 937#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 938#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 939#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 940 941 942/* 943 * Receive Data Completion Control registers 944 */ 945#define BGE_RDC_MODE 0x2800 946 947/* Receive Data Completion Mode register */ 948#define BGE_RDCMODE_RESET 0x00000001 949#define BGE_RDCMODE_ENABLE 0x00000002 950#define BGE_RDCMODE_ATTN 0x00000004 951 952/* 953 * Receive BD Initiator Control registers 954 */ 955#define BGE_RBDI_MODE 0x2C00 956#define BGE_RBDI_STATUS 0x2C04 957#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 958#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 959#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 960#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 961#define BGE_RBDI_STD_REPL_THRESH 0x2C18 962#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 963 964/* Receive BD Initiator Mode register */ 965#define BGE_RBDIMODE_RESET 0x00000001 966#define BGE_RBDIMODE_ENABLE 0x00000002 967#define BGE_RBDIMODE_ATTN 0x00000004 968 969/* Receive BD Initiator Status register */ 970#define BGE_RBDISTAT_ATTN 0x00000004 971 972/* 973 * Receive BD Completion Control registers 974 */ 975#define BGE_RBDC_MODE 0x3000 976#define BGE_RBDC_STATUS 0x3004 977#define BGE_RBDC_JUMBO_BD_PROD 0x3008 978#define BGE_RBDC_STD_BD_PROD 0x300C 979#define BGE_RBDC_MINI_BD_PROD 0x3010 980 981/* Receive BD completion mode register */ 982#define BGE_RBDCMODE_RESET 0x00000001 983#define BGE_RBDCMODE_ENABLE 0x00000002 984#define BGE_RBDCMODE_ATTN 0x00000004 985 986/* Receive BD completion status register */ 987#define BGE_RBDCSTAT_ERROR 0x00000004 988 989/* 990 * Receive List Selector Control registers 991 */ 992#define BGE_RXLS_MODE 0x3400 993#define BGE_RXLS_STATUS 0x3404 994 995/* Receive List Selector Mode register */ 996#define BGE_RXLSMODE_RESET 0x00000001 997#define BGE_RXLSMODE_ENABLE 0x00000002 998#define BGE_RXLSMODE_ATTN 0x00000004 999 1000/* Receive List Selector Status register */ 1001#define BGE_RXLSSTAT_ERROR 0x00000004 1002 1003/* 1004 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1005 */ 1006#define BGE_MBCF_MODE 0x3800 1007#define BGE_MBCF_STATUS 0x3804 1008 1009/* Mbuf Cluster Free mode register */ 1010#define BGE_MBCFMODE_RESET 0x00000001 1011#define BGE_MBCFMODE_ENABLE 0x00000002 1012#define BGE_MBCFMODE_ATTN 0x00000004 1013 1014/* Mbuf Cluster Free status register */ 1015#define BGE_MBCFSTAT_ERROR 0x00000004 1016 1017/* 1018 * Host Coalescing Control registers 1019 */ 1020#define BGE_HCC_MODE 0x3C00 1021#define BGE_HCC_STATUS 0x3C04 1022#define BGE_HCC_RX_COAL_TICKS 0x3C08 1023#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1024#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1025#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1026#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1027#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1028#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1029#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C34 /* BDs during interrupt */ 1030#define BGE_HCC_STATS_TICKS 0x3C28 1031#define BGE_HCC_STATS_ADDR_HI 0x3C30 1032#define BGE_HCC_STATS_ADDR_LO 0x3C34 1033#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1034#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1035#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1036#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1037#define BGE_FLOW_ATTN 0x3C48 1038#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1039#define BGE_HCC_STD_BD_CONS 0x3C54 1040#define BGE_HCC_MINI_BD_CONS 0x3C58 1041#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1042#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1043#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1044#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1045#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1046#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1047#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1048#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1049#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1050#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1051#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1052#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1053#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1054#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1055#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1056#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1057#define BGE_HCC_TX_BD_CONS0 0x3CC0 1058#define BGE_HCC_TX_BD_CONS1 0x3CC4 1059#define BGE_HCC_TX_BD_CONS2 0x3CC8 1060#define BGE_HCC_TX_BD_CONS3 0x3CCC 1061#define BGE_HCC_TX_BD_CONS4 0x3CD0 1062#define BGE_HCC_TX_BD_CONS5 0x3CD4 1063#define BGE_HCC_TX_BD_CONS6 0x3CD8 1064#define BGE_HCC_TX_BD_CONS7 0x3CDC 1065#define BGE_HCC_TX_BD_CONS8 0x3CE0 1066#define BGE_HCC_TX_BD_CONS9 0x3CE4 1067#define BGE_HCC_TX_BD_CONS10 0x3CE8 1068#define BGE_HCC_TX_BD_CONS11 0x3CEC 1069#define BGE_HCC_TX_BD_CONS12 0x3CF0 1070#define BGE_HCC_TX_BD_CONS13 0x3CF4 1071#define BGE_HCC_TX_BD_CONS14 0x3CF8 1072#define BGE_HCC_TX_BD_CONS15 0x3CFC 1073 1074 1075/* Host coalescing mode register */ 1076#define BGE_HCCMODE_RESET 0x00000001 1077#define BGE_HCCMODE_ENABLE 0x00000002 1078#define BGE_HCCMODE_ATTN 0x00000004 1079#define BGE_HCCMODE_COAL_NOW 0x00000008 1080#define BGE_HCCMODE_MSI_BITS 0x0x000070 1081#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1082 1083#define BGE_STATBLKSZ_FULL 0x00000000 1084#define BGE_STATBLKSZ_64BYTE 0x00000080 1085#define BGE_STATBLKSZ_32BYTE 0x00000100 1086 1087/* Host coalescing status register */ 1088#define BGE_HCCSTAT_ERROR 0x00000004 1089 1090/* Flow attention register */ 1091#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1092#define BGE_FLOWATTN_MEMARB 0x00000080 1093#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1094#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1095#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1096#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1097#define BGE_FLOWATTN_RDBDI 0x00080000 1098#define BGE_FLOWATTN_RXLS 0x00100000 1099#define BGE_FLOWATTN_RXLP 0x00200000 1100#define BGE_FLOWATTN_RBDC 0x00400000 1101#define BGE_FLOWATTN_RBDI 0x00800000 1102#define BGE_FLOWATTN_SDC 0x08000000 1103#define BGE_FLOWATTN_SDI 0x10000000 1104#define BGE_FLOWATTN_SRS 0x20000000 1105#define BGE_FLOWATTN_SBDC 0x40000000 1106#define BGE_FLOWATTN_SBDI 0x80000000 1107 1108/* 1109 * Memory arbiter registers 1110 */ 1111#define BGE_MARB_MODE 0x4000 1112#define BGE_MARB_STATUS 0x4004 1113#define BGE_MARB_TRAPADDR_HI 0x4008 1114#define BGE_MARB_TRAPADDR_LO 0x400C 1115 1116/* Memory arbiter mode register */ 1117#define BGE_MARBMODE_RESET 0x00000001 1118#define BGE_MARBMODE_ENABLE 0x00000002 1119#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1120#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1121#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1122#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1123#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1124#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1125#define BGE_MARBMODE_PCI_TRAP 0x00000100 1126#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1127#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1128#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1129#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1130#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1131#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1132#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1133#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1134#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1135#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1136#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1137#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1138#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1139#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1140#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1141#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1142#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1143 1144/* Memory arbiter status register */ 1145#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1146#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1147#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1148#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1149#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1150#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1151#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1152#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1153#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1154#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1155#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1156#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1157#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1158#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1159#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1160#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1161#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1162#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1163#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1164#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1165#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1166#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1167#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1168#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1169 1170/* 1171 * Buffer manager control registers 1172 */ 1173#define BGE_BMAN_MODE 0x4400 1174#define BGE_BMAN_STATUS 0x4404 1175#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1176#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1177#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1178#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1179#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1180#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1181#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1182#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1183#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1184#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1185#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1186#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1187#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1188#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1189#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1190#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1191#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1192#define BGE_BMAN_HWDIAG_1 0x444C 1193#define BGE_BMAN_HWDIAG_2 0x4450 1194#define BGE_BMAN_HWDIAG_3 0x4454 1195 1196/* Buffer manager mode register */ 1197#define BGE_BMANMODE_RESET 0x00000001 1198#define BGE_BMANMODE_ENABLE 0x00000002 1199#define BGE_BMANMODE_ATTN 0x00000004 1200#define BGE_BMANMODE_TESTMODE 0x00000008 1201#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1202 1203/* Buffer manager status register */ 1204#define BGE_BMANSTAT_ERRO 0x00000004 1205#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1206 1207 1208/* 1209 * Read DMA Control registers 1210 */ 1211#define BGE_RDMA_MODE 0x4800 1212#define BGE_RDMA_STATUS 0x4804 1213 1214/* Read DMA mode register */ 1215#define BGE_RDMAMODE_RESET 0x00000001 1216#define BGE_RDMAMODE_ENABLE 0x00000002 1217#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1218#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1219#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1220#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1221#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1222#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1223#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1224#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1225#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1226 1227/* Read DMA status register */ 1228#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1229#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1230#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1231#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1232#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1233#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1234#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1235#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1236 1237/* 1238 * Write DMA control registers 1239 */ 1240#define BGE_WDMA_MODE 0x4C00 1241#define BGE_WDMA_STATUS 0x4C04 1242 1243/* Write DMA mode register */ 1244#define BGE_WDMAMODE_RESET 0x00000001 1245#define BGE_WDMAMODE_ENABLE 0x00000002 1246#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1247#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1248#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1249#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1250#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1251#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1252#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1253#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1254#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1255 1256/* Write DMA status register */ 1257#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1258#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1259#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1260#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1261#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1262#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1263#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1264#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1265 1266 1267/* 1268 * RX CPU registers 1269 */ 1270#define BGE_RXCPU_MODE 0x5000 1271#define BGE_RXCPU_STATUS 0x5004 1272#define BGE_RXCPU_PC 0x501C 1273 1274/* RX CPU mode register */ 1275#define BGE_RXCPUMODE_RESET 0x00000001 1276#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1277#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1278#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1279#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1280#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1281#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1282#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1283#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1284#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1285#define BGE_RXCPUMODE_HALTCPU 0x00000400 1286#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1287#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1288#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1289 1290/* RX CPU status register */ 1291#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1292#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1293#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1294#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1295#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1296#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1297#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1298#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1299#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1300#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1301#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1302#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1303#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1304#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1305#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1306#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1307#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1308 1309 1310/* 1311 * TX CPU registers 1312 */ 1313#define BGE_TXCPU_MODE 0x5400 1314#define BGE_TXCPU_STATUS 0x5404 1315#define BGE_TXCPU_PC 0x541C 1316 1317/* TX CPU mode register */ 1318#define BGE_TXCPUMODE_RESET 0x00000001 1319#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1320#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1321#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1322#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1323#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1324#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1325#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1326#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1327#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1328#define BGE_TXCPUMODE_HALTCPU 0x00000400 1329#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1330#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1331 1332/* TX CPU status register */ 1333#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1334#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1335#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1336#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1337#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1338#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1339#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1340#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1341#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1342#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1343#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1344#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1345#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1346#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1347#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1348#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1349#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1350 1351 1352/* 1353 * Low priority mailbox registers 1354 */ 1355#define BGE_LPMBX_IRQ0_HI 0x5800 1356#define BGE_LPMBX_IRQ0_LO 0x5804 1357#define BGE_LPMBX_IRQ1_HI 0x5808 1358#define BGE_LPMBX_IRQ1_LO 0x580C 1359#define BGE_LPMBX_IRQ2_HI 0x5810 1360#define BGE_LPMBX_IRQ2_LO 0x5814 1361#define BGE_LPMBX_IRQ3_HI 0x5818 1362#define BGE_LPMBX_IRQ3_LO 0x581C 1363#define BGE_LPMBX_GEN0_HI 0x5820 1364#define BGE_LPMBX_GEN0_LO 0x5824 1365#define BGE_LPMBX_GEN1_HI 0x5828 1366#define BGE_LPMBX_GEN1_LO 0x582C 1367#define BGE_LPMBX_GEN2_HI 0x5830 1368#define BGE_LPMBX_GEN2_LO 0x5834 1369#define BGE_LPMBX_GEN3_HI 0x5828 1370#define BGE_LPMBX_GEN3_LO 0x582C 1371#define BGE_LPMBX_GEN4_HI 0x5840 1372#define BGE_LPMBX_GEN4_LO 0x5844 1373#define BGE_LPMBX_GEN5_HI 0x5848 1374#define BGE_LPMBX_GEN5_LO 0x584C 1375#define BGE_LPMBX_GEN6_HI 0x5850 1376#define BGE_LPMBX_GEN6_LO 0x5854 1377#define BGE_LPMBX_GEN7_HI 0x5858 1378#define BGE_LPMBX_GEN7_LO 0x585C 1379#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1380#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1381#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1382#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1383#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1384#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1385#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1386#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1387#define BGE_LPMBX_RX_CONS0_HI 0x5880 1388#define BGE_LPMBX_RX_CONS0_LO 0x5884 1389#define BGE_LPMBX_RX_CONS1_HI 0x5888 1390#define BGE_LPMBX_RX_CONS1_LO 0x588C 1391#define BGE_LPMBX_RX_CONS2_HI 0x5890 1392#define BGE_LPMBX_RX_CONS2_LO 0x5894 1393#define BGE_LPMBX_RX_CONS3_HI 0x5898 1394#define BGE_LPMBX_RX_CONS3_LO 0x589C 1395#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1396#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1397#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1398#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1399#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1400#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1401#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1402#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1403#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1404#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1405#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1406#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1407#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1408#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1409#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1410#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1411#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1412#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1413#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1414#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1415#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1416#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1417#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1418#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1419#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1420#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1421#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1422#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1423#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1424#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1425#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1426#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1427#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1428#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1429#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1430#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1431#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1432#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1433#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1434#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1435#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1436#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1437#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1438#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1439#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1440#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1441#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1442#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1443#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1444#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1445#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1446#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1447#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1448#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1449#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1450#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1451#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1452#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1453#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1454#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1455#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1456#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1457#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1458#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1459#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1460#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1461#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1462#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1463#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1464#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1465#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1466#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1467#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1468#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1469#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1470#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1471#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1472#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1473#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1474#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1475#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1476#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1477#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1478#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1479#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1480#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1481#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1482#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1483 1484/* 1485 * Flow throw Queue reset register 1486 */ 1487#define BGE_FTQ_RESET 0x5C00 1488 1489#define BGE_FTQRESET_DMAREAD 0x00000002 1490#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1491#define BGE_FTQRESET_DMADONE 0x00000010 1492#define BGE_FTQRESET_SBDC 0x00000020 1493#define BGE_FTQRESET_SDI 0x00000040 1494#define BGE_FTQRESET_WDMA 0x00000080 1495#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1496#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1497#define BGE_FTQRESET_SDC 0x00000400 1498#define BGE_FTQRESET_HCC 0x00000800 1499#define BGE_FTQRESET_TXFIFO 0x00001000 1500#define BGE_FTQRESET_MBC 0x00002000 1501#define BGE_FTQRESET_RBDC 0x00004000 1502#define BGE_FTQRESET_RXLP 0x00008000 1503#define BGE_FTQRESET_RDBDI 0x00010000 1504#define BGE_FTQRESET_RDC 0x00020000 1505#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1506 1507/* 1508 * Message Signaled Interrupt registers 1509 */ 1510#define BGE_MSI_MODE 0x6000 1511#define BGE_MSI_STATUS 0x6004 1512#define BGE_MSI_FIFOACCESS 0x6008 1513 1514/* MSI mode register */ 1515#define BGE_MSIMODE_RESET 0x00000001 1516#define BGE_MSIMODE_ENABLE 0x00000002 1517#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1518#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1519#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1520#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1521#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1522 1523/* MSI status register */ 1524#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1525#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1526#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1527#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1528#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1529 1530 1531/* 1532 * DMA Completion registers 1533 */ 1534#define BGE_DMAC_MODE 0x6400 1535 1536/* DMA Completion mode register */ 1537#define BGE_DMACMODE_RESET 0x00000001 1538#define BGE_DMACMODE_ENABLE 0x00000002 1539 1540 1541/* 1542 * General control registers. 1543 */ 1544#define BGE_MODE_CTL 0x6800 1545#define BGE_MISC_CFG 0x6804 1546#define BGE_MISC_LOCAL_CTL 0x6808 1547#define BGE_EE_ADDR 0x6838 1548#define BGE_EE_DATA 0x683C 1549#define BGE_EE_CTL 0x6840 1550#define BGE_MDI_CTL 0x6844 1551#define BGE_EE_DELAY 0x6848 1552 1553/* Mode control register */ 1554#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1555#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1556#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1557#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1558#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1559#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1560#define BGE_MODECTL_NO_RX_CRC 0x00000400 1561#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1562#define BGE_MODECTL_NO_TX_INTR 0x00002000 1563#define BGE_MODECTL_NO_RX_INTR 0x00004000 1564#define BGE_MODECTL_FORCE_PCI32 0x00008000 1565#define BGE_MODECTL_STACKUP 0x00010000 1566#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1567#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1568#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1569#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1570#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1571#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1572#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1573#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1574#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1575#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1576 1577/* Misc. config register */ 1578#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1579#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1580 1581#define BGE_32BITTIME_66MHZ (0x41 << 1) 1582 1583/* Misc. Local Control */ 1584#define BGE_MLC_INTR_STATE 0x00000001 1585#define BGE_MLC_INTR_CLR 0x00000002 1586#define BGE_MLC_INTR_SET 0x00000004 1587#define BGE_MLC_INTR_ONATTN 0x00000008 1588#define BGE_MLC_MISCIO_IN0 0x00000100 1589#define BGE_MLC_MISCIO_IN1 0x00000200 1590#define BGE_MLC_MISCIO_IN2 0x00000400 1591#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1592#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1593#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1594#define BGE_MLC_MISCIO_OUT0 0x00004000 1595#define BGE_MLC_MISCIO_OUT1 0x00008000 1596#define BGE_MLC_MISCIO_OUT2 0x00010000 1597#define BGE_MLC_EXTRAM_ENB 0x00020000 1598#define BGE_MLC_SRAM_SIZE 0x001C0000 1599#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1600#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1601#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1602#define BGE_MLC_AUTO_EEPROM 0x01000000 1603 1604#define BGE_SSRAMSIZE_256KB 0x00000000 1605#define BGE_SSRAMSIZE_512KB 0x00040000 1606#define BGE_SSRAMSIZE_1MB 0x00080000 1607#define BGE_SSRAMSIZE_2MB 0x000C0000 1608#define BGE_SSRAMSIZE_4MB 0x00100000 1609#define BGE_SSRAMSIZE_8MB 0x00140000 1610#define BGE_SSRAMSIZE_16M 0x00180000 1611 1612/* EEPROM address register */ 1613#define BGE_EEADDR_ADDRESS 0x0000FFFC 1614#define BGE_EEADDR_HALFCLK 0x01FF0000 1615#define BGE_EEADDR_START 0x02000000 1616#define BGE_EEADDR_DEVID 0x1C000000 1617#define BGE_EEADDR_RESET 0x20000000 1618#define BGE_EEADDR_DONE 0x40000000 1619#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1620 1621#define BGE_EEDEVID(x) ((x & 7) << 26) 1622#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1623#define BGE_HALFCLK_384SCL 0x60 1624#define BGE_EE_READCMD \ 1625 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1626 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1627#define BGE_EE_WRCMD \ 1628 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1629 BGE_EEADDR_START|BGE_EEADDR_DONE) 1630 1631/* EEPROM Control register */ 1632#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1633#define BGE_EECTL_CLKOUT 0x00000002 1634#define BGE_EECTL_CLKIN 0x00000004 1635#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1636#define BGE_EECTL_DATAOUT 0x00000010 1637#define BGE_EECTL_DATAIN 0x00000020 1638 1639/* MDI (MII/GMII) access register */ 1640#define BGE_MDI_DATA 0x00000001 1641#define BGE_MDI_DIR 0x00000002 1642#define BGE_MDI_SEL 0x00000004 1643#define BGE_MDI_CLK 0x00000008 1644 1645#define BGE_MEMWIN_START 0x00008000 1646#define BGE_MEMWIN_END 0x0000FFFF 1647 1648 1649#define BGE_MEMWIN_READ(pc, tag, x, val) \ 1650 do { \ 1651 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1652 (0xFFFF0000 & x)); \ 1653 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1654 } while(0) 1655 1656#define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 1657 do { \ 1658 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1659 (0xFFFF0000 & x)); \ 1660 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1661 } while(0) 1662 1663/* 1664 * This magic number is used to prevent PXE restart when we 1665 * issue a software reset. We write this magic number to the 1666 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1667 * code from running. 1668 */ 1669#define BGE_MAGIC_NUMBER 0x4B657654 1670 1671typedef struct { 1672 u_int32_t bge_addr_hi; 1673 u_int32_t bge_addr_lo; 1674} bge_hostaddr; 1675#define BGE_HOSTADDR(x) x.bge_addr_lo 1676 1677/* Ring control block structure */ 1678struct bge_rcb { 1679 bge_hostaddr bge_hostaddr; 1680 u_int16_t bge_flags; 1681 u_int16_t bge_max_len; 1682 u_int32_t bge_nicaddr; 1683}; 1684 1685#define RCB_WRITE_4(sc, rcb, offset, val) \ 1686 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1687 rcb + offsetof(struct bge_rcb, offset), val) 1688 1689#define RCB_WRITE_2(sc, rcb, offset, val) \ 1690 bus_space_write_2(sc->bge_btag, sc->bge_bhandle, \ 1691 rcb + offsetof(struct bge_rcb, offset), val) 1692 1693struct bge_rcb_opaque { 1694 u_int32_t bge_reg0; 1695 u_int32_t bge_reg1; 1696 u_int32_t bge_reg2; 1697 u_int32_t bge_reg3; 1698}; 1699 1700#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1701#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1702 1703struct bge_tx_bd { 1704 bge_hostaddr bge_addr; 1705 u_int16_t bge_flags; 1706 u_int16_t bge_len; 1707 u_int16_t bge_vlan_tag; 1708 u_int16_t bge_rsvd; 1709}; 1710 1711#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1712#define BGE_TXBDFLAG_IP_CSUM 0x0002 1713#define BGE_TXBDFLAG_END 0x0004 1714#define BGE_TXBDFLAG_IP_FRAG 0x0008 1715#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1716#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1717#define BGE_TXBDFLAG_COAL_NOW 0x0080 1718#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1719#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1720#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1721#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1722#define BGE_TXBDFLAG_NO_CRC 0x8000 1723 1724#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1725 BGE_SEND_RING_1_TO_4 + \ 1726 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1727 1728struct bge_rx_bd { 1729 bge_hostaddr bge_addr; 1730 u_int16_t bge_len; 1731 u_int16_t bge_idx; 1732 u_int16_t bge_flags; 1733 u_int16_t bge_type; 1734 u_int16_t bge_tcp_udp_csum; 1735 u_int16_t bge_ip_csum; 1736 u_int16_t bge_vlan_tag; 1737 u_int16_t bge_error_flag; 1738 u_int32_t bge_rsvd; 1739 u_int32_t bge_opaque; 1740}; 1741 1742#define BGE_RXBDFLAG_END 0x0004 1743#define BGE_RXBDFLAG_JUMBO_RING 0x0020 1744#define BGE_RXBDFLAG_VLAN_TAG 0x0040 1745#define BGE_RXBDFLAG_ERROR 0x0400 1746#define BGE_RXBDFLAG_MINI_RING 0x0800 1747#define BGE_RXBDFLAG_IP_CSUM 0x1000 1748#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1749#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1750 1751#define BGE_RXERRFLAG_BAD_CRC 0x0001 1752#define BGE_RXERRFLAG_COLL_DETECT 0x0002 1753#define BGE_RXERRFLAG_LINK_LOST 0x0004 1754#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1755#define BGE_RXERRFLAG_MAC_ABORT 0x0010 1756#define BGE_RXERRFLAG_RUNT 0x0020 1757#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1758#define BGE_RXERRFLAG_GIANT 0x0080 1759 1760struct bge_sts_idx { 1761 u_int16_t bge_rx_prod_idx; 1762 u_int16_t bge_tx_cons_idx; 1763}; 1764 1765struct bge_status_block { 1766 u_int32_t bge_status; 1767 u_int32_t bge_rsvd0; 1768 u_int16_t bge_rx_jumbo_cons_idx; 1769 u_int16_t bge_rx_std_cons_idx; 1770 u_int16_t bge_rx_mini_cons_idx; 1771 u_int16_t bge_rsvd1; 1772 struct bge_sts_idx bge_idx[16]; 1773}; 1774 1775#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1776#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1777 1778#define BGE_STATFLAG_UPDATED 0x00000001 1779#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1780#define BGE_STATFLAG_ERROR 0x00000004 1781 1782/* 1783 * SysKonnect Subsystem IDs 1784 */ 1785#define SK_SUBSYSID_9D21 0x4421 1786#define SK_SUBSYSID_9D41 0x4441 1787 1788/* 1789 * Offset of MAC address inside EEPROM. 1790 */ 1791#define BGE_EE_MAC_OFFSET 0x7C 1792#define BGE_EE_HWCFG_OFFSET 0xC8 1793 1794#define BGE_HWCFG_VOLTAGE 0x00000003 1795#define BGE_HWCFG_PHYLED_MODE 0x0000000C 1796#define BGE_HWCFG_MEDIA 0x00000030 1797 1798#define BGE_VOLTAGE_1POINT3 0x00000000 1799#define BGE_VOLTAGE_1POINT8 0x00000001 1800 1801#define BGE_PHYLEDMODE_UNSPEC 0x00000000 1802#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 1803#define BGE_PHYLEDMODE_SINGLELED 0x00000008 1804 1805#define BGE_MEDIA_UNSPEC 0x00000000 1806#define BGE_MEDIA_COPPER 0x00000010 1807#define BGE_MEDIA_FIBER 0x00000020 1808 1809#define BGE_PCI_READ_CMD 0x06000000 1810#define BGE_PCI_WRITE_CMD 0x70000000 1811 1812#define BGE_TICKS_PER_SEC 1000000 1813 1814/* 1815 * Ring size constants. 1816 */ 1817#define BGE_EVENT_RING_CNT 256 1818#define BGE_CMD_RING_CNT 64 1819#define BGE_STD_RX_RING_CNT 512 1820#define BGE_JUMBO_RX_RING_CNT 256 1821#define BGE_MINI_RX_RING_CNT 1024 1822#define BGE_RETURN_RING_CNT 1024 1823 1824/* 1825 * Possible TX ring sizes. 1826 */ 1827#define BGE_TX_RING_CNT_128 128 1828#define BGE_TX_RING_BASE_128 0x3800 1829 1830#define BGE_TX_RING_CNT_256 256 1831#define BGE_TX_RING_BASE_256 0x3000 1832 1833#define BGE_TX_RING_CNT_512 512 1834#define BGE_TX_RING_BASE_512 0x2000 1835 1836#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 1837#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 1838 1839/* 1840 * Tigon III statistics counters. 1841 */ 1842struct bge_stats { 1843 u_int8_t Reserved0[256]; 1844 1845 /* Statistics maintained by Receive MAC. */ 1846 bge_hostaddr ifHCInOctets; 1847 bge_hostaddr Reserved1; 1848 bge_hostaddr etherStatsFragments; 1849 bge_hostaddr ifHCInUcastPkts; 1850 bge_hostaddr ifHCInMulticastPkts; 1851 bge_hostaddr ifHCInBroadcastPkts; 1852 bge_hostaddr dot3StatsFCSErrors; 1853 bge_hostaddr dot3StatsAlignmentErrors; 1854 bge_hostaddr xonPauseFramesReceived; 1855 bge_hostaddr xoffPauseFramesReceived; 1856 bge_hostaddr macControlFramesReceived; 1857 bge_hostaddr xoffStateEntered; 1858 bge_hostaddr dot3StatsFramesTooLong; 1859 bge_hostaddr etherStatsJabbers; 1860 bge_hostaddr etherStatsUndersizePkts; 1861 bge_hostaddr inRangeLengthError; 1862 bge_hostaddr outRangeLengthError; 1863 bge_hostaddr etherStatsPkts64Octets; 1864 bge_hostaddr etherStatsPkts65Octetsto127Octets; 1865 bge_hostaddr etherStatsPkts128Octetsto255Octets; 1866 bge_hostaddr etherStatsPkts256Octetsto511Octets; 1867 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 1868 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 1869 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 1870 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 1871 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 1872 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 1873 1874 bge_hostaddr Unused1[37]; 1875 1876 /* Statistics maintained by Transmit MAC. */ 1877 bge_hostaddr ifHCOutOctets; 1878 bge_hostaddr Reserved2; 1879 bge_hostaddr etherStatsCollisions; 1880 bge_hostaddr outXonSent; 1881 bge_hostaddr outXoffSent; 1882 bge_hostaddr flowControlDone; 1883 bge_hostaddr dot3StatsInternalMacTransmitErrors; 1884 bge_hostaddr dot3StatsSingleCollisionFrames; 1885 bge_hostaddr dot3StatsMultipleCollisionFrames; 1886 bge_hostaddr dot3StatsDeferredTransmissions; 1887 bge_hostaddr Reserved3; 1888 bge_hostaddr dot3StatsExcessiveCollisions; 1889 bge_hostaddr dot3StatsLateCollisions; 1890 bge_hostaddr dot3Collided2Times; 1891 bge_hostaddr dot3Collided3Times; 1892 bge_hostaddr dot3Collided4Times; 1893 bge_hostaddr dot3Collided5Times; 1894 bge_hostaddr dot3Collided6Times; 1895 bge_hostaddr dot3Collided7Times; 1896 bge_hostaddr dot3Collided8Times; 1897 bge_hostaddr dot3Collided9Times; 1898 bge_hostaddr dot3Collided10Times; 1899 bge_hostaddr dot3Collided11Times; 1900 bge_hostaddr dot3Collided12Times; 1901 bge_hostaddr dot3Collided13Times; 1902 bge_hostaddr dot3Collided14Times; 1903 bge_hostaddr dot3Collided15Times; 1904 bge_hostaddr ifHCOutUcastPkts; 1905 bge_hostaddr ifHCOutMulticastPkts; 1906 bge_hostaddr ifHCOutBroadcastPkts; 1907 bge_hostaddr dot3StatsCarrierSenseErrors; 1908 bge_hostaddr ifOutDiscards; 1909 bge_hostaddr ifOutErrors; 1910 1911 bge_hostaddr Unused2[31]; 1912 1913 /* Statistics maintained by Receive List Placement. */ 1914 bge_hostaddr COSIfHCInPkts[16]; 1915 bge_hostaddr COSFramesDroppedDueToFilters; 1916 bge_hostaddr nicDmaWriteQueueFull; 1917 bge_hostaddr nicDmaWriteHighPriQueueFull; 1918 bge_hostaddr nicNoMoreRxBDs; 1919 bge_hostaddr ifInDiscards; 1920 bge_hostaddr ifInErrors; 1921 bge_hostaddr nicRecvThresholdHit; 1922 1923 bge_hostaddr Unused3[9]; 1924 1925 /* Statistics maintained by Send Data Initiator. */ 1926 bge_hostaddr COSIfHCOutPkts[16]; 1927 bge_hostaddr nicDmaReadQueueFull; 1928 bge_hostaddr nicDmaReadHighPriQueueFull; 1929 bge_hostaddr nicSendDataCompQueueFull; 1930 1931 /* Statistics maintained by Host Coalescing. */ 1932 bge_hostaddr nicRingSetSendProdIndex; 1933 bge_hostaddr nicRingStatusUpdate; 1934 bge_hostaddr nicInterrupts; 1935 bge_hostaddr nicAvoidedInterrupts; 1936 bge_hostaddr nicSendThresholdHit; 1937 1938 u_int8_t Reserved4[320]; 1939}; 1940 1941/* 1942 * Tigon general information block. This resides in host memory 1943 * and contains the status counters, ring control blocks and 1944 * producer pointers. 1945 */ 1946 1947struct bge_gib { 1948 struct bge_stats bge_stats; 1949 struct bge_rcb bge_tx_rcb[16]; 1950 struct bge_rcb bge_std_rx_rcb; 1951 struct bge_rcb bge_jumbo_rx_rcb; 1952 struct bge_rcb bge_mini_rx_rcb; 1953 struct bge_rcb bge_return_rcb; 1954}; 1955 1956/* 1957 * NOTE! On the Alpha, we have an alignment constraint. 1958 * The first thing in the packet is a 14-byte Ethernet header. 1959 * This means that the packet is misaligned. To compensate, 1960 * we actually offset the data 2 bytes into the cluster. This 1961 * alignes the packet after the Ethernet header at a 32-bit 1962 * boundary. 1963 */ 1964 1965#define ETHER_ALIGN 2 1966 1967#define BGE_FRAMELEN 1518 1968#define BGE_MAX_FRAMELEN 1536 1969#define BGE_JUMBO_FRAMELEN 9018 1970#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1971#define BGE_PAGE_SIZE PAGE_SIZE 1972#define BGE_MIN_FRAMELEN 60 1973 1974/* 1975 * Other utility macros. 1976 */ 1977#define BGE_INC(x, y) (x) = (x + 1) % y 1978 1979/* 1980 * Vital product data and structures. 1981 */ 1982#define BGE_VPD_FLAG 0x8000 1983 1984/* VPD structures */ 1985struct vpd_res { 1986 u_int8_t vr_id; 1987 u_int8_t vr_len; 1988 u_int8_t vr_pad; 1989}; 1990 1991struct vpd_key { 1992 char vk_key[2]; 1993 u_int8_t vk_len; 1994}; 1995 1996#define VPD_RES_ID 0x82 /* ID string */ 1997#define VPD_RES_READ 0x90 /* start of read only area */ 1998#define VPD_RES_WRITE 0x81 /* start of read/write area */ 1999#define VPD_RES_END 0x78 /* end tag */ 2000 2001 2002/* 2003 * Register access macros. The Tigon always uses memory mapped register 2004 * accesses and all registers must be accessed with 32 bit operations. 2005 */ 2006 2007#define CSR_WRITE_4(sc, reg, val) \ 2008 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2009 2010#define CSR_READ_4(sc, reg) \ 2011 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2012 2013#define BGE_SETBIT(sc, reg, x) \ 2014 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2015#define BGE_CLRBIT(sc, reg, x) \ 2016 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2017 2018#define PCI_SETBIT(pc, tag, reg, x) \ 2019 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 2020#define PCI_CLRBIT(pc, tag, reg, x) \ 2021 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 2022 2023/* 2024 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2025 * values are tuneable. They control the actual amount of buffers 2026 * allocated for the standard, mini and jumbo receive rings. 2027 */ 2028 2029#define BGE_SSLOTS 256 2030#define BGE_MSLOTS 256 2031#define BGE_JSLOTS 384 2032 2033#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2034#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2035 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2036#define BGE_JPAGESZ PAGE_SIZE 2037#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2038#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2039 2040/* 2041 * Ring structures. Most of these reside in host memory and we tell 2042 * the NIC where they are via the ring control blocks. The exceptions 2043 * are the tx and command rings, which live in NIC memory and which 2044 * we access via the shared memory window. 2045 */ 2046struct bge_ring_data { 2047 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2048 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2049 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2050 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2051 struct bge_status_block bge_status_block; 2052 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2053 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2054 struct bge_gib bge_info; 2055}; 2056 2057#define BGE_RING_DMA_ADDR(sc, offset) \ 2058 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2059 offsetof(struct bge_ring_data, offset)) 2060 2061/* 2062 * Number of DMA segments in a TxCB. Note that this is carefully 2063 * chosen to make the total struct size an even power of two. It's 2064 * critical that no TxCB be split across a page boundry since 2065 * no attempt is made to allocate physically contiguous memory. 2066 * 2067 */ 2068#ifdef __alpha__ /* XXX - should be conditional on pointer size */ 2069#define BGE_NTXSEG 30 2070#else 2071#define BGE_NTXSEG 31 2072#endif 2073 2074/* 2075 * Mbuf pointers. We need these to keep track of the virtual addresses 2076 * of our mbuf chains since we can only convert from physical to virtual, 2077 * not the other way around. 2078 */ 2079struct bge_chain_data { 2080 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2081 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2082 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2083 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2084 bus_dmamap_t bge_tx_map[BGE_TX_RING_CNT]; 2085 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2086 bus_dmamap_t bge_rx_jumbo_map; 2087 /* Stick the jumbo mem management stuff here too. */ 2088 caddr_t bge_jslots[BGE_JSLOTS]; 2089 void *bge_jumbo_buf; 2090}; 2091 2092#define BGE_JUMBO_DMA_ADDR(sc, m) \ 2093 ((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \ 2094 (mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf)) 2095 2096struct bge_type { 2097 u_int16_t bge_vid; 2098 u_int16_t bge_did; 2099 char *bge_name; 2100}; 2101 2102#define BGE_HWREV_TIGON 0x01 2103#define BGE_HWREV_TIGON_II 0x02 2104#define BGE_TIMEOUT 1000 2105#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2106 2107struct bge_jpool_entry { 2108 int slot; 2109 LIST_ENTRY(bge_jpool_entry) jpool_entries; 2110}; 2111 2112struct bge_bcom_hack { 2113 int reg; 2114 int val; 2115}; 2116 2117struct bge_softc { 2118 struct device bge_dev; 2119 struct arpcom arpcom; /* interface info */ 2120 bus_space_handle_t bge_bhandle; 2121 bus_space_tag_t bge_btag; 2122 void *bge_intrhand; 2123 struct pci_attach_args bge_pa; 2124 struct mii_data bge_mii; 2125 struct ifmedia bge_ifmedia; /* media info */ 2126 u_int8_t bge_extram; /* has external SSRAM */ 2127 u_int8_t bge_tbi; 2128 u_int8_t bge_rx_alignment_bug; 2129 bus_dma_tag_t bge_dmatag; 2130 u_int32_t bge_asicrev; 2131 struct bge_ring_data *bge_rdata; /* rings */ 2132 struct bge_chain_data bge_cdata; /* mbufs */ 2133 bus_dmamap_t bge_ring_map; 2134 u_int16_t bge_tx_saved_considx; 2135 u_int16_t bge_rx_saved_considx; 2136 u_int16_t bge_ev_saved_considx; 2137 u_int16_t bge_std; /* current std ring head */ 2138 u_int16_t bge_jumbo; /* current jumo ring head */ 2139 LIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2140 LIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2141 u_int32_t bge_stat_ticks; 2142 u_int32_t bge_rx_coal_ticks; 2143 u_int32_t bge_tx_coal_ticks; 2144 u_int32_t bge_rx_max_coal_bds; 2145 u_int32_t bge_tx_max_coal_bds; 2146 u_int32_t bge_tx_buf_ratio; 2147 int bge_if_flags; 2148 int bge_txcnt; 2149 int bge_link; 2150 struct timeout bge_timeout; 2151 char *bge_vpd_prodname; 2152 char *bge_vpd_readonly; 2153}; 2154