if_bgereg.h revision 1.47
1/* $OpenBSD: if_bgereg.h,v 1.47 2006/05/28 00:20:21 brad Exp $ */ 2 3/* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bgereg.h,v 1.11 2002/11/14 23:54:50 sam Exp $ 36 */ 37 38/* 39 * BCM570x memory map. The internal memory layout varies somewhat 40 * depending on whether or not we have external SSRAM attached. 41 * The BCM5700 can have up to 16MB of external memory. The BCM5701 42 * is apparently not designed to use external SSRAM. The mappings 43 * up to the first 4 send rings are the same for both internal and 44 * external memory configurations. Note that mini RX ring space is 45 * only available with external SSRAM configurations, which means 46 * the mini RX ring is not supported on the BCM5701. 47 * 48 * The NIC's memory can be accessed by the host in one of 3 ways: 49 * 50 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 51 * registers in PCI config space can be used to read any 32-bit 52 * address within the NIC's memory. 53 * 54 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 55 * space can be used in conjunction with the memory window in the 56 * device register space at offset 0x8000 to read any 32K chunk 57 * of NIC memory. 58 * 59 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 60 * set, the device I/O mapping consumes 32MB of host address space, 61 * allowing all of the registers and internal NIC memory to be 62 * accessed directly. NIC memory addresses are offset by 0x01000000. 63 * Flat mode consumes so much host address space that it is not 64 * recommended. 65 */ 66#define BGE_PAGE_ZERO 0x00000000 67#define BGE_PAGE_ZERO_END 0x000000FF 68#define BGE_SEND_RING_RCB 0x00000100 69#define BGE_SEND_RING_RCB_END 0x000001FF 70#define BGE_RX_RETURN_RING_RCB 0x00000200 71#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 72#define BGE_STATS_BLOCK 0x00000300 73#define BGE_STATS_BLOCK_END 0x00000AFF 74#define BGE_STATUS_BLOCK 0x00000B00 75#define BGE_STATUS_BLOCK_END 0x00000B4F 76#define BGE_SOFTWARE_GENCOMM 0x00000B50 77#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 78#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 79#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 80#define BGE_FW_PAUSE 0x00000002 81#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 82#define BGE_UNMAPPED 0x00001000 83#define BGE_UNMAPPED_END 0x00001FFF 84#define BGE_DMA_DESCRIPTORS 0x00002000 85#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 86#define BGE_SEND_RING_1_TO_4 0x00004000 87#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 88 89/* Mappings for internal memory configuration */ 90#define BGE_STD_RX_RINGS 0x00006000 91#define BGE_STD_RX_RINGS_END 0x00006FFF 92#define BGE_JUMBO_RX_RINGS 0x00007000 93#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 94#define BGE_BUFFPOOL_1 0x00008000 95#define BGE_BUFFPOOL_1_END 0x0000FFFF 96#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 97#define BGE_BUFFPOOL_2_END 0x00017FFF 98#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 99#define BGE_BUFFPOOL_3_END 0x0001FFFF 100 101/* Mappings for external SSRAM configurations */ 102#define BGE_SEND_RING_5_TO_6 0x00006000 103#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 104#define BGE_SEND_RING_7_TO_8 0x00007000 105#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 106#define BGE_SEND_RING_9_TO_16 0x00008000 107#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 108#define BGE_EXT_STD_RX_RINGS 0x0000C000 109#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 110#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 111#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 112#define BGE_MINI_RX_RINGS 0x0000E000 113#define BGE_MINI_RX_RINGS_END 0x0000FFFF 114#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 115#define BGE_AVAIL_REGION1_END 0x00017FFF 116#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 117#define BGE_AVAIL_REGION2_END 0x0001FFFF 118#define BGE_EXT_SSRAM 0x00020000 119#define BGE_EXT_SSRAM_END 0x000FFFFF 120 121 122/* 123 * BCM570x register offsets. These are memory mapped registers 124 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 125 * Each register must be accessed using 32 bit operations. 126 * 127 * All registers are accessed through a 32K shared memory block. 128 * The first group of registers are actually copies of the PCI 129 * configuration space registers. 130 */ 131 132/* 133 * PCI registers defined in the PCI 2.2 spec. 134 */ 135#define BGE_PCI_VID 0x00 136#define BGE_PCI_DID 0x02 137#define BGE_PCI_CMD 0x04 138#define BGE_PCI_STS 0x06 139#define BGE_PCI_REV 0x08 140#define BGE_PCI_CLASS 0x09 141#define BGE_PCI_CACHESZ 0x0C 142#define BGE_PCI_LATTIMER 0x0D 143#define BGE_PCI_HDRTYPE 0x0E 144#define BGE_PCI_BIST 0x0F 145#define BGE_PCI_BAR0 0x10 146#define BGE_PCI_BAR1 0x14 147#define BGE_PCI_SUBSYS 0x2C 148#define BGE_PCI_SUBVID 0x2E 149#define BGE_PCI_ROMBASE 0x30 150#define BGE_PCI_CAPPTR 0x34 151#define BGE_PCI_INTLINE 0x3C 152#define BGE_PCI_INTPIN 0x3D 153#define BGE_PCI_MINGNT 0x3E 154#define BGE_PCI_MAXLAT 0x3F 155#define BGE_PCI_PCIXCAP 0x40 156#define BGE_PCI_NEXTPTR_PM 0x41 157#define BGE_PCI_PCIX_CMD 0x42 158#define BGE_PCI_PCIX_STS 0x44 159#define BGE_PCI_PWRMGMT_CAPID 0x48 160#define BGE_PCI_NEXTPTR_VPD 0x49 161#define BGE_PCI_PWRMGMT_CAPS 0x4A 162#define BGE_PCI_PWRMGMT_CMD 0x4C 163#define BGE_PCI_PWRMGMT_STS 0x4D 164#define BGE_PCI_PWRMGMT_DATA 0x4F 165#define BGE_PCI_VPD_CAPID 0x50 166#define BGE_PCI_NEXTPTR_MSI 0x51 167#define BGE_PCI_VPD_ADDR 0x52 168#define BGE_PCI_VPD_DATA 0x54 169#define BGE_PCI_MSI_CAPID 0x58 170#define BGE_PCI_NEXTPTR_NONE 0x59 171#define BGE_PCI_MSI_CTL 0x5A 172#define BGE_PCI_MSI_ADDR_HI 0x5C 173#define BGE_PCI_MSI_ADDR_LO 0x60 174#define BGE_PCI_MSI_DATA 0x64 175 176/* PCI MSI. ??? */ 177#define BGE_PCIE_CAPID_REG 0xD0 178#define BGE_PCIE_CAPID 0x10 179 180/* 181 * PCI registers specific to the BCM570x family. 182 */ 183#define BGE_PCI_MISC_CTL 0x68 184#define BGE_PCI_DMA_RW_CTL 0x6C 185#define BGE_PCI_PCISTATE 0x70 186#define BGE_PCI_CLKCTL 0x74 187#define BGE_PCI_REG_BASEADDR 0x78 188#define BGE_PCI_MEMWIN_BASEADDR 0x7C 189#define BGE_PCI_REG_DATA 0x80 190#define BGE_PCI_MEMWIN_DATA 0x84 191#define BGE_PCI_MODECTL 0x88 192#define BGE_PCI_MISC_CFG 0x8C 193#define BGE_PCI_MISC_LOCALCTL 0x90 194#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 195#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 196#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 197#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 198#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 199#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 200#define BGE_PCI_ISR_MBX_HI 0xB0 201#define BGE_PCI_ISR_MBX_LO 0xB4 202 203/* XXX: 204 * Used in PCI-Express code for 575x chips. 205 * Should be replaced with checking for a PCI config-space 206 * capability for PCI-Express, and PCI-Express standard 207 * offsets into that capability block. 208 */ 209#define BGE_PCI_CONF_DEV_CTRL 0xD8 210#define BGE_PCI_CONF_DEV_STUS 0xDA 211 212/* PCI Misc. Host control register */ 213#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 214#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 215#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 216#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 217#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 218#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 219#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 220#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 221#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 222 223#if BYTE_ORDER == LITTLE_ENDIAN 224#define BGE_DMA_SWAP_OPTIONS \ 225 BGE_MODECTL_WORDSWAP_NONFRAME| \ 226 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 227#else 228#define BGE_DMA_SWAP_OPTIONS \ 229 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 230 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 231#endif 232 233#define BGE_INIT \ 234 (BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 235 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 236 237#define BGE_CHIPID_BCM5700_A0 0x70000000 238#define BGE_CHIPID_BCM5700_A1 0x70010000 239#define BGE_CHIPID_BCM5700_B0 0x71000000 240#define BGE_CHIPID_BCM5700_B1 0x71010000 241#define BGE_CHIPID_BCM5700_B2 0x71020000 242#define BGE_CHIPID_BCM5700_B3 0x71030000 243#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 244#define BGE_CHIPID_BCM5700_C0 0x72000000 245#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 246#define BGE_CHIPID_BCM5701_B0 0x01000000 247#define BGE_CHIPID_BCM5701_B2 0x01020000 248#define BGE_CHIPID_BCM5701_B5 0x01050000 249#define BGE_CHIPID_BCM5703_A0 0x10000000 250#define BGE_CHIPID_BCM5703_A1 0x10010000 251#define BGE_CHIPID_BCM5703_A2 0x10020000 252#define BGE_CHIPID_BCM5703_A3 0x10030000 253#define BGE_CHIPID_BCM5704_A0 0x20000000 254#define BGE_CHIPID_BCM5704_A1 0x20010000 255#define BGE_CHIPID_BCM5704_A2 0x20020000 256#define BGE_CHIPID_BCM5704_A3 0x20030000 257#define BGE_CHIPID_BCM5704_B0 0x21000000 258#define BGE_CHIPID_BCM5705_A0 0x30000000 259#define BGE_CHIPID_BCM5705_A1 0x30010000 260#define BGE_CHIPID_BCM5705_A2 0x30020000 261#define BGE_CHIPID_BCM5705_A3 0x30030000 262#define BGE_CHIPID_BCM5750_A0 0x40000000 263#define BGE_CHIPID_BCM5750_A1 0x40010000 264#define BGE_CHIPID_BCM5750_A3 0x40030000 265#define BGE_CHIPID_BCM5750_B0 0x40100000 266#define BGE_CHIPID_BCM5750_B1 0x41010000 267#define BGE_CHIPID_BCM5750_C0 0x42000000 268#define BGE_CHIPID_BCM5750_C1 0x42010000 269#define BGE_CHIPID_BCM5714_A0 0x50000000 270#define BGE_CHIPID_BCM5752_A0 0x60000000 271#define BGE_CHIPID_BCM5752_A1 0x60010000 272#define BGE_CHIPID_BCM5752_A2 0x60020000 273#define BGE_CHIPID_BCM5714_B0 0x80000000 274#define BGE_CHIPID_BCM5714_B3 0x80030000 275#define BGE_CHIPID_BCM5715_A0 0x90000000 276#define BGE_CHIPID_BCM5715_A1 0x90010000 277 278/* shorthand one */ 279#define BGE_ASICREV(x) ((x) >> 28) 280#define BGE_ASICREV_BCM5700 0x07 281#define BGE_ASICREV_BCM5701 0x00 282#define BGE_ASICREV_BCM5703 0x01 283#define BGE_ASICREV_BCM5704 0x02 284#define BGE_ASICREV_BCM5705 0x03 285#define BGE_ASICREV_BCM5750 0x04 286#define BGE_ASICREV_BCM5714_A0 0x05 /* 5714, 5715 */ 287#define BGE_ASICREV_BCM5752 0x06 288#define BGE_ASICREV_BCM5780 0x08 289#define BGE_ASICREV_BCM5714 0x09 /* 5714, 5715 */ 290 291/* chip revisions */ 292#define BGE_CHIPREV(x) ((x) >> 24) 293#define BGE_CHIPREV_5700_AX 0x70 294#define BGE_CHIPREV_5700_BX 0x71 295#define BGE_CHIPREV_5700_CX 0x72 296#define BGE_CHIPREV_5701_AX 0x00 297#define BGE_CHIPREV_5703_AX 0x10 298#define BGE_CHIPREV_5704_AX 0x20 299#define BGE_CHIPREV_5704_BX 0x21 300#define BGE_CHIPREV_5750_AX 0x40 301#define BGE_CHIPREV_5750_BX 0x41 302 303/* PCI DMA Read/Write Control register */ 304#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 305#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 306#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 307#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 308#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 309#define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 310#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 311#define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 312#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 313#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 314#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 315#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD_SHIFT 24 316#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 317#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD_SHIFT 28 318 319/* PCI DMA Read/Write Control register, alternate usage for PCI-Express */ 320#define BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128 0x00180000 321#define BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256 0x00380000 322 323#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 324#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 325#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 326#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 327#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 328#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 329#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 330#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 331 332#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 333#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 334#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 335#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 336#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 337#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 338#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 339#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 340 341/* 342 * PCI state register -- note, this register is read only 343 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 344 * register is set. 345 */ 346#define BGE_PCISTATE_FORCE_RESET 0x00000001 347#define BGE_PCISTATE_INTR_NOT_ACTIVE 0x00000002 348#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 349#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 350#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 351#define BGE_PCISTATE_WANT_EXPROM 0x00000020 352#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 353#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 354#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 355 356/* 357 * The following bits in PCI state register are reserved. 358 * If we check that the register values reverts on reset, 359 * do not check these bits. On some 5704C (rev A3) and some 360 * Altima chips, these bits do not revert until much later 361 * in the bge driver's bge_reset() chip-reset state machine. 362 */ 363#define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 364 365/* 366 * PCI Clock Control register -- note, this register is read only 367 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 368 * register is set. 369 */ 370#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 371#define BGE_PCICLOCKCTL_M66EN 0x00000080 372#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 373#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 374#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 375#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 376#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 377#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 378#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 379#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 380 381/* 382 * High priority mailbox registers 383 * Each mailbox is 64-bits wide, though we only use the 384 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 385 * first. The NIC will load the mailbox after the lower 32 bit word 386 * has been updated. 387 */ 388#define BGE_MBX_IRQ0_HI 0x0200 389#define BGE_MBX_IRQ0_LO 0x0204 390#define BGE_MBX_IRQ1_HI 0x0208 391#define BGE_MBX_IRQ1_LO 0x020C 392#define BGE_MBX_IRQ2_HI 0x0210 393#define BGE_MBX_IRQ2_LO 0x0214 394#define BGE_MBX_IRQ3_HI 0x0218 395#define BGE_MBX_IRQ3_LO 0x021C 396#define BGE_MBX_GEN0_HI 0x0220 397#define BGE_MBX_GEN0_LO 0x0224 398#define BGE_MBX_GEN1_HI 0x0228 399#define BGE_MBX_GEN1_LO 0x022C 400#define BGE_MBX_GEN2_HI 0x0230 401#define BGE_MBX_GEN2_LO 0x0234 402#define BGE_MBX_GEN3_HI 0x0228 403#define BGE_MBX_GEN3_LO 0x022C 404#define BGE_MBX_GEN4_HI 0x0240 405#define BGE_MBX_GEN4_LO 0x0244 406#define BGE_MBX_GEN5_HI 0x0248 407#define BGE_MBX_GEN5_LO 0x024C 408#define BGE_MBX_GEN6_HI 0x0250 409#define BGE_MBX_GEN6_LO 0x0254 410#define BGE_MBX_GEN7_HI 0x0258 411#define BGE_MBX_GEN7_LO 0x025C 412#define BGE_MBX_RELOAD_STATS_HI 0x0260 413#define BGE_MBX_RELOAD_STATS_LO 0x0264 414#define BGE_MBX_RX_STD_PROD_HI 0x0268 415#define BGE_MBX_RX_STD_PROD_LO 0x026C 416#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 417#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 418#define BGE_MBX_RX_MINI_PROD_HI 0x0278 419#define BGE_MBX_RX_MINI_PROD_LO 0x027C 420#define BGE_MBX_RX_CONS0_HI 0x0280 421#define BGE_MBX_RX_CONS0_LO 0x0284 422#define BGE_MBX_RX_CONS1_HI 0x0288 423#define BGE_MBX_RX_CONS1_LO 0x028C 424#define BGE_MBX_RX_CONS2_HI 0x0290 425#define BGE_MBX_RX_CONS2_LO 0x0294 426#define BGE_MBX_RX_CONS3_HI 0x0298 427#define BGE_MBX_RX_CONS3_LO 0x029C 428#define BGE_MBX_RX_CONS4_HI 0x02A0 429#define BGE_MBX_RX_CONS4_LO 0x02A4 430#define BGE_MBX_RX_CONS5_HI 0x02A8 431#define BGE_MBX_RX_CONS5_LO 0x02AC 432#define BGE_MBX_RX_CONS6_HI 0x02B0 433#define BGE_MBX_RX_CONS6_LO 0x02B4 434#define BGE_MBX_RX_CONS7_HI 0x02B8 435#define BGE_MBX_RX_CONS7_LO 0x02BC 436#define BGE_MBX_RX_CONS8_HI 0x02C0 437#define BGE_MBX_RX_CONS8_LO 0x02C4 438#define BGE_MBX_RX_CONS9_HI 0x02C8 439#define BGE_MBX_RX_CONS9_LO 0x02CC 440#define BGE_MBX_RX_CONS10_HI 0x02D0 441#define BGE_MBX_RX_CONS10_LO 0x02D4 442#define BGE_MBX_RX_CONS11_HI 0x02D8 443#define BGE_MBX_RX_CONS11_LO 0x02DC 444#define BGE_MBX_RX_CONS12_HI 0x02E0 445#define BGE_MBX_RX_CONS12_LO 0x02E4 446#define BGE_MBX_RX_CONS13_HI 0x02E8 447#define BGE_MBX_RX_CONS13_LO 0x02EC 448#define BGE_MBX_RX_CONS14_HI 0x02F0 449#define BGE_MBX_RX_CONS14_LO 0x02F4 450#define BGE_MBX_RX_CONS15_HI 0x02F8 451#define BGE_MBX_RX_CONS15_LO 0x02FC 452#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 453#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 454#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 455#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 456#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 457#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 458#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 459#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 460#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 461#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 462#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 463#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 464#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 465#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 466#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 467#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 468#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 469#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 470#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 471#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 472#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 473#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 474#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 475#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 476#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 477#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 478#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 479#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 480#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 481#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 482#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 483#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 484#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 485#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 486#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 487#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 488#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 489#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 490#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 491#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 492#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 493#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 494#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 495#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 496#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 497#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 498#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 499#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 500#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 501#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 502#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 503#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 504#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 505#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 506#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 507#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 508#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 509#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 510#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 511#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 512#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 513#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 514#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 515#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 516 517#define BGE_TX_RINGS_MAX 4 518#define BGE_TX_RINGS_EXTSSRAM_MAX 16 519#define BGE_RX_RINGS_MAX 16 520 521/* Ethernet MAC control registers */ 522#define BGE_MAC_MODE 0x0400 523#define BGE_MAC_STS 0x0404 524#define BGE_MAC_EVT_ENB 0x0408 525#define BGE_MAC_LED_CTL 0x040C 526#define BGE_MAC_ADDR1_LO 0x0410 527#define BGE_MAC_ADDR1_HI 0x0414 528#define BGE_MAC_ADDR2_LO 0x0418 529#define BGE_MAC_ADDR2_HI 0x041C 530#define BGE_MAC_ADDR3_LO 0x0420 531#define BGE_MAC_ADDR3_HI 0x0424 532#define BGE_MAC_ADDR4_LO 0x0428 533#define BGE_MAC_ADDR4_HI 0x042C 534#define BGE_WOL_PATPTR 0x0430 535#define BGE_WOL_PATCFG 0x0434 536#define BGE_TX_RANDOM_BACKOFF 0x0438 537#define BGE_RX_MTU 0x043C 538#define BGE_GBIT_PCS_TEST 0x0440 539#define BGE_TX_TBI_AUTONEG 0x0444 540#define BGE_RX_TBI_AUTONEG 0x0448 541#define BGE_MI_COMM 0x044C 542#define BGE_MI_STS 0x0450 543#define BGE_MI_MODE 0x0454 544#define BGE_AUTOPOLL_STS 0x0458 545#define BGE_TX_MODE 0x045C 546#define BGE_TX_STS 0x0460 547#define BGE_TX_LENGTHS 0x0464 548#define BGE_RX_MODE 0x0468 549#define BGE_RX_STS 0x046C 550#define BGE_MAR0 0x0470 551#define BGE_MAR1 0x0474 552#define BGE_MAR2 0x0478 553#define BGE_MAR3 0x047C 554#define BGE_RX_BD_RULES_CTL0 0x0480 555#define BGE_RX_BD_RULES_MASKVAL0 0x0484 556#define BGE_RX_BD_RULES_CTL1 0x0488 557#define BGE_RX_BD_RULES_MASKVAL1 0x048C 558#define BGE_RX_BD_RULES_CTL2 0x0490 559#define BGE_RX_BD_RULES_MASKVAL2 0x0494 560#define BGE_RX_BD_RULES_CTL3 0x0498 561#define BGE_RX_BD_RULES_MASKVAL3 0x049C 562#define BGE_RX_BD_RULES_CTL4 0x04A0 563#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 564#define BGE_RX_BD_RULES_CTL5 0x04A8 565#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 566#define BGE_RX_BD_RULES_CTL6 0x04B0 567#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 568#define BGE_RX_BD_RULES_CTL7 0x04B8 569#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 570#define BGE_RX_BD_RULES_CTL8 0x04C0 571#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 572#define BGE_RX_BD_RULES_CTL9 0x04C8 573#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 574#define BGE_RX_BD_RULES_CTL10 0x04D0 575#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 576#define BGE_RX_BD_RULES_CTL11 0x04D8 577#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 578#define BGE_RX_BD_RULES_CTL12 0x04E0 579#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 580#define BGE_RX_BD_RULES_CTL13 0x04E8 581#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 582#define BGE_RX_BD_RULES_CTL14 0x04F0 583#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 584#define BGE_RX_BD_RULES_CTL15 0x04F8 585#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 586#define BGE_RX_RULES_CFG 0x0500 587#define BGE_MAX_RX_FRAME_LOWAT 0x0504 588#define BGE_SERDES_CFG 0x0590 589#define BGE_SERDES_STS 0x0594 590#define BGE_SGDIG_CFG 0x05B0 591#define BGE_SGDIG_STS 0x05B4 592#define BGE_RX_STATS 0x0800 593#define BGE_TX_STATS 0x0880 594 595/* Ethernet MAC Mode register */ 596#define BGE_MACMODE_RESET 0x00000001 597#define BGE_MACMODE_HALF_DUPLEX 0x00000002 598#define BGE_MACMODE_PORTMODE 0x0000000C 599#define BGE_MACMODE_LOOPBACK 0x00000010 600#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 601#define BGE_MACMODE_TX_BURST_ENB 0x00000100 602#define BGE_MACMODE_MAX_DEFER 0x00000200 603#define BGE_MACMODE_LINK_POLARITY 0x00000400 604#define BGE_MACMODE_RX_STATS_ENB 0x00000800 605#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 606#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 607#define BGE_MACMODE_TX_STATS_ENB 0x00004000 608#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 609#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 610#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 611#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 612#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 613#define BGE_MACMODE_MIP_ENB 0x00100000 614#define BGE_MACMODE_TXDMA_ENB 0x00200000 615#define BGE_MACMODE_RXDMA_ENB 0x00400000 616#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 617 618#define BGE_PORTMODE_NONE 0x00000000 619#define BGE_PORTMODE_MII 0x00000004 620#define BGE_PORTMODE_GMII 0x00000008 621#define BGE_PORTMODE_TBI 0x0000000C 622 623/* MAC Status register */ 624#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 625#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 626#define BGE_MACSTAT_RX_CFG 0x00000004 627#define BGE_MACSTAT_CFG_CHANGED 0x00000008 628#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 629#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 630#define BGE_MACSTAT_LINK_CHANGED 0x00001000 631#define BGE_MACSTAT_MI_COMPLETE 0x00400000 632#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 633#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 634#define BGE_MACSTAT_ODI_ERROR 0x02000000 635#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 636#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 637 638/* MAC Event Enable Register */ 639#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 640#define BGE_EVTENB_LINK_CHANGED 0x00001000 641#define BGE_EVTENB_MI_COMPLETE 0x00400000 642#define BGE_EVTENB_MI_INTERRUPT 0x00800000 643#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 644#define BGE_EVTENB_ODI_ERROR 0x02000000 645#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 646#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 647 648/* LED Control Register */ 649#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 650#define BGE_LEDCTL_1000MBPS_LED 0x00000002 651#define BGE_LEDCTL_100MBPS_LED 0x00000004 652#define BGE_LEDCTL_10MBPS_LED 0x00000008 653#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 654#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 655#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 656#define BGE_LEDCTL_1000MBPS_STS 0x00000080 657#define BGE_LEDCTL_100MBPS_STS 0x00000100 658#define BGE_LEDCTL_10MBPS_STS 0x00000200 659#define BGE_LEDCTL_TRADLED_STS 0x00000400 660#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 661#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 662 663/* TX backoff seed register */ 664#define BGE_TX_BACKOFF_SEED_MASK 0x3F 665 666/* Autopoll status register */ 667#define BGE_AUTOPOLLSTS_ERROR 0x00000001 668 669/* Transmit MAC mode register */ 670#define BGE_TXMODE_RESET 0x00000001 671#define BGE_TXMODE_ENABLE 0x00000002 672#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 673#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 674#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 675 676/* Transmit MAC status register */ 677#define BGE_TXSTAT_RX_XOFFED 0x00000001 678#define BGE_TXSTAT_SENT_XOFF 0x00000002 679#define BGE_TXSTAT_SENT_XON 0x00000004 680#define BGE_TXSTAT_LINK_UP 0x00000008 681#define BGE_TXSTAT_ODI_UFLOW 0x00000010 682#define BGE_TXSTAT_ODI_OFLOW 0x00000020 683 684/* Transmit MAC lengths register */ 685#define BGE_TXLEN_SLOTTIME 0x000000FF 686#define BGE_TXLEN_IPG 0x00000F00 687#define BGE_TXLEN_CRS 0x00003000 688 689/* Receive MAC mode register */ 690#define BGE_RXMODE_RESET 0x00000001 691#define BGE_RXMODE_ENABLE 0x00000002 692#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 693#define BGE_RXMODE_RX_GIANTS 0x00000020 694#define BGE_RXMODE_RX_RUNTS 0x00000040 695#define BGE_RXMODE_8022_LENCHECK 0x00000080 696#define BGE_RXMODE_RX_PROMISC 0x00000100 697#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 698#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 699 700/* Receive MAC status register */ 701#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 702#define BGE_RXSTAT_RCVD_XOFF 0x00000002 703#define BGE_RXSTAT_RCVD_XON 0x00000004 704 705/* Receive Rules Control register */ 706#define BGE_RXRULECTL_OFFSET 0x000000FF 707#define BGE_RXRULECTL_CLASS 0x00001F00 708#define BGE_RXRULECTL_HDRTYPE 0x0000E000 709#define BGE_RXRULECTL_COMPARE_OP 0x00030000 710#define BGE_RXRULECTL_MAP 0x01000000 711#define BGE_RXRULECTL_DISCARD 0x02000000 712#define BGE_RXRULECTL_MASK 0x04000000 713#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 714#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 715#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 716#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 717 718/* Receive Rules Mask register */ 719#define BGE_RXRULEMASK_VALUE 0x0000FFFF 720#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 721 722/* SERDES configuration register */ 723#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 724#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 725#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 726#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 727#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 728#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 729#define BGE_SERDESCFG_TXMODE 0x00001000 730#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 731#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 732#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 733#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 734#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 735#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 736#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 737#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 738#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 739 740/* SERDES status register */ 741#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 742#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 743 744/* SGDIG config (not documented) */ 745#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 746#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 747#define BGE_SGDIGCFG_SEND 0x40000000 748#define BGE_SGDIGCFG_AUTO 0x80000000 749 750/* SGDIG status (not documented) */ 751#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 752#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 753#define BGE_SGDIGSTS_DONE 0x00000002 754 755/* MI communication register */ 756#define BGE_MICOMM_DATA 0x0000FFFF 757#define BGE_MICOMM_REG 0x001F0000 758#define BGE_MICOMM_PHY 0x03E00000 759#define BGE_MICOMM_CMD 0x0C000000 760#define BGE_MICOMM_READFAIL 0x10000000 761#define BGE_MICOMM_BUSY 0x20000000 762 763#define BGE_MIREG(x) ((x & 0x1F) << 16) 764#define BGE_MIPHY(x) ((x & 0x1F) << 21) 765#define BGE_MICMD_WRITE 0x04000000 766#define BGE_MICMD_READ 0x08000000 767 768/* MI status register */ 769#define BGE_MISTS_LINK 0x00000001 770#define BGE_MISTS_10MBPS 0x00000002 771 772#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 773#define BGE_MIMODE_AUTOPOLL 0x00000010 774#define BGE_MIMODE_CLKCNT 0x001F0000 775 776 777/* 778 * Send data initiator control registers. 779 */ 780#define BGE_SDI_MODE 0x0C00 781#define BGE_SDI_STATUS 0x0C04 782#define BGE_SDI_STATS_CTL 0x0C08 783#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 784#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 785#define BGE_LOCSTATS_COS0 0x0C80 786#define BGE_LOCSTATS_COS1 0x0C84 787#define BGE_LOCSTATS_COS2 0x0C88 788#define BGE_LOCSTATS_COS3 0x0C8C 789#define BGE_LOCSTATS_COS4 0x0C90 790#define BGE_LOCSTATS_COS5 0x0C84 791#define BGE_LOCSTATS_COS6 0x0C98 792#define BGE_LOCSTATS_COS7 0x0C9C 793#define BGE_LOCSTATS_COS8 0x0CA0 794#define BGE_LOCSTATS_COS9 0x0CA4 795#define BGE_LOCSTATS_COS10 0x0CA8 796#define BGE_LOCSTATS_COS11 0x0CAC 797#define BGE_LOCSTATS_COS12 0x0CB0 798#define BGE_LOCSTATS_COS13 0x0CB4 799#define BGE_LOCSTATS_COS14 0x0CB8 800#define BGE_LOCSTATS_COS15 0x0CBC 801#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 802#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 803#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 804#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 805#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 806#define BGE_LOCSTATS_IRQS 0x0CD4 807#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 808#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 809 810/* Send Data Initiator mode register */ 811#define BGE_SDIMODE_RESET 0x00000001 812#define BGE_SDIMODE_ENABLE 0x00000002 813#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 814 815/* Send Data Initiator stats register */ 816#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 817 818/* Send Data Initiator stats control register */ 819#define BGE_SDISTATSCTL_ENABLE 0x00000001 820#define BGE_SDISTATSCTL_FASTER 0x00000002 821#define BGE_SDISTATSCTL_CLEAR 0x00000004 822#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 823#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 824 825/* 826 * Send Data Completion Control registers 827 */ 828#define BGE_SDC_MODE 0x1000 829#define BGE_SDC_STATUS 0x1004 830 831/* Send Data completion mode register */ 832#define BGE_SDCMODE_RESET 0x00000001 833#define BGE_SDCMODE_ENABLE 0x00000002 834#define BGE_SDCMODE_ATTN 0x00000004 835 836/* Send Data completion status register */ 837#define BGE_SDCSTAT_ATTN 0x00000004 838 839/* 840 * Send BD Ring Selector Control registers 841 */ 842#define BGE_SRS_MODE 0x1400 843#define BGE_SRS_STATUS 0x1404 844#define BGE_SRS_HWDIAG 0x1408 845#define BGE_SRS_LOC_NIC_CONS0 0x1440 846#define BGE_SRS_LOC_NIC_CONS1 0x1444 847#define BGE_SRS_LOC_NIC_CONS2 0x1448 848#define BGE_SRS_LOC_NIC_CONS3 0x144C 849#define BGE_SRS_LOC_NIC_CONS4 0x1450 850#define BGE_SRS_LOC_NIC_CONS5 0x1454 851#define BGE_SRS_LOC_NIC_CONS6 0x1458 852#define BGE_SRS_LOC_NIC_CONS7 0x145C 853#define BGE_SRS_LOC_NIC_CONS8 0x1460 854#define BGE_SRS_LOC_NIC_CONS9 0x1464 855#define BGE_SRS_LOC_NIC_CONS10 0x1468 856#define BGE_SRS_LOC_NIC_CONS11 0x146C 857#define BGE_SRS_LOC_NIC_CONS12 0x1470 858#define BGE_SRS_LOC_NIC_CONS13 0x1474 859#define BGE_SRS_LOC_NIC_CONS14 0x1478 860#define BGE_SRS_LOC_NIC_CONS15 0x147C 861 862/* Send BD Ring Selector Mode register */ 863#define BGE_SRSMODE_RESET 0x00000001 864#define BGE_SRSMODE_ENABLE 0x00000002 865#define BGE_SRSMODE_ATTN 0x00000004 866 867/* Send BD Ring Selector Status register */ 868#define BGE_SRSSTAT_ERROR 0x00000004 869 870/* Send BD Ring Selector HW Diagnostics register */ 871#define BGE_SRSHWDIAG_STATE 0x0000000F 872#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 873#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 874#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 875 876/* 877 * Send BD Initiator Selector Control registers 878 */ 879#define BGE_SBDI_MODE 0x1800 880#define BGE_SBDI_STATUS 0x1804 881#define BGE_SBDI_LOC_NIC_PROD0 0x1808 882#define BGE_SBDI_LOC_NIC_PROD1 0x180C 883#define BGE_SBDI_LOC_NIC_PROD2 0x1810 884#define BGE_SBDI_LOC_NIC_PROD3 0x1814 885#define BGE_SBDI_LOC_NIC_PROD4 0x1818 886#define BGE_SBDI_LOC_NIC_PROD5 0x181C 887#define BGE_SBDI_LOC_NIC_PROD6 0x1820 888#define BGE_SBDI_LOC_NIC_PROD7 0x1824 889#define BGE_SBDI_LOC_NIC_PROD8 0x1828 890#define BGE_SBDI_LOC_NIC_PROD9 0x182C 891#define BGE_SBDI_LOC_NIC_PROD10 0x1830 892#define BGE_SBDI_LOC_NIC_PROD11 0x1834 893#define BGE_SBDI_LOC_NIC_PROD12 0x1838 894#define BGE_SBDI_LOC_NIC_PROD13 0x183C 895#define BGE_SBDI_LOC_NIC_PROD14 0x1840 896#define BGE_SBDI_LOC_NIC_PROD15 0x1844 897 898/* Send BD Initiator Mode register */ 899#define BGE_SBDIMODE_RESET 0x00000001 900#define BGE_SBDIMODE_ENABLE 0x00000002 901#define BGE_SBDIMODE_ATTN 0x00000004 902 903/* Send BD Initiator Status register */ 904#define BGE_SBDISTAT_ERROR 0x00000004 905 906/* 907 * Send BD Completion Control registers 908 */ 909#define BGE_SBDC_MODE 0x1C00 910#define BGE_SBDC_STATUS 0x1C04 911 912/* Send BD Completion Control Mode register */ 913#define BGE_SBDCMODE_RESET 0x00000001 914#define BGE_SBDCMODE_ENABLE 0x00000002 915#define BGE_SBDCMODE_ATTN 0x00000004 916 917/* Send BD Completion Control Status register */ 918#define BGE_SBDCSTAT_ATTN 0x00000004 919 920/* 921 * Receive List Placement Control registers 922 */ 923#define BGE_RXLP_MODE 0x2000 924#define BGE_RXLP_STATUS 0x2004 925#define BGE_RXLP_SEL_LIST_LOCK 0x2008 926#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 927#define BGE_RXLP_CFG 0x2010 928#define BGE_RXLP_STATS_CTL 0x2014 929#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 930#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 931#define BGE_RXLP_HEAD0 0x2100 932#define BGE_RXLP_TAIL0 0x2104 933#define BGE_RXLP_COUNT0 0x2108 934#define BGE_RXLP_HEAD1 0x2110 935#define BGE_RXLP_TAIL1 0x2114 936#define BGE_RXLP_COUNT1 0x2118 937#define BGE_RXLP_HEAD2 0x2120 938#define BGE_RXLP_TAIL2 0x2124 939#define BGE_RXLP_COUNT2 0x2128 940#define BGE_RXLP_HEAD3 0x2130 941#define BGE_RXLP_TAIL3 0x2134 942#define BGE_RXLP_COUNT3 0x2138 943#define BGE_RXLP_HEAD4 0x2140 944#define BGE_RXLP_TAIL4 0x2144 945#define BGE_RXLP_COUNT4 0x2148 946#define BGE_RXLP_HEAD5 0x2150 947#define BGE_RXLP_TAIL5 0x2154 948#define BGE_RXLP_COUNT5 0x2158 949#define BGE_RXLP_HEAD6 0x2160 950#define BGE_RXLP_TAIL6 0x2164 951#define BGE_RXLP_COUNT6 0x2168 952#define BGE_RXLP_HEAD7 0x2170 953#define BGE_RXLP_TAIL7 0x2174 954#define BGE_RXLP_COUNT7 0x2178 955#define BGE_RXLP_HEAD8 0x2180 956#define BGE_RXLP_TAIL8 0x2184 957#define BGE_RXLP_COUNT8 0x2188 958#define BGE_RXLP_HEAD9 0x2190 959#define BGE_RXLP_TAIL9 0x2194 960#define BGE_RXLP_COUNT9 0x2198 961#define BGE_RXLP_HEAD10 0x21A0 962#define BGE_RXLP_TAIL10 0x21A4 963#define BGE_RXLP_COUNT10 0x21A8 964#define BGE_RXLP_HEAD11 0x21B0 965#define BGE_RXLP_TAIL11 0x21B4 966#define BGE_RXLP_COUNT11 0x21B8 967#define BGE_RXLP_HEAD12 0x21C0 968#define BGE_RXLP_TAIL12 0x21C4 969#define BGE_RXLP_COUNT12 0x21C8 970#define BGE_RXLP_HEAD13 0x21D0 971#define BGE_RXLP_TAIL13 0x21D4 972#define BGE_RXLP_COUNT13 0x21D8 973#define BGE_RXLP_HEAD14 0x21E0 974#define BGE_RXLP_TAIL14 0x21E4 975#define BGE_RXLP_COUNT14 0x21E8 976#define BGE_RXLP_HEAD15 0x21F0 977#define BGE_RXLP_TAIL15 0x21F4 978#define BGE_RXLP_COUNT15 0x21F8 979#define BGE_RXLP_LOCSTAT_COS0 0x2200 980#define BGE_RXLP_LOCSTAT_COS1 0x2204 981#define BGE_RXLP_LOCSTAT_COS2 0x2208 982#define BGE_RXLP_LOCSTAT_COS3 0x220C 983#define BGE_RXLP_LOCSTAT_COS4 0x2210 984#define BGE_RXLP_LOCSTAT_COS5 0x2214 985#define BGE_RXLP_LOCSTAT_COS6 0x2218 986#define BGE_RXLP_LOCSTAT_COS7 0x221C 987#define BGE_RXLP_LOCSTAT_COS8 0x2220 988#define BGE_RXLP_LOCSTAT_COS9 0x2224 989#define BGE_RXLP_LOCSTAT_COS10 0x2228 990#define BGE_RXLP_LOCSTAT_COS11 0x222C 991#define BGE_RXLP_LOCSTAT_COS12 0x2230 992#define BGE_RXLP_LOCSTAT_COS13 0x2234 993#define BGE_RXLP_LOCSTAT_COS14 0x2238 994#define BGE_RXLP_LOCSTAT_COS15 0x223C 995#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 996#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 997#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 998#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 999#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1000#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1001#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1002 1003 1004/* Receive List Placement mode register */ 1005#define BGE_RXLPMODE_RESET 0x00000001 1006#define BGE_RXLPMODE_ENABLE 0x00000002 1007#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1008#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1009#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1010 1011/* Receive List Placement Status register */ 1012#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1013#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1014#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1015 1016/* 1017 * Receive Data and Receive BD Initiator Control Registers 1018 */ 1019#define BGE_RDBDI_MODE 0x2400 1020#define BGE_RDBDI_STATUS 0x2404 1021#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1022#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1023#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1024#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1025#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1026#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1027#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1028#define BGE_RX_STD_RCB_NICADDR 0x245C 1029#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1030#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1031#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1032#define BGE_RX_MINI_RCB_NICADDR 0x246C 1033#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1034#define BGE_RDBDI_STD_RX_CONS 0x2474 1035#define BGE_RDBDI_MINI_RX_CONS 0x2478 1036#define BGE_RDBDI_RETURN_PROD0 0x2480 1037#define BGE_RDBDI_RETURN_PROD1 0x2484 1038#define BGE_RDBDI_RETURN_PROD2 0x2488 1039#define BGE_RDBDI_RETURN_PROD3 0x248C 1040#define BGE_RDBDI_RETURN_PROD4 0x2490 1041#define BGE_RDBDI_RETURN_PROD5 0x2494 1042#define BGE_RDBDI_RETURN_PROD6 0x2498 1043#define BGE_RDBDI_RETURN_PROD7 0x249C 1044#define BGE_RDBDI_RETURN_PROD8 0x24A0 1045#define BGE_RDBDI_RETURN_PROD9 0x24A4 1046#define BGE_RDBDI_RETURN_PROD10 0x24A8 1047#define BGE_RDBDI_RETURN_PROD11 0x24AC 1048#define BGE_RDBDI_RETURN_PROD12 0x24B0 1049#define BGE_RDBDI_RETURN_PROD13 0x24B4 1050#define BGE_RDBDI_RETURN_PROD14 0x24B8 1051#define BGE_RDBDI_RETURN_PROD15 0x24BC 1052#define BGE_RDBDI_HWDIAG 0x24C0 1053 1054 1055/* Receive Data and Receive BD Initiator Mode register */ 1056#define BGE_RDBDIMODE_RESET 0x00000001 1057#define BGE_RDBDIMODE_ENABLE 0x00000002 1058#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1059#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1060#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1061 1062/* Receive Data and Receive BD Initiator Status register */ 1063#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1064#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1065#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1066 1067 1068/* 1069 * Receive Data Completion Control registers 1070 */ 1071#define BGE_RDC_MODE 0x2800 1072 1073/* Receive Data Completion Mode register */ 1074#define BGE_RDCMODE_RESET 0x00000001 1075#define BGE_RDCMODE_ENABLE 0x00000002 1076#define BGE_RDCMODE_ATTN 0x00000004 1077 1078/* 1079 * Receive BD Initiator Control registers 1080 */ 1081#define BGE_RBDI_MODE 0x2C00 1082#define BGE_RBDI_STATUS 0x2C04 1083#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1084#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1085#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1086#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1087#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1088#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1089 1090/* Receive BD Initiator Mode register */ 1091#define BGE_RBDIMODE_RESET 0x00000001 1092#define BGE_RBDIMODE_ENABLE 0x00000002 1093#define BGE_RBDIMODE_ATTN 0x00000004 1094 1095/* Receive BD Initiator Status register */ 1096#define BGE_RBDISTAT_ATTN 0x00000004 1097 1098/* 1099 * Receive BD Completion Control registers 1100 */ 1101#define BGE_RBDC_MODE 0x3000 1102#define BGE_RBDC_STATUS 0x3004 1103#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1104#define BGE_RBDC_STD_BD_PROD 0x300C 1105#define BGE_RBDC_MINI_BD_PROD 0x3010 1106 1107/* Receive BD completion mode register */ 1108#define BGE_RBDCMODE_RESET 0x00000001 1109#define BGE_RBDCMODE_ENABLE 0x00000002 1110#define BGE_RBDCMODE_ATTN 0x00000004 1111 1112/* Receive BD completion status register */ 1113#define BGE_RBDCSTAT_ERROR 0x00000004 1114 1115/* 1116 * Receive List Selector Control registers 1117 */ 1118#define BGE_RXLS_MODE 0x3400 1119#define BGE_RXLS_STATUS 0x3404 1120 1121/* Receive List Selector Mode register */ 1122#define BGE_RXLSMODE_RESET 0x00000001 1123#define BGE_RXLSMODE_ENABLE 0x00000002 1124#define BGE_RXLSMODE_ATTN 0x00000004 1125 1126/* Receive List Selector Status register */ 1127#define BGE_RXLSSTAT_ERROR 0x00000004 1128 1129/* 1130 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1131 */ 1132#define BGE_MBCF_MODE 0x3800 1133#define BGE_MBCF_STATUS 0x3804 1134 1135/* Mbuf Cluster Free mode register */ 1136#define BGE_MBCFMODE_RESET 0x00000001 1137#define BGE_MBCFMODE_ENABLE 0x00000002 1138#define BGE_MBCFMODE_ATTN 0x00000004 1139 1140/* Mbuf Cluster Free status register */ 1141#define BGE_MBCFSTAT_ERROR 0x00000004 1142 1143/* 1144 * Host Coalescing Control registers 1145 */ 1146#define BGE_HCC_MODE 0x3C00 1147#define BGE_HCC_STATUS 0x3C04 1148#define BGE_HCC_RX_COAL_TICKS 0x3C08 1149#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1150#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1151#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1152#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1153#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1154#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1155#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1156#define BGE_HCC_STATS_TICKS 0x3C28 1157#define BGE_HCC_STATS_ADDR_HI 0x3C30 1158#define BGE_HCC_STATS_ADDR_LO 0x3C34 1159#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1160#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1161#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1162#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1163#define BGE_FLOW_ATTN 0x3C48 1164#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1165#define BGE_HCC_STD_BD_CONS 0x3C54 1166#define BGE_HCC_MINI_BD_CONS 0x3C58 1167#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1168#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1169#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1170#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1171#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1172#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1173#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1174#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1175#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1176#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1177#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1178#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1179#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1180#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1181#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1182#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1183#define BGE_HCC_TX_BD_CONS0 0x3CC0 1184#define BGE_HCC_TX_BD_CONS1 0x3CC4 1185#define BGE_HCC_TX_BD_CONS2 0x3CC8 1186#define BGE_HCC_TX_BD_CONS3 0x3CCC 1187#define BGE_HCC_TX_BD_CONS4 0x3CD0 1188#define BGE_HCC_TX_BD_CONS5 0x3CD4 1189#define BGE_HCC_TX_BD_CONS6 0x3CD8 1190#define BGE_HCC_TX_BD_CONS7 0x3CDC 1191#define BGE_HCC_TX_BD_CONS8 0x3CE0 1192#define BGE_HCC_TX_BD_CONS9 0x3CE4 1193#define BGE_HCC_TX_BD_CONS10 0x3CE8 1194#define BGE_HCC_TX_BD_CONS11 0x3CEC 1195#define BGE_HCC_TX_BD_CONS12 0x3CF0 1196#define BGE_HCC_TX_BD_CONS13 0x3CF4 1197#define BGE_HCC_TX_BD_CONS14 0x3CF8 1198#define BGE_HCC_TX_BD_CONS15 0x3CFC 1199 1200 1201/* Host coalescing mode register */ 1202#define BGE_HCCMODE_RESET 0x00000001 1203#define BGE_HCCMODE_ENABLE 0x00000002 1204#define BGE_HCCMODE_ATTN 0x00000004 1205#define BGE_HCCMODE_COAL_NOW 0x00000008 1206#define BGE_HCCMODE_MSI_BITS 0x00000070 1207#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1208 1209#define BGE_STATBLKSZ_FULL 0x00000000 1210#define BGE_STATBLKSZ_64BYTE 0x00000080 1211#define BGE_STATBLKSZ_32BYTE 0x00000100 1212 1213/* Host coalescing status register */ 1214#define BGE_HCCSTAT_ERROR 0x00000004 1215 1216/* Flow attention register */ 1217#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1218#define BGE_FLOWATTN_MEMARB 0x00000080 1219#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1220#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1221#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1222#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1223#define BGE_FLOWATTN_RDBDI 0x00080000 1224#define BGE_FLOWATTN_RXLS 0x00100000 1225#define BGE_FLOWATTN_RXLP 0x00200000 1226#define BGE_FLOWATTN_RBDC 0x00400000 1227#define BGE_FLOWATTN_RBDI 0x00800000 1228#define BGE_FLOWATTN_SDC 0x08000000 1229#define BGE_FLOWATTN_SDI 0x10000000 1230#define BGE_FLOWATTN_SRS 0x20000000 1231#define BGE_FLOWATTN_SBDC 0x40000000 1232#define BGE_FLOWATTN_SBDI 0x80000000 1233 1234/* 1235 * Memory arbiter registers 1236 */ 1237#define BGE_MARB_MODE 0x4000 1238#define BGE_MARB_STATUS 0x4004 1239#define BGE_MARB_TRAPADDR_HI 0x4008 1240#define BGE_MARB_TRAPADDR_LO 0x400C 1241 1242/* Memory arbiter mode register */ 1243#define BGE_MARBMODE_RESET 0x00000001 1244#define BGE_MARBMODE_ENABLE 0x00000002 1245#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1246#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1247#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1248#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1249#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1250#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1251#define BGE_MARBMODE_PCI_TRAP 0x00000100 1252#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1253#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1254#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1255#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1256#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1257#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1258#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1259#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1260#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1261#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1262#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1263#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1264#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1265#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1266#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1267#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1268#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1269 1270/* Memory arbiter status register */ 1271#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1272#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1273#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1274#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1275#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1276#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1277#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1278#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1279#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1280#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1281#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1282#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1283#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1284#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1285#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1286#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1287#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1288#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1289#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1290#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1291#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1292#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1293#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1294#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1295 1296/* 1297 * Buffer manager control registers 1298 */ 1299#define BGE_BMAN_MODE 0x4400 1300#define BGE_BMAN_STATUS 0x4404 1301#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1302#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1303#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1304#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1305#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1306#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1307#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1308#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1309#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1310#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1311#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1312#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1313#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1314#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1315#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1316#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1317#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1318#define BGE_BMAN_HWDIAG_1 0x444C 1319#define BGE_BMAN_HWDIAG_2 0x4450 1320#define BGE_BMAN_HWDIAG_3 0x4454 1321 1322/* Buffer manager mode register */ 1323#define BGE_BMANMODE_RESET 0x00000001 1324#define BGE_BMANMODE_ENABLE 0x00000002 1325#define BGE_BMANMODE_ATTN 0x00000004 1326#define BGE_BMANMODE_TESTMODE 0x00000008 1327#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1328 1329/* Buffer manager status register */ 1330#define BGE_BMANSTAT_ERRO 0x00000004 1331#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1332 1333 1334/* 1335 * Read DMA Control registers 1336 */ 1337#define BGE_RDMA_MODE 0x4800 1338#define BGE_RDMA_STATUS 0x4804 1339 1340/* Read DMA mode register */ 1341#define BGE_RDMAMODE_RESET 0x00000001 1342#define BGE_RDMAMODE_ENABLE 0x00000002 1343#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1344#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1345#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1346#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1347#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1348#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1349#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1350#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1351#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1352 1353/* Alternate encodings for PCI-Express, from Broadcom-supplied Linux driver */ 1354#define BGE_RDMA_MODE_FIFO_LONG_BURST ((1<<17) || (1 << 16)) 1355#define BGE_RDMA_MODE_FIFO_SIZE_128 (1 << 17) 1356 1357/* Read DMA status register */ 1358#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1359#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1360#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1361#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1362#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1363#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1364#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1365#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1366 1367/* 1368 * Write DMA control registers 1369 */ 1370#define BGE_WDMA_MODE 0x4C00 1371#define BGE_WDMA_STATUS 0x4C04 1372 1373/* Write DMA mode register */ 1374#define BGE_WDMAMODE_RESET 0x00000001 1375#define BGE_WDMAMODE_ENABLE 0x00000002 1376#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1377#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1378#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1379#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1380#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1381#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1382#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1383#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1384#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1385 1386/* Write DMA status register */ 1387#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1388#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1389#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1390#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1391#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1392#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1393#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1394#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1395 1396 1397/* 1398 * RX CPU registers 1399 */ 1400#define BGE_RXCPU_MODE 0x5000 1401#define BGE_RXCPU_STATUS 0x5004 1402#define BGE_RXCPU_PC 0x501C 1403 1404/* RX CPU mode register */ 1405#define BGE_RXCPUMODE_RESET 0x00000001 1406#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1407#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1408#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1409#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1410#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1411#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1412#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1413#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1414#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1415#define BGE_RXCPUMODE_HALTCPU 0x00000400 1416#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1417#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1418#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1419 1420/* RX CPU status register */ 1421#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1422#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1423#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1424#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1425#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1426#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1427#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1428#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1429#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1430#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1431#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1432#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1433#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1434#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1435#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1436#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1437#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1438 1439 1440/* 1441 * TX CPU registers 1442 */ 1443#define BGE_TXCPU_MODE 0x5400 1444#define BGE_TXCPU_STATUS 0x5404 1445#define BGE_TXCPU_PC 0x541C 1446 1447/* TX CPU mode register */ 1448#define BGE_TXCPUMODE_RESET 0x00000001 1449#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1450#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1451#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1452#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1453#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1454#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1455#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1456#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1457#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1458#define BGE_TXCPUMODE_HALTCPU 0x00000400 1459#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1460#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1461 1462/* TX CPU status register */ 1463#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1464#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1465#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1466#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1467#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1468#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1469#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1470#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1471#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1472#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1473#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1474#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1475#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1476#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1477#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1478#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1479#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1480 1481 1482/* 1483 * Low priority mailbox registers 1484 */ 1485#define BGE_LPMBX_IRQ0_HI 0x5800 1486#define BGE_LPMBX_IRQ0_LO 0x5804 1487#define BGE_LPMBX_IRQ1_HI 0x5808 1488#define BGE_LPMBX_IRQ1_LO 0x580C 1489#define BGE_LPMBX_IRQ2_HI 0x5810 1490#define BGE_LPMBX_IRQ2_LO 0x5814 1491#define BGE_LPMBX_IRQ3_HI 0x5818 1492#define BGE_LPMBX_IRQ3_LO 0x581C 1493#define BGE_LPMBX_GEN0_HI 0x5820 1494#define BGE_LPMBX_GEN0_LO 0x5824 1495#define BGE_LPMBX_GEN1_HI 0x5828 1496#define BGE_LPMBX_GEN1_LO 0x582C 1497#define BGE_LPMBX_GEN2_HI 0x5830 1498#define BGE_LPMBX_GEN2_LO 0x5834 1499#define BGE_LPMBX_GEN3_HI 0x5828 1500#define BGE_LPMBX_GEN3_LO 0x582C 1501#define BGE_LPMBX_GEN4_HI 0x5840 1502#define BGE_LPMBX_GEN4_LO 0x5844 1503#define BGE_LPMBX_GEN5_HI 0x5848 1504#define BGE_LPMBX_GEN5_LO 0x584C 1505#define BGE_LPMBX_GEN6_HI 0x5850 1506#define BGE_LPMBX_GEN6_LO 0x5854 1507#define BGE_LPMBX_GEN7_HI 0x5858 1508#define BGE_LPMBX_GEN7_LO 0x585C 1509#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1510#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1511#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1512#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1513#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1514#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1515#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1516#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1517#define BGE_LPMBX_RX_CONS0_HI 0x5880 1518#define BGE_LPMBX_RX_CONS0_LO 0x5884 1519#define BGE_LPMBX_RX_CONS1_HI 0x5888 1520#define BGE_LPMBX_RX_CONS1_LO 0x588C 1521#define BGE_LPMBX_RX_CONS2_HI 0x5890 1522#define BGE_LPMBX_RX_CONS2_LO 0x5894 1523#define BGE_LPMBX_RX_CONS3_HI 0x5898 1524#define BGE_LPMBX_RX_CONS3_LO 0x589C 1525#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1526#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1527#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1528#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1529#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1530#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1531#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1532#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1533#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1534#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1535#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1536#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1537#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1538#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1539#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1540#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1541#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1542#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1543#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1544#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1545#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1546#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1547#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1548#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1549#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1550#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1551#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1552#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1553#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1554#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1555#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1556#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1557#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1558#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1559#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1560#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1561#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1562#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1563#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1564#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1565#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1566#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1567#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1568#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1569#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1570#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1571#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1572#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1573#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1574#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1575#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1576#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1577#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1578#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1579#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1580#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1581#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1582#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1583#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1584#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1585#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1586#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1587#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1588#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1589#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1590#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1591#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1592#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1593#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1594#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1595#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1596#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1597#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1598#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1599#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1600#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1601#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1602#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1603#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1604#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1605#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1606#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1607#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1608#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1609#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1610#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1611#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1612#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1613 1614/* 1615 * Flow throw Queue reset register 1616 */ 1617#define BGE_FTQ_RESET 0x5C00 1618 1619#define BGE_FTQRESET_DMAREAD 0x00000002 1620#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1621#define BGE_FTQRESET_DMADONE 0x00000010 1622#define BGE_FTQRESET_SBDC 0x00000020 1623#define BGE_FTQRESET_SDI 0x00000040 1624#define BGE_FTQRESET_WDMA 0x00000080 1625#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1626#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1627#define BGE_FTQRESET_SDC 0x00000400 1628#define BGE_FTQRESET_HCC 0x00000800 1629#define BGE_FTQRESET_TXFIFO 0x00001000 1630#define BGE_FTQRESET_MBC 0x00002000 1631#define BGE_FTQRESET_RBDC 0x00004000 1632#define BGE_FTQRESET_RXLP 0x00008000 1633#define BGE_FTQRESET_RDBDI 0x00010000 1634#define BGE_FTQRESET_RDC 0x00020000 1635#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1636 1637/* 1638 * Message Signaled Interrupt registers 1639 */ 1640#define BGE_MSI_MODE 0x6000 1641#define BGE_MSI_STATUS 0x6004 1642#define BGE_MSI_FIFOACCESS 0x6008 1643 1644/* MSI mode register */ 1645#define BGE_MSIMODE_RESET 0x00000001 1646#define BGE_MSIMODE_ENABLE 0x00000002 1647#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1648#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1649#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1650#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1651#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1652 1653/* MSI status register */ 1654#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1655#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1656#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1657#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1658#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1659 1660 1661/* 1662 * DMA Completion registers 1663 */ 1664#define BGE_DMAC_MODE 0x6400 1665 1666/* DMA Completion mode register */ 1667#define BGE_DMACMODE_RESET 0x00000001 1668#define BGE_DMACMODE_ENABLE 0x00000002 1669 1670 1671/* 1672 * General control registers. 1673 */ 1674#define BGE_MODE_CTL 0x6800 1675#define BGE_MISC_CFG 0x6804 1676#define BGE_MISC_LOCAL_CTL 0x6808 1677#define BGE_CPU_EVENT 0x6810 1678#define BGE_EE_ADDR 0x6838 1679#define BGE_EE_DATA 0x683C 1680#define BGE_EE_CTL 0x6840 1681#define BGE_MDI_CTL 0x6844 1682#define BGE_EE_DELAY 0x6848 1683 1684/* 1685 * TLP Control Register 1686 * Applicable to BCM5721 and BCM5751 only 1687 */ 1688#define BGE_TLP_CONTROL_REG 0x7c00 1689#define BGE_TLP_DATA_FIFO_PROTECT 0x02000000 1690 1691/* 1692 * PHY Test Control Register 1693 * Applicable to BCM5721 and BCM5751 only 1694 */ 1695#define BGE_PHY_TEST_CTRL_REG 0x7e2c 1696#define BGE_PHY_PCIE_SCRAM_MODE 0x0020 1697#define BGE_PHY_PCIE_LTASS_MODE 0x0040 1698 1699/* Mode control register */ 1700#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1701#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1702#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1703#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1704#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1705#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1706#define BGE_MODECTL_NO_RX_CRC 0x00000400 1707#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1708#define BGE_MODECTL_NO_TX_INTR 0x00002000 1709#define BGE_MODECTL_NO_RX_INTR 0x00004000 1710#define BGE_MODECTL_FORCE_PCI32 0x00008000 1711#define BGE_MODECTL_STACKUP 0x00010000 1712#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1713#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1714#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1715#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1716#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1717#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1718#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1719#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1720#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1721#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1722 1723/* Misc. config register */ 1724#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1725#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1726#define BGE_MISCCFG_GPHY_POWER_RESET 0x04000000 1727 1728#define BGE_32BITTIME_66MHZ (0x41 << 1) 1729 1730/* Misc. Local Control */ 1731#define BGE_MLC_INTR_STATE 0x00000001 1732#define BGE_MLC_INTR_CLR 0x00000002 1733#define BGE_MLC_INTR_SET 0x00000004 1734#define BGE_MLC_INTR_ONATTN 0x00000008 1735#define BGE_MLC_MISCIO_IN0 0x00000100 1736#define BGE_MLC_MISCIO_IN1 0x00000200 1737#define BGE_MLC_MISCIO_IN2 0x00000400 1738#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1739#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1740#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1741#define BGE_MLC_MISCIO_OUT0 0x00004000 1742#define BGE_MLC_MISCIO_OUT1 0x00008000 1743#define BGE_MLC_MISCIO_OUT2 0x00010000 1744#define BGE_MLC_EXTRAM_ENB 0x00020000 1745#define BGE_MLC_SRAM_SIZE 0x001C0000 1746#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1747#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1748#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1749#define BGE_MLC_AUTO_EEPROM 0x01000000 1750 1751#define BGE_SSRAMSIZE_256KB 0x00000000 1752#define BGE_SSRAMSIZE_512KB 0x00040000 1753#define BGE_SSRAMSIZE_1MB 0x00080000 1754#define BGE_SSRAMSIZE_2MB 0x000C0000 1755#define BGE_SSRAMSIZE_4MB 0x00100000 1756#define BGE_SSRAMSIZE_8MB 0x00140000 1757#define BGE_SSRAMSIZE_16M 0x00180000 1758 1759/* EEPROM address register */ 1760#define BGE_EEADDR_ADDRESS 0x0000FFFC 1761#define BGE_EEADDR_HALFCLK 0x01FF0000 1762#define BGE_EEADDR_START 0x02000000 1763#define BGE_EEADDR_DEVID 0x1C000000 1764#define BGE_EEADDR_RESET 0x20000000 1765#define BGE_EEADDR_DONE 0x40000000 1766#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1767 1768#define BGE_EEDEVID(x) ((x & 7) << 26) 1769#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1770#define BGE_HALFCLK_384SCL 0x60 1771#define BGE_EE_READCMD \ 1772 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1773 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1774#define BGE_EE_WRCMD \ 1775 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1776 BGE_EEADDR_START|BGE_EEADDR_DONE) 1777 1778/* EEPROM Control register */ 1779#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1780#define BGE_EECTL_CLKOUT 0x00000002 1781#define BGE_EECTL_CLKIN 0x00000004 1782#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1783#define BGE_EECTL_DATAOUT 0x00000010 1784#define BGE_EECTL_DATAIN 0x00000020 1785 1786/* MDI (MII/GMII) access register */ 1787#define BGE_MDI_DATA 0x00000001 1788#define BGE_MDI_DIR 0x00000002 1789#define BGE_MDI_SEL 0x00000004 1790#define BGE_MDI_CLK 0x00000008 1791 1792#define BGE_MEMWIN_START 0x00008000 1793#define BGE_MEMWIN_END 0x0000FFFF 1794 1795 1796#define BGE_MEMWIN_READ(pc, tag, x, val) \ 1797 do { \ 1798 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1799 (0xFFFF0000 & x)); \ 1800 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1801 } while(0) 1802 1803#define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 1804 do { \ 1805 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1806 (0xFFFF0000 & x)); \ 1807 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1808 } while(0) 1809 1810/* 1811 * This magic number is used to prevent PXE restart when we 1812 * issue a software reset. We write this magic number to the 1813 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1814 * code from running. 1815 */ 1816#define BGE_MAGIC_NUMBER 0x4B657654 1817 1818typedef struct { 1819 u_int32_t bge_addr_hi; 1820 u_int32_t bge_addr_lo; 1821} bge_hostaddr; 1822#define BGE_HOSTADDR(x,y) \ 1823 do { \ 1824 (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 1825 if (sizeof(bus_addr_t) == 8) \ 1826 (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 1827 else \ 1828 (x).bge_addr_hi = 0; \ 1829 } while(0) 1830 1831/* Ring control block structure */ 1832struct bge_rcb { 1833 bge_hostaddr bge_hostaddr; 1834 u_int32_t bge_maxlen_flags; 1835 u_int32_t bge_nicaddr; 1836}; 1837 1838#define RCB_WRITE_4(sc, rcb, offset, val) \ 1839 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1840 rcb + offsetof(struct bge_rcb, offset), val) 1841 1842#define RCB_WRITE_2(sc, rcb, offset, val) \ 1843 bus_space_write_2(sc->bge_btag, sc->bge_bhandle, \ 1844 rcb + offsetof(struct bge_rcb, offset), val) 1845 1846#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1847 1848#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1849#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1850 1851struct bge_tx_bd { 1852 bge_hostaddr bge_addr; 1853#if BYTE_ORDER == LITTLE_ENDIAN 1854 u_int16_t bge_flags; 1855 u_int16_t bge_len; 1856 u_int16_t bge_vlan_tag; 1857 u_int16_t bge_rsvd; 1858#else 1859 u_int16_t bge_len; 1860 u_int16_t bge_flags; 1861 u_int16_t bge_rsvd; 1862 u_int16_t bge_vlan_tag; 1863#endif 1864}; 1865 1866#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1867#define BGE_TXBDFLAG_IP_CSUM 0x0002 1868#define BGE_TXBDFLAG_END 0x0004 1869#define BGE_TXBDFLAG_IP_FRAG 0x0008 1870#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1871#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1872#define BGE_TXBDFLAG_COAL_NOW 0x0080 1873#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1874#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1875#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1876#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1877#define BGE_TXBDFLAG_NO_CRC 0x8000 1878 1879#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1880 BGE_SEND_RING_1_TO_4 + \ 1881 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1882 1883struct bge_rx_bd { 1884 bge_hostaddr bge_addr; 1885#if BYTE_ORDER == LITTLE_ENDIAN 1886 u_int16_t bge_len; 1887 u_int16_t bge_idx; 1888 u_int16_t bge_flags; 1889 u_int16_t bge_type; 1890 u_int16_t bge_tcp_udp_csum; 1891 u_int16_t bge_ip_csum; 1892 u_int16_t bge_vlan_tag; 1893 u_int16_t bge_error_flag; 1894#else 1895 u_int16_t bge_idx; 1896 u_int16_t bge_len; 1897 u_int16_t bge_type; 1898 u_int16_t bge_flags; 1899 u_int16_t bge_ip_csum; 1900 u_int16_t bge_tcp_udp_csum; 1901 u_int16_t bge_error_flag; 1902 u_int16_t bge_vlan_tag; 1903#endif 1904 u_int32_t bge_rsvd; 1905 u_int32_t bge_opaque; 1906}; 1907 1908#define BGE_RXBDFLAG_END 0x0004 1909#define BGE_RXBDFLAG_JUMBO_RING 0x0020 1910#define BGE_RXBDFLAG_VLAN_TAG 0x0040 1911#define BGE_RXBDFLAG_ERROR 0x0400 1912#define BGE_RXBDFLAG_MINI_RING 0x0800 1913#define BGE_RXBDFLAG_IP_CSUM 0x1000 1914#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1915#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1916 1917#define BGE_RXERRFLAG_BAD_CRC 0x0001 1918#define BGE_RXERRFLAG_COLL_DETECT 0x0002 1919#define BGE_RXERRFLAG_LINK_LOST 0x0004 1920#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1921#define BGE_RXERRFLAG_MAC_ABORT 0x0010 1922#define BGE_RXERRFLAG_RUNT 0x0020 1923#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1924#define BGE_RXERRFLAG_GIANT 0x0080 1925 1926struct bge_sts_idx { 1927#if BYTE_ORDER == LITTLE_ENDIAN 1928 u_int16_t bge_rx_prod_idx; 1929 u_int16_t bge_tx_cons_idx; 1930#else 1931 u_int16_t bge_tx_cons_idx; 1932 u_int16_t bge_rx_prod_idx; 1933#endif 1934}; 1935 1936struct bge_status_block { 1937 u_int32_t bge_status; 1938 u_int32_t bge_rsvd0; 1939#if BYTE_ORDER == LITTLE_ENDIAN 1940 u_int16_t bge_rx_jumbo_cons_idx; 1941 u_int16_t bge_rx_std_cons_idx; 1942 u_int16_t bge_rx_mini_cons_idx; 1943 u_int16_t bge_rsvd1; 1944#else 1945 u_int16_t bge_rx_std_cons_idx; 1946 u_int16_t bge_rx_jumbo_cons_idx; 1947 u_int16_t bge_rsvd1; 1948 u_int16_t bge_rx_mini_cons_idx; 1949#endif 1950 struct bge_sts_idx bge_idx[16]; 1951}; 1952 1953#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1954#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1955 1956#define BGE_STATFLAG_UPDATED 0x00000001 1957#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1958#define BGE_STATFLAG_ERROR 0x00000004 1959 1960/* 1961 * SysKonnect Subsystem IDs 1962 */ 1963#define SK_SUBSYSID_9D21 0x4421 1964#define SK_SUBSYSID_9D41 0x4441 1965 1966/* 1967 * Offset of MAC address inside EEPROM. 1968 */ 1969#define BGE_EE_MAC_OFFSET 0x7C 1970#define BGE_EE_HWCFG_OFFSET 0xC8 1971 1972#define BGE_HWCFG_VOLTAGE 0x00000003 1973#define BGE_HWCFG_PHYLED_MODE 0x0000000C 1974#define BGE_HWCFG_MEDIA 0x00000030 1975#define BGE_HWCFG_ASF 0x00000080 1976 1977#define BGE_VOLTAGE_1POINT3 0x00000000 1978#define BGE_VOLTAGE_1POINT8 0x00000001 1979 1980#define BGE_PHYLEDMODE_UNSPEC 0x00000000 1981#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 1982#define BGE_PHYLEDMODE_SINGLELED 0x00000008 1983 1984#define BGE_MEDIA_UNSPEC 0x00000000 1985#define BGE_MEDIA_COPPER 0x00000010 1986#define BGE_MEDIA_FIBER 0x00000020 1987 1988#define BGE_PCI_READ_CMD 0x06000000 1989#define BGE_PCI_WRITE_CMD 0x70000000 1990 1991#define BGE_TICKS_PER_SEC 1000000 1992 1993/* 1994 * Ring size constants. 1995 */ 1996#define BGE_EVENT_RING_CNT 256 1997#define BGE_CMD_RING_CNT 64 1998#define BGE_STD_RX_RING_CNT 512 1999#define BGE_JUMBO_RX_RING_CNT 256 2000#define BGE_MINI_RX_RING_CNT 1024 2001#define BGE_RETURN_RING_CNT 1024 2002 2003/* 5705 has smaller return ring size */ 2004#define BGE_RETURN_RING_CNT_5705 512 2005 2006/* 2007 * Possible TX ring sizes. 2008 */ 2009#define BGE_TX_RING_CNT_128 128 2010#define BGE_TX_RING_BASE_128 0x3800 2011 2012#define BGE_TX_RING_CNT_256 256 2013#define BGE_TX_RING_BASE_256 0x3000 2014 2015#define BGE_TX_RING_CNT_512 512 2016#define BGE_TX_RING_BASE_512 0x2000 2017 2018#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2019#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2020 2021/* 2022 * Tigon III statistics counters. 2023 */ 2024/* Statistics maintained MAC Receive block. */ 2025struct bge_rx_mac_stats { 2026 bge_hostaddr ifHCInOctets; 2027 bge_hostaddr Reserved1; 2028 bge_hostaddr etherStatsFragments; 2029 bge_hostaddr ifHCInUcastPkts; 2030 bge_hostaddr ifHCInMulticastPkts; 2031 bge_hostaddr ifHCInBroadcastPkts; 2032 bge_hostaddr dot3StatsFCSErrors; 2033 bge_hostaddr dot3StatsAlignmentErrors; 2034 bge_hostaddr xonPauseFramesReceived; 2035 bge_hostaddr xoffPauseFramesReceived; 2036 bge_hostaddr macControlFramesReceived; 2037 bge_hostaddr xoffStateEntered; 2038 bge_hostaddr dot3StatsFramesTooLong; 2039 bge_hostaddr etherStatsJabbers; 2040 bge_hostaddr etherStatsUndersizePkts; 2041 bge_hostaddr inRangeLengthError; 2042 bge_hostaddr outRangeLengthError; 2043 bge_hostaddr etherStatsPkts64Octets; 2044 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2045 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2046 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2047 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2048 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2049 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2050 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2051 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2052 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2053}; 2054 2055/* Statistics maintained MAC Transmit block. */ 2056struct bge_tx_mac_stats { 2057 bge_hostaddr ifHCOutOctets; 2058 bge_hostaddr Reserved2; 2059 bge_hostaddr etherStatsCollisions; 2060 bge_hostaddr outXonSent; 2061 bge_hostaddr outXoffSent; 2062 bge_hostaddr flowControlDone; 2063 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2064 bge_hostaddr dot3StatsSingleCollisionFrames; 2065 bge_hostaddr dot3StatsMultipleCollisionFrames; 2066 bge_hostaddr dot3StatsDeferredTransmissions; 2067 bge_hostaddr Reserved3; 2068 bge_hostaddr dot3StatsExcessiveCollisions; 2069 bge_hostaddr dot3StatsLateCollisions; 2070 bge_hostaddr dot3Collided2Times; 2071 bge_hostaddr dot3Collided3Times; 2072 bge_hostaddr dot3Collided4Times; 2073 bge_hostaddr dot3Collided5Times; 2074 bge_hostaddr dot3Collided6Times; 2075 bge_hostaddr dot3Collided7Times; 2076 bge_hostaddr dot3Collided8Times; 2077 bge_hostaddr dot3Collided9Times; 2078 bge_hostaddr dot3Collided10Times; 2079 bge_hostaddr dot3Collided11Times; 2080 bge_hostaddr dot3Collided12Times; 2081 bge_hostaddr dot3Collided13Times; 2082 bge_hostaddr dot3Collided14Times; 2083 bge_hostaddr dot3Collided15Times; 2084 bge_hostaddr ifHCOutUcastPkts; 2085 bge_hostaddr ifHCOutMulticastPkts; 2086 bge_hostaddr ifHCOutBroadcastPkts; 2087 bge_hostaddr dot3StatsCarrierSenseErrors; 2088 bge_hostaddr ifOutDiscards; 2089 bge_hostaddr ifOutErrors; 2090}; 2091 2092/* Stats counters access through registers */ 2093struct bge_mac_stats_regs { 2094 u_int32_t ifHCOutOctets; 2095 u_int32_t Reserved0; 2096 u_int32_t etherStatsCollisions; 2097 u_int32_t outXonSent; 2098 u_int32_t outXoffSent; 2099 u_int32_t Reserved1; 2100 u_int32_t dot3StatsInternalMacTransmitErrors; 2101 u_int32_t dot3StatsSingleCollisionFrames; 2102 u_int32_t dot3StatsMultipleCollisionFrames; 2103 u_int32_t dot3StatsDeferredTransmissions; 2104 u_int32_t Reserved2; 2105 u_int32_t dot3StatsExcessiveCollisions; 2106 u_int32_t dot3StatsLateCollisions; 2107 u_int32_t Reserved3[14]; 2108 u_int32_t ifHCOutUcastPkts; 2109 u_int32_t ifHCOutMulticastPkts; 2110 u_int32_t ifHCOutBroadcastPkts; 2111 u_int32_t Reserved4[2]; 2112 u_int32_t ifHCInOctets; 2113 u_int32_t Reserved5; 2114 u_int32_t etherStatsFragments; 2115 u_int32_t ifHCInUcastPkts; 2116 u_int32_t ifHCInMulticastPkts; 2117 u_int32_t ifHCInBroadcastPkts; 2118 u_int32_t dot3StatsFCSErrors; 2119 u_int32_t dot3StatsAlignmentErrors; 2120 u_int32_t xonPauseFramesReceived; 2121 u_int32_t xoffPauseFramesReceived; 2122 u_int32_t macControlFramesReceived; 2123 u_int32_t xoffStateEntered; 2124 u_int32_t dot3StatsFramesTooLong; 2125 u_int32_t etherStatsJabbers; 2126 u_int32_t etherStatsUndersizePkts; 2127}; 2128 2129struct bge_stats { 2130 u_int8_t Reserved0[256]; 2131 2132 /* Statistics maintained by Receive MAC. */ 2133 struct bge_rx_mac_stats rxstats; 2134 2135 bge_hostaddr Unused1[37]; 2136 2137 /* Statistics maintained by Transmit MAC. */ 2138 struct bge_tx_mac_stats txstats; 2139 2140 bge_hostaddr Unused2[31]; 2141 2142 /* Statistics maintained by Receive List Placement. */ 2143 bge_hostaddr COSIfHCInPkts[16]; 2144 bge_hostaddr COSFramesDroppedDueToFilters; 2145 bge_hostaddr nicDmaWriteQueueFull; 2146 bge_hostaddr nicDmaWriteHighPriQueueFull; 2147 bge_hostaddr nicNoMoreRxBDs; 2148 bge_hostaddr ifInDiscards; 2149 bge_hostaddr ifInErrors; 2150 bge_hostaddr nicRecvThresholdHit; 2151 2152 bge_hostaddr Unused3[9]; 2153 2154 /* Statistics maintained by Send Data Initiator. */ 2155 bge_hostaddr COSIfHCOutPkts[16]; 2156 bge_hostaddr nicDmaReadQueueFull; 2157 bge_hostaddr nicDmaReadHighPriQueueFull; 2158 bge_hostaddr nicSendDataCompQueueFull; 2159 2160 /* Statistics maintained by Host Coalescing. */ 2161 bge_hostaddr nicRingSetSendProdIndex; 2162 bge_hostaddr nicRingStatusUpdate; 2163 bge_hostaddr nicInterrupts; 2164 bge_hostaddr nicAvoidedInterrupts; 2165 bge_hostaddr nicSendThresholdHit; 2166 2167 u_int8_t Reserved4[320]; 2168}; 2169 2170/* 2171 * Tigon general information block. This resides in host memory 2172 * and contains the status counters, ring control blocks and 2173 * producer pointers. 2174 */ 2175 2176struct bge_gib { 2177 struct bge_stats bge_stats; 2178 struct bge_rcb bge_tx_rcb[16]; 2179 struct bge_rcb bge_std_rx_rcb; 2180 struct bge_rcb bge_jumbo_rx_rcb; 2181 struct bge_rcb bge_mini_rx_rcb; 2182 struct bge_rcb bge_return_rcb; 2183}; 2184 2185/* 2186 * NOTE! On the Alpha, we have an alignment constraint. 2187 * The first thing in the packet is a 14-byte Ethernet header. 2188 * This means that the packet is misaligned. To compensate, 2189 * we actually offset the data 2 bytes into the cluster. This 2190 * alignes the packet after the Ethernet header at a 32-bit 2191 * boundary. 2192 */ 2193 2194#define BGE_JUMBO_FRAMELEN 9018 2195#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 2196#define BGE_PAGE_SIZE PAGE_SIZE 2197#define BGE_MIN_FRAMELEN 60 2198 2199/* 2200 * Other utility macros. 2201 */ 2202#define BGE_INC(x, y) (x) = (x + 1) % y 2203 2204/* 2205 * Vital product data and structures. 2206 */ 2207#define BGE_VPD_FLAG 0x8000 2208 2209#define VPD_RES_ID 0x82 /* ID string */ 2210#define VPD_RES_READ 0x90 /* start of read only area */ 2211#define VPD_RES_WRITE 0x81 /* start of read/write area */ 2212#define VPD_RES_END 0x78 /* end tag */ 2213 2214/* 2215 * Register access macros. The Tigon always uses memory mapped register 2216 * accesses and all registers must be accessed with 32 bit operations. 2217 */ 2218 2219#define CSR_WRITE_4(sc, reg, val) \ 2220 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2221 2222#define CSR_READ_4(sc, reg) \ 2223 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2224 2225#define BGE_SETBIT(sc, reg, x) \ 2226 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2227#define BGE_CLRBIT(sc, reg, x) \ 2228 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2229 2230#define PCI_SETBIT(pc, tag, reg, x) \ 2231 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 2232#define PCI_CLRBIT(pc, tag, reg, x) \ 2233 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 2234 2235/* 2236 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2237 * values are tuneable. They control the actual amount of buffers 2238 * allocated for the standard, mini and jumbo receive rings. 2239 */ 2240 2241#define BGE_SSLOTS 256 2242#define BGE_MSLOTS 256 2243#ifdef __sparc64__ 2244#define BGE_JSLOTS 54 2245#else 2246#define BGE_JSLOTS 384 2247#endif 2248 2249#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2250#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2251 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2252#define BGE_JPAGESZ PAGE_SIZE 2253#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2254#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2255 2256/* 2257 * Ring structures. Most of these reside in host memory and we tell 2258 * the NIC where they are via the ring control blocks. The exceptions 2259 * are the tx and command rings, which live in NIC memory and which 2260 * we access via the shared memory window. 2261 */ 2262struct bge_ring_data { 2263 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2264 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2265 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2266 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2267 struct bge_status_block bge_status_block; 2268 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2269 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2270 struct bge_gib bge_info; 2271}; 2272 2273#define BGE_RING_DMA_ADDR(sc, offset) \ 2274 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2275 offsetof(struct bge_ring_data, offset)) 2276 2277/* 2278 * Number of DMA segments in a TxCB. Note that this is carefully 2279 * chosen to make the total struct size an even power of two. It's 2280 * critical that no TxCB be split across a page boundary since 2281 * no attempt is made to allocate physically contiguous memory. 2282 * 2283 */ 2284#ifdef __LP64__ 2285#define BGE_NTXSEG 30 2286#else 2287#define BGE_NTXSEG 31 2288#endif 2289 2290/* 2291 * Mbuf pointers. We need these to keep track of the virtual addresses 2292 * of our mbuf chains since we can only convert from physical to virtual, 2293 * not the other way around. 2294 */ 2295struct bge_chain_data { 2296 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2297 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2298 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2299 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2300 bus_dmamap_t bge_tx_map[BGE_TX_RING_CNT]; 2301 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2302 bus_dmamap_t bge_rx_jumbo_map; 2303 /* Stick the jumbo mem management stuff here too. */ 2304 caddr_t bge_jslots[BGE_JSLOTS]; 2305 void *bge_jumbo_buf; 2306}; 2307 2308#define BGE_JUMBO_DMA_ADDR(sc, m) \ 2309 ((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \ 2310 (mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf)) 2311 2312struct bge_type { 2313 u_int16_t bge_vid; 2314 u_int16_t bge_did; 2315 char *bge_name; 2316}; 2317 2318#define BGE_TIMEOUT 100000 2319#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2320 2321struct bge_jpool_entry { 2322 int slot; 2323 SLIST_ENTRY(bge_jpool_entry) jpool_entries; 2324}; 2325 2326struct txdmamap_pool_entry { 2327 bus_dmamap_t dmamap; 2328 SLIST_ENTRY(txdmamap_pool_entry) link; 2329}; 2330 2331/* 2332 * Flags for bge_flags. 2333 */ 2334#define BGE_TXRING_VALID 0x0001 2335#define BGE_RXRING_VALID 0x0002 2336#define BGE_JUMBO_RXRING_VALID 0x0004 2337 2338#define ASF_ENABLE 1 2339#define ASF_NEW_HANDSHAKE 2 2340#define ASF_STACKUP 4 2341 2342struct bge_softc { 2343 struct device bge_dev; 2344 struct arpcom arpcom; /* interface info */ 2345 bus_space_handle_t bge_bhandle; 2346 bus_space_tag_t bge_btag; 2347 void *bge_intrhand; 2348 struct pci_attach_args bge_pa; 2349 struct mii_data bge_mii; 2350 struct ifmedia bge_ifmedia; /* media info */ 2351 u_int8_t bge_extram; /* has external SSRAM */ 2352 u_int8_t bge_tbi; 2353 u_int8_t bge_rx_alignment_bug; 2354 bus_dma_tag_t bge_dmatag; 2355 u_int32_t bge_chipid; 2356 u_int8_t bge_no_3_led; 2357 u_int8_t bge_asf_mode; 2358 u_int8_t bge_pcie; 2359 u_int8_t bge_pcix; 2360 struct bge_ring_data *bge_rdata; /* rings */ 2361 struct bge_chain_data bge_cdata; /* mbufs */ 2362 bus_dmamap_t bge_ring_map; 2363 u_int16_t bge_tx_saved_considx; 2364 u_int16_t bge_rx_saved_considx; 2365 u_int16_t bge_ev_saved_considx; 2366 u_int16_t bge_return_ring_cnt; 2367 u_int32_t bge_tx_prodidx; 2368 u_int16_t bge_std; /* current std ring head */ 2369 u_int16_t bge_jumbo; /* current jumo ring head */ 2370 SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2371 SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2372 u_int32_t bge_stat_ticks; 2373 u_int32_t bge_rx_coal_ticks; 2374 u_int32_t bge_tx_coal_ticks; 2375 u_int32_t bge_rx_max_coal_bds; 2376 u_int32_t bge_tx_max_coal_bds; 2377 u_int32_t bge_tx_buf_ratio; 2378 int bge_if_flags; 2379 int bge_flags; 2380 int bge_txcnt; 2381 int bge_link; /* link state */ 2382 int bge_link_evt; /* pending link event */ 2383 struct timeout bge_timeout; 2384 void *sc_powerhook; 2385 void *sc_shutdownhook; 2386 u_long bge_rx_discards; 2387 u_long bge_tx_discards; 2388 u_long bge_tx_collisions; 2389 SLIST_HEAD(, txdmamap_pool_entry) txdma_list; 2390 struct txdmamap_pool_entry *txdma[BGE_TX_RING_CNT]; 2391}; 2392