if_bgereg.h revision 1.4
1/* $OpenBSD: if_bgereg.h,v 1.4 2002/04/08 21:46:23 nate Exp $ */ 2/* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bgereg.h,v 1.4 2002/04/04 06:01:31 wpaul Exp $ 35 */ 36 37/* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65#define BGE_PAGE_ZERO 0x00000000 66#define BGE_PAGE_ZERO_END 0x000000FF 67#define BGE_SEND_RING_RCB 0x00000100 68#define BGE_SEND_RING_RCB_END 0x000001FF 69#define BGE_RX_RETURN_RING_RCB 0x00000200 70#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 71#define BGE_STATS_BLOCK 0x00000300 72#define BGE_STATS_BLOCK_END 0x00000AFF 73#define BGE_STATUS_BLOCK 0x00000B00 74#define BGE_STATUS_BLOCK_END 0x00000B4F 75#define BGE_SOFTWARE_GENCOMM 0x00000B50 76#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 77#define BGE_UNMAPPED 0x00001000 78#define BGE_UNMAPPED_END 0x00001FFF 79#define BGE_DMA_DESCRIPTORS 0x00002000 80#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 81#define BGE_SEND_RING_1_TO_4 0x00004000 82#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 83 84/* Mappings for internal memory configuration */ 85#define BGE_STD_RX_RINGS 0x00006000 86#define BGE_STD_RX_RINGS_END 0x00006FFF 87#define BGE_JUMBO_RX_RINGS 0x00007000 88#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 89#define BGE_BUFFPOOL_1 0x00008000 90#define BGE_BUFFPOOL_1_END 0x0000FFFF 91#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 92#define BGE_BUFFPOOL_2_END 0x00017FFF 93#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 94#define BGE_BUFFPOOL_3_END 0x0001FFFF 95 96/* Mappings for external SSRAM configurations */ 97#define BGE_SEND_RING_5_TO_6 0x00006000 98#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 99#define BGE_SEND_RING_7_TO_8 0x00007000 100#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 101#define BGE_SEND_RING_9_TO_16 0x00008000 102#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 103#define BGE_EXT_STD_RX_RINGS 0x0000C000 104#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 105#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 106#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 107#define BGE_MINI_RX_RINGS 0x0000E000 108#define BGE_MINI_RX_RINGS_END 0x0000FFFF 109#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 110#define BGE_AVAIL_REGION1_END 0x00017FFF 111#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 112#define BGE_AVAIL_REGION2_END 0x0001FFFF 113#define BGE_EXT_SSRAM 0x00020000 114#define BGE_EXT_SSRAM_END 0x000FFFFF 115 116 117/* 118 * BCM570x register offsets. These are memory mapped registers 119 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 120 * Each register must be accessed using 32 bit operations. 121 * 122 * All registers are accessed through a 32K shared memory block. 123 * The first group of registers are actually copies of the PCI 124 * configuration space registers. 125 */ 126 127/* 128 * PCI registers defined in the PCI 2.2 spec. 129 */ 130#define BGE_PCI_VID 0x00 131#define BGE_PCI_DID 0x02 132#define BGE_PCI_CMD 0x04 133#define BGE_PCI_STS 0x06 134#define BGE_PCI_REV 0x08 135#define BGE_PCI_CLASS 0x09 136#define BGE_PCI_CACHESZ 0x0C 137#define BGE_PCI_LATTIMER 0x0D 138#define BGE_PCI_HDRTYPE 0x0E 139#define BGE_PCI_BIST 0x0F 140#define BGE_PCI_BAR0 0x10 141#define BGE_PCI_BAR1 0x14 142#define BGE_PCI_SUBSYS 0x2C 143#define BGE_PCI_SUBVID 0x2E 144#define BGE_PCI_ROMBASE 0x30 145#define BGE_PCI_CAPPTR 0x34 146#define BGE_PCI_INTLINE 0x3C 147#define BGE_PCI_INTPIN 0x3D 148#define BGE_PCI_MINGNT 0x3E 149#define BGE_PCI_MAXLAT 0x3F 150#define BGE_PCI_PCIXCAP 0x40 151#define BGE_PCI_NEXTPTR_PM 0x41 152#define BGE_PCI_PCIX_CMD 0x42 153#define BGE_PCI_PCIX_STS 0x44 154#define BGE_PCI_PWRMGMT_CAPID 0x48 155#define BGE_PCI_NEXTPTR_VPD 0x49 156#define BGE_PCI_PWRMGMT_CAPS 0x4A 157#define BGE_PCI_PWRMGMT_CMD 0x4C 158#define BGE_PCI_PWRMGMT_STS 0x4D 159#define BGE_PCI_PWRMGMT_DATA 0x4F 160#define BGE_PCI_VPD_CAPID 0x50 161#define BGE_PCI_NEXTPTR_MSI 0x51 162#define BGE_PCI_VPD_ADDR 0x52 163#define BGE_PCI_VPD_DATA 0x54 164#define BGE_PCI_MSI_CAPID 0x58 165#define BGE_PCI_NEXTPTR_NONE 0x59 166#define BGE_PCI_MSI_CTL 0x5A 167#define BGE_PCI_MSI_ADDR_HI 0x5C 168#define BGE_PCI_MSI_ADDR_LO 0x60 169#define BGE_PCI_MSI_DATA 0x64 170 171/* 172 * PCI registers specific to the BCM570x family. 173 */ 174#define BGE_PCI_MISC_CTL 0x68 175#define BGE_PCI_DMA_RW_CTL 0x6C 176#define BGE_PCI_PCISTATE 0x70 177#define BGE_PCI_CLKCTL 0x74 178#define BGE_PCI_REG_BASEADDR 0x78 179#define BGE_PCI_MEMWIN_BASEADDR 0x7C 180#define BGE_PCI_REG_DATA 0x80 181#define BGE_PCI_MEMWIN_DATA 0x84 182#define BGE_PCI_MODECTL 0x88 183#define BGE_PCI_MISC_CFG 0x8C 184#define BGE_PCI_MISC_LOCALCTL 0x90 185#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 186#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 187#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 188#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 189#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 190#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 191#define BGE_PCI_ISR_MBX_HI 0xB0 192#define BGE_PCI_ISR_MBX_LO 0xB4 193 194/* PCI Misc. Host control register */ 195#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 196#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 197#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 198#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 199#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 200#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 201#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 202#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 203#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 204 205#define BGE_BIGENDIAN_INIT \ 206 (BGE_BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \ 207 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 208 BGE_PCIMISCCTL_INDIRECT_ACCESS|PCIMISCCTL_MASK_PCI_INTR) 209 210#define BGE_LITTLEENDIAN_INIT \ 211 (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \ 212 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS) 213 214#define BGE_ASICREV_TIGON_I 0x40000000 215#define BGE_ASICREV_TIGON_II 0x60000000 216#define BGE_ASICREV_BCM5700_B0 0x71000000 217#define BGE_ASICREV_BCM5700_B1 0x71020000 218#define BGE_ASICREV_BCM5700_B2 0x71030000 219#define BGE_ASICREV_BCM5700_ALTIMA 0x71040000 220#define BGE_ASICREV_BCM5700_C0 0x72000000 221#define BGE_ASICREV_BCM5701_A0 0x00000000 /* grrrr */ 222#define BGE_ASICREV_BCM5701_B0 0x01000000 223#define BGE_ASICREV_BCM5701_B2 0x01020000 224#define BGE_ASICREV_BCM5701_B5 0x01050000 225 226/* shorthand one */ 227#define BGE_ASICREV_BCM5700 0x71000000 228 229/* PCI DMA Read/Write Control register */ 230#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 231#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 232#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 233#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 234#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 235#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 236#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 237#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 238#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 239#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 240 241#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 242#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 243#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 244#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 245#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 246#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 247#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 248#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 249 250#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 251#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 252#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 253#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 254#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 255#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 256#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 257#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 258 259/* 260 * PCI state register -- note, this register is read only 261 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 262 * register is set. 263 */ 264#define BGE_PCISTATE_FORCE_RESET 0x00000001 265#define BGE_PCISTATE_INTR_STATE 0x00000002 266#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 267#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 268#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 269#define BGE_PCISTATE_WANT_EXPROM 0x00000020 270#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 271#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 272#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 273 274/* 275 * PCI Clock Control register -- note, this register is read only 276 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 277 * register is set. 278 */ 279#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 280#define BGE_PCICLOCKCTL_M66EN 0x00000080 281#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 282#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 283#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 284#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 285#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 286#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 287#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 288#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 289 290 291#ifndef PCIM_CMD_MWIEN 292#define PCIM_CMD_MWIEN 0x0010 293#endif 294 295/* 296 * High priority mailbox registers 297 * Each mailbox is 64-bits wide, though we only use the 298 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 299 * first. The NIC will load the mailbox after the lower 32 bit word 300 * has been updated. 301 */ 302#define BGE_MBX_IRQ0_HI 0x0200 303#define BGE_MBX_IRQ0_LO 0x0204 304#define BGE_MBX_IRQ1_HI 0x0208 305#define BGE_MBX_IRQ1_LO 0x020C 306#define BGE_MBX_IRQ2_HI 0x0210 307#define BGE_MBX_IRQ2_LO 0x0214 308#define BGE_MBX_IRQ3_HI 0x0218 309#define BGE_MBX_IRQ3_LO 0x021C 310#define BGE_MBX_GEN0_HI 0x0220 311#define BGE_MBX_GEN0_LO 0x0224 312#define BGE_MBX_GEN1_HI 0x0228 313#define BGE_MBX_GEN1_LO 0x022C 314#define BGE_MBX_GEN2_HI 0x0230 315#define BGE_MBX_GEN2_LO 0x0234 316#define BGE_MBX_GEN3_HI 0x0228 317#define BGE_MBX_GEN3_LO 0x022C 318#define BGE_MBX_GEN4_HI 0x0240 319#define BGE_MBX_GEN4_LO 0x0244 320#define BGE_MBX_GEN5_HI 0x0248 321#define BGE_MBX_GEN5_LO 0x024C 322#define BGE_MBX_GEN6_HI 0x0250 323#define BGE_MBX_GEN6_LO 0x0254 324#define BGE_MBX_GEN7_HI 0x0258 325#define BGE_MBX_GEN7_LO 0x025C 326#define BGE_MBX_RELOAD_STATS_HI 0x0260 327#define BGE_MBX_RELOAD_STATS_LO 0x0264 328#define BGE_MBX_RX_STD_PROD_HI 0x0268 329#define BGE_MBX_RX_STD_PROD_LO 0x026C 330#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 331#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 332#define BGE_MBX_RX_MINI_PROD_HI 0x0278 333#define BGE_MBX_RX_MINI_PROD_LO 0x027C 334#define BGE_MBX_RX_CONS0_HI 0x0280 335#define BGE_MBX_RX_CONS0_LO 0x0284 336#define BGE_MBX_RX_CONS1_HI 0x0288 337#define BGE_MBX_RX_CONS1_LO 0x028C 338#define BGE_MBX_RX_CONS2_HI 0x0290 339#define BGE_MBX_RX_CONS2_LO 0x0294 340#define BGE_MBX_RX_CONS3_HI 0x0298 341#define BGE_MBX_RX_CONS3_LO 0x029C 342#define BGE_MBX_RX_CONS4_HI 0x02A0 343#define BGE_MBX_RX_CONS4_LO 0x02A4 344#define BGE_MBX_RX_CONS5_HI 0x02A8 345#define BGE_MBX_RX_CONS5_LO 0x02AC 346#define BGE_MBX_RX_CONS6_HI 0x02B0 347#define BGE_MBX_RX_CONS6_LO 0x02B4 348#define BGE_MBX_RX_CONS7_HI 0x02B8 349#define BGE_MBX_RX_CONS7_LO 0x02BC 350#define BGE_MBX_RX_CONS8_HI 0x02C0 351#define BGE_MBX_RX_CONS8_LO 0x02C4 352#define BGE_MBX_RX_CONS9_HI 0x02C8 353#define BGE_MBX_RX_CONS9_LO 0x02CC 354#define BGE_MBX_RX_CONS10_HI 0x02D0 355#define BGE_MBX_RX_CONS10_LO 0x02D4 356#define BGE_MBX_RX_CONS11_HI 0x02D8 357#define BGE_MBX_RX_CONS11_LO 0x02DC 358#define BGE_MBX_RX_CONS12_HI 0x02E0 359#define BGE_MBX_RX_CONS12_LO 0x02E4 360#define BGE_MBX_RX_CONS13_HI 0x02E8 361#define BGE_MBX_RX_CONS13_LO 0x02EC 362#define BGE_MBX_RX_CONS14_HI 0x02F0 363#define BGE_MBX_RX_CONS14_LO 0x02F4 364#define BGE_MBX_RX_CONS15_HI 0x02F8 365#define BGE_MBX_RX_CONS15_LO 0x02FC 366#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 367#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 368#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 369#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 370#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 371#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 372#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 373#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 374#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 375#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 376#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 377#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 378#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 379#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 380#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 381#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 382#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 383#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 384#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 385#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 386#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 387#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 388#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 389#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 390#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 391#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 392#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 393#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 394#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 395#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 396#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 397#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 398#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 399#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 400#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 401#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 402#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 403#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 404#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 405#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 406#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 407#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 408#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 409#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 410#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 411#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 412#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 413#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 414#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 415#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 416#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 417#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 418#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 419#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 420#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 421#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 422#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 423#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 424#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 425#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 426#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 427#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 428#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 429#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 430 431#define BGE_TX_RINGS_MAX 4 432#define BGE_TX_RINGS_EXTSSRAM_MAX 16 433#define BGE_RX_RINGS_MAX 16 434 435/* Ethernet MAC control registers */ 436#define BGE_MAC_MODE 0x0400 437#define BGE_MAC_STS 0x0404 438#define BGE_MAC_EVT_ENB 0x0408 439#define BGE_MAC_LED_CTL 0x040C 440#define BGE_MAC_ADDR1_LO 0x0410 441#define BGE_MAC_ADDR1_HI 0x0414 442#define BGE_MAC_ADDR2_LO 0x0418 443#define BGE_MAC_ADDR2_HI 0x041C 444#define BGE_MAC_ADDR3_LO 0x0420 445#define BGE_MAC_ADDR3_HI 0x0424 446#define BGE_MAC_ADDR4_LO 0x0428 447#define BGE_MAC_ADDR4_HI 0x042C 448#define BGE_WOL_PATPTR 0x0430 449#define BGE_WOL_PATCFG 0x0434 450#define BGE_TX_RANDOM_BACKOFF 0x0438 451#define BGE_RX_MTU 0x043C 452#define BGE_GBIT_PCS_TEST 0x0440 453#define BGE_TX_TBI_AUTONEG 0x0444 454#define BGE_RX_TBI_AUTONEG 0x0448 455#define BGE_MI_COMM 0x044C 456#define BGE_MI_STS 0x0450 457#define BGE_MI_MODE 0x0454 458#define BGE_AUTOPOLL_STS 0x0458 459#define BGE_TX_MODE 0x045C 460#define BGE_TX_STS 0x0460 461#define BGE_TX_LENGTHS 0x0464 462#define BGE_RX_MODE 0x0468 463#define BGE_RX_STS 0x046C 464#define BGE_MAR0 0x0470 465#define BGE_MAR1 0x0474 466#define BGE_MAR2 0x0478 467#define BGE_MAR3 0x047C 468#define BGE_RX_BD_RULES_CTL0 0x0480 469#define BGE_RX_BD_RULES_MASKVAL0 0x0484 470#define BGE_RX_BD_RULES_CTL1 0x0488 471#define BGE_RX_BD_RULES_MASKVAL1 0x048C 472#define BGE_RX_BD_RULES_CTL2 0x0490 473#define BGE_RX_BD_RULES_MASKVAL2 0x0494 474#define BGE_RX_BD_RULES_CTL3 0x0498 475#define BGE_RX_BD_RULES_MASKVAL3 0x049C 476#define BGE_RX_BD_RULES_CTL4 0x04A0 477#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 478#define BGE_RX_BD_RULES_CTL5 0x04A8 479#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 480#define BGE_RX_BD_RULES_CTL6 0x04B0 481#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 482#define BGE_RX_BD_RULES_CTL7 0x04B8 483#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 484#define BGE_RX_BD_RULES_CTL8 0x04C0 485#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 486#define BGE_RX_BD_RULES_CTL9 0x04C8 487#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 488#define BGE_RX_BD_RULES_CTL10 0x04D0 489#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 490#define BGE_RX_BD_RULES_CTL11 0x04D8 491#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 492#define BGE_RX_BD_RULES_CTL12 0x04E0 493#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 494#define BGE_RX_BD_RULES_CTL13 0x04E8 495#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 496#define BGE_RX_BD_RULES_CTL14 0x04F0 497#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 498#define BGE_RX_BD_RULES_CTL15 0x04F8 499#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 500#define BGE_RX_RULES_CFG 0x0500 501#define BGE_RX_STATS 0x0800 502#define BGE_TX_STATS 0x0880 503 504/* Ethernet MAC Mode register */ 505#define BGE_MACMODE_RESET 0x00000001 506#define BGE_MACMODE_HALF_DUPLEX 0x00000002 507#define BGE_MACMODE_PORTMODE 0x0000000C 508#define BGE_MACMODE_LOOPBACK 0x00000010 509#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 510#define BGE_MACMODE_TX_BURST_ENB 0x00000100 511#define BGE_MACMODE_MAX_DEFER 0x00000200 512#define BGE_MACMODE_LINK_POLARITY 0x00000400 513#define BGE_MACMODE_RX_STATS_ENB 0x00000800 514#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 515#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 516#define BGE_MACMODE_TX_STATS_ENB 0x00004000 517#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 518#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 519#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 520#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 521#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 522#define BGE_MACMODE_MIP_ENB 0x00100000 523#define BGE_MACMODE_TXDMA_ENB 0x00200000 524#define BGE_MACMODE_RXDMA_ENB 0x00400000 525#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 526 527#define BGE_PORTMODE_NONE 0x00000000 528#define BGE_PORTMODE_MII 0x00000004 529#define BGE_PORTMODE_GMII 0x00000008 530#define BGE_PORTMODE_TBI 0x0000000C 531 532/* MAC Status register */ 533#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 534#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 535#define BGE_MACSTAT_RX_CFG 0x00000004 536#define BGE_MACSTAT_CFG_CHANGED 0x00000008 537#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 538#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 539#define BGE_MACSTAT_LINK_CHANGED 0x00001000 540#define BGE_MACSTAT_MI_COMPLETE 0x00400000 541#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 542#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 543#define BGE_MACSTAT_ODI_ERROR 0x02000000 544#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 545#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 546 547/* MAC Event Enable Register */ 548#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 549#define BGE_EVTENB_LINK_CHANGED 0x00001000 550#define BGE_EVTENB_MI_COMPLETE 0x00400000 551#define BGE_EVTENB_MI_INTERRUPT 0x00800000 552#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 553#define BGE_EVTENB_ODI_ERROR 0x02000000 554#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 555#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 556 557/* LED Control Register */ 558#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 559#define BGE_LEDCTL_1000MBPS_LED 0x00000002 560#define BGE_LEDCTL_100MBPS_LED 0x00000004 561#define BGE_LEDCTL_10MBPS_LED 0x00000008 562#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 563#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 564#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 565#define BGE_LEDCTL_1000MBPS_STS 0x00000080 566#define BGE_LEDCTL_100MBPS_STS 0x00000100 567#define BGE_LEDCTL_10MBPS_STS 0x00000200 568#define BGE_LEDCTL_TRADLED_STS 0x00000400 569#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 570#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 571 572/* TX backoff seed register */ 573#define BGE_TX_BACKOFF_SEED_MASK 0x3F 574 575/* Autopoll status register */ 576#define BGE_AUTOPOLLSTS_ERROR 0x00000001 577 578/* Transmit MAC mode register */ 579#define BGE_TXMODE_RESET 0x00000001 580#define BGE_TXMODE_ENABLE 0x00000002 581#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 582#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 583#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 584 585/* Transmit MAC status register */ 586#define BGE_TXSTAT_RX_XOFFED 0x00000001 587#define BGE_TXSTAT_SENT_XOFF 0x00000002 588#define BGE_TXSTAT_SENT_XON 0x00000004 589#define BGE_TXSTAT_LINK_UP 0x00000008 590#define BGE_TXSTAT_ODI_UFLOW 0x00000010 591#define BGE_TXSTAT_ODI_OFLOW 0x00000020 592 593/* Transmit MAC lengths register */ 594#define BGE_TXLEN_SLOTTIME 0x000000FF 595#define BGE_TXLEN_IPG 0x00000F00 596#define BGE_TXLEN_CRS 0x00003000 597 598/* Receive MAC mode register */ 599#define BGE_RXMODE_RESET 0x00000001 600#define BGE_RXMODE_ENABLE 0x00000002 601#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 602#define BGE_RXMODE_RX_GIANTS 0x00000020 603#define BGE_RXMODE_RX_RUNTS 0x00000040 604#define BGE_RXMODE_8022_LENCHECK 0x00000080 605#define BGE_RXMODE_RX_PROMISC 0x00000100 606#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 607#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 608 609/* Receive MAC status register */ 610#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 611#define BGE_RXSTAT_RCVD_XOFF 0x00000002 612#define BGE_RXSTAT_RCVD_XON 0x00000004 613 614/* Receive Rules Control register */ 615#define BGE_RXRULECTL_OFFSET 0x000000FF 616#define BGE_RXRULECTL_CLASS 0x00001F00 617#define BGE_RXRULECTL_HDRTYPE 0x0000E000 618#define BGE_RXRULECTL_COMPARE_OP 0x00030000 619#define BGE_RXRULECTL_MAP 0x01000000 620#define BGE_RXRULECTL_DISCARD 0x02000000 621#define BGE_RXRULECTL_MASK 0x04000000 622#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 623#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 624#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 625#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 626 627/* Receive Rules Mask register */ 628#define BGE_RXRULEMASK_VALUE 0x0000FFFF 629#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 630 631/* MI communication register */ 632#define BGE_MICOMM_DATA 0x0000FFFF 633#define BGE_MICOMM_REG 0x001F0000 634#define BGE_MICOMM_PHY 0x03E00000 635#define BGE_MICOMM_CMD 0x0C000000 636#define BGE_MICOMM_READFAIL 0x10000000 637#define BGE_MICOMM_BUSY 0x20000000 638 639#define BGE_MIREG(x) ((x & 0x1F) << 16) 640#define BGE_MIPHY(x) ((x & 0x1F) << 21) 641#define BGE_MICMD_WRITE 0x04000000 642#define BGE_MICMD_READ 0x08000000 643 644/* MI status register */ 645#define BGE_MISTS_LINK 0x00000001 646#define BGE_MISTS_10MBPS 0x00000002 647 648#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 649#define BGE_MIMODE_AUTOPOLL 0x00000010 650#define BGE_MIMODE_CLKCNT 0x001F0000 651 652 653/* 654 * Send data initiator control registers. 655 */ 656#define BGE_SDI_MODE 0x0C00 657#define BGE_SDI_STATUS 0x0C04 658#define BGE_SDI_STATS_CTL 0x0C08 659#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 660#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 661#define BGE_LOCSTATS_COS0 0x0C80 662#define BGE_LOCSTATS_COS1 0x0C84 663#define BGE_LOCSTATS_COS2 0x0C88 664#define BGE_LOCSTATS_COS3 0x0C8C 665#define BGE_LOCSTATS_COS4 0x0C90 666#define BGE_LOCSTATS_COS5 0x0C84 667#define BGE_LOCSTATS_COS6 0x0C98 668#define BGE_LOCSTATS_COS7 0x0C9C 669#define BGE_LOCSTATS_COS8 0x0CA0 670#define BGE_LOCSTATS_COS9 0x0CA4 671#define BGE_LOCSTATS_COS10 0x0CA8 672#define BGE_LOCSTATS_COS11 0x0CAC 673#define BGE_LOCSTATS_COS12 0x0CB0 674#define BGE_LOCSTATS_COS13 0x0CB4 675#define BGE_LOCSTATS_COS14 0x0CB8 676#define BGE_LOCSTATS_COS15 0x0CBC 677#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 678#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 679#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 680#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 681#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 682#define BGE_LOCSTATS_IRQS 0x0CD4 683#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 684#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 685 686/* Send Data Initiator mode register */ 687#define BGE_SDIMODE_RESET 0x00000001 688#define BGE_SDIMODE_ENABLE 0x00000002 689#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 690 691/* Send Data Initiator stats register */ 692#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 693 694/* Send Data Initiator stats control register */ 695#define BGE_SDISTATSCTL_ENABLE 0x00000001 696#define BGE_SDISTATSCTL_FASTER 0x00000002 697#define BGE_SDISTATSCTL_CLEAR 0x00000004 698#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 699#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 700 701/* 702 * Send Data Completion Control registers 703 */ 704#define BGE_SDC_MODE 0x1000 705#define BGE_SDC_STATUS 0x1004 706 707/* Send Data completion mode register */ 708#define BGE_SDCMODE_RESET 0x00000001 709#define BGE_SDCMODE_ENABLE 0x00000002 710#define BGE_SDCMODE_ATTN 0x00000004 711 712/* Send Data completion status register */ 713#define BGE_SDCSTAT_ATTN 0x00000004 714 715/* 716 * Send BD Ring Selector Control registers 717 */ 718#define BGE_SRS_MODE 0x1400 719#define BGE_SRS_STATUS 0x1404 720#define BGE_SRS_HWDIAG 0x1408 721#define BGE_SRS_LOC_NIC_CONS0 0x1440 722#define BGE_SRS_LOC_NIC_CONS1 0x1444 723#define BGE_SRS_LOC_NIC_CONS2 0x1448 724#define BGE_SRS_LOC_NIC_CONS3 0x144C 725#define BGE_SRS_LOC_NIC_CONS4 0x1450 726#define BGE_SRS_LOC_NIC_CONS5 0x1454 727#define BGE_SRS_LOC_NIC_CONS6 0x1458 728#define BGE_SRS_LOC_NIC_CONS7 0x145C 729#define BGE_SRS_LOC_NIC_CONS8 0x1460 730#define BGE_SRS_LOC_NIC_CONS9 0x1464 731#define BGE_SRS_LOC_NIC_CONS10 0x1468 732#define BGE_SRS_LOC_NIC_CONS11 0x146C 733#define BGE_SRS_LOC_NIC_CONS12 0x1470 734#define BGE_SRS_LOC_NIC_CONS13 0x1474 735#define BGE_SRS_LOC_NIC_CONS14 0x1478 736#define BGE_SRS_LOC_NIC_CONS15 0x147C 737 738/* Send BD Ring Selector Mode register */ 739#define BGE_SRSMODE_RESET 0x00000001 740#define BGE_SRSMODE_ENABLE 0x00000002 741#define BGE_SRSMODE_ATTN 0x00000004 742 743/* Send BD Ring Selector Status register */ 744#define BGE_SRSSTAT_ERROR 0x00000004 745 746/* Send BD Ring Selector HW Diagnostics register */ 747#define BGE_SRSHWDIAG_STATE 0x0000000F 748#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 749#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 750#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 751 752/* 753 * Send BD Initiator Selector Control registers 754 */ 755#define BGE_SBDI_MODE 0x1800 756#define BGE_SBDI_STATUS 0x1804 757#define BGE_SBDI_LOC_NIC_PROD0 0x1808 758#define BGE_SBDI_LOC_NIC_PROD1 0x180C 759#define BGE_SBDI_LOC_NIC_PROD2 0x1810 760#define BGE_SBDI_LOC_NIC_PROD3 0x1814 761#define BGE_SBDI_LOC_NIC_PROD4 0x1818 762#define BGE_SBDI_LOC_NIC_PROD5 0x181C 763#define BGE_SBDI_LOC_NIC_PROD6 0x1820 764#define BGE_SBDI_LOC_NIC_PROD7 0x1824 765#define BGE_SBDI_LOC_NIC_PROD8 0x1828 766#define BGE_SBDI_LOC_NIC_PROD9 0x182C 767#define BGE_SBDI_LOC_NIC_PROD10 0x1830 768#define BGE_SBDI_LOC_NIC_PROD11 0x1834 769#define BGE_SBDI_LOC_NIC_PROD12 0x1838 770#define BGE_SBDI_LOC_NIC_PROD13 0x183C 771#define BGE_SBDI_LOC_NIC_PROD14 0x1840 772#define BGE_SBDI_LOC_NIC_PROD15 0x1844 773 774/* Send BD Initiator Mode register */ 775#define BGE_SBDIMODE_RESET 0x00000001 776#define BGE_SBDIMODE_ENABLE 0x00000002 777#define BGE_SBDIMODE_ATTN 0x00000004 778 779/* Send BD Initiator Status register */ 780#define BGE_SBDISTAT_ERROR 0x00000004 781 782/* 783 * Send BD Completion Control registers 784 */ 785#define BGE_SBDC_MODE 0x1C00 786#define BGE_SBDC_STATUS 0x1C04 787 788/* Send BD Completion Control Mode register */ 789#define BGE_SBDCMODE_RESET 0x00000001 790#define BGE_SBDCMODE_ENABLE 0x00000002 791#define BGE_SBDCMODE_ATTN 0x00000004 792 793/* Send BD Completion Control Status register */ 794#define BGE_SBDCSTAT_ATTN 0x00000004 795 796/* 797 * Receive List Placement Control registers 798 */ 799#define BGE_RXLP_MODE 0x2000 800#define BGE_RXLP_STATUS 0x2004 801#define BGE_RXLP_SEL_LIST_LOCK 0x2008 802#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 803#define BGE_RXLP_CFG 0x2010 804#define BGE_RXLP_STATS_CTL 0x2014 805#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 806#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 807#define BGE_RXLP_HEAD0 0x2100 808#define BGE_RXLP_TAIL0 0x2104 809#define BGE_RXLP_COUNT0 0x2108 810#define BGE_RXLP_HEAD1 0x2110 811#define BGE_RXLP_TAIL1 0x2114 812#define BGE_RXLP_COUNT1 0x2118 813#define BGE_RXLP_HEAD2 0x2120 814#define BGE_RXLP_TAIL2 0x2124 815#define BGE_RXLP_COUNT2 0x2128 816#define BGE_RXLP_HEAD3 0x2130 817#define BGE_RXLP_TAIL3 0x2134 818#define BGE_RXLP_COUNT3 0x2138 819#define BGE_RXLP_HEAD4 0x2140 820#define BGE_RXLP_TAIL4 0x2144 821#define BGE_RXLP_COUNT4 0x2148 822#define BGE_RXLP_HEAD5 0x2150 823#define BGE_RXLP_TAIL5 0x2154 824#define BGE_RXLP_COUNT5 0x2158 825#define BGE_RXLP_HEAD6 0x2160 826#define BGE_RXLP_TAIL6 0x2164 827#define BGE_RXLP_COUNT6 0x2168 828#define BGE_RXLP_HEAD7 0x2170 829#define BGE_RXLP_TAIL7 0x2174 830#define BGE_RXLP_COUNT7 0x2178 831#define BGE_RXLP_HEAD8 0x2180 832#define BGE_RXLP_TAIL8 0x2184 833#define BGE_RXLP_COUNT8 0x2188 834#define BGE_RXLP_HEAD9 0x2190 835#define BGE_RXLP_TAIL9 0x2194 836#define BGE_RXLP_COUNT9 0x2198 837#define BGE_RXLP_HEAD10 0x21A0 838#define BGE_RXLP_TAIL10 0x21A4 839#define BGE_RXLP_COUNT10 0x21A8 840#define BGE_RXLP_HEAD11 0x21B0 841#define BGE_RXLP_TAIL11 0x21B4 842#define BGE_RXLP_COUNT11 0x21B8 843#define BGE_RXLP_HEAD12 0x21C0 844#define BGE_RXLP_TAIL12 0x21C4 845#define BGE_RXLP_COUNT12 0x21C8 846#define BGE_RXLP_HEAD13 0x21D0 847#define BGE_RXLP_TAIL13 0x21D4 848#define BGE_RXLP_COUNT13 0x21D8 849#define BGE_RXLP_HEAD14 0x21E0 850#define BGE_RXLP_TAIL14 0x21E4 851#define BGE_RXLP_COUNT14 0x21E8 852#define BGE_RXLP_HEAD15 0x21F0 853#define BGE_RXLP_TAIL15 0x21F4 854#define BGE_RXLP_COUNT15 0x21F8 855#define BGE_RXLP_LOCSTAT_COS0 0x2200 856#define BGE_RXLP_LOCSTAT_COS1 0x2204 857#define BGE_RXLP_LOCSTAT_COS2 0x2208 858#define BGE_RXLP_LOCSTAT_COS3 0x220C 859#define BGE_RXLP_LOCSTAT_COS4 0x2210 860#define BGE_RXLP_LOCSTAT_COS5 0x2214 861#define BGE_RXLP_LOCSTAT_COS6 0x2218 862#define BGE_RXLP_LOCSTAT_COS7 0x221C 863#define BGE_RXLP_LOCSTAT_COS8 0x2220 864#define BGE_RXLP_LOCSTAT_COS9 0x2224 865#define BGE_RXLP_LOCSTAT_COS10 0x2228 866#define BGE_RXLP_LOCSTAT_COS11 0x222C 867#define BGE_RXLP_LOCSTAT_COS12 0x2230 868#define BGE_RXLP_LOCSTAT_COS13 0x2234 869#define BGE_RXLP_LOCSTAT_COS14 0x2238 870#define BGE_RXLP_LOCSTAT_COS15 0x223C 871#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 872#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 873#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 874#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 875#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 876#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 877#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 878 879 880/* Receive List Placement mode register */ 881#define BGE_RXLPMODE_RESET 0x00000001 882#define BGE_RXLPMODE_ENABLE 0x00000002 883#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 884#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 885#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 886 887/* Receive List Placement Status register */ 888#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 889#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 890#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 891 892/* 893 * Receive Data and Receive BD Initiator Control Registers 894 */ 895#define BGE_RDBDI_MODE 0x2400 896#define BGE_RDBDI_STATUS 0x2404 897#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 898#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 899#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 900#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 901#define BGE_RX_STD_RCB_HADDR_HI 0x2450 902#define BGE_RX_STD_RCB_HADDR_LO 0x2454 903#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 904#define BGE_RX_STD_RCB_NICADDR 0x245C 905#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 906#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 907#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 908#define BGE_RX_MINI_RCB_NICADDR 0x246C 909#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 910#define BGE_RDBDI_STD_RX_CONS 0x2474 911#define BGE_RDBDI_MINI_RX_CONS 0x2478 912#define BGE_RDBDI_RETURN_PROD0 0x2480 913#define BGE_RDBDI_RETURN_PROD1 0x2484 914#define BGE_RDBDI_RETURN_PROD2 0x2488 915#define BGE_RDBDI_RETURN_PROD3 0x248C 916#define BGE_RDBDI_RETURN_PROD4 0x2490 917#define BGE_RDBDI_RETURN_PROD5 0x2494 918#define BGE_RDBDI_RETURN_PROD6 0x2498 919#define BGE_RDBDI_RETURN_PROD7 0x249C 920#define BGE_RDBDI_RETURN_PROD8 0x24A0 921#define BGE_RDBDI_RETURN_PROD9 0x24A4 922#define BGE_RDBDI_RETURN_PROD10 0x24A8 923#define BGE_RDBDI_RETURN_PROD11 0x24AC 924#define BGE_RDBDI_RETURN_PROD12 0x24B0 925#define BGE_RDBDI_RETURN_PROD13 0x24B4 926#define BGE_RDBDI_RETURN_PROD14 0x24B8 927#define BGE_RDBDI_RETURN_PROD15 0x24BC 928#define BGE_RDBDI_HWDIAG 0x24C0 929 930 931/* Receive Data and Receive BD Initiator Mode register */ 932#define BGE_RDBDIMODE_RESET 0x00000001 933#define BGE_RDBDIMODE_ENABLE 0x00000002 934#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 935#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 936#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 937 938/* Receive Data and Receive BD Initiator Status register */ 939#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 940#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 941#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 942 943 944/* 945 * Receive Data Completion Control registers 946 */ 947#define BGE_RDC_MODE 0x2800 948 949/* Receive Data Completion Mode register */ 950#define BGE_RDCMODE_RESET 0x00000001 951#define BGE_RDCMODE_ENABLE 0x00000002 952#define BGE_RDCMODE_ATTN 0x00000004 953 954/* 955 * Receive BD Initiator Control registers 956 */ 957#define BGE_RBDI_MODE 0x2C00 958#define BGE_RBDI_STATUS 0x2C04 959#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 960#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 961#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 962#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 963#define BGE_RBDI_STD_REPL_THRESH 0x2C18 964#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 965 966/* Receive BD Initiator Mode register */ 967#define BGE_RBDIMODE_RESET 0x00000001 968#define BGE_RBDIMODE_ENABLE 0x00000002 969#define BGE_RBDIMODE_ATTN 0x00000004 970 971/* Receive BD Initiator Status register */ 972#define BGE_RBDISTAT_ATTN 0x00000004 973 974/* 975 * Receive BD Completion Control registers 976 */ 977#define BGE_RBDC_MODE 0x3000 978#define BGE_RBDC_STATUS 0x3004 979#define BGE_RBDC_JUMBO_BD_PROD 0x3008 980#define BGE_RBDC_STD_BD_PROD 0x300C 981#define BGE_RBDC_MINI_BD_PROD 0x3010 982 983/* Receive BD completion mode register */ 984#define BGE_RBDCMODE_RESET 0x00000001 985#define BGE_RBDCMODE_ENABLE 0x00000002 986#define BGE_RBDCMODE_ATTN 0x00000004 987 988/* Receive BD completion status register */ 989#define BGE_RBDCSTAT_ERROR 0x00000004 990 991/* 992 * Receive List Selector Control registers 993 */ 994#define BGE_RXLS_MODE 0x3400 995#define BGE_RXLS_STATUS 0x3404 996 997/* Receive List Selector Mode register */ 998#define BGE_RXLSMODE_RESET 0x00000001 999#define BGE_RXLSMODE_ENABLE 0x00000002 1000#define BGE_RXLSMODE_ATTN 0x00000004 1001 1002/* Receive List Selector Status register */ 1003#define BGE_RXLSSTAT_ERROR 0x00000004 1004 1005/* 1006 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1007 */ 1008#define BGE_MBCF_MODE 0x3800 1009#define BGE_MBCF_STATUS 0x3804 1010 1011/* Mbuf Cluster Free mode register */ 1012#define BGE_MBCFMODE_RESET 0x00000001 1013#define BGE_MBCFMODE_ENABLE 0x00000002 1014#define BGE_MBCFMODE_ATTN 0x00000004 1015 1016/* Mbuf Cluster Free status register */ 1017#define BGE_MBCFSTAT_ERROR 0x00000004 1018 1019/* 1020 * Host Coalescing Control registers 1021 */ 1022#define BGE_HCC_MODE 0x3C00 1023#define BGE_HCC_STATUS 0x3C04 1024#define BGE_HCC_RX_COAL_TICKS 0x3C08 1025#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1026#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1027#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1028#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1029#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1030#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1031#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C34 /* BDs during interrupt */ 1032#define BGE_HCC_STATS_TICKS 0x3C28 1033#define BGE_HCC_STATS_ADDR_HI 0x3C30 1034#define BGE_HCC_STATS_ADDR_LO 0x3C34 1035#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1036#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1037#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1038#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1039#define BGE_FLOW_ATTN 0x3C48 1040#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1041#define BGE_HCC_STD_BD_CONS 0x3C54 1042#define BGE_HCC_MINI_BD_CONS 0x3C58 1043#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1044#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1045#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1046#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1047#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1048#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1049#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1050#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1051#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1052#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1053#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1054#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1055#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1056#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1057#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1058#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1059#define BGE_HCC_TX_BD_CONS0 0x3CC0 1060#define BGE_HCC_TX_BD_CONS1 0x3CC4 1061#define BGE_HCC_TX_BD_CONS2 0x3CC8 1062#define BGE_HCC_TX_BD_CONS3 0x3CCC 1063#define BGE_HCC_TX_BD_CONS4 0x3CD0 1064#define BGE_HCC_TX_BD_CONS5 0x3CD4 1065#define BGE_HCC_TX_BD_CONS6 0x3CD8 1066#define BGE_HCC_TX_BD_CONS7 0x3CDC 1067#define BGE_HCC_TX_BD_CONS8 0x3CE0 1068#define BGE_HCC_TX_BD_CONS9 0x3CE4 1069#define BGE_HCC_TX_BD_CONS10 0x3CE8 1070#define BGE_HCC_TX_BD_CONS11 0x3CEC 1071#define BGE_HCC_TX_BD_CONS12 0x3CF0 1072#define BGE_HCC_TX_BD_CONS13 0x3CF4 1073#define BGE_HCC_TX_BD_CONS14 0x3CF8 1074#define BGE_HCC_TX_BD_CONS15 0x3CFC 1075 1076 1077/* Host coalescing mode register */ 1078#define BGE_HCCMODE_RESET 0x00000001 1079#define BGE_HCCMODE_ENABLE 0x00000002 1080#define BGE_HCCMODE_ATTN 0x00000004 1081#define BGE_HCCMODE_COAL_NOW 0x00000008 1082#define BGE_HCCMODE_MSI_BITS 0x0x000070 1083#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1084 1085#define BGE_STATBLKSZ_FULL 0x00000000 1086#define BGE_STATBLKSZ_64BYTE 0x00000080 1087#define BGE_STATBLKSZ_32BYTE 0x00000100 1088 1089/* Host coalescing status register */ 1090#define BGE_HCCSTAT_ERROR 0x00000004 1091 1092/* Flow attention register */ 1093#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1094#define BGE_FLOWATTN_MEMARB 0x00000080 1095#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1096#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1097#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1098#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1099#define BGE_FLOWATTN_RDBDI 0x00080000 1100#define BGE_FLOWATTN_RXLS 0x00100000 1101#define BGE_FLOWATTN_RXLP 0x00200000 1102#define BGE_FLOWATTN_RBDC 0x00400000 1103#define BGE_FLOWATTN_RBDI 0x00800000 1104#define BGE_FLOWATTN_SDC 0x08000000 1105#define BGE_FLOWATTN_SDI 0x10000000 1106#define BGE_FLOWATTN_SRS 0x20000000 1107#define BGE_FLOWATTN_SBDC 0x40000000 1108#define BGE_FLOWATTN_SBDI 0x80000000 1109 1110/* 1111 * Memory arbiter registers 1112 */ 1113#define BGE_MARB_MODE 0x4000 1114#define BGE_MARB_STATUS 0x4004 1115#define BGE_MARB_TRAPADDR_HI 0x4008 1116#define BGE_MARB_TRAPADDR_LO 0x400C 1117 1118/* Memory arbiter mode register */ 1119#define BGE_MARBMODE_RESET 0x00000001 1120#define BGE_MARBMODE_ENABLE 0x00000002 1121#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1122#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1123#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1124#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1125#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1126#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1127#define BGE_MARBMODE_PCI_TRAP 0x00000100 1128#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1129#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1130#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1131#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1132#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1133#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1134#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1135#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1136#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1137#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1138#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1139#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1140#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1141#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1142#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1143#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1144#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1145 1146/* Memory arbiter status register */ 1147#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1148#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1149#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1150#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1151#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1152#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1153#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1154#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1155#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1156#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1157#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1158#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1159#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1160#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1161#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1162#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1163#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1164#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1165#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1166#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1167#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1168#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1169#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1170#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1171 1172/* 1173 * Buffer manager control registers 1174 */ 1175#define BGE_BMAN_MODE 0x4400 1176#define BGE_BMAN_STATUS 0x4404 1177#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1178#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1179#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1180#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1181#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1182#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1183#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1184#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1185#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1186#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1187#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1188#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1189#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1190#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1191#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1192#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1193#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1194#define BGE_BMAN_HWDIAG_1 0x444C 1195#define BGE_BMAN_HWDIAG_2 0x4450 1196#define BGE_BMAN_HWDIAG_3 0x4454 1197 1198/* Buffer manager mode register */ 1199#define BGE_BMANMODE_RESET 0x00000001 1200#define BGE_BMANMODE_ENABLE 0x00000002 1201#define BGE_BMANMODE_ATTN 0x00000004 1202#define BGE_BMANMODE_TESTMODE 0x00000008 1203#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1204 1205/* Buffer manager status register */ 1206#define BGE_BMANSTAT_ERRO 0x00000004 1207#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1208 1209 1210/* 1211 * Read DMA Control registers 1212 */ 1213#define BGE_RDMA_MODE 0x4800 1214#define BGE_RDMA_STATUS 0x4804 1215 1216/* Read DMA mode register */ 1217#define BGE_RDMAMODE_RESET 0x00000001 1218#define BGE_RDMAMODE_ENABLE 0x00000002 1219#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1220#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1221#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1222#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1223#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1224#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1225#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1226#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1227#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1228 1229/* Read DMA status register */ 1230#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1231#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1232#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1233#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1234#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1235#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1236#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1237#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1238 1239/* 1240 * Write DMA control registers 1241 */ 1242#define BGE_WDMA_MODE 0x4C00 1243#define BGE_WDMA_STATUS 0x4C04 1244 1245/* Write DMA mode register */ 1246#define BGE_WDMAMODE_RESET 0x00000001 1247#define BGE_WDMAMODE_ENABLE 0x00000002 1248#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1249#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1250#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1251#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1252#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1253#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1254#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1255#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1256#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1257 1258/* Write DMA status register */ 1259#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1260#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1261#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1262#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1263#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1264#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1265#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1266#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1267 1268 1269/* 1270 * RX CPU registers 1271 */ 1272#define BGE_RXCPU_MODE 0x5000 1273#define BGE_RXCPU_STATUS 0x5004 1274#define BGE_RXCPU_PC 0x501C 1275 1276/* RX CPU mode register */ 1277#define BGE_RXCPUMODE_RESET 0x00000001 1278#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1279#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1280#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1281#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1282#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1283#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1284#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1285#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1286#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1287#define BGE_RXCPUMODE_HALTCPU 0x00000400 1288#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1289#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1290#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1291 1292/* RX CPU status register */ 1293#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1294#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1295#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1296#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1297#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1298#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1299#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1300#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1301#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1302#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1303#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1304#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1305#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1306#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1307#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1308#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1309#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1310 1311 1312/* 1313 * TX CPU registers 1314 */ 1315#define BGE_TXCPU_MODE 0x5400 1316#define BGE_TXCPU_STATUS 0x5404 1317#define BGE_TXCPU_PC 0x541C 1318 1319/* TX CPU mode register */ 1320#define BGE_TXCPUMODE_RESET 0x00000001 1321#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1322#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1323#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1324#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1325#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1326#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1327#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1328#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1329#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1330#define BGE_TXCPUMODE_HALTCPU 0x00000400 1331#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1332#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1333 1334/* TX CPU status register */ 1335#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1336#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1337#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1338#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1339#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1340#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1341#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1342#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1343#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1344#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1345#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1346#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1347#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1348#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1349#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1350#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1351#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1352 1353 1354/* 1355 * Low priority mailbox registers 1356 */ 1357#define BGE_LPMBX_IRQ0_HI 0x5800 1358#define BGE_LPMBX_IRQ0_LO 0x5804 1359#define BGE_LPMBX_IRQ1_HI 0x5808 1360#define BGE_LPMBX_IRQ1_LO 0x580C 1361#define BGE_LPMBX_IRQ2_HI 0x5810 1362#define BGE_LPMBX_IRQ2_LO 0x5814 1363#define BGE_LPMBX_IRQ3_HI 0x5818 1364#define BGE_LPMBX_IRQ3_LO 0x581C 1365#define BGE_LPMBX_GEN0_HI 0x5820 1366#define BGE_LPMBX_GEN0_LO 0x5824 1367#define BGE_LPMBX_GEN1_HI 0x5828 1368#define BGE_LPMBX_GEN1_LO 0x582C 1369#define BGE_LPMBX_GEN2_HI 0x5830 1370#define BGE_LPMBX_GEN2_LO 0x5834 1371#define BGE_LPMBX_GEN3_HI 0x5828 1372#define BGE_LPMBX_GEN3_LO 0x582C 1373#define BGE_LPMBX_GEN4_HI 0x5840 1374#define BGE_LPMBX_GEN4_LO 0x5844 1375#define BGE_LPMBX_GEN5_HI 0x5848 1376#define BGE_LPMBX_GEN5_LO 0x584C 1377#define BGE_LPMBX_GEN6_HI 0x5850 1378#define BGE_LPMBX_GEN6_LO 0x5854 1379#define BGE_LPMBX_GEN7_HI 0x5858 1380#define BGE_LPMBX_GEN7_LO 0x585C 1381#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1382#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1383#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1384#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1385#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1386#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1387#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1388#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1389#define BGE_LPMBX_RX_CONS0_HI 0x5880 1390#define BGE_LPMBX_RX_CONS0_LO 0x5884 1391#define BGE_LPMBX_RX_CONS1_HI 0x5888 1392#define BGE_LPMBX_RX_CONS1_LO 0x588C 1393#define BGE_LPMBX_RX_CONS2_HI 0x5890 1394#define BGE_LPMBX_RX_CONS2_LO 0x5894 1395#define BGE_LPMBX_RX_CONS3_HI 0x5898 1396#define BGE_LPMBX_RX_CONS3_LO 0x589C 1397#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1398#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1399#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1400#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1401#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1402#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1403#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1404#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1405#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1406#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1407#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1408#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1409#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1410#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1411#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1412#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1413#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1414#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1415#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1416#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1417#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1418#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1419#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1420#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1421#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1422#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1423#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1424#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1425#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1426#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1427#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1428#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1429#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1430#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1431#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1432#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1433#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1434#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1435#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1436#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1437#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1438#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1439#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1440#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1441#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1442#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1443#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1444#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1445#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1446#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1447#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1448#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1449#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1450#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1451#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1452#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1453#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1454#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1455#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1456#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1457#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1458#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1459#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1460#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1461#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1462#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1463#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1464#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1465#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1466#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1467#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1468#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1469#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1470#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1471#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1472#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1473#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1474#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1475#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1476#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1477#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1478#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1479#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1480#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1481#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1482#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1483#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1484#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1485 1486/* 1487 * Flow throw Queue reset register 1488 */ 1489#define BGE_FTQ_RESET 0x5C00 1490 1491#define BGE_FTQRESET_DMAREAD 0x00000002 1492#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1493#define BGE_FTQRESET_DMADONE 0x00000010 1494#define BGE_FTQRESET_SBDC 0x00000020 1495#define BGE_FTQRESET_SDI 0x00000040 1496#define BGE_FTQRESET_WDMA 0x00000080 1497#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1498#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1499#define BGE_FTQRESET_SDC 0x00000400 1500#define BGE_FTQRESET_HCC 0x00000800 1501#define BGE_FTQRESET_TXFIFO 0x00001000 1502#define BGE_FTQRESET_MBC 0x00002000 1503#define BGE_FTQRESET_RBDC 0x00004000 1504#define BGE_FTQRESET_RXLP 0x00008000 1505#define BGE_FTQRESET_RDBDI 0x00010000 1506#define BGE_FTQRESET_RDC 0x00020000 1507#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1508 1509/* 1510 * Message Signaled Interrupt registers 1511 */ 1512#define BGE_MSI_MODE 0x6000 1513#define BGE_MSI_STATUS 0x6004 1514#define BGE_MSI_FIFOACCESS 0x6008 1515 1516/* MSI mode register */ 1517#define BGE_MSIMODE_RESET 0x00000001 1518#define BGE_MSIMODE_ENABLE 0x00000002 1519#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1520#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1521#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1522#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1523#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1524 1525/* MSI status register */ 1526#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1527#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1528#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1529#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1530#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1531 1532 1533/* 1534 * DMA Completion registers 1535 */ 1536#define BGE_DMAC_MODE 0x6400 1537 1538/* DMA Completion mode register */ 1539#define BGE_DMACMODE_RESET 0x00000001 1540#define BGE_DMACMODE_ENABLE 0x00000002 1541 1542 1543/* 1544 * General control registers. 1545 */ 1546#define BGE_MODE_CTL 0x6800 1547#define BGE_MISC_CFG 0x6804 1548#define BGE_MISC_LOCAL_CTL 0x6808 1549#define BGE_EE_ADDR 0x6838 1550#define BGE_EE_DATA 0x683C 1551#define BGE_EE_CTL 0x6840 1552#define BGE_MDI_CTL 0x6844 1553#define BGE_EE_DELAY 0x6848 1554 1555/* Mode control register */ 1556#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1557#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1558#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1559#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1560#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1561#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1562#define BGE_MODECTL_NO_RX_CRC 0x00000400 1563#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1564#define BGE_MODECTL_NO_TX_INTR 0x00002000 1565#define BGE_MODECTL_NO_RX_INTR 0x00004000 1566#define BGE_MODECTL_FORCE_PCI32 0x00008000 1567#define BGE_MODECTL_STACKUP 0x00010000 1568#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1569#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1570#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1571#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1572#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1573#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1574#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1575#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1576#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1577#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1578 1579/* Misc. config register */ 1580#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1581#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1582 1583#define BGE_32BITTIME_66MHZ (0x41 << 1) 1584 1585/* Misc. Local Control */ 1586#define BGE_MLC_INTR_STATE 0x00000001 1587#define BGE_MLC_INTR_CLR 0x00000002 1588#define BGE_MLC_INTR_SET 0x00000004 1589#define BGE_MLC_INTR_ONATTN 0x00000008 1590#define BGE_MLC_MISCIO_IN0 0x00000100 1591#define BGE_MLC_MISCIO_IN1 0x00000200 1592#define BGE_MLC_MISCIO_IN2 0x00000400 1593#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1594#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1595#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1596#define BGE_MLC_MISCIO_OUT0 0x00004000 1597#define BGE_MLC_MISCIO_OUT1 0x00008000 1598#define BGE_MLC_MISCIO_OUT2 0x00010000 1599#define BGE_MLC_EXTRAM_ENB 0x00020000 1600#define BGE_MLC_SRAM_SIZE 0x001C0000 1601#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1602#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1603#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1604#define BGE_MLC_AUTO_EEPROM 0x01000000 1605 1606#define BGE_SSRAMSIZE_256KB 0x00000000 1607#define BGE_SSRAMSIZE_512KB 0x00040000 1608#define BGE_SSRAMSIZE_1MB 0x00080000 1609#define BGE_SSRAMSIZE_2MB 0x000C0000 1610#define BGE_SSRAMSIZE_4MB 0x00100000 1611#define BGE_SSRAMSIZE_8MB 0x00140000 1612#define BGE_SSRAMSIZE_16M 0x00180000 1613 1614/* EEPROM address register */ 1615#define BGE_EEADDR_ADDRESS 0x0000FFFC 1616#define BGE_EEADDR_HALFCLK 0x01FF0000 1617#define BGE_EEADDR_START 0x02000000 1618#define BGE_EEADDR_DEVID 0x1C000000 1619#define BGE_EEADDR_RESET 0x20000000 1620#define BGE_EEADDR_DONE 0x40000000 1621#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1622 1623#define BGE_EEDEVID(x) ((x & 7) << 26) 1624#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1625#define BGE_HALFCLK_384SCL 0x60 1626#define BGE_EE_READCMD \ 1627 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1628 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1629#define BGE_EE_WRCMD \ 1630 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1631 BGE_EEADDR_START|BGE_EEADDR_DONE) 1632 1633/* EEPROM Control register */ 1634#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1635#define BGE_EECTL_CLKOUT 0x00000002 1636#define BGE_EECTL_CLKIN 0x00000004 1637#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1638#define BGE_EECTL_DATAOUT 0x00000010 1639#define BGE_EECTL_DATAIN 0x00000020 1640 1641/* MDI (MII/GMII) access register */ 1642#define BGE_MDI_DATA 0x00000001 1643#define BGE_MDI_DIR 0x00000002 1644#define BGE_MDI_SEL 0x00000004 1645#define BGE_MDI_CLK 0x00000008 1646 1647#define BGE_MEMWIN_START 0x00008000 1648#define BGE_MEMWIN_END 0x0000FFFF 1649 1650 1651#define BGE_MEMWIN_READ(pc, tag, x, val) \ 1652 do { \ 1653 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1654 (0xFFFF0000 & x)); \ 1655 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1656 } while(0) 1657 1658#define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 1659 do { \ 1660 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1661 (0xFFFF0000 & x)); \ 1662 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1663 } while(0) 1664 1665/* 1666 * This magic number is used to prevent PXE restart when we 1667 * issue a software reset. We write this magic number to the 1668 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1669 * code from running. 1670 */ 1671#define BGE_MAGIC_NUMBER 0x4B657654 1672 1673typedef struct { 1674 u_int32_t bge_addr_hi; 1675 u_int32_t bge_addr_lo; 1676} bge_hostaddr; 1677#define BGE_HOSTADDR(x) x.bge_addr_lo 1678 1679/* Ring control block structure */ 1680struct bge_rcb { 1681 bge_hostaddr bge_hostaddr; 1682 u_int16_t bge_flags; 1683 u_int16_t bge_max_len; 1684 u_int32_t bge_nicaddr; 1685}; 1686 1687#define RCB_WRITE_4(sc, rcb, offset, val) \ 1688 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1689 rcb + offsetof(struct bge_rcb, offset), val) 1690 1691#define RCB_WRITE_2(sc, rcb, offset, val) \ 1692 bus_space_write_2(sc->bge_btag, sc->bge_bhandle, \ 1693 rcb + offsetof(struct bge_rcb, offset), val) 1694 1695struct bge_rcb_opaque { 1696 u_int32_t bge_reg0; 1697 u_int32_t bge_reg1; 1698 u_int32_t bge_reg2; 1699 u_int32_t bge_reg3; 1700}; 1701 1702#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1703#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1704 1705struct bge_tx_bd { 1706 bge_hostaddr bge_addr; 1707 u_int16_t bge_flags; 1708 u_int16_t bge_len; 1709 u_int16_t bge_vlan_tag; 1710 u_int16_t bge_rsvd; 1711}; 1712 1713#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1714#define BGE_TXBDFLAG_IP_CSUM 0x0002 1715#define BGE_TXBDFLAG_END 0x0004 1716#define BGE_TXBDFLAG_IP_FRAG 0x0008 1717#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1718#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1719#define BGE_TXBDFLAG_COAL_NOW 0x0080 1720#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1721#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1722#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1723#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1724#define BGE_TXBDFLAG_NO_CRC 0x8000 1725 1726#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1727 BGE_SEND_RING_1_TO_4 + \ 1728 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1729 1730struct bge_rx_bd { 1731 bge_hostaddr bge_addr; 1732 u_int16_t bge_len; 1733 u_int16_t bge_idx; 1734 u_int16_t bge_flags; 1735 u_int16_t bge_type; 1736 u_int16_t bge_tcp_udp_csum; 1737 u_int16_t bge_ip_csum; 1738 u_int16_t bge_vlan_tag; 1739 u_int16_t bge_error_flag; 1740 u_int32_t bge_rsvd; 1741 u_int32_t bge_opaque; 1742}; 1743 1744#define BGE_RXBDFLAG_END 0x0004 1745#define BGE_RXBDFLAG_JUMBO_RING 0x0020 1746#define BGE_RXBDFLAG_VLAN_TAG 0x0040 1747#define BGE_RXBDFLAG_ERROR 0x0400 1748#define BGE_RXBDFLAG_MINI_RING 0x0800 1749#define BGE_RXBDFLAG_IP_CSUM 0x1000 1750#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1751#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1752 1753#define BGE_RXERRFLAG_BAD_CRC 0x0001 1754#define BGE_RXERRFLAG_COLL_DETECT 0x0002 1755#define BGE_RXERRFLAG_LINK_LOST 0x0004 1756#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1757#define BGE_RXERRFLAG_MAC_ABORT 0x0010 1758#define BGE_RXERRFLAG_RUNT 0x0020 1759#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1760#define BGE_RXERRFLAG_GIANT 0x0080 1761 1762struct bge_sts_idx { 1763 u_int16_t bge_rx_prod_idx; 1764 u_int16_t bge_tx_cons_idx; 1765}; 1766 1767struct bge_status_block { 1768 u_int32_t bge_status; 1769 u_int32_t bge_rsvd0; 1770 u_int16_t bge_rx_jumbo_cons_idx; 1771 u_int16_t bge_rx_std_cons_idx; 1772 u_int16_t bge_rx_mini_cons_idx; 1773 u_int16_t bge_rsvd1; 1774 struct bge_sts_idx bge_idx[16]; 1775}; 1776 1777#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1778#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1779 1780#define BGE_STATFLAG_UPDATED 0x00000001 1781#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1782#define BGE_STATFLAG_ERROR 0x00000004 1783 1784 1785/* 1786 * Broadcom Vendor ID 1787 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 1788 * even though they're now manufactured by Broadcom) 1789 */ 1790#define BCOM_VENDORID 0x14E4 1791#define BCOM_DEVICEID_BCM5700 0x1644 1792#define BCOM_DEVICEID_BCM5701 0x1645 1793 1794/* 1795 * Alteon AceNIC PCI vendor/device ID. 1796 */ 1797#define ALT_VENDORID 0x12AE 1798#define ALT_DEVICEID_ACENIC 0x0001 1799#define ALT_DEVICEID_ACENIC_COPPER 0x0002 1800#define ALT_DEVICEID_BCM5700 0x0003 1801#define ALT_DEVICEID_BCM5701 0x0004 1802 1803/* 1804 * 3Com 3c985 PCI vendor/device ID. 1805 */ 1806#define TC_VENDORID 0x10B7 1807#define TC_DEVICEID_3C985 0x0001 1808#define TC_DEVICEID_3C996 0x0003 1809 1810/* 1811 * SysKonnect PCI vendor ID 1812 */ 1813#define SK_VENDORID 0x1148 1814#define SK_DEVICEID_ALTIMA 0x4400 1815#define SK_SUBSYSID_9D21 0x4421 1816#define SK_SUBSYSID_9D41 0x4441 1817 1818/* 1819 * Altima PCI vendor/device ID. 1820 */ 1821#define ALTIMA_VENDORID 0x173b 1822#define ALTIMA_DEVICE_AC1000 0x03e8 1823 1824/* 1825 * Offset of MAC address inside EEPROM. 1826 */ 1827#define BGE_EE_MAC_OFFSET 0x7C 1828#define BGE_EE_HWCFG_OFFSET 0xC8 1829 1830#define BGE_HWCFG_VOLTAGE 0x00000003 1831#define BGE_HWCFG_PHYLED_MODE 0x0000000C 1832#define BGE_HWCFG_MEDIA 0x00000030 1833 1834#define BGE_VOLTAGE_1POINT3 0x00000000 1835#define BGE_VOLTAGE_1POINT8 0x00000001 1836 1837#define BGE_PHYLEDMODE_UNSPEC 0x00000000 1838#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 1839#define BGE_PHYLEDMODE_SINGLELED 0x00000008 1840 1841#define BGE_MEDIA_UNSPEC 0x00000000 1842#define BGE_MEDIA_COPPER 0x00000010 1843#define BGE_MEDIA_FIBER 0x00000020 1844 1845#define BGE_PCI_READ_CMD 0x06000000 1846#define BGE_PCI_WRITE_CMD 0x70000000 1847 1848#define BGE_TICKS_PER_SEC 1000000 1849 1850/* 1851 * Ring size constants. 1852 */ 1853#define BGE_EVENT_RING_CNT 256 1854#define BGE_CMD_RING_CNT 64 1855#define BGE_STD_RX_RING_CNT 512 1856#define BGE_JUMBO_RX_RING_CNT 256 1857#define BGE_MINI_RX_RING_CNT 1024 1858#define BGE_RETURN_RING_CNT 1024 1859 1860/* 1861 * Possible TX ring sizes. 1862 */ 1863#define BGE_TX_RING_CNT_128 128 1864#define BGE_TX_RING_BASE_128 0x3800 1865 1866#define BGE_TX_RING_CNT_256 256 1867#define BGE_TX_RING_BASE_256 0x3000 1868 1869#define BGE_TX_RING_CNT_512 512 1870#define BGE_TX_RING_BASE_512 0x2000 1871 1872#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 1873#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 1874 1875/* 1876 * Tigon III statistics counters. 1877 */ 1878struct bge_stats { 1879 u_int8_t Reserved0[256]; 1880 1881 /* Statistics maintained by Receive MAC. */ 1882 bge_hostaddr ifHCInOctets; 1883 bge_hostaddr Reserved1; 1884 bge_hostaddr etherStatsFragments; 1885 bge_hostaddr ifHCInUcastPkts; 1886 bge_hostaddr ifHCInMulticastPkts; 1887 bge_hostaddr ifHCInBroadcastPkts; 1888 bge_hostaddr dot3StatsFCSErrors; 1889 bge_hostaddr dot3StatsAlignmentErrors; 1890 bge_hostaddr xonPauseFramesReceived; 1891 bge_hostaddr xoffPauseFramesReceived; 1892 bge_hostaddr macControlFramesReceived; 1893 bge_hostaddr xoffStateEntered; 1894 bge_hostaddr dot3StatsFramesTooLong; 1895 bge_hostaddr etherStatsJabbers; 1896 bge_hostaddr etherStatsUndersizePkts; 1897 bge_hostaddr inRangeLengthError; 1898 bge_hostaddr outRangeLengthError; 1899 bge_hostaddr etherStatsPkts64Octets; 1900 bge_hostaddr etherStatsPkts65Octetsto127Octets; 1901 bge_hostaddr etherStatsPkts128Octetsto255Octets; 1902 bge_hostaddr etherStatsPkts256Octetsto511Octets; 1903 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 1904 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 1905 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 1906 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 1907 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 1908 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 1909 1910 bge_hostaddr Unused1[37]; 1911 1912 /* Statistics maintained by Transmit MAC. */ 1913 bge_hostaddr ifHCOutOctets; 1914 bge_hostaddr Reserved2; 1915 bge_hostaddr etherStatsCollisions; 1916 bge_hostaddr outXonSent; 1917 bge_hostaddr outXoffSent; 1918 bge_hostaddr flowControlDone; 1919 bge_hostaddr dot3StatsInternalMacTransmitErrors; 1920 bge_hostaddr dot3StatsSingleCollisionFrames; 1921 bge_hostaddr dot3StatsMultipleCollisionFrames; 1922 bge_hostaddr dot3StatsDeferredTransmissions; 1923 bge_hostaddr Reserved3; 1924 bge_hostaddr dot3StatsExcessiveCollisions; 1925 bge_hostaddr dot3StatsLateCollisions; 1926 bge_hostaddr dot3Collided2Times; 1927 bge_hostaddr dot3Collided3Times; 1928 bge_hostaddr dot3Collided4Times; 1929 bge_hostaddr dot3Collided5Times; 1930 bge_hostaddr dot3Collided6Times; 1931 bge_hostaddr dot3Collided7Times; 1932 bge_hostaddr dot3Collided8Times; 1933 bge_hostaddr dot3Collided9Times; 1934 bge_hostaddr dot3Collided10Times; 1935 bge_hostaddr dot3Collided11Times; 1936 bge_hostaddr dot3Collided12Times; 1937 bge_hostaddr dot3Collided13Times; 1938 bge_hostaddr dot3Collided14Times; 1939 bge_hostaddr dot3Collided15Times; 1940 bge_hostaddr ifHCOutUcastPkts; 1941 bge_hostaddr ifHCOutMulticastPkts; 1942 bge_hostaddr ifHCOutBroadcastPkts; 1943 bge_hostaddr dot3StatsCarrierSenseErrors; 1944 bge_hostaddr ifOutDiscards; 1945 bge_hostaddr ifOutErrors; 1946 1947 bge_hostaddr Unused2[31]; 1948 1949 /* Statistics maintained by Receive List Placement. */ 1950 bge_hostaddr COSIfHCInPkts[16]; 1951 bge_hostaddr COSFramesDroppedDueToFilters; 1952 bge_hostaddr nicDmaWriteQueueFull; 1953 bge_hostaddr nicDmaWriteHighPriQueueFull; 1954 bge_hostaddr nicNoMoreRxBDs; 1955 bge_hostaddr ifInDiscards; 1956 bge_hostaddr ifInErrors; 1957 bge_hostaddr nicRecvThresholdHit; 1958 1959 bge_hostaddr Unused3[9]; 1960 1961 /* Statistics maintained by Send Data Initiator. */ 1962 bge_hostaddr COSIfHCOutPkts[16]; 1963 bge_hostaddr nicDmaReadQueueFull; 1964 bge_hostaddr nicDmaReadHighPriQueueFull; 1965 bge_hostaddr nicSendDataCompQueueFull; 1966 1967 /* Statistics maintained by Host Coalescing. */ 1968 bge_hostaddr nicRingSetSendProdIndex; 1969 bge_hostaddr nicRingStatusUpdate; 1970 bge_hostaddr nicInterrupts; 1971 bge_hostaddr nicAvoidedInterrupts; 1972 bge_hostaddr nicSendThresholdHit; 1973 1974 u_int8_t Reserved4[320]; 1975}; 1976 1977/* 1978 * Tigon general information block. This resides in host memory 1979 * and contains the status counters, ring control blocks and 1980 * producer pointers. 1981 */ 1982 1983struct bge_gib { 1984 struct bge_stats bge_stats; 1985 struct bge_rcb bge_tx_rcb[16]; 1986 struct bge_rcb bge_std_rx_rcb; 1987 struct bge_rcb bge_jumbo_rx_rcb; 1988 struct bge_rcb bge_mini_rx_rcb; 1989 struct bge_rcb bge_return_rcb; 1990}; 1991 1992/* 1993 * NOTE! On the Alpha, we have an alignment constraint. 1994 * The first thing in the packet is a 14-byte Ethernet header. 1995 * This means that the packet is misaligned. To compensate, 1996 * we actually offset the data 2 bytes into the cluster. This 1997 * alignes the packet after the Ethernet header at a 32-bit 1998 * boundary. 1999 */ 2000 2001#define ETHER_ALIGN 2 2002 2003#define BGE_FRAMELEN 1518 2004#define BGE_MAX_FRAMELEN 1536 2005#define BGE_JUMBO_FRAMELEN 9018 2006#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2007#define BGE_PAGE_SIZE PAGE_SIZE 2008#define BGE_MIN_FRAMELEN 60 2009 2010/* 2011 * Other utility macros. 2012 */ 2013#define BGE_INC(x, y) (x) = (x + 1) % y 2014 2015/* 2016 * Vital product data and structures. 2017 */ 2018#define BGE_VPD_FLAG 0x8000 2019 2020/* VPD structures */ 2021struct vpd_res { 2022 u_int8_t vr_id; 2023 u_int8_t vr_len; 2024 u_int8_t vr_pad; 2025}; 2026 2027struct vpd_key { 2028 char vk_key[2]; 2029 u_int8_t vk_len; 2030}; 2031 2032#define VPD_RES_ID 0x82 /* ID string */ 2033#define VPD_RES_READ 0x90 /* start of read only area */ 2034#define VPD_RES_WRITE 0x81 /* start of read/write area */ 2035#define VPD_RES_END 0x78 /* end tag */ 2036 2037 2038/* 2039 * Register access macros. The Tigon always uses memory mapped register 2040 * accesses and all registers must be accessed with 32 bit operations. 2041 */ 2042 2043#define CSR_WRITE_4(sc, reg, val) \ 2044 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2045 2046#define CSR_READ_4(sc, reg) \ 2047 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2048 2049#define BGE_SETBIT(sc, reg, x) \ 2050 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 2051#define BGE_CLRBIT(sc, reg, x) \ 2052 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 2053 2054#define PCI_SETBIT(pc, tag, reg, x) \ 2055 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | x)) 2056#define PCI_CLRBIT(pc, tag, reg, x) \ 2057 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~x)) 2058 2059/* 2060 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2061 * values are tuneable. They control the actual amount of buffers 2062 * allocated for the standard, mini and jumbo receive rings. 2063 */ 2064 2065#define BGE_SSLOTS 256 2066#define BGE_MSLOTS 256 2067#define BGE_JSLOTS 384 2068 2069#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2070#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2071 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2072#define BGE_JPAGESZ PAGE_SIZE 2073#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2074#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2075 2076/* 2077 * Ring structures. Most of these reside in host memory and we tell 2078 * the NIC where they are via the ring control blocks. The exceptions 2079 * are the tx and command rings, which live in NIC memory and which 2080 * we access via the shared memory window. 2081 */ 2082struct bge_ring_data { 2083 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2084 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2085 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2086 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2087 struct bge_status_block bge_status_block; 2088 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2089 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2090 struct bge_gib bge_info; 2091}; 2092 2093#define BGE_RING_DMA_ADDR(sc, offset) \ 2094 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2095 offsetof(struct bge_ring_data, offset)) 2096 2097/* 2098 * Number of DMA segments in a TxCB. Note that this is carefully 2099 * chosen to make the total struct size an even power of two. It's 2100 * critical that no TxCB be split across a page boundry since 2101 * no attempt is made to allocate physically contiguous memory. 2102 * 2103 */ 2104#ifdef __alpha__ /* XXX - should be conditional on pointer size */ 2105#define BGE_NTXSEG 30 2106#else 2107#define BGE_NTXSEG 31 2108#endif 2109 2110/* 2111 * Mbuf pointers. We need these to keep track of the virtual addresses 2112 * of our mbuf chains since we can only convert from physical to virtual, 2113 * not the other way around. 2114 */ 2115struct bge_chain_data { 2116 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2117 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2118 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2119 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2120 bus_dmamap_t bge_tx_map[BGE_TX_RING_CNT]; 2121 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2122 bus_dmamap_t bge_rx_jumbo_map; 2123 /* Stick the jumbo mem management stuff here too. */ 2124 caddr_t bge_jslots[BGE_JSLOTS]; 2125 void *bge_jumbo_buf; 2126}; 2127 2128#define BGE_JUMBO_DMA_ADDR(sc, m) \ 2129 ((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \ 2130 (mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf)) 2131 2132struct bge_type { 2133 u_int16_t bge_vid; 2134 u_int16_t bge_did; 2135 char *bge_name; 2136}; 2137 2138#define BGE_HWREV_TIGON 0x01 2139#define BGE_HWREV_TIGON_II 0x02 2140#define BGE_TIMEOUT 1000 2141#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2142 2143struct bge_jpool_entry { 2144 int slot; 2145 LIST_ENTRY(bge_jpool_entry) jpool_entries; 2146}; 2147 2148struct bge_bcom_hack { 2149 int reg; 2150 int val; 2151}; 2152 2153struct bge_softc { 2154 struct device bge_dev; 2155 struct arpcom arpcom; /* interface info */ 2156 bus_space_handle_t bge_bhandle; 2157 bus_space_tag_t bge_btag; 2158 void *bge_intrhand; 2159 struct pci_attach_args bge_pa; 2160 struct mii_data bge_mii; 2161 struct ifmedia bge_ifmedia; /* media info */ 2162 u_int8_t bge_extram; /* has external SSRAM */ 2163 u_int8_t bge_tbi; 2164 bus_dma_tag_t bge_dmatag; 2165 u_int32_t bge_asicrev; 2166 struct bge_ring_data *bge_rdata; /* rings */ 2167 struct bge_chain_data bge_cdata; /* mbufs */ 2168 bus_dmamap_t bge_ring_map; 2169 u_int16_t bge_tx_saved_considx; 2170 u_int16_t bge_rx_saved_considx; 2171 u_int16_t bge_ev_saved_considx; 2172 u_int16_t bge_std; /* current std ring head */ 2173 u_int16_t bge_jumbo; /* current jumo ring head */ 2174 LIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2175 LIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2176 u_int32_t bge_stat_ticks; 2177 u_int32_t bge_rx_coal_ticks; 2178 u_int32_t bge_tx_coal_ticks; 2179 u_int32_t bge_rx_max_coal_bds; 2180 u_int32_t bge_tx_max_coal_bds; 2181 u_int32_t bge_tx_buf_ratio; 2182 int bge_if_flags; 2183 int bge_txcnt; 2184 int bge_link; 2185 struct timeout bge_timeout; 2186 char *bge_vpd_prodname; 2187 char *bge_vpd_readonly; 2188}; 2189