if_bgereg.h revision 1.30
1/* $OpenBSD: if_bgereg.h,v 1.30 2005/10/09 23:41:55 brad Exp $ */ 2 3/* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bgereg.h,v 1.11 2002/11/14 23:54:50 sam Exp $ 36 */ 37 38/* 39 * BCM570x memory map. The internal memory layout varies somewhat 40 * depending on whether or not we have external SSRAM attached. 41 * The BCM5700 can have up to 16MB of external memory. The BCM5701 42 * is apparently not designed to use external SSRAM. The mappings 43 * up to the first 4 send rings are the same for both internal and 44 * external memory configurations. Note that mini RX ring space is 45 * only available with external SSRAM configurations, which means 46 * the mini RX ring is not supported on the BCM5701. 47 * 48 * The NIC's memory can be accessed by the host in one of 3 ways: 49 * 50 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 51 * registers in PCI config space can be used to read any 32-bit 52 * address within the NIC's memory. 53 * 54 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 55 * space can be used in conjunction with the memory window in the 56 * device register space at offset 0x8000 to read any 32K chunk 57 * of NIC memory. 58 * 59 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 60 * set, the device I/O mapping consumes 32MB of host address space, 61 * allowing all of the registers and internal NIC memory to be 62 * accessed directly. NIC memory addresses are offset by 0x01000000. 63 * Flat mode consumes so much host address space that it is not 64 * recommended. 65 */ 66#define BGE_PAGE_ZERO 0x00000000 67#define BGE_PAGE_ZERO_END 0x000000FF 68#define BGE_SEND_RING_RCB 0x00000100 69#define BGE_SEND_RING_RCB_END 0x000001FF 70#define BGE_RX_RETURN_RING_RCB 0x00000200 71#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 72#define BGE_STATS_BLOCK 0x00000300 73#define BGE_STATS_BLOCK_END 0x00000AFF 74#define BGE_STATUS_BLOCK 0x00000B00 75#define BGE_STATUS_BLOCK_END 0x00000B4F 76#define BGE_SOFTWARE_GENCOMM 0x00000B50 77#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 78#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 79#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 80#define BGE_UNMAPPED 0x00001000 81#define BGE_UNMAPPED_END 0x00001FFF 82#define BGE_DMA_DESCRIPTORS 0x00002000 83#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 84#define BGE_SEND_RING_1_TO_4 0x00004000 85#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 86 87/* Mappings for internal memory configuration */ 88#define BGE_STD_RX_RINGS 0x00006000 89#define BGE_STD_RX_RINGS_END 0x00006FFF 90#define BGE_JUMBO_RX_RINGS 0x00007000 91#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 92#define BGE_BUFFPOOL_1 0x00008000 93#define BGE_BUFFPOOL_1_END 0x0000FFFF 94#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 95#define BGE_BUFFPOOL_2_END 0x00017FFF 96#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 97#define BGE_BUFFPOOL_3_END 0x0001FFFF 98 99/* Mappings for external SSRAM configurations */ 100#define BGE_SEND_RING_5_TO_6 0x00006000 101#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 102#define BGE_SEND_RING_7_TO_8 0x00007000 103#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 104#define BGE_SEND_RING_9_TO_16 0x00008000 105#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 106#define BGE_EXT_STD_RX_RINGS 0x0000C000 107#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 108#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 109#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 110#define BGE_MINI_RX_RINGS 0x0000E000 111#define BGE_MINI_RX_RINGS_END 0x0000FFFF 112#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 113#define BGE_AVAIL_REGION1_END 0x00017FFF 114#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 115#define BGE_AVAIL_REGION2_END 0x0001FFFF 116#define BGE_EXT_SSRAM 0x00020000 117#define BGE_EXT_SSRAM_END 0x000FFFFF 118 119 120/* 121 * BCM570x register offsets. These are memory mapped registers 122 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 123 * Each register must be accessed using 32 bit operations. 124 * 125 * All registers are accessed through a 32K shared memory block. 126 * The first group of registers are actually copies of the PCI 127 * configuration space registers. 128 */ 129 130/* 131 * PCI registers defined in the PCI 2.2 spec. 132 */ 133#define BGE_PCI_VID 0x00 134#define BGE_PCI_DID 0x02 135#define BGE_PCI_CMD 0x04 136#define BGE_PCI_STS 0x06 137#define BGE_PCI_REV 0x08 138#define BGE_PCI_CLASS 0x09 139#define BGE_PCI_CACHESZ 0x0C 140#define BGE_PCI_LATTIMER 0x0D 141#define BGE_PCI_HDRTYPE 0x0E 142#define BGE_PCI_BIST 0x0F 143#define BGE_PCI_BAR0 0x10 144#define BGE_PCI_BAR1 0x14 145#define BGE_PCI_SUBSYS 0x2C 146#define BGE_PCI_SUBVID 0x2E 147#define BGE_PCI_ROMBASE 0x30 148#define BGE_PCI_CAPPTR 0x34 149#define BGE_PCI_INTLINE 0x3C 150#define BGE_PCI_INTPIN 0x3D 151#define BGE_PCI_MINGNT 0x3E 152#define BGE_PCI_MAXLAT 0x3F 153#define BGE_PCI_PCIXCAP 0x40 154#define BGE_PCI_NEXTPTR_PM 0x41 155#define BGE_PCI_PCIX_CMD 0x42 156#define BGE_PCI_PCIX_STS 0x44 157#define BGE_PCI_PWRMGMT_CAPID 0x48 158#define BGE_PCI_NEXTPTR_VPD 0x49 159#define BGE_PCI_PWRMGMT_CAPS 0x4A 160#define BGE_PCI_PWRMGMT_CMD 0x4C 161#define BGE_PCI_PWRMGMT_STS 0x4D 162#define BGE_PCI_PWRMGMT_DATA 0x4F 163#define BGE_PCI_VPD_CAPID 0x50 164#define BGE_PCI_NEXTPTR_MSI 0x51 165#define BGE_PCI_VPD_ADDR 0x52 166#define BGE_PCI_VPD_DATA 0x54 167#define BGE_PCI_MSI_CAPID 0x58 168#define BGE_PCI_NEXTPTR_NONE 0x59 169#define BGE_PCI_MSI_CTL 0x5A 170#define BGE_PCI_MSI_ADDR_HI 0x5C 171#define BGE_PCI_MSI_ADDR_LO 0x60 172#define BGE_PCI_MSI_DATA 0x64 173 174/* PCI MSI. ??? */ 175#define BGE_PCIE_CAPID_REG 0xD0 176#define BGE_PCIE_CAPID 0x10 177 178/* 179 * PCI registers specific to the BCM570x family. 180 */ 181#define BGE_PCI_MISC_CTL 0x68 182#define BGE_PCI_DMA_RW_CTL 0x6C 183#define BGE_PCI_PCISTATE 0x70 184#define BGE_PCI_CLKCTL 0x74 185#define BGE_PCI_REG_BASEADDR 0x78 186#define BGE_PCI_MEMWIN_BASEADDR 0x7C 187#define BGE_PCI_REG_DATA 0x80 188#define BGE_PCI_MEMWIN_DATA 0x84 189#define BGE_PCI_MODECTL 0x88 190#define BGE_PCI_MISC_CFG 0x8C 191#define BGE_PCI_MISC_LOCALCTL 0x90 192#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 193#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 194#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 195#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 196#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 197#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 198#define BGE_PCI_ISR_MBX_HI 0xB0 199#define BGE_PCI_ISR_MBX_LO 0xB4 200 201/* PCI Misc. Host control register */ 202#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 203#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 204#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 205#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 206#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 207#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 208#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 209#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 210#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 211 212#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 213#if BYTE_ORDER == LITTLE_ENDIAN 214#define BGE_DMA_SWAP_OPTIONS \ 215 BGE_MODECTL_WORDSWAP_NONFRAME| \ 216 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 217#else 218#define BGE_DMA_SWAP_OPTIONS \ 219 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 220 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 221#endif 222 223#define BGE_INIT \ 224 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 225 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 226 227#define BGE_CHIPID_BCM5700_A0 0x70000000 228#define BGE_CHIPID_BCM5700_A1 0x70010000 229#define BGE_CHIPID_BCM5700_B0 0x71000000 230#define BGE_CHIPID_BCM5700_B1 0x71010000 231#define BGE_CHIPID_BCM5700_B2 0x71020000 232#define BGE_CHIPID_BCM5700_B3 0x71030000 233#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 234#define BGE_CHIPID_BCM5700_C0 0x72000000 235#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 236#define BGE_CHIPID_BCM5701_B0 0x01000000 237#define BGE_CHIPID_BCM5701_B2 0x01020000 238#define BGE_CHIPID_BCM5701_B5 0x01050000 239#define BGE_CHIPID_BCM5703_A0 0x10000000 240#define BGE_CHIPID_BCM5703_A1 0x10010000 241#define BGE_CHIPID_BCM5703_A2 0x10020000 242#define BGE_CHIPID_BCM5703_A3 0x10030000 243#define BGE_CHIPID_BCM5704_A0 0x20000000 244#define BGE_CHIPID_BCM5704_A1 0x20010000 245#define BGE_CHIPID_BCM5704_A2 0x20020000 246#define BGE_CHIPID_BCM5704_A3 0x20030000 247#define BGE_CHIPID_BCM5704_B0 0x21000000 248#define BGE_CHIPID_BCM5705_A0 0x30000000 249#define BGE_CHIPID_BCM5705_A1 0x30010000 250#define BGE_CHIPID_BCM5705_A2 0x30020000 251#define BGE_CHIPID_BCM5705_A3 0x30030000 252#define BGE_CHIPID_BCM5750_A0 0x40000000 253#define BGE_CHIPID_BCM5750_A1 0x40010000 254#define BGE_CHIPID_BCM5750_A3 0x40030000 255#define BGE_CHIPID_BCM5750_B0 0x40100000 256#define BGE_CHIPID_BCM5750_B1 0x41010000 257#define BGE_CHIPID_BCM5750_C0 0x42000000 258#define BGE_CHIPID_BCM5714_A0 0x50000000 259#define BGE_CHIPID_BCM5752_A0 0x60000000 260#define BGE_CHIPID_BCM5752_A1 0x60010000 261#define BGE_CHIPID_BCM5714 0x80000000 262 263/* shorthand one */ 264#define BGE_ASICREV(x) ((x) >> 28) 265#define BGE_ASICREV_BCM5700 0x07 266#define BGE_ASICREV_BCM5701 0x00 267#define BGE_ASICREV_BCM5703 0x01 268#define BGE_ASICREV_BCM5704 0x02 269#define BGE_ASICREV_BCM5705 0x03 270#define BGE_ASICREV_BCM5750 0x04 271#define BGE_ASICREV_BCM5714 0x05 /* 5714, 5715 */ 272#define BGE_ASICREV_BCM5752 0x06 273#define BGE_ASICREV_BCM5780 0x08 274 275/* chip revisions */ 276#define BGE_CHIPREV(x) ((x) >> 24) 277#define BGE_CHIPREV_5700_AX 0x70 278#define BGE_CHIPREV_5700_BX 0x71 279#define BGE_CHIPREV_5700_CX 0x72 280#define BGE_CHIPREV_5701_AX 0x00 281#define BGE_CHIPREV_5703_AX 0x10 282#define BGE_CHIPREV_5704_AX 0x20 283#define BGE_CHIPREV_5704_BX 0x21 284#define BGE_CHIPREV_5750_AX 0x40 285#define BGE_CHIPREV_5750_BX 0x41 286 287/* PCI DMA Read/Write Control register */ 288#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 289#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 290#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 291#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 292#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 293#define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 294#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 295#define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 296#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 297#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 298#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 299#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD_SHIFT 24 300#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 301#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD_SHIFT 28 302 303#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 304#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 305#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 306#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 307#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 308#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 309#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 310#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 311 312#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 313#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 314#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 315#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 316#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 317#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 318#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 319#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 320 321/* 322 * PCI state register -- note, this register is read only 323 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 324 * register is set. 325 */ 326#define BGE_PCISTATE_FORCE_RESET 0x00000001 327#define BGE_PCISTATE_INTR_STATE 0x00000002 328#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 329#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 330#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 331#define BGE_PCISTATE_WANT_EXPROM 0x00000020 332#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 333#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 334#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 335 336/* 337 * The following bits in PCI state register are reserved. 338 * If we check that the register values reverts on reset, 339 * do not check these bits. On some 5704C (rev A3) and some 340 * Altima chips, these bits do not revert until much later 341 * in the bge driver's bge_reset() chip-reset state machine. 342 */ 343#define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 344 345/* 346 * PCI Clock Control register -- note, this register is read only 347 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 348 * register is set. 349 */ 350#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 351#define BGE_PCICLOCKCTL_M66EN 0x00000080 352#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 353#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 354#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 355#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 356#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 357#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 358#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 359#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 360 361/* 362 * High priority mailbox registers 363 * Each mailbox is 64-bits wide, though we only use the 364 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 365 * first. The NIC will load the mailbox after the lower 32 bit word 366 * has been updated. 367 */ 368#define BGE_MBX_IRQ0_HI 0x0200 369#define BGE_MBX_IRQ0_LO 0x0204 370#define BGE_MBX_IRQ1_HI 0x0208 371#define BGE_MBX_IRQ1_LO 0x020C 372#define BGE_MBX_IRQ2_HI 0x0210 373#define BGE_MBX_IRQ2_LO 0x0214 374#define BGE_MBX_IRQ3_HI 0x0218 375#define BGE_MBX_IRQ3_LO 0x021C 376#define BGE_MBX_GEN0_HI 0x0220 377#define BGE_MBX_GEN0_LO 0x0224 378#define BGE_MBX_GEN1_HI 0x0228 379#define BGE_MBX_GEN1_LO 0x022C 380#define BGE_MBX_GEN2_HI 0x0230 381#define BGE_MBX_GEN2_LO 0x0234 382#define BGE_MBX_GEN3_HI 0x0228 383#define BGE_MBX_GEN3_LO 0x022C 384#define BGE_MBX_GEN4_HI 0x0240 385#define BGE_MBX_GEN4_LO 0x0244 386#define BGE_MBX_GEN5_HI 0x0248 387#define BGE_MBX_GEN5_LO 0x024C 388#define BGE_MBX_GEN6_HI 0x0250 389#define BGE_MBX_GEN6_LO 0x0254 390#define BGE_MBX_GEN7_HI 0x0258 391#define BGE_MBX_GEN7_LO 0x025C 392#define BGE_MBX_RELOAD_STATS_HI 0x0260 393#define BGE_MBX_RELOAD_STATS_LO 0x0264 394#define BGE_MBX_RX_STD_PROD_HI 0x0268 395#define BGE_MBX_RX_STD_PROD_LO 0x026C 396#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 397#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 398#define BGE_MBX_RX_MINI_PROD_HI 0x0278 399#define BGE_MBX_RX_MINI_PROD_LO 0x027C 400#define BGE_MBX_RX_CONS0_HI 0x0280 401#define BGE_MBX_RX_CONS0_LO 0x0284 402#define BGE_MBX_RX_CONS1_HI 0x0288 403#define BGE_MBX_RX_CONS1_LO 0x028C 404#define BGE_MBX_RX_CONS2_HI 0x0290 405#define BGE_MBX_RX_CONS2_LO 0x0294 406#define BGE_MBX_RX_CONS3_HI 0x0298 407#define BGE_MBX_RX_CONS3_LO 0x029C 408#define BGE_MBX_RX_CONS4_HI 0x02A0 409#define BGE_MBX_RX_CONS4_LO 0x02A4 410#define BGE_MBX_RX_CONS5_HI 0x02A8 411#define BGE_MBX_RX_CONS5_LO 0x02AC 412#define BGE_MBX_RX_CONS6_HI 0x02B0 413#define BGE_MBX_RX_CONS6_LO 0x02B4 414#define BGE_MBX_RX_CONS7_HI 0x02B8 415#define BGE_MBX_RX_CONS7_LO 0x02BC 416#define BGE_MBX_RX_CONS8_HI 0x02C0 417#define BGE_MBX_RX_CONS8_LO 0x02C4 418#define BGE_MBX_RX_CONS9_HI 0x02C8 419#define BGE_MBX_RX_CONS9_LO 0x02CC 420#define BGE_MBX_RX_CONS10_HI 0x02D0 421#define BGE_MBX_RX_CONS10_LO 0x02D4 422#define BGE_MBX_RX_CONS11_HI 0x02D8 423#define BGE_MBX_RX_CONS11_LO 0x02DC 424#define BGE_MBX_RX_CONS12_HI 0x02E0 425#define BGE_MBX_RX_CONS12_LO 0x02E4 426#define BGE_MBX_RX_CONS13_HI 0x02E8 427#define BGE_MBX_RX_CONS13_LO 0x02EC 428#define BGE_MBX_RX_CONS14_HI 0x02F0 429#define BGE_MBX_RX_CONS14_LO 0x02F4 430#define BGE_MBX_RX_CONS15_HI 0x02F8 431#define BGE_MBX_RX_CONS15_LO 0x02FC 432#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 433#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 434#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 435#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 436#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 437#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 438#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 439#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 440#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 441#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 442#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 443#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 444#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 445#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 446#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 447#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 448#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 449#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 450#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 451#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 452#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 453#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 454#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 455#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 456#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 457#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 458#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 459#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 460#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 461#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 462#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 463#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 464#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 465#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 466#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 467#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 468#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 469#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 470#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 471#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 472#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 473#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 474#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 475#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 476#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 477#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 478#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 479#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 480#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 481#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 482#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 483#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 484#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 485#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 486#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 487#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 488#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 489#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 490#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 491#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 492#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 493#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 494#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 495#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 496 497#define BGE_TX_RINGS_MAX 4 498#define BGE_TX_RINGS_EXTSSRAM_MAX 16 499#define BGE_RX_RINGS_MAX 16 500 501/* Ethernet MAC control registers */ 502#define BGE_MAC_MODE 0x0400 503#define BGE_MAC_STS 0x0404 504#define BGE_MAC_EVT_ENB 0x0408 505#define BGE_MAC_LED_CTL 0x040C 506#define BGE_MAC_ADDR1_LO 0x0410 507#define BGE_MAC_ADDR1_HI 0x0414 508#define BGE_MAC_ADDR2_LO 0x0418 509#define BGE_MAC_ADDR2_HI 0x041C 510#define BGE_MAC_ADDR3_LO 0x0420 511#define BGE_MAC_ADDR3_HI 0x0424 512#define BGE_MAC_ADDR4_LO 0x0428 513#define BGE_MAC_ADDR4_HI 0x042C 514#define BGE_WOL_PATPTR 0x0430 515#define BGE_WOL_PATCFG 0x0434 516#define BGE_TX_RANDOM_BACKOFF 0x0438 517#define BGE_RX_MTU 0x043C 518#define BGE_GBIT_PCS_TEST 0x0440 519#define BGE_TX_TBI_AUTONEG 0x0444 520#define BGE_RX_TBI_AUTONEG 0x0448 521#define BGE_MI_COMM 0x044C 522#define BGE_MI_STS 0x0450 523#define BGE_MI_MODE 0x0454 524#define BGE_AUTOPOLL_STS 0x0458 525#define BGE_TX_MODE 0x045C 526#define BGE_TX_STS 0x0460 527#define BGE_TX_LENGTHS 0x0464 528#define BGE_RX_MODE 0x0468 529#define BGE_RX_STS 0x046C 530#define BGE_MAR0 0x0470 531#define BGE_MAR1 0x0474 532#define BGE_MAR2 0x0478 533#define BGE_MAR3 0x047C 534#define BGE_RX_BD_RULES_CTL0 0x0480 535#define BGE_RX_BD_RULES_MASKVAL0 0x0484 536#define BGE_RX_BD_RULES_CTL1 0x0488 537#define BGE_RX_BD_RULES_MASKVAL1 0x048C 538#define BGE_RX_BD_RULES_CTL2 0x0490 539#define BGE_RX_BD_RULES_MASKVAL2 0x0494 540#define BGE_RX_BD_RULES_CTL3 0x0498 541#define BGE_RX_BD_RULES_MASKVAL3 0x049C 542#define BGE_RX_BD_RULES_CTL4 0x04A0 543#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 544#define BGE_RX_BD_RULES_CTL5 0x04A8 545#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 546#define BGE_RX_BD_RULES_CTL6 0x04B0 547#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 548#define BGE_RX_BD_RULES_CTL7 0x04B8 549#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 550#define BGE_RX_BD_RULES_CTL8 0x04C0 551#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 552#define BGE_RX_BD_RULES_CTL9 0x04C8 553#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 554#define BGE_RX_BD_RULES_CTL10 0x04D0 555#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 556#define BGE_RX_BD_RULES_CTL11 0x04D8 557#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 558#define BGE_RX_BD_RULES_CTL12 0x04E0 559#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 560#define BGE_RX_BD_RULES_CTL13 0x04E8 561#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 562#define BGE_RX_BD_RULES_CTL14 0x04F0 563#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 564#define BGE_RX_BD_RULES_CTL15 0x04F8 565#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 566#define BGE_RX_RULES_CFG 0x0500 567#define BGE_MAX_RX_FRAME_LOWAT 0x0504 568#define BGE_SERDES_CFG 0x0590 569#define BGE_SERDES_STS 0x0594 570#define BGE_SGDIG_CFG 0x05B0 571#define BGE_SGDIG_STS 0x05B4 572#define BGE_RX_STATS 0x0800 573#define BGE_TX_STATS 0x0880 574 575/* Ethernet MAC Mode register */ 576#define BGE_MACMODE_RESET 0x00000001 577#define BGE_MACMODE_HALF_DUPLEX 0x00000002 578#define BGE_MACMODE_PORTMODE 0x0000000C 579#define BGE_MACMODE_LOOPBACK 0x00000010 580#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 581#define BGE_MACMODE_TX_BURST_ENB 0x00000100 582#define BGE_MACMODE_MAX_DEFER 0x00000200 583#define BGE_MACMODE_LINK_POLARITY 0x00000400 584#define BGE_MACMODE_RX_STATS_ENB 0x00000800 585#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 586#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 587#define BGE_MACMODE_TX_STATS_ENB 0x00004000 588#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 589#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 590#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 591#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 592#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 593#define BGE_MACMODE_MIP_ENB 0x00100000 594#define BGE_MACMODE_TXDMA_ENB 0x00200000 595#define BGE_MACMODE_RXDMA_ENB 0x00400000 596#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 597 598#define BGE_PORTMODE_NONE 0x00000000 599#define BGE_PORTMODE_MII 0x00000004 600#define BGE_PORTMODE_GMII 0x00000008 601#define BGE_PORTMODE_TBI 0x0000000C 602 603/* MAC Status register */ 604#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 605#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 606#define BGE_MACSTAT_RX_CFG 0x00000004 607#define BGE_MACSTAT_CFG_CHANGED 0x00000008 608#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 609#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 610#define BGE_MACSTAT_LINK_CHANGED 0x00001000 611#define BGE_MACSTAT_MI_COMPLETE 0x00400000 612#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 613#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 614#define BGE_MACSTAT_ODI_ERROR 0x02000000 615#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 616#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 617 618/* MAC Event Enable Register */ 619#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 620#define BGE_EVTENB_LINK_CHANGED 0x00001000 621#define BGE_EVTENB_MI_COMPLETE 0x00400000 622#define BGE_EVTENB_MI_INTERRUPT 0x00800000 623#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 624#define BGE_EVTENB_ODI_ERROR 0x02000000 625#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 626#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 627 628/* LED Control Register */ 629#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 630#define BGE_LEDCTL_1000MBPS_LED 0x00000002 631#define BGE_LEDCTL_100MBPS_LED 0x00000004 632#define BGE_LEDCTL_10MBPS_LED 0x00000008 633#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 634#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 635#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 636#define BGE_LEDCTL_1000MBPS_STS 0x00000080 637#define BGE_LEDCTL_100MBPS_STS 0x00000100 638#define BGE_LEDCTL_10MBPS_STS 0x00000200 639#define BGE_LEDCTL_TRADLED_STS 0x00000400 640#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 641#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 642 643/* TX backoff seed register */ 644#define BGE_TX_BACKOFF_SEED_MASK 0x3F 645 646/* Autopoll status register */ 647#define BGE_AUTOPOLLSTS_ERROR 0x00000001 648 649/* Transmit MAC mode register */ 650#define BGE_TXMODE_RESET 0x00000001 651#define BGE_TXMODE_ENABLE 0x00000002 652#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 653#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 654#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 655 656/* Transmit MAC status register */ 657#define BGE_TXSTAT_RX_XOFFED 0x00000001 658#define BGE_TXSTAT_SENT_XOFF 0x00000002 659#define BGE_TXSTAT_SENT_XON 0x00000004 660#define BGE_TXSTAT_LINK_UP 0x00000008 661#define BGE_TXSTAT_ODI_UFLOW 0x00000010 662#define BGE_TXSTAT_ODI_OFLOW 0x00000020 663 664/* Transmit MAC lengths register */ 665#define BGE_TXLEN_SLOTTIME 0x000000FF 666#define BGE_TXLEN_IPG 0x00000F00 667#define BGE_TXLEN_CRS 0x00003000 668 669/* Receive MAC mode register */ 670#define BGE_RXMODE_RESET 0x00000001 671#define BGE_RXMODE_ENABLE 0x00000002 672#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 673#define BGE_RXMODE_RX_GIANTS 0x00000020 674#define BGE_RXMODE_RX_RUNTS 0x00000040 675#define BGE_RXMODE_8022_LENCHECK 0x00000080 676#define BGE_RXMODE_RX_PROMISC 0x00000100 677#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 678#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 679 680/* Receive MAC status register */ 681#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 682#define BGE_RXSTAT_RCVD_XOFF 0x00000002 683#define BGE_RXSTAT_RCVD_XON 0x00000004 684 685/* Receive Rules Control register */ 686#define BGE_RXRULECTL_OFFSET 0x000000FF 687#define BGE_RXRULECTL_CLASS 0x00001F00 688#define BGE_RXRULECTL_HDRTYPE 0x0000E000 689#define BGE_RXRULECTL_COMPARE_OP 0x00030000 690#define BGE_RXRULECTL_MAP 0x01000000 691#define BGE_RXRULECTL_DISCARD 0x02000000 692#define BGE_RXRULECTL_MASK 0x04000000 693#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 694#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 695#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 696#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 697 698/* Receive Rules Mask register */ 699#define BGE_RXRULEMASK_VALUE 0x0000FFFF 700#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 701 702/* SERDES configuration register */ 703#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 704#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 705#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 706#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 707#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 708#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 709#define BGE_SERDESCFG_TXMODE 0x00001000 710#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 711#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 712#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 713#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 714#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 715#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 716#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 717#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 718#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 719 720/* SERDES status register */ 721#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 722#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 723 724/* SGDIG config (not documented) */ 725#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 726#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 727#define BGE_SGDIGCFG_SEND 0x40000000 728#define BGE_SGDIGCFG_AUTO 0x80000000 729 730/* SGDIG status (not documented) */ 731#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 732#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 733#define BGE_SGDIGSTS_DONE 0x00000002 734 735/* MI communication register */ 736#define BGE_MICOMM_DATA 0x0000FFFF 737#define BGE_MICOMM_REG 0x001F0000 738#define BGE_MICOMM_PHY 0x03E00000 739#define BGE_MICOMM_CMD 0x0C000000 740#define BGE_MICOMM_READFAIL 0x10000000 741#define BGE_MICOMM_BUSY 0x20000000 742 743#define BGE_MIREG(x) ((x & 0x1F) << 16) 744#define BGE_MIPHY(x) ((x & 0x1F) << 21) 745#define BGE_MICMD_WRITE 0x04000000 746#define BGE_MICMD_READ 0x08000000 747 748/* MI status register */ 749#define BGE_MISTS_LINK 0x00000001 750#define BGE_MISTS_10MBPS 0x00000002 751 752#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 753#define BGE_MIMODE_AUTOPOLL 0x00000010 754#define BGE_MIMODE_CLKCNT 0x001F0000 755 756 757/* 758 * Send data initiator control registers. 759 */ 760#define BGE_SDI_MODE 0x0C00 761#define BGE_SDI_STATUS 0x0C04 762#define BGE_SDI_STATS_CTL 0x0C08 763#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 764#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 765#define BGE_LOCSTATS_COS0 0x0C80 766#define BGE_LOCSTATS_COS1 0x0C84 767#define BGE_LOCSTATS_COS2 0x0C88 768#define BGE_LOCSTATS_COS3 0x0C8C 769#define BGE_LOCSTATS_COS4 0x0C90 770#define BGE_LOCSTATS_COS5 0x0C84 771#define BGE_LOCSTATS_COS6 0x0C98 772#define BGE_LOCSTATS_COS7 0x0C9C 773#define BGE_LOCSTATS_COS8 0x0CA0 774#define BGE_LOCSTATS_COS9 0x0CA4 775#define BGE_LOCSTATS_COS10 0x0CA8 776#define BGE_LOCSTATS_COS11 0x0CAC 777#define BGE_LOCSTATS_COS12 0x0CB0 778#define BGE_LOCSTATS_COS13 0x0CB4 779#define BGE_LOCSTATS_COS14 0x0CB8 780#define BGE_LOCSTATS_COS15 0x0CBC 781#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 782#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 783#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 784#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 785#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 786#define BGE_LOCSTATS_IRQS 0x0CD4 787#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 788#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 789 790/* Send Data Initiator mode register */ 791#define BGE_SDIMODE_RESET 0x00000001 792#define BGE_SDIMODE_ENABLE 0x00000002 793#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 794 795/* Send Data Initiator stats register */ 796#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 797 798/* Send Data Initiator stats control register */ 799#define BGE_SDISTATSCTL_ENABLE 0x00000001 800#define BGE_SDISTATSCTL_FASTER 0x00000002 801#define BGE_SDISTATSCTL_CLEAR 0x00000004 802#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 803#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 804 805/* 806 * Send Data Completion Control registers 807 */ 808#define BGE_SDC_MODE 0x1000 809#define BGE_SDC_STATUS 0x1004 810 811/* Send Data completion mode register */ 812#define BGE_SDCMODE_RESET 0x00000001 813#define BGE_SDCMODE_ENABLE 0x00000002 814#define BGE_SDCMODE_ATTN 0x00000004 815 816/* Send Data completion status register */ 817#define BGE_SDCSTAT_ATTN 0x00000004 818 819/* 820 * Send BD Ring Selector Control registers 821 */ 822#define BGE_SRS_MODE 0x1400 823#define BGE_SRS_STATUS 0x1404 824#define BGE_SRS_HWDIAG 0x1408 825#define BGE_SRS_LOC_NIC_CONS0 0x1440 826#define BGE_SRS_LOC_NIC_CONS1 0x1444 827#define BGE_SRS_LOC_NIC_CONS2 0x1448 828#define BGE_SRS_LOC_NIC_CONS3 0x144C 829#define BGE_SRS_LOC_NIC_CONS4 0x1450 830#define BGE_SRS_LOC_NIC_CONS5 0x1454 831#define BGE_SRS_LOC_NIC_CONS6 0x1458 832#define BGE_SRS_LOC_NIC_CONS7 0x145C 833#define BGE_SRS_LOC_NIC_CONS8 0x1460 834#define BGE_SRS_LOC_NIC_CONS9 0x1464 835#define BGE_SRS_LOC_NIC_CONS10 0x1468 836#define BGE_SRS_LOC_NIC_CONS11 0x146C 837#define BGE_SRS_LOC_NIC_CONS12 0x1470 838#define BGE_SRS_LOC_NIC_CONS13 0x1474 839#define BGE_SRS_LOC_NIC_CONS14 0x1478 840#define BGE_SRS_LOC_NIC_CONS15 0x147C 841 842/* Send BD Ring Selector Mode register */ 843#define BGE_SRSMODE_RESET 0x00000001 844#define BGE_SRSMODE_ENABLE 0x00000002 845#define BGE_SRSMODE_ATTN 0x00000004 846 847/* Send BD Ring Selector Status register */ 848#define BGE_SRSSTAT_ERROR 0x00000004 849 850/* Send BD Ring Selector HW Diagnostics register */ 851#define BGE_SRSHWDIAG_STATE 0x0000000F 852#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 853#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 854#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 855 856/* 857 * Send BD Initiator Selector Control registers 858 */ 859#define BGE_SBDI_MODE 0x1800 860#define BGE_SBDI_STATUS 0x1804 861#define BGE_SBDI_LOC_NIC_PROD0 0x1808 862#define BGE_SBDI_LOC_NIC_PROD1 0x180C 863#define BGE_SBDI_LOC_NIC_PROD2 0x1810 864#define BGE_SBDI_LOC_NIC_PROD3 0x1814 865#define BGE_SBDI_LOC_NIC_PROD4 0x1818 866#define BGE_SBDI_LOC_NIC_PROD5 0x181C 867#define BGE_SBDI_LOC_NIC_PROD6 0x1820 868#define BGE_SBDI_LOC_NIC_PROD7 0x1824 869#define BGE_SBDI_LOC_NIC_PROD8 0x1828 870#define BGE_SBDI_LOC_NIC_PROD9 0x182C 871#define BGE_SBDI_LOC_NIC_PROD10 0x1830 872#define BGE_SBDI_LOC_NIC_PROD11 0x1834 873#define BGE_SBDI_LOC_NIC_PROD12 0x1838 874#define BGE_SBDI_LOC_NIC_PROD13 0x183C 875#define BGE_SBDI_LOC_NIC_PROD14 0x1840 876#define BGE_SBDI_LOC_NIC_PROD15 0x1844 877 878/* Send BD Initiator Mode register */ 879#define BGE_SBDIMODE_RESET 0x00000001 880#define BGE_SBDIMODE_ENABLE 0x00000002 881#define BGE_SBDIMODE_ATTN 0x00000004 882 883/* Send BD Initiator Status register */ 884#define BGE_SBDISTAT_ERROR 0x00000004 885 886/* 887 * Send BD Completion Control registers 888 */ 889#define BGE_SBDC_MODE 0x1C00 890#define BGE_SBDC_STATUS 0x1C04 891 892/* Send BD Completion Control Mode register */ 893#define BGE_SBDCMODE_RESET 0x00000001 894#define BGE_SBDCMODE_ENABLE 0x00000002 895#define BGE_SBDCMODE_ATTN 0x00000004 896 897/* Send BD Completion Control Status register */ 898#define BGE_SBDCSTAT_ATTN 0x00000004 899 900/* 901 * Receive List Placement Control registers 902 */ 903#define BGE_RXLP_MODE 0x2000 904#define BGE_RXLP_STATUS 0x2004 905#define BGE_RXLP_SEL_LIST_LOCK 0x2008 906#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 907#define BGE_RXLP_CFG 0x2010 908#define BGE_RXLP_STATS_CTL 0x2014 909#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 910#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 911#define BGE_RXLP_HEAD0 0x2100 912#define BGE_RXLP_TAIL0 0x2104 913#define BGE_RXLP_COUNT0 0x2108 914#define BGE_RXLP_HEAD1 0x2110 915#define BGE_RXLP_TAIL1 0x2114 916#define BGE_RXLP_COUNT1 0x2118 917#define BGE_RXLP_HEAD2 0x2120 918#define BGE_RXLP_TAIL2 0x2124 919#define BGE_RXLP_COUNT2 0x2128 920#define BGE_RXLP_HEAD3 0x2130 921#define BGE_RXLP_TAIL3 0x2134 922#define BGE_RXLP_COUNT3 0x2138 923#define BGE_RXLP_HEAD4 0x2140 924#define BGE_RXLP_TAIL4 0x2144 925#define BGE_RXLP_COUNT4 0x2148 926#define BGE_RXLP_HEAD5 0x2150 927#define BGE_RXLP_TAIL5 0x2154 928#define BGE_RXLP_COUNT5 0x2158 929#define BGE_RXLP_HEAD6 0x2160 930#define BGE_RXLP_TAIL6 0x2164 931#define BGE_RXLP_COUNT6 0x2168 932#define BGE_RXLP_HEAD7 0x2170 933#define BGE_RXLP_TAIL7 0x2174 934#define BGE_RXLP_COUNT7 0x2178 935#define BGE_RXLP_HEAD8 0x2180 936#define BGE_RXLP_TAIL8 0x2184 937#define BGE_RXLP_COUNT8 0x2188 938#define BGE_RXLP_HEAD9 0x2190 939#define BGE_RXLP_TAIL9 0x2194 940#define BGE_RXLP_COUNT9 0x2198 941#define BGE_RXLP_HEAD10 0x21A0 942#define BGE_RXLP_TAIL10 0x21A4 943#define BGE_RXLP_COUNT10 0x21A8 944#define BGE_RXLP_HEAD11 0x21B0 945#define BGE_RXLP_TAIL11 0x21B4 946#define BGE_RXLP_COUNT11 0x21B8 947#define BGE_RXLP_HEAD12 0x21C0 948#define BGE_RXLP_TAIL12 0x21C4 949#define BGE_RXLP_COUNT12 0x21C8 950#define BGE_RXLP_HEAD13 0x21D0 951#define BGE_RXLP_TAIL13 0x21D4 952#define BGE_RXLP_COUNT13 0x21D8 953#define BGE_RXLP_HEAD14 0x21E0 954#define BGE_RXLP_TAIL14 0x21E4 955#define BGE_RXLP_COUNT14 0x21E8 956#define BGE_RXLP_HEAD15 0x21F0 957#define BGE_RXLP_TAIL15 0x21F4 958#define BGE_RXLP_COUNT15 0x21F8 959#define BGE_RXLP_LOCSTAT_COS0 0x2200 960#define BGE_RXLP_LOCSTAT_COS1 0x2204 961#define BGE_RXLP_LOCSTAT_COS2 0x2208 962#define BGE_RXLP_LOCSTAT_COS3 0x220C 963#define BGE_RXLP_LOCSTAT_COS4 0x2210 964#define BGE_RXLP_LOCSTAT_COS5 0x2214 965#define BGE_RXLP_LOCSTAT_COS6 0x2218 966#define BGE_RXLP_LOCSTAT_COS7 0x221C 967#define BGE_RXLP_LOCSTAT_COS8 0x2220 968#define BGE_RXLP_LOCSTAT_COS9 0x2224 969#define BGE_RXLP_LOCSTAT_COS10 0x2228 970#define BGE_RXLP_LOCSTAT_COS11 0x222C 971#define BGE_RXLP_LOCSTAT_COS12 0x2230 972#define BGE_RXLP_LOCSTAT_COS13 0x2234 973#define BGE_RXLP_LOCSTAT_COS14 0x2238 974#define BGE_RXLP_LOCSTAT_COS15 0x223C 975#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 976#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 977#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 978#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 979#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 980#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 981#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 982 983 984/* Receive List Placement mode register */ 985#define BGE_RXLPMODE_RESET 0x00000001 986#define BGE_RXLPMODE_ENABLE 0x00000002 987#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 988#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 989#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 990 991/* Receive List Placement Status register */ 992#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 993#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 994#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 995 996/* 997 * Receive Data and Receive BD Initiator Control Registers 998 */ 999#define BGE_RDBDI_MODE 0x2400 1000#define BGE_RDBDI_STATUS 0x2404 1001#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1002#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1003#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1004#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1005#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1006#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1007#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1008#define BGE_RX_STD_RCB_NICADDR 0x245C 1009#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1010#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1011#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1012#define BGE_RX_MINI_RCB_NICADDR 0x246C 1013#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1014#define BGE_RDBDI_STD_RX_CONS 0x2474 1015#define BGE_RDBDI_MINI_RX_CONS 0x2478 1016#define BGE_RDBDI_RETURN_PROD0 0x2480 1017#define BGE_RDBDI_RETURN_PROD1 0x2484 1018#define BGE_RDBDI_RETURN_PROD2 0x2488 1019#define BGE_RDBDI_RETURN_PROD3 0x248C 1020#define BGE_RDBDI_RETURN_PROD4 0x2490 1021#define BGE_RDBDI_RETURN_PROD5 0x2494 1022#define BGE_RDBDI_RETURN_PROD6 0x2498 1023#define BGE_RDBDI_RETURN_PROD7 0x249C 1024#define BGE_RDBDI_RETURN_PROD8 0x24A0 1025#define BGE_RDBDI_RETURN_PROD9 0x24A4 1026#define BGE_RDBDI_RETURN_PROD10 0x24A8 1027#define BGE_RDBDI_RETURN_PROD11 0x24AC 1028#define BGE_RDBDI_RETURN_PROD12 0x24B0 1029#define BGE_RDBDI_RETURN_PROD13 0x24B4 1030#define BGE_RDBDI_RETURN_PROD14 0x24B8 1031#define BGE_RDBDI_RETURN_PROD15 0x24BC 1032#define BGE_RDBDI_HWDIAG 0x24C0 1033 1034 1035/* Receive Data and Receive BD Initiator Mode register */ 1036#define BGE_RDBDIMODE_RESET 0x00000001 1037#define BGE_RDBDIMODE_ENABLE 0x00000002 1038#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1039#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1040#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1041 1042/* Receive Data and Receive BD Initiator Status register */ 1043#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1044#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1045#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1046 1047 1048/* 1049 * Receive Data Completion Control registers 1050 */ 1051#define BGE_RDC_MODE 0x2800 1052 1053/* Receive Data Completion Mode register */ 1054#define BGE_RDCMODE_RESET 0x00000001 1055#define BGE_RDCMODE_ENABLE 0x00000002 1056#define BGE_RDCMODE_ATTN 0x00000004 1057 1058/* 1059 * Receive BD Initiator Control registers 1060 */ 1061#define BGE_RBDI_MODE 0x2C00 1062#define BGE_RBDI_STATUS 0x2C04 1063#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1064#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1065#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1066#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1067#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1068#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1069 1070/* Receive BD Initiator Mode register */ 1071#define BGE_RBDIMODE_RESET 0x00000001 1072#define BGE_RBDIMODE_ENABLE 0x00000002 1073#define BGE_RBDIMODE_ATTN 0x00000004 1074 1075/* Receive BD Initiator Status register */ 1076#define BGE_RBDISTAT_ATTN 0x00000004 1077 1078/* 1079 * Receive BD Completion Control registers 1080 */ 1081#define BGE_RBDC_MODE 0x3000 1082#define BGE_RBDC_STATUS 0x3004 1083#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1084#define BGE_RBDC_STD_BD_PROD 0x300C 1085#define BGE_RBDC_MINI_BD_PROD 0x3010 1086 1087/* Receive BD completion mode register */ 1088#define BGE_RBDCMODE_RESET 0x00000001 1089#define BGE_RBDCMODE_ENABLE 0x00000002 1090#define BGE_RBDCMODE_ATTN 0x00000004 1091 1092/* Receive BD completion status register */ 1093#define BGE_RBDCSTAT_ERROR 0x00000004 1094 1095/* 1096 * Receive List Selector Control registers 1097 */ 1098#define BGE_RXLS_MODE 0x3400 1099#define BGE_RXLS_STATUS 0x3404 1100 1101/* Receive List Selector Mode register */ 1102#define BGE_RXLSMODE_RESET 0x00000001 1103#define BGE_RXLSMODE_ENABLE 0x00000002 1104#define BGE_RXLSMODE_ATTN 0x00000004 1105 1106/* Receive List Selector Status register */ 1107#define BGE_RXLSSTAT_ERROR 0x00000004 1108 1109/* 1110 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1111 */ 1112#define BGE_MBCF_MODE 0x3800 1113#define BGE_MBCF_STATUS 0x3804 1114 1115/* Mbuf Cluster Free mode register */ 1116#define BGE_MBCFMODE_RESET 0x00000001 1117#define BGE_MBCFMODE_ENABLE 0x00000002 1118#define BGE_MBCFMODE_ATTN 0x00000004 1119 1120/* Mbuf Cluster Free status register */ 1121#define BGE_MBCFSTAT_ERROR 0x00000004 1122 1123/* 1124 * Host Coalescing Control registers 1125 */ 1126#define BGE_HCC_MODE 0x3C00 1127#define BGE_HCC_STATUS 0x3C04 1128#define BGE_HCC_RX_COAL_TICKS 0x3C08 1129#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1130#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1131#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1132#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1133#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1134#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1135#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1136#define BGE_HCC_STATS_TICKS 0x3C28 1137#define BGE_HCC_STATS_ADDR_HI 0x3C30 1138#define BGE_HCC_STATS_ADDR_LO 0x3C34 1139#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1140#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1141#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1142#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1143#define BGE_FLOW_ATTN 0x3C48 1144#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1145#define BGE_HCC_STD_BD_CONS 0x3C54 1146#define BGE_HCC_MINI_BD_CONS 0x3C58 1147#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1148#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1149#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1150#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1151#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1152#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1153#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1154#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1155#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1156#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1157#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1158#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1159#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1160#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1161#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1162#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1163#define BGE_HCC_TX_BD_CONS0 0x3CC0 1164#define BGE_HCC_TX_BD_CONS1 0x3CC4 1165#define BGE_HCC_TX_BD_CONS2 0x3CC8 1166#define BGE_HCC_TX_BD_CONS3 0x3CCC 1167#define BGE_HCC_TX_BD_CONS4 0x3CD0 1168#define BGE_HCC_TX_BD_CONS5 0x3CD4 1169#define BGE_HCC_TX_BD_CONS6 0x3CD8 1170#define BGE_HCC_TX_BD_CONS7 0x3CDC 1171#define BGE_HCC_TX_BD_CONS8 0x3CE0 1172#define BGE_HCC_TX_BD_CONS9 0x3CE4 1173#define BGE_HCC_TX_BD_CONS10 0x3CE8 1174#define BGE_HCC_TX_BD_CONS11 0x3CEC 1175#define BGE_HCC_TX_BD_CONS12 0x3CF0 1176#define BGE_HCC_TX_BD_CONS13 0x3CF4 1177#define BGE_HCC_TX_BD_CONS14 0x3CF8 1178#define BGE_HCC_TX_BD_CONS15 0x3CFC 1179 1180 1181/* Host coalescing mode register */ 1182#define BGE_HCCMODE_RESET 0x00000001 1183#define BGE_HCCMODE_ENABLE 0x00000002 1184#define BGE_HCCMODE_ATTN 0x00000004 1185#define BGE_HCCMODE_COAL_NOW 0x00000008 1186#define BGE_HCCMODE_MSI_BITS 0x0x000070 1187#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1188 1189#define BGE_STATBLKSZ_FULL 0x00000000 1190#define BGE_STATBLKSZ_64BYTE 0x00000080 1191#define BGE_STATBLKSZ_32BYTE 0x00000100 1192 1193/* Host coalescing status register */ 1194#define BGE_HCCSTAT_ERROR 0x00000004 1195 1196/* Flow attention register */ 1197#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1198#define BGE_FLOWATTN_MEMARB 0x00000080 1199#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1200#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1201#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1202#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1203#define BGE_FLOWATTN_RDBDI 0x00080000 1204#define BGE_FLOWATTN_RXLS 0x00100000 1205#define BGE_FLOWATTN_RXLP 0x00200000 1206#define BGE_FLOWATTN_RBDC 0x00400000 1207#define BGE_FLOWATTN_RBDI 0x00800000 1208#define BGE_FLOWATTN_SDC 0x08000000 1209#define BGE_FLOWATTN_SDI 0x10000000 1210#define BGE_FLOWATTN_SRS 0x20000000 1211#define BGE_FLOWATTN_SBDC 0x40000000 1212#define BGE_FLOWATTN_SBDI 0x80000000 1213 1214/* 1215 * Memory arbiter registers 1216 */ 1217#define BGE_MARB_MODE 0x4000 1218#define BGE_MARB_STATUS 0x4004 1219#define BGE_MARB_TRAPADDR_HI 0x4008 1220#define BGE_MARB_TRAPADDR_LO 0x400C 1221 1222/* Memory arbiter mode register */ 1223#define BGE_MARBMODE_RESET 0x00000001 1224#define BGE_MARBMODE_ENABLE 0x00000002 1225#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1226#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1227#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1228#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1229#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1230#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1231#define BGE_MARBMODE_PCI_TRAP 0x00000100 1232#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1233#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1234#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1235#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1236#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1237#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1238#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1239#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1240#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1241#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1242#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1243#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1244#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1245#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1246#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1247#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1248#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1249 1250/* Memory arbiter status register */ 1251#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1252#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1253#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1254#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1255#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1256#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1257#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1258#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1259#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1260#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1261#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1262#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1263#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1264#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1265#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1266#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1267#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1268#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1269#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1270#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1271#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1272#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1273#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1274#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1275 1276/* 1277 * Buffer manager control registers 1278 */ 1279#define BGE_BMAN_MODE 0x4400 1280#define BGE_BMAN_STATUS 0x4404 1281#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1282#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1283#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1284#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1285#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1286#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1287#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1288#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1289#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1290#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1291#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1292#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1293#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1294#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1295#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1296#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1297#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1298#define BGE_BMAN_HWDIAG_1 0x444C 1299#define BGE_BMAN_HWDIAG_2 0x4450 1300#define BGE_BMAN_HWDIAG_3 0x4454 1301 1302/* Buffer manager mode register */ 1303#define BGE_BMANMODE_RESET 0x00000001 1304#define BGE_BMANMODE_ENABLE 0x00000002 1305#define BGE_BMANMODE_ATTN 0x00000004 1306#define BGE_BMANMODE_TESTMODE 0x00000008 1307#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1308 1309/* Buffer manager status register */ 1310#define BGE_BMANSTAT_ERRO 0x00000004 1311#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1312 1313 1314/* 1315 * Read DMA Control registers 1316 */ 1317#define BGE_RDMA_MODE 0x4800 1318#define BGE_RDMA_STATUS 0x4804 1319 1320/* Read DMA mode register */ 1321#define BGE_RDMAMODE_RESET 0x00000001 1322#define BGE_RDMAMODE_ENABLE 0x00000002 1323#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1324#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1325#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1326#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1327#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1328#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1329#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1330#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1331#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1332 1333/* Read DMA status register */ 1334#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1335#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1336#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1337#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1338#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1339#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1340#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1341#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1342 1343/* 1344 * Write DMA control registers 1345 */ 1346#define BGE_WDMA_MODE 0x4C00 1347#define BGE_WDMA_STATUS 0x4C04 1348 1349/* Write DMA mode register */ 1350#define BGE_WDMAMODE_RESET 0x00000001 1351#define BGE_WDMAMODE_ENABLE 0x00000002 1352#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1353#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1354#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1355#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1356#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1357#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1358#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1359#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1360#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1361 1362/* Write DMA status register */ 1363#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1364#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1365#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1366#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1367#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1368#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1369#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1370#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1371 1372 1373/* 1374 * RX CPU registers 1375 */ 1376#define BGE_RXCPU_MODE 0x5000 1377#define BGE_RXCPU_STATUS 0x5004 1378#define BGE_RXCPU_PC 0x501C 1379 1380/* RX CPU mode register */ 1381#define BGE_RXCPUMODE_RESET 0x00000001 1382#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1383#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1384#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1385#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1386#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1387#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1388#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1389#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1390#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1391#define BGE_RXCPUMODE_HALTCPU 0x00000400 1392#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1393#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1394#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1395 1396/* RX CPU status register */ 1397#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1398#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1399#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1400#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1401#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1402#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1403#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1404#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1405#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1406#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1407#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1408#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1409#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1410#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1411#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1412#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1413#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1414 1415 1416/* 1417 * TX CPU registers 1418 */ 1419#define BGE_TXCPU_MODE 0x5400 1420#define BGE_TXCPU_STATUS 0x5404 1421#define BGE_TXCPU_PC 0x541C 1422 1423/* TX CPU mode register */ 1424#define BGE_TXCPUMODE_RESET 0x00000001 1425#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1426#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1427#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1428#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1429#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1430#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1431#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1432#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1433#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1434#define BGE_TXCPUMODE_HALTCPU 0x00000400 1435#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1436#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1437 1438/* TX CPU status register */ 1439#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1440#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1441#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1442#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1443#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1444#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1445#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1446#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1447#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1448#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1449#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1450#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1451#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1452#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1453#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1454#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1455#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1456 1457 1458/* 1459 * Low priority mailbox registers 1460 */ 1461#define BGE_LPMBX_IRQ0_HI 0x5800 1462#define BGE_LPMBX_IRQ0_LO 0x5804 1463#define BGE_LPMBX_IRQ1_HI 0x5808 1464#define BGE_LPMBX_IRQ1_LO 0x580C 1465#define BGE_LPMBX_IRQ2_HI 0x5810 1466#define BGE_LPMBX_IRQ2_LO 0x5814 1467#define BGE_LPMBX_IRQ3_HI 0x5818 1468#define BGE_LPMBX_IRQ3_LO 0x581C 1469#define BGE_LPMBX_GEN0_HI 0x5820 1470#define BGE_LPMBX_GEN0_LO 0x5824 1471#define BGE_LPMBX_GEN1_HI 0x5828 1472#define BGE_LPMBX_GEN1_LO 0x582C 1473#define BGE_LPMBX_GEN2_HI 0x5830 1474#define BGE_LPMBX_GEN2_LO 0x5834 1475#define BGE_LPMBX_GEN3_HI 0x5828 1476#define BGE_LPMBX_GEN3_LO 0x582C 1477#define BGE_LPMBX_GEN4_HI 0x5840 1478#define BGE_LPMBX_GEN4_LO 0x5844 1479#define BGE_LPMBX_GEN5_HI 0x5848 1480#define BGE_LPMBX_GEN5_LO 0x584C 1481#define BGE_LPMBX_GEN6_HI 0x5850 1482#define BGE_LPMBX_GEN6_LO 0x5854 1483#define BGE_LPMBX_GEN7_HI 0x5858 1484#define BGE_LPMBX_GEN7_LO 0x585C 1485#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1486#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1487#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1488#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1489#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1490#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1491#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1492#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1493#define BGE_LPMBX_RX_CONS0_HI 0x5880 1494#define BGE_LPMBX_RX_CONS0_LO 0x5884 1495#define BGE_LPMBX_RX_CONS1_HI 0x5888 1496#define BGE_LPMBX_RX_CONS1_LO 0x588C 1497#define BGE_LPMBX_RX_CONS2_HI 0x5890 1498#define BGE_LPMBX_RX_CONS2_LO 0x5894 1499#define BGE_LPMBX_RX_CONS3_HI 0x5898 1500#define BGE_LPMBX_RX_CONS3_LO 0x589C 1501#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1502#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1503#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1504#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1505#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1506#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1507#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1508#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1509#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1510#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1511#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1512#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1513#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1514#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1515#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1516#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1517#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1518#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1519#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1520#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1521#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1522#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1523#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1524#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1525#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1526#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1527#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1528#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1529#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1530#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1531#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1532#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1533#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1534#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1535#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1536#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1537#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1538#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1539#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1540#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1541#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1542#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1543#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1544#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1545#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1546#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1547#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1548#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1549#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1550#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1551#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1552#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1553#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1554#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1555#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1556#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1557#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1558#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1559#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1560#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1561#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1562#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1563#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1564#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1565#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1566#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1567#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1568#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1569#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1570#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1571#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1572#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1573#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1574#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1575#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1576#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1577#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1578#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1579#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1580#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1581#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1582#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1583#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1584#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1585#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1586#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1587#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1588#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1589 1590/* 1591 * Flow throw Queue reset register 1592 */ 1593#define BGE_FTQ_RESET 0x5C00 1594 1595#define BGE_FTQRESET_DMAREAD 0x00000002 1596#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1597#define BGE_FTQRESET_DMADONE 0x00000010 1598#define BGE_FTQRESET_SBDC 0x00000020 1599#define BGE_FTQRESET_SDI 0x00000040 1600#define BGE_FTQRESET_WDMA 0x00000080 1601#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1602#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1603#define BGE_FTQRESET_SDC 0x00000400 1604#define BGE_FTQRESET_HCC 0x00000800 1605#define BGE_FTQRESET_TXFIFO 0x00001000 1606#define BGE_FTQRESET_MBC 0x00002000 1607#define BGE_FTQRESET_RBDC 0x00004000 1608#define BGE_FTQRESET_RXLP 0x00008000 1609#define BGE_FTQRESET_RDBDI 0x00010000 1610#define BGE_FTQRESET_RDC 0x00020000 1611#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1612 1613/* 1614 * Message Signaled Interrupt registers 1615 */ 1616#define BGE_MSI_MODE 0x6000 1617#define BGE_MSI_STATUS 0x6004 1618#define BGE_MSI_FIFOACCESS 0x6008 1619 1620/* MSI mode register */ 1621#define BGE_MSIMODE_RESET 0x00000001 1622#define BGE_MSIMODE_ENABLE 0x00000002 1623#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1624#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1625#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1626#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1627#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1628 1629/* MSI status register */ 1630#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1631#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1632#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1633#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1634#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1635 1636 1637/* 1638 * DMA Completion registers 1639 */ 1640#define BGE_DMAC_MODE 0x6400 1641 1642/* DMA Completion mode register */ 1643#define BGE_DMACMODE_RESET 0x00000001 1644#define BGE_DMACMODE_ENABLE 0x00000002 1645 1646 1647/* 1648 * General control registers. 1649 */ 1650#define BGE_MODE_CTL 0x6800 1651#define BGE_MISC_CFG 0x6804 1652#define BGE_MISC_LOCAL_CTL 0x6808 1653#define BGE_EE_ADDR 0x6838 1654#define BGE_EE_DATA 0x683C 1655#define BGE_EE_CTL 0x6840 1656#define BGE_MDI_CTL 0x6844 1657#define BGE_EE_DELAY 0x6848 1658 1659/* Mode control register */ 1660#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1661#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1662#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1663#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1664#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1665#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1666#define BGE_MODECTL_NO_RX_CRC 0x00000400 1667#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1668#define BGE_MODECTL_NO_TX_INTR 0x00002000 1669#define BGE_MODECTL_NO_RX_INTR 0x00004000 1670#define BGE_MODECTL_FORCE_PCI32 0x00008000 1671#define BGE_MODECTL_STACKUP 0x00010000 1672#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1673#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1674#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1675#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1676#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1677#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1678#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1679#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1680#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1681#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1682 1683/* Misc. config register */ 1684#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1685#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1686 1687#define BGE_32BITTIME_66MHZ (0x41 << 1) 1688 1689/* Misc. Local Control */ 1690#define BGE_MLC_INTR_STATE 0x00000001 1691#define BGE_MLC_INTR_CLR 0x00000002 1692#define BGE_MLC_INTR_SET 0x00000004 1693#define BGE_MLC_INTR_ONATTN 0x00000008 1694#define BGE_MLC_MISCIO_IN0 0x00000100 1695#define BGE_MLC_MISCIO_IN1 0x00000200 1696#define BGE_MLC_MISCIO_IN2 0x00000400 1697#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1698#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1699#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1700#define BGE_MLC_MISCIO_OUT0 0x00004000 1701#define BGE_MLC_MISCIO_OUT1 0x00008000 1702#define BGE_MLC_MISCIO_OUT2 0x00010000 1703#define BGE_MLC_EXTRAM_ENB 0x00020000 1704#define BGE_MLC_SRAM_SIZE 0x001C0000 1705#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1706#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1707#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1708#define BGE_MLC_AUTO_EEPROM 0x01000000 1709 1710#define BGE_SSRAMSIZE_256KB 0x00000000 1711#define BGE_SSRAMSIZE_512KB 0x00040000 1712#define BGE_SSRAMSIZE_1MB 0x00080000 1713#define BGE_SSRAMSIZE_2MB 0x000C0000 1714#define BGE_SSRAMSIZE_4MB 0x00100000 1715#define BGE_SSRAMSIZE_8MB 0x00140000 1716#define BGE_SSRAMSIZE_16M 0x00180000 1717 1718/* EEPROM address register */ 1719#define BGE_EEADDR_ADDRESS 0x0000FFFC 1720#define BGE_EEADDR_HALFCLK 0x01FF0000 1721#define BGE_EEADDR_START 0x02000000 1722#define BGE_EEADDR_DEVID 0x1C000000 1723#define BGE_EEADDR_RESET 0x20000000 1724#define BGE_EEADDR_DONE 0x40000000 1725#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1726 1727#define BGE_EEDEVID(x) ((x & 7) << 26) 1728#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1729#define BGE_HALFCLK_384SCL 0x60 1730#define BGE_EE_READCMD \ 1731 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1732 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1733#define BGE_EE_WRCMD \ 1734 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1735 BGE_EEADDR_START|BGE_EEADDR_DONE) 1736 1737/* EEPROM Control register */ 1738#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1739#define BGE_EECTL_CLKOUT 0x00000002 1740#define BGE_EECTL_CLKIN 0x00000004 1741#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1742#define BGE_EECTL_DATAOUT 0x00000010 1743#define BGE_EECTL_DATAIN 0x00000020 1744 1745/* MDI (MII/GMII) access register */ 1746#define BGE_MDI_DATA 0x00000001 1747#define BGE_MDI_DIR 0x00000002 1748#define BGE_MDI_SEL 0x00000004 1749#define BGE_MDI_CLK 0x00000008 1750 1751#define BGE_MEMWIN_START 0x00008000 1752#define BGE_MEMWIN_END 0x0000FFFF 1753 1754 1755#define BGE_MEMWIN_READ(pc, tag, x, val) \ 1756 do { \ 1757 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1758 (0xFFFF0000 & x)); \ 1759 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1760 } while(0) 1761 1762#define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 1763 do { \ 1764 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1765 (0xFFFF0000 & x)); \ 1766 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1767 } while(0) 1768 1769/* 1770 * This magic number is used to prevent PXE restart when we 1771 * issue a software reset. We write this magic number to the 1772 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1773 * code from running. 1774 */ 1775#define BGE_MAGIC_NUMBER 0x4B657654 1776 1777typedef struct { 1778 u_int32_t bge_addr_hi; 1779 u_int32_t bge_addr_lo; 1780} bge_hostaddr; 1781#define BGE_HOSTADDR(x,y) \ 1782 do { \ 1783 (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 1784 if (sizeof(bus_addr_t) == 8) \ 1785 (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 1786 else \ 1787 (x).bge_addr_hi = 0; \ 1788 } while(0) 1789 1790/* Ring control block structure */ 1791struct bge_rcb { 1792 bge_hostaddr bge_hostaddr; 1793 u_int32_t bge_maxlen_flags; 1794 u_int32_t bge_nicaddr; 1795}; 1796 1797#define RCB_WRITE_4(sc, rcb, offset, val) \ 1798 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1799 rcb + offsetof(struct bge_rcb, offset), val) 1800 1801#define RCB_WRITE_2(sc, rcb, offset, val) \ 1802 bus_space_write_2(sc->bge_btag, sc->bge_bhandle, \ 1803 rcb + offsetof(struct bge_rcb, offset), val) 1804 1805#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1806 1807#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1808#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1809 1810struct bge_tx_bd { 1811 bge_hostaddr bge_addr; 1812#if BYTE_ORDER == LITTLE_ENDIAN 1813 u_int16_t bge_flags; 1814 u_int16_t bge_len; 1815 u_int16_t bge_vlan_tag; 1816 u_int16_t bge_rsvd; 1817#else 1818 u_int16_t bge_len; 1819 u_int16_t bge_flags; 1820 u_int16_t bge_rsvd; 1821 u_int16_t bge_vlan_tag; 1822#endif 1823}; 1824 1825#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1826#define BGE_TXBDFLAG_IP_CSUM 0x0002 1827#define BGE_TXBDFLAG_END 0x0004 1828#define BGE_TXBDFLAG_IP_FRAG 0x0008 1829#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1830#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1831#define BGE_TXBDFLAG_COAL_NOW 0x0080 1832#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1833#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1834#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1835#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1836#define BGE_TXBDFLAG_NO_CRC 0x8000 1837 1838#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1839 BGE_SEND_RING_1_TO_4 + \ 1840 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1841 1842struct bge_rx_bd { 1843 bge_hostaddr bge_addr; 1844#if BYTE_ORDER == LITTLE_ENDIAN 1845 u_int16_t bge_len; 1846 u_int16_t bge_idx; 1847 u_int16_t bge_flags; 1848 u_int16_t bge_type; 1849 u_int16_t bge_tcp_udp_csum; 1850 u_int16_t bge_ip_csum; 1851 u_int16_t bge_vlan_tag; 1852 u_int16_t bge_error_flag; 1853#else 1854 u_int16_t bge_idx; 1855 u_int16_t bge_len; 1856 u_int16_t bge_type; 1857 u_int16_t bge_flags; 1858 u_int16_t bge_ip_csum; 1859 u_int16_t bge_tcp_udp_csum; 1860 u_int16_t bge_error_flag; 1861 u_int16_t bge_vlan_tag; 1862#endif 1863 u_int32_t bge_rsvd; 1864 u_int32_t bge_opaque; 1865}; 1866 1867#define BGE_RXBDFLAG_END 0x0004 1868#define BGE_RXBDFLAG_JUMBO_RING 0x0020 1869#define BGE_RXBDFLAG_VLAN_TAG 0x0040 1870#define BGE_RXBDFLAG_ERROR 0x0400 1871#define BGE_RXBDFLAG_MINI_RING 0x0800 1872#define BGE_RXBDFLAG_IP_CSUM 0x1000 1873#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1874#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1875 1876#define BGE_RXERRFLAG_BAD_CRC 0x0001 1877#define BGE_RXERRFLAG_COLL_DETECT 0x0002 1878#define BGE_RXERRFLAG_LINK_LOST 0x0004 1879#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1880#define BGE_RXERRFLAG_MAC_ABORT 0x0010 1881#define BGE_RXERRFLAG_RUNT 0x0020 1882#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1883#define BGE_RXERRFLAG_GIANT 0x0080 1884 1885struct bge_sts_idx { 1886#if BYTE_ORDER == LITTLE_ENDIAN 1887 u_int16_t bge_rx_prod_idx; 1888 u_int16_t bge_tx_cons_idx; 1889#else 1890 u_int16_t bge_tx_cons_idx; 1891 u_int16_t bge_rx_prod_idx; 1892#endif 1893}; 1894 1895struct bge_status_block { 1896 u_int32_t bge_status; 1897 u_int32_t bge_rsvd0; 1898#if BYTE_ORDER == LITTLE_ENDIAN 1899 u_int16_t bge_rx_jumbo_cons_idx; 1900 u_int16_t bge_rx_std_cons_idx; 1901 u_int16_t bge_rx_mini_cons_idx; 1902 u_int16_t bge_rsvd1; 1903#else 1904 u_int16_t bge_rx_std_cons_idx; 1905 u_int16_t bge_rx_jumbo_cons_idx; 1906 u_int16_t bge_rsvd1; 1907 u_int16_t bge_rx_mini_cons_idx; 1908#endif 1909 struct bge_sts_idx bge_idx[16]; 1910}; 1911 1912#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1913#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1914 1915#define BGE_STATFLAG_UPDATED 0x00000001 1916#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1917#define BGE_STATFLAG_ERROR 0x00000004 1918 1919/* 1920 * SysKonnect Subsystem IDs 1921 */ 1922#define SK_SUBSYSID_9D21 0x4421 1923#define SK_SUBSYSID_9D41 0x4441 1924 1925/* 1926 * Offset of MAC address inside EEPROM. 1927 */ 1928#define BGE_EE_MAC_OFFSET 0x7C 1929#define BGE_EE_HWCFG_OFFSET 0xC8 1930 1931#define BGE_HWCFG_VOLTAGE 0x00000003 1932#define BGE_HWCFG_PHYLED_MODE 0x0000000C 1933#define BGE_HWCFG_MEDIA 0x00000030 1934 1935#define BGE_VOLTAGE_1POINT3 0x00000000 1936#define BGE_VOLTAGE_1POINT8 0x00000001 1937 1938#define BGE_PHYLEDMODE_UNSPEC 0x00000000 1939#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 1940#define BGE_PHYLEDMODE_SINGLELED 0x00000008 1941 1942#define BGE_MEDIA_UNSPEC 0x00000000 1943#define BGE_MEDIA_COPPER 0x00000010 1944#define BGE_MEDIA_FIBER 0x00000020 1945 1946#define BGE_PCI_READ_CMD 0x06000000 1947#define BGE_PCI_WRITE_CMD 0x70000000 1948 1949#define BGE_TICKS_PER_SEC 1000000 1950 1951/* 1952 * Ring size constants. 1953 */ 1954#define BGE_EVENT_RING_CNT 256 1955#define BGE_CMD_RING_CNT 64 1956#define BGE_STD_RX_RING_CNT 512 1957#define BGE_JUMBO_RX_RING_CNT 256 1958#define BGE_MINI_RX_RING_CNT 1024 1959#define BGE_RETURN_RING_CNT 1024 1960 1961/* 5705 has smaller return ring size */ 1962#define BGE_RETURN_RING_CNT_5705 512 1963 1964/* 1965 * Possible TX ring sizes. 1966 */ 1967#define BGE_TX_RING_CNT_128 128 1968#define BGE_TX_RING_BASE_128 0x3800 1969 1970#define BGE_TX_RING_CNT_256 256 1971#define BGE_TX_RING_BASE_256 0x3000 1972 1973#define BGE_TX_RING_CNT_512 512 1974#define BGE_TX_RING_BASE_512 0x2000 1975 1976#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 1977#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 1978 1979/* 1980 * Tigon III statistics counters. 1981 */ 1982/* Statistics maintained MAC Receive block. */ 1983struct bge_rx_mac_stats { 1984 bge_hostaddr ifHCInOctets; 1985 bge_hostaddr Reserved1; 1986 bge_hostaddr etherStatsFragments; 1987 bge_hostaddr ifHCInUcastPkts; 1988 bge_hostaddr ifHCInMulticastPkts; 1989 bge_hostaddr ifHCInBroadcastPkts; 1990 bge_hostaddr dot3StatsFCSErrors; 1991 bge_hostaddr dot3StatsAlignmentErrors; 1992 bge_hostaddr xonPauseFramesReceived; 1993 bge_hostaddr xoffPauseFramesReceived; 1994 bge_hostaddr macControlFramesReceived; 1995 bge_hostaddr xoffStateEntered; 1996 bge_hostaddr dot3StatsFramesTooLong; 1997 bge_hostaddr etherStatsJabbers; 1998 bge_hostaddr etherStatsUndersizePkts; 1999 bge_hostaddr inRangeLengthError; 2000 bge_hostaddr outRangeLengthError; 2001 bge_hostaddr etherStatsPkts64Octets; 2002 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2003 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2004 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2005 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2006 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2007 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2008 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2009 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2010 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2011}; 2012 2013/* Statistics maintained MAC Transmit block. */ 2014struct bge_tx_mac_stats { 2015 bge_hostaddr ifHCOutOctets; 2016 bge_hostaddr Reserved2; 2017 bge_hostaddr etherStatsCollisions; 2018 bge_hostaddr outXonSent; 2019 bge_hostaddr outXoffSent; 2020 bge_hostaddr flowControlDone; 2021 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2022 bge_hostaddr dot3StatsSingleCollisionFrames; 2023 bge_hostaddr dot3StatsMultipleCollisionFrames; 2024 bge_hostaddr dot3StatsDeferredTransmissions; 2025 bge_hostaddr Reserved3; 2026 bge_hostaddr dot3StatsExcessiveCollisions; 2027 bge_hostaddr dot3StatsLateCollisions; 2028 bge_hostaddr dot3Collided2Times; 2029 bge_hostaddr dot3Collided3Times; 2030 bge_hostaddr dot3Collided4Times; 2031 bge_hostaddr dot3Collided5Times; 2032 bge_hostaddr dot3Collided6Times; 2033 bge_hostaddr dot3Collided7Times; 2034 bge_hostaddr dot3Collided8Times; 2035 bge_hostaddr dot3Collided9Times; 2036 bge_hostaddr dot3Collided10Times; 2037 bge_hostaddr dot3Collided11Times; 2038 bge_hostaddr dot3Collided12Times; 2039 bge_hostaddr dot3Collided13Times; 2040 bge_hostaddr dot3Collided14Times; 2041 bge_hostaddr dot3Collided15Times; 2042 bge_hostaddr ifHCOutUcastPkts; 2043 bge_hostaddr ifHCOutMulticastPkts; 2044 bge_hostaddr ifHCOutBroadcastPkts; 2045 bge_hostaddr dot3StatsCarrierSenseErrors; 2046 bge_hostaddr ifOutDiscards; 2047 bge_hostaddr ifOutErrors; 2048}; 2049 2050/* Stats counters access through registers */ 2051struct bge_mac_stats_regs { 2052 u_int32_t ifHCOutOctets; 2053 u_int32_t Reserved0; 2054 u_int32_t etherStatsCollisions; 2055 u_int32_t outXonSent; 2056 u_int32_t outXoffSent; 2057 u_int32_t Reserved1; 2058 u_int32_t dot3StatsInternalMacTransmitErrors; 2059 u_int32_t dot3StatsSingleCollisionFrames; 2060 u_int32_t dot3StatsMultipleCollisionFrames; 2061 u_int32_t dot3StatsDeferredTransmissions; 2062 u_int32_t Reserved2; 2063 u_int32_t dot3StatsExcessiveCollisions; 2064 u_int32_t dot3StatsLateCollisions; 2065 u_int32_t Reserved3[14]; 2066 u_int32_t ifHCOutUcastPkts; 2067 u_int32_t ifHCOutMulticastPkts; 2068 u_int32_t ifHCOutBroadcastPkts; 2069 u_int32_t Reserved4[2]; 2070 u_int32_t ifHCInOctets; 2071 u_int32_t Reserved5; 2072 u_int32_t etherStatsFragments; 2073 u_int32_t ifHCInUcastPkts; 2074 u_int32_t ifHCInMulticastPkts; 2075 u_int32_t ifHCInBroadcastPkts; 2076 u_int32_t dot3StatsFCSErrors; 2077 u_int32_t dot3StatsAlignmentErrors; 2078 u_int32_t xonPauseFramesReceived; 2079 u_int32_t xoffPauseFramesReceived; 2080 u_int32_t macControlFramesReceived; 2081 u_int32_t xoffStateEntered; 2082 u_int32_t dot3StatsFramesTooLong; 2083 u_int32_t etherStatsJabbers; 2084 u_int32_t etherStatsUndersizePkts; 2085}; 2086 2087struct bge_stats { 2088 u_int8_t Reserved0[256]; 2089 2090 /* Statistics maintained by Receive MAC. */ 2091 struct bge_rx_mac_stats rxstats; 2092 2093 bge_hostaddr Unused1[37]; 2094 2095 /* Statistics maintained by Transmit MAC. */ 2096 struct bge_tx_mac_stats txstats; 2097 2098 bge_hostaddr Unused2[31]; 2099 2100 /* Statistics maintained by Receive List Placement. */ 2101 bge_hostaddr COSIfHCInPkts[16]; 2102 bge_hostaddr COSFramesDroppedDueToFilters; 2103 bge_hostaddr nicDmaWriteQueueFull; 2104 bge_hostaddr nicDmaWriteHighPriQueueFull; 2105 bge_hostaddr nicNoMoreRxBDs; 2106 bge_hostaddr ifInDiscards; 2107 bge_hostaddr ifInErrors; 2108 bge_hostaddr nicRecvThresholdHit; 2109 2110 bge_hostaddr Unused3[9]; 2111 2112 /* Statistics maintained by Send Data Initiator. */ 2113 bge_hostaddr COSIfHCOutPkts[16]; 2114 bge_hostaddr nicDmaReadQueueFull; 2115 bge_hostaddr nicDmaReadHighPriQueueFull; 2116 bge_hostaddr nicSendDataCompQueueFull; 2117 2118 /* Statistics maintained by Host Coalescing. */ 2119 bge_hostaddr nicRingSetSendProdIndex; 2120 bge_hostaddr nicRingStatusUpdate; 2121 bge_hostaddr nicInterrupts; 2122 bge_hostaddr nicAvoidedInterrupts; 2123 bge_hostaddr nicSendThresholdHit; 2124 2125 u_int8_t Reserved4[320]; 2126}; 2127 2128/* 2129 * Tigon general information block. This resides in host memory 2130 * and contains the status counters, ring control blocks and 2131 * producer pointers. 2132 */ 2133 2134struct bge_gib { 2135 struct bge_stats bge_stats; 2136 struct bge_rcb bge_tx_rcb[16]; 2137 struct bge_rcb bge_std_rx_rcb; 2138 struct bge_rcb bge_jumbo_rx_rcb; 2139 struct bge_rcb bge_mini_rx_rcb; 2140 struct bge_rcb bge_return_rcb; 2141}; 2142 2143/* 2144 * NOTE! On the Alpha, we have an alignment constraint. 2145 * The first thing in the packet is a 14-byte Ethernet header. 2146 * This means that the packet is misaligned. To compensate, 2147 * we actually offset the data 2 bytes into the cluster. This 2148 * alignes the packet after the Ethernet header at a 32-bit 2149 * boundary. 2150 */ 2151 2152#define BGE_PAGE_SIZE PAGE_SIZE 2153#define BGE_MIN_FRAMELEN 60 2154 2155/* 2156 * Other utility macros. 2157 */ 2158#define BGE_INC(x, y) (x) = (x + 1) % y 2159 2160/* 2161 * Vital product data and structures. 2162 */ 2163#define BGE_VPD_FLAG 0x8000 2164 2165/* VPD structures */ 2166struct vpd_res { 2167 u_int8_t vr_id; 2168 u_int8_t vr_len; 2169 u_int8_t vr_pad; 2170}; 2171 2172struct vpd_key { 2173 char vk_key[2]; 2174 u_int8_t vk_len; 2175}; 2176 2177#define VPD_RES_ID 0x82 /* ID string */ 2178#define VPD_RES_READ 0x90 /* start of read only area */ 2179#define VPD_RES_WRITE 0x81 /* start of read/write area */ 2180#define VPD_RES_END 0x78 /* end tag */ 2181 2182 2183/* 2184 * Register access macros. The Tigon always uses memory mapped register 2185 * accesses and all registers must be accessed with 32 bit operations. 2186 */ 2187 2188#define CSR_WRITE_4(sc, reg, val) \ 2189 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2190 2191#define CSR_READ_4(sc, reg) \ 2192 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2193 2194#define BGE_SETBIT(sc, reg, x) \ 2195 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2196#define BGE_CLRBIT(sc, reg, x) \ 2197 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2198 2199#define PCI_SETBIT(pc, tag, reg, x) \ 2200 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 2201#define PCI_CLRBIT(pc, tag, reg, x) \ 2202 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 2203 2204/* 2205 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2206 * values are tuneable. They control the actual amount of buffers 2207 * allocated for the standard, mini and jumbo receive rings. 2208 */ 2209 2210#define BGE_SSLOTS 256 2211#define BGE_MSLOTS 256 2212#ifdef __sparc64__ 2213#define BGE_JSLOTS 54 2214#else 2215#define BGE_JSLOTS 384 2216#endif 2217 2218#define BGE_JRAWLEN (ETHER_MAX_LEN_JUMBO + ETHER_ALIGN) 2219#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2220 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2221#define BGE_JPAGESZ PAGE_SIZE 2222#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2223#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2224 2225/* 2226 * Ring structures. Most of these reside in host memory and we tell 2227 * the NIC where they are via the ring control blocks. The exceptions 2228 * are the tx and command rings, which live in NIC memory and which 2229 * we access via the shared memory window. 2230 */ 2231struct bge_ring_data { 2232 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2233 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2234 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2235 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2236 struct bge_status_block bge_status_block; 2237 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2238 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2239 struct bge_gib bge_info; 2240}; 2241 2242#define BGE_RING_DMA_ADDR(sc, offset) \ 2243 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2244 offsetof(struct bge_ring_data, offset)) 2245 2246/* 2247 * Number of DMA segments in a TxCB. Note that this is carefully 2248 * chosen to make the total struct size an even power of two. It's 2249 * critical that no TxCB be split across a page boundary since 2250 * no attempt is made to allocate physically contiguous memory. 2251 * 2252 */ 2253#ifdef __LP64__ 2254#define BGE_NTXSEG 30 2255#else 2256#define BGE_NTXSEG 31 2257#endif 2258 2259/* 2260 * Mbuf pointers. We need these to keep track of the virtual addresses 2261 * of our mbuf chains since we can only convert from physical to virtual, 2262 * not the other way around. 2263 */ 2264struct bge_chain_data { 2265 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2266 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2267 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2268 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2269 bus_dmamap_t bge_tx_map[BGE_TX_RING_CNT]; 2270 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2271 bus_dmamap_t bge_rx_jumbo_map; 2272 /* Stick the jumbo mem management stuff here too. */ 2273 caddr_t bge_jslots[BGE_JSLOTS]; 2274 void *bge_jumbo_buf; 2275}; 2276 2277#define BGE_JUMBO_DMA_ADDR(sc, m) \ 2278 ((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \ 2279 (mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf)) 2280 2281struct bge_type { 2282 u_int16_t bge_vid; 2283 u_int16_t bge_did; 2284 char *bge_name; 2285}; 2286 2287#define BGE_TIMEOUT 100000 2288#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2289 2290struct bge_jpool_entry { 2291 int slot; 2292 SLIST_ENTRY(bge_jpool_entry) jpool_entries; 2293}; 2294 2295struct txdmamap_pool_entry { 2296 bus_dmamap_t dmamap; 2297 SLIST_ENTRY(txdmamap_pool_entry) link; 2298}; 2299 2300/* 2301 * Flags for bge_flags. 2302 */ 2303#define BGE_TXRING_VALID 0x0001 2304#define BGE_RXRING_VALID 0x0002 2305#define BGE_JUMBO_RXRING_VALID 0x0004 2306 2307struct bge_softc { 2308 struct device bge_dev; 2309 struct arpcom arpcom; /* interface info */ 2310 bus_space_handle_t bge_bhandle; 2311 bus_space_tag_t bge_btag; 2312 void *bge_intrhand; 2313 struct pci_attach_args bge_pa; 2314 struct mii_data bge_mii; 2315 struct ifmedia bge_ifmedia; /* media info */ 2316 u_int8_t bge_extram; /* has external SSRAM */ 2317 u_int8_t bge_tbi; 2318 u_int8_t bge_rx_alignment_bug; 2319 bus_dma_tag_t bge_dmatag; 2320 u_int32_t bge_chipid; 2321 u_int32_t bge_quirks; 2322 u_int8_t bge_no_3_led; 2323 u_int8_t bge_pcie; 2324 struct bge_ring_data *bge_rdata; /* rings */ 2325 struct bge_chain_data bge_cdata; /* mbufs */ 2326 bus_dmamap_t bge_ring_map; 2327 u_int16_t bge_tx_saved_considx; 2328 u_int16_t bge_rx_saved_considx; 2329 u_int16_t bge_ev_saved_considx; 2330 u_int16_t bge_return_ring_cnt; 2331 u_int16_t bge_std; /* current std ring head */ 2332 u_int16_t bge_jumbo; /* current jumo ring head */ 2333 SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2334 SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2335 u_int32_t bge_stat_ticks; 2336 u_int32_t bge_rx_coal_ticks; 2337 u_int32_t bge_tx_coal_ticks; 2338 u_int32_t bge_rx_max_coal_bds; 2339 u_int32_t bge_tx_max_coal_bds; 2340 u_int32_t bge_tx_buf_ratio; 2341 int bge_if_flags; 2342 int bge_flags; 2343 int bge_txcnt; 2344 int bge_link; 2345 struct timeout bge_timeout; 2346 char *bge_vpd_prodname; 2347 char *bge_vpd_readonly; 2348 SLIST_HEAD(, txdmamap_pool_entry) txdma_list; 2349 struct txdmamap_pool_entry *txdma[BGE_TX_RING_CNT]; 2350}; 2351