if_bgereg.h revision 1.21
1/* $OpenBSD: if_bgereg.h,v 1.21 2005/04/05 01:12:52 brad Exp $ */ 2/* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bgereg.h,v 1.11 2002/11/14 23:54:50 sam Exp $ 35 */ 36 37/* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65#define BGE_PAGE_ZERO 0x00000000 66#define BGE_PAGE_ZERO_END 0x000000FF 67#define BGE_SEND_RING_RCB 0x00000100 68#define BGE_SEND_RING_RCB_END 0x000001FF 69#define BGE_RX_RETURN_RING_RCB 0x00000200 70#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 71#define BGE_STATS_BLOCK 0x00000300 72#define BGE_STATS_BLOCK_END 0x00000AFF 73#define BGE_STATUS_BLOCK 0x00000B00 74#define BGE_STATUS_BLOCK_END 0x00000B4F 75#define BGE_SOFTWARE_GENCOMM 0x00000B50 76#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 77#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 78#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 79#define BGE_UNMAPPED 0x00001000 80#define BGE_UNMAPPED_END 0x00001FFF 81#define BGE_DMA_DESCRIPTORS 0x00002000 82#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 83#define BGE_SEND_RING_1_TO_4 0x00004000 84#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 85 86/* Mappings for internal memory configuration */ 87#define BGE_STD_RX_RINGS 0x00006000 88#define BGE_STD_RX_RINGS_END 0x00006FFF 89#define BGE_JUMBO_RX_RINGS 0x00007000 90#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 91#define BGE_BUFFPOOL_1 0x00008000 92#define BGE_BUFFPOOL_1_END 0x0000FFFF 93#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 94#define BGE_BUFFPOOL_2_END 0x00017FFF 95#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 96#define BGE_BUFFPOOL_3_END 0x0001FFFF 97 98/* Mappings for external SSRAM configurations */ 99#define BGE_SEND_RING_5_TO_6 0x00006000 100#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 101#define BGE_SEND_RING_7_TO_8 0x00007000 102#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 103#define BGE_SEND_RING_9_TO_16 0x00008000 104#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 105#define BGE_EXT_STD_RX_RINGS 0x0000C000 106#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 107#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 108#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 109#define BGE_MINI_RX_RINGS 0x0000E000 110#define BGE_MINI_RX_RINGS_END 0x0000FFFF 111#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 112#define BGE_AVAIL_REGION1_END 0x00017FFF 113#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 114#define BGE_AVAIL_REGION2_END 0x0001FFFF 115#define BGE_EXT_SSRAM 0x00020000 116#define BGE_EXT_SSRAM_END 0x000FFFFF 117 118 119/* 120 * BCM570x register offsets. These are memory mapped registers 121 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 122 * Each register must be accessed using 32 bit operations. 123 * 124 * All registers are accessed through a 32K shared memory block. 125 * The first group of registers are actually copies of the PCI 126 * configuration space registers. 127 */ 128 129/* 130 * PCI registers defined in the PCI 2.2 spec. 131 */ 132#define BGE_PCI_VID 0x00 133#define BGE_PCI_DID 0x02 134#define BGE_PCI_CMD 0x04 135#define BGE_PCI_STS 0x06 136#define BGE_PCI_REV 0x08 137#define BGE_PCI_CLASS 0x09 138#define BGE_PCI_CACHESZ 0x0C 139#define BGE_PCI_LATTIMER 0x0D 140#define BGE_PCI_HDRTYPE 0x0E 141#define BGE_PCI_BIST 0x0F 142#define BGE_PCI_BAR0 0x10 143#define BGE_PCI_BAR1 0x14 144#define BGE_PCI_SUBSYS 0x2C 145#define BGE_PCI_SUBVID 0x2E 146#define BGE_PCI_ROMBASE 0x30 147#define BGE_PCI_CAPPTR 0x34 148#define BGE_PCI_INTLINE 0x3C 149#define BGE_PCI_INTPIN 0x3D 150#define BGE_PCI_MINGNT 0x3E 151#define BGE_PCI_MAXLAT 0x3F 152#define BGE_PCI_PCIXCAP 0x40 153#define BGE_PCI_NEXTPTR_PM 0x41 154#define BGE_PCI_PCIX_CMD 0x42 155#define BGE_PCI_PCIX_STS 0x44 156#define BGE_PCI_PWRMGMT_CAPID 0x48 157#define BGE_PCI_NEXTPTR_VPD 0x49 158#define BGE_PCI_PWRMGMT_CAPS 0x4A 159#define BGE_PCI_PWRMGMT_CMD 0x4C 160#define BGE_PCI_PWRMGMT_STS 0x4D 161#define BGE_PCI_PWRMGMT_DATA 0x4F 162#define BGE_PCI_VPD_CAPID 0x50 163#define BGE_PCI_NEXTPTR_MSI 0x51 164#define BGE_PCI_VPD_ADDR 0x52 165#define BGE_PCI_VPD_DATA 0x54 166#define BGE_PCI_MSI_CAPID 0x58 167#define BGE_PCI_NEXTPTR_NONE 0x59 168#define BGE_PCI_MSI_CTL 0x5A 169#define BGE_PCI_MSI_ADDR_HI 0x5C 170#define BGE_PCI_MSI_ADDR_LO 0x60 171#define BGE_PCI_MSI_DATA 0x64 172 173/* PCI MSI. ??? */ 174#define BGE_PCIE_CAPID_REG 0xD0 175#define BGE_PCIE_CAPID 0x10 176 177/* 178 * PCI registers specific to the BCM570x family. 179 */ 180#define BGE_PCI_MISC_CTL 0x68 181#define BGE_PCI_DMA_RW_CTL 0x6C 182#define BGE_PCI_PCISTATE 0x70 183#define BGE_PCI_CLKCTL 0x74 184#define BGE_PCI_REG_BASEADDR 0x78 185#define BGE_PCI_MEMWIN_BASEADDR 0x7C 186#define BGE_PCI_REG_DATA 0x80 187#define BGE_PCI_MEMWIN_DATA 0x84 188#define BGE_PCI_MODECTL 0x88 189#define BGE_PCI_MISC_CFG 0x8C 190#define BGE_PCI_MISC_LOCALCTL 0x90 191#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 192#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 193#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 194#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 195#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 196#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 197#define BGE_PCI_ISR_MBX_HI 0xB0 198#define BGE_PCI_ISR_MBX_LO 0xB4 199 200/* PCI Misc. Host control register */ 201#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 202#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 203#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 204#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 205#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 206#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 207#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 208#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 209#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 210 211#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 212#if BYTE_ORDER == LITTLE_ENDIAN 213#define BGE_DMA_SWAP_OPTIONS \ 214 BGE_MODECTL_WORDSWAP_NONFRAME| \ 215 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 216#else 217#define BGE_DMA_SWAP_OPTIONS \ 218 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 219 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 220#endif 221 222#define BGE_INIT \ 223 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 224 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 225 226#define BGE_CHIPID_TIGON_I 0x40000000 227#define BGE_CHIPID_TIGON_II 0x60000000 228#define BGE_CHIPID_BCM5700_A0 0x70000000 229#define BGE_CHIPID_BCM5700_A1 0x70010000 230#define BGE_CHIPID_BCM5700_B0 0x71000000 231#define BGE_CHIPID_BCM5700_B1 0x71020000 232#define BGE_CHIPID_BCM5700_B2 0x71030000 233#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 234#define BGE_CHIPID_BCM5700_C0 0x72000000 235#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 236#define BGE_CHIPID_BCM5701_B0 0x01000000 237#define BGE_CHIPID_BCM5701_B2 0x01020000 238#define BGE_CHIPID_BCM5701_B5 0x01050000 239#define BGE_CHIPID_BCM5703_A0 0x10000000 240#define BGE_CHIPID_BCM5703_A1 0x10010000 241#define BGE_CHIPID_BCM5703_A2 0x10020000 242#define BGE_CHIPID_BCM5703_A3 0x11000000 243#define BGE_CHIPID_BCM5704_A0 0x20000000 244#define BGE_CHIPID_BCM5704_A1 0x20010000 245#define BGE_CHIPID_BCM5704_A2 0x20020000 246#define BGE_CHIPID_BCM5704_A3 0x20030000 247#define BGE_CHIPID_BCM5705_A0 0x30000000 248#define BGE_CHIPID_BCM5705_A1 0x30010000 249#define BGE_CHIPID_BCM5705_A2 0x30020000 250#define BGE_CHIPID_BCM5705_A3 0x30030000 251#define BGE_CHIPID_BCM5750_A0 0x40000000 252#define BGE_CHIPID_BCM5750_A1 0x40010000 253 254/* shorthand one */ 255#define BGE_ASICREV(x) ((x) >> 28) 256#define BGE_ASICREV_BCM5700 0x07 257#define BGE_ASICREV_BCM5701 0x00 258#define BGE_ASICREV_BCM5703 0x01 259#define BGE_ASICREV_BCM5704 0x02 260#define BGE_ASICREV_BCM5705 0x03 261#define BGE_ASICREV_BCM5750 0x04 262 263/* chip revisions */ 264#define BGE_CHIPREV(x) ((x) >> 24) 265#define BGE_CHIPREV_5700_AX 0x70 266#define BGE_CHIPREV_5700_BX 0x71 267#define BGE_CHIPREV_5700_CX 0x72 268#define BGE_CHIPREV_5701_AX 0x00 269 270/* PCI DMA Read/Write Control register */ 271#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 272#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 273#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 274#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 275#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 276#define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 277#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 278#define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 279#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 280#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 281#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 282#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD_SHIFT 24 283#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 284#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD_SHIFT 28 285 286#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 287#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 288#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 289#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 290#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 291#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 292#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 293#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 294 295#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 296#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 297#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 298#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 299#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 300#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 301#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 302#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 303 304/* 305 * PCI state register -- note, this register is read only 306 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 307 * register is set. 308 */ 309#define BGE_PCISTATE_FORCE_RESET 0x00000001 310#define BGE_PCISTATE_INTR_STATE 0x00000002 311#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 312#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 313#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 314#define BGE_PCISTATE_WANT_EXPROM 0x00000020 315#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 316#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 317#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 318 319/* 320 * The following bits in PCI state register are reserved. 321 * If we check that the register values reverts on reset, 322 * do not check these bits. On some 5704C (rev A3) and some 323 * Altima chips, these bits do not revert until much later 324 * in the bge driver's bge_reset() chip-reset state machine. 325 */ 326#define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 327 328/* 329 * PCI Clock Control register -- note, this register is read only 330 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 331 * register is set. 332 */ 333#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 334#define BGE_PCICLOCKCTL_M66EN 0x00000080 335#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 336#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 337#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 338#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 339#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 340#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 341#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 342#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 343 344/* 345 * High priority mailbox registers 346 * Each mailbox is 64-bits wide, though we only use the 347 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 348 * first. The NIC will load the mailbox after the lower 32 bit word 349 * has been updated. 350 */ 351#define BGE_MBX_IRQ0_HI 0x0200 352#define BGE_MBX_IRQ0_LO 0x0204 353#define BGE_MBX_IRQ1_HI 0x0208 354#define BGE_MBX_IRQ1_LO 0x020C 355#define BGE_MBX_IRQ2_HI 0x0210 356#define BGE_MBX_IRQ2_LO 0x0214 357#define BGE_MBX_IRQ3_HI 0x0218 358#define BGE_MBX_IRQ3_LO 0x021C 359#define BGE_MBX_GEN0_HI 0x0220 360#define BGE_MBX_GEN0_LO 0x0224 361#define BGE_MBX_GEN1_HI 0x0228 362#define BGE_MBX_GEN1_LO 0x022C 363#define BGE_MBX_GEN2_HI 0x0230 364#define BGE_MBX_GEN2_LO 0x0234 365#define BGE_MBX_GEN3_HI 0x0228 366#define BGE_MBX_GEN3_LO 0x022C 367#define BGE_MBX_GEN4_HI 0x0240 368#define BGE_MBX_GEN4_LO 0x0244 369#define BGE_MBX_GEN5_HI 0x0248 370#define BGE_MBX_GEN5_LO 0x024C 371#define BGE_MBX_GEN6_HI 0x0250 372#define BGE_MBX_GEN6_LO 0x0254 373#define BGE_MBX_GEN7_HI 0x0258 374#define BGE_MBX_GEN7_LO 0x025C 375#define BGE_MBX_RELOAD_STATS_HI 0x0260 376#define BGE_MBX_RELOAD_STATS_LO 0x0264 377#define BGE_MBX_RX_STD_PROD_HI 0x0268 378#define BGE_MBX_RX_STD_PROD_LO 0x026C 379#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 380#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 381#define BGE_MBX_RX_MINI_PROD_HI 0x0278 382#define BGE_MBX_RX_MINI_PROD_LO 0x027C 383#define BGE_MBX_RX_CONS0_HI 0x0280 384#define BGE_MBX_RX_CONS0_LO 0x0284 385#define BGE_MBX_RX_CONS1_HI 0x0288 386#define BGE_MBX_RX_CONS1_LO 0x028C 387#define BGE_MBX_RX_CONS2_HI 0x0290 388#define BGE_MBX_RX_CONS2_LO 0x0294 389#define BGE_MBX_RX_CONS3_HI 0x0298 390#define BGE_MBX_RX_CONS3_LO 0x029C 391#define BGE_MBX_RX_CONS4_HI 0x02A0 392#define BGE_MBX_RX_CONS4_LO 0x02A4 393#define BGE_MBX_RX_CONS5_HI 0x02A8 394#define BGE_MBX_RX_CONS5_LO 0x02AC 395#define BGE_MBX_RX_CONS6_HI 0x02B0 396#define BGE_MBX_RX_CONS6_LO 0x02B4 397#define BGE_MBX_RX_CONS7_HI 0x02B8 398#define BGE_MBX_RX_CONS7_LO 0x02BC 399#define BGE_MBX_RX_CONS8_HI 0x02C0 400#define BGE_MBX_RX_CONS8_LO 0x02C4 401#define BGE_MBX_RX_CONS9_HI 0x02C8 402#define BGE_MBX_RX_CONS9_LO 0x02CC 403#define BGE_MBX_RX_CONS10_HI 0x02D0 404#define BGE_MBX_RX_CONS10_LO 0x02D4 405#define BGE_MBX_RX_CONS11_HI 0x02D8 406#define BGE_MBX_RX_CONS11_LO 0x02DC 407#define BGE_MBX_RX_CONS12_HI 0x02E0 408#define BGE_MBX_RX_CONS12_LO 0x02E4 409#define BGE_MBX_RX_CONS13_HI 0x02E8 410#define BGE_MBX_RX_CONS13_LO 0x02EC 411#define BGE_MBX_RX_CONS14_HI 0x02F0 412#define BGE_MBX_RX_CONS14_LO 0x02F4 413#define BGE_MBX_RX_CONS15_HI 0x02F8 414#define BGE_MBX_RX_CONS15_LO 0x02FC 415#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 416#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 417#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 418#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 419#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 420#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 421#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 422#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 423#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 424#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 425#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 426#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 427#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 428#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 429#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 430#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 431#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 432#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 433#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 434#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 435#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 436#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 437#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 438#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 439#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 440#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 441#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 442#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 443#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 444#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 445#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 446#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 447#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 448#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 449#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 450#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 451#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 452#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 453#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 454#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 455#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 456#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 457#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 458#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 459#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 460#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 461#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 462#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 463#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 464#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 465#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 466#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 467#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 468#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 469#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 470#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 471#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 472#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 473#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 474#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 475#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 476#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 477#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 478#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 479 480#define BGE_TX_RINGS_MAX 4 481#define BGE_TX_RINGS_EXTSSRAM_MAX 16 482#define BGE_RX_RINGS_MAX 16 483 484/* Ethernet MAC control registers */ 485#define BGE_MAC_MODE 0x0400 486#define BGE_MAC_STS 0x0404 487#define BGE_MAC_EVT_ENB 0x0408 488#define BGE_MAC_LED_CTL 0x040C 489#define BGE_MAC_ADDR1_LO 0x0410 490#define BGE_MAC_ADDR1_HI 0x0414 491#define BGE_MAC_ADDR2_LO 0x0418 492#define BGE_MAC_ADDR2_HI 0x041C 493#define BGE_MAC_ADDR3_LO 0x0420 494#define BGE_MAC_ADDR3_HI 0x0424 495#define BGE_MAC_ADDR4_LO 0x0428 496#define BGE_MAC_ADDR4_HI 0x042C 497#define BGE_WOL_PATPTR 0x0430 498#define BGE_WOL_PATCFG 0x0434 499#define BGE_TX_RANDOM_BACKOFF 0x0438 500#define BGE_RX_MTU 0x043C 501#define BGE_GBIT_PCS_TEST 0x0440 502#define BGE_TX_TBI_AUTONEG 0x0444 503#define BGE_RX_TBI_AUTONEG 0x0448 504#define BGE_MI_COMM 0x044C 505#define BGE_MI_STS 0x0450 506#define BGE_MI_MODE 0x0454 507#define BGE_AUTOPOLL_STS 0x0458 508#define BGE_TX_MODE 0x045C 509#define BGE_TX_STS 0x0460 510#define BGE_TX_LENGTHS 0x0464 511#define BGE_RX_MODE 0x0468 512#define BGE_RX_STS 0x046C 513#define BGE_MAR0 0x0470 514#define BGE_MAR1 0x0474 515#define BGE_MAR2 0x0478 516#define BGE_MAR3 0x047C 517#define BGE_RX_BD_RULES_CTL0 0x0480 518#define BGE_RX_BD_RULES_MASKVAL0 0x0484 519#define BGE_RX_BD_RULES_CTL1 0x0488 520#define BGE_RX_BD_RULES_MASKVAL1 0x048C 521#define BGE_RX_BD_RULES_CTL2 0x0490 522#define BGE_RX_BD_RULES_MASKVAL2 0x0494 523#define BGE_RX_BD_RULES_CTL3 0x0498 524#define BGE_RX_BD_RULES_MASKVAL3 0x049C 525#define BGE_RX_BD_RULES_CTL4 0x04A0 526#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 527#define BGE_RX_BD_RULES_CTL5 0x04A8 528#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 529#define BGE_RX_BD_RULES_CTL6 0x04B0 530#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 531#define BGE_RX_BD_RULES_CTL7 0x04B8 532#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 533#define BGE_RX_BD_RULES_CTL8 0x04C0 534#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 535#define BGE_RX_BD_RULES_CTL9 0x04C8 536#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 537#define BGE_RX_BD_RULES_CTL10 0x04D0 538#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 539#define BGE_RX_BD_RULES_CTL11 0x04D8 540#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 541#define BGE_RX_BD_RULES_CTL12 0x04E0 542#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 543#define BGE_RX_BD_RULES_CTL13 0x04E8 544#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 545#define BGE_RX_BD_RULES_CTL14 0x04F0 546#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 547#define BGE_RX_BD_RULES_CTL15 0x04F8 548#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 549#define BGE_RX_RULES_CFG 0x0500 550#define BGE_MAX_RX_FRAME_LOWAT 0x0504 551#define BGE_SERDES_CFG 0x0590 552#define BGE_SERDES_STS 0x0594 553#define BGE_SGDIG_CFG 0x05B0 554#define BGE_SGDIG_STS 0x05B4 555#define BGE_RX_STATS 0x0800 556#define BGE_TX_STATS 0x0880 557 558/* Ethernet MAC Mode register */ 559#define BGE_MACMODE_RESET 0x00000001 560#define BGE_MACMODE_HALF_DUPLEX 0x00000002 561#define BGE_MACMODE_PORTMODE 0x0000000C 562#define BGE_MACMODE_LOOPBACK 0x00000010 563#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 564#define BGE_MACMODE_TX_BURST_ENB 0x00000100 565#define BGE_MACMODE_MAX_DEFER 0x00000200 566#define BGE_MACMODE_LINK_POLARITY 0x00000400 567#define BGE_MACMODE_RX_STATS_ENB 0x00000800 568#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 569#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 570#define BGE_MACMODE_TX_STATS_ENB 0x00004000 571#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 572#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 573#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 574#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 575#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 576#define BGE_MACMODE_MIP_ENB 0x00100000 577#define BGE_MACMODE_TXDMA_ENB 0x00200000 578#define BGE_MACMODE_RXDMA_ENB 0x00400000 579#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 580 581#define BGE_PORTMODE_NONE 0x00000000 582#define BGE_PORTMODE_MII 0x00000004 583#define BGE_PORTMODE_GMII 0x00000008 584#define BGE_PORTMODE_TBI 0x0000000C 585 586/* MAC Status register */ 587#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 588#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 589#define BGE_MACSTAT_RX_CFG 0x00000004 590#define BGE_MACSTAT_CFG_CHANGED 0x00000008 591#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 592#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 593#define BGE_MACSTAT_LINK_CHANGED 0x00001000 594#define BGE_MACSTAT_MI_COMPLETE 0x00400000 595#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 596#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 597#define BGE_MACSTAT_ODI_ERROR 0x02000000 598#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 599#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 600 601/* MAC Event Enable Register */ 602#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 603#define BGE_EVTENB_LINK_CHANGED 0x00001000 604#define BGE_EVTENB_MI_COMPLETE 0x00400000 605#define BGE_EVTENB_MI_INTERRUPT 0x00800000 606#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 607#define BGE_EVTENB_ODI_ERROR 0x02000000 608#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 609#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 610 611/* LED Control Register */ 612#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 613#define BGE_LEDCTL_1000MBPS_LED 0x00000002 614#define BGE_LEDCTL_100MBPS_LED 0x00000004 615#define BGE_LEDCTL_10MBPS_LED 0x00000008 616#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 617#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 618#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 619#define BGE_LEDCTL_1000MBPS_STS 0x00000080 620#define BGE_LEDCTL_100MBPS_STS 0x00000100 621#define BGE_LEDCTL_10MBPS_STS 0x00000200 622#define BGE_LEDCTL_TRADLED_STS 0x00000400 623#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 624#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 625 626/* TX backoff seed register */ 627#define BGE_TX_BACKOFF_SEED_MASK 0x3F 628 629/* Autopoll status register */ 630#define BGE_AUTOPOLLSTS_ERROR 0x00000001 631 632/* Transmit MAC mode register */ 633#define BGE_TXMODE_RESET 0x00000001 634#define BGE_TXMODE_ENABLE 0x00000002 635#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 636#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 637#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 638 639/* Transmit MAC status register */ 640#define BGE_TXSTAT_RX_XOFFED 0x00000001 641#define BGE_TXSTAT_SENT_XOFF 0x00000002 642#define BGE_TXSTAT_SENT_XON 0x00000004 643#define BGE_TXSTAT_LINK_UP 0x00000008 644#define BGE_TXSTAT_ODI_UFLOW 0x00000010 645#define BGE_TXSTAT_ODI_OFLOW 0x00000020 646 647/* Transmit MAC lengths register */ 648#define BGE_TXLEN_SLOTTIME 0x000000FF 649#define BGE_TXLEN_IPG 0x00000F00 650#define BGE_TXLEN_CRS 0x00003000 651 652/* Receive MAC mode register */ 653#define BGE_RXMODE_RESET 0x00000001 654#define BGE_RXMODE_ENABLE 0x00000002 655#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 656#define BGE_RXMODE_RX_GIANTS 0x00000020 657#define BGE_RXMODE_RX_RUNTS 0x00000040 658#define BGE_RXMODE_8022_LENCHECK 0x00000080 659#define BGE_RXMODE_RX_PROMISC 0x00000100 660#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 661#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 662 663/* Receive MAC status register */ 664#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 665#define BGE_RXSTAT_RCVD_XOFF 0x00000002 666#define BGE_RXSTAT_RCVD_XON 0x00000004 667 668/* Receive Rules Control register */ 669#define BGE_RXRULECTL_OFFSET 0x000000FF 670#define BGE_RXRULECTL_CLASS 0x00001F00 671#define BGE_RXRULECTL_HDRTYPE 0x0000E000 672#define BGE_RXRULECTL_COMPARE_OP 0x00030000 673#define BGE_RXRULECTL_MAP 0x01000000 674#define BGE_RXRULECTL_DISCARD 0x02000000 675#define BGE_RXRULECTL_MASK 0x04000000 676#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 677#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 678#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 679#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 680 681/* Receive Rules Mask register */ 682#define BGE_RXRULEMASK_VALUE 0x0000FFFF 683#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 684 685/* SERDES configuration register */ 686#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 687#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 688#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 689#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 690#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 691#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 692#define BGE_SERDESCFG_TXMODE 0x00001000 693#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 694#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 695#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 696#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 697#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 698#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 699#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 700#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 701#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 702 703/* SERDES status register */ 704#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 705#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 706 707/* SGDIG config (not documented) */ 708#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 709#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 710#define BGE_SGDIGCFG_SEND 0x40000000 711#define BGE_SGDIGCFG_AUTO 0x80000000 712 713/* SGDIG status (not documented) */ 714#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 715#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 716#define BGE_SGDIGSTS_DONE 0x00000002 717 718/* MI communication register */ 719#define BGE_MICOMM_DATA 0x0000FFFF 720#define BGE_MICOMM_REG 0x001F0000 721#define BGE_MICOMM_PHY 0x03E00000 722#define BGE_MICOMM_CMD 0x0C000000 723#define BGE_MICOMM_READFAIL 0x10000000 724#define BGE_MICOMM_BUSY 0x20000000 725 726#define BGE_MIREG(x) ((x & 0x1F) << 16) 727#define BGE_MIPHY(x) ((x & 0x1F) << 21) 728#define BGE_MICMD_WRITE 0x04000000 729#define BGE_MICMD_READ 0x08000000 730 731/* MI status register */ 732#define BGE_MISTS_LINK 0x00000001 733#define BGE_MISTS_10MBPS 0x00000002 734 735#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 736#define BGE_MIMODE_AUTOPOLL 0x00000010 737#define BGE_MIMODE_CLKCNT 0x001F0000 738 739 740/* 741 * Send data initiator control registers. 742 */ 743#define BGE_SDI_MODE 0x0C00 744#define BGE_SDI_STATUS 0x0C04 745#define BGE_SDI_STATS_CTL 0x0C08 746#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 747#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 748#define BGE_LOCSTATS_COS0 0x0C80 749#define BGE_LOCSTATS_COS1 0x0C84 750#define BGE_LOCSTATS_COS2 0x0C88 751#define BGE_LOCSTATS_COS3 0x0C8C 752#define BGE_LOCSTATS_COS4 0x0C90 753#define BGE_LOCSTATS_COS5 0x0C84 754#define BGE_LOCSTATS_COS6 0x0C98 755#define BGE_LOCSTATS_COS7 0x0C9C 756#define BGE_LOCSTATS_COS8 0x0CA0 757#define BGE_LOCSTATS_COS9 0x0CA4 758#define BGE_LOCSTATS_COS10 0x0CA8 759#define BGE_LOCSTATS_COS11 0x0CAC 760#define BGE_LOCSTATS_COS12 0x0CB0 761#define BGE_LOCSTATS_COS13 0x0CB4 762#define BGE_LOCSTATS_COS14 0x0CB8 763#define BGE_LOCSTATS_COS15 0x0CBC 764#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 765#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 766#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 767#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 768#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 769#define BGE_LOCSTATS_IRQS 0x0CD4 770#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 771#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 772 773/* Send Data Initiator mode register */ 774#define BGE_SDIMODE_RESET 0x00000001 775#define BGE_SDIMODE_ENABLE 0x00000002 776#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 777 778/* Send Data Initiator stats register */ 779#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 780 781/* Send Data Initiator stats control register */ 782#define BGE_SDISTATSCTL_ENABLE 0x00000001 783#define BGE_SDISTATSCTL_FASTER 0x00000002 784#define BGE_SDISTATSCTL_CLEAR 0x00000004 785#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 786#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 787 788/* 789 * Send Data Completion Control registers 790 */ 791#define BGE_SDC_MODE 0x1000 792#define BGE_SDC_STATUS 0x1004 793 794/* Send Data completion mode register */ 795#define BGE_SDCMODE_RESET 0x00000001 796#define BGE_SDCMODE_ENABLE 0x00000002 797#define BGE_SDCMODE_ATTN 0x00000004 798 799/* Send Data completion status register */ 800#define BGE_SDCSTAT_ATTN 0x00000004 801 802/* 803 * Send BD Ring Selector Control registers 804 */ 805#define BGE_SRS_MODE 0x1400 806#define BGE_SRS_STATUS 0x1404 807#define BGE_SRS_HWDIAG 0x1408 808#define BGE_SRS_LOC_NIC_CONS0 0x1440 809#define BGE_SRS_LOC_NIC_CONS1 0x1444 810#define BGE_SRS_LOC_NIC_CONS2 0x1448 811#define BGE_SRS_LOC_NIC_CONS3 0x144C 812#define BGE_SRS_LOC_NIC_CONS4 0x1450 813#define BGE_SRS_LOC_NIC_CONS5 0x1454 814#define BGE_SRS_LOC_NIC_CONS6 0x1458 815#define BGE_SRS_LOC_NIC_CONS7 0x145C 816#define BGE_SRS_LOC_NIC_CONS8 0x1460 817#define BGE_SRS_LOC_NIC_CONS9 0x1464 818#define BGE_SRS_LOC_NIC_CONS10 0x1468 819#define BGE_SRS_LOC_NIC_CONS11 0x146C 820#define BGE_SRS_LOC_NIC_CONS12 0x1470 821#define BGE_SRS_LOC_NIC_CONS13 0x1474 822#define BGE_SRS_LOC_NIC_CONS14 0x1478 823#define BGE_SRS_LOC_NIC_CONS15 0x147C 824 825/* Send BD Ring Selector Mode register */ 826#define BGE_SRSMODE_RESET 0x00000001 827#define BGE_SRSMODE_ENABLE 0x00000002 828#define BGE_SRSMODE_ATTN 0x00000004 829 830/* Send BD Ring Selector Status register */ 831#define BGE_SRSSTAT_ERROR 0x00000004 832 833/* Send BD Ring Selector HW Diagnostics register */ 834#define BGE_SRSHWDIAG_STATE 0x0000000F 835#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 836#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 837#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 838 839/* 840 * Send BD Initiator Selector Control registers 841 */ 842#define BGE_SBDI_MODE 0x1800 843#define BGE_SBDI_STATUS 0x1804 844#define BGE_SBDI_LOC_NIC_PROD0 0x1808 845#define BGE_SBDI_LOC_NIC_PROD1 0x180C 846#define BGE_SBDI_LOC_NIC_PROD2 0x1810 847#define BGE_SBDI_LOC_NIC_PROD3 0x1814 848#define BGE_SBDI_LOC_NIC_PROD4 0x1818 849#define BGE_SBDI_LOC_NIC_PROD5 0x181C 850#define BGE_SBDI_LOC_NIC_PROD6 0x1820 851#define BGE_SBDI_LOC_NIC_PROD7 0x1824 852#define BGE_SBDI_LOC_NIC_PROD8 0x1828 853#define BGE_SBDI_LOC_NIC_PROD9 0x182C 854#define BGE_SBDI_LOC_NIC_PROD10 0x1830 855#define BGE_SBDI_LOC_NIC_PROD11 0x1834 856#define BGE_SBDI_LOC_NIC_PROD12 0x1838 857#define BGE_SBDI_LOC_NIC_PROD13 0x183C 858#define BGE_SBDI_LOC_NIC_PROD14 0x1840 859#define BGE_SBDI_LOC_NIC_PROD15 0x1844 860 861/* Send BD Initiator Mode register */ 862#define BGE_SBDIMODE_RESET 0x00000001 863#define BGE_SBDIMODE_ENABLE 0x00000002 864#define BGE_SBDIMODE_ATTN 0x00000004 865 866/* Send BD Initiator Status register */ 867#define BGE_SBDISTAT_ERROR 0x00000004 868 869/* 870 * Send BD Completion Control registers 871 */ 872#define BGE_SBDC_MODE 0x1C00 873#define BGE_SBDC_STATUS 0x1C04 874 875/* Send BD Completion Control Mode register */ 876#define BGE_SBDCMODE_RESET 0x00000001 877#define BGE_SBDCMODE_ENABLE 0x00000002 878#define BGE_SBDCMODE_ATTN 0x00000004 879 880/* Send BD Completion Control Status register */ 881#define BGE_SBDCSTAT_ATTN 0x00000004 882 883/* 884 * Receive List Placement Control registers 885 */ 886#define BGE_RXLP_MODE 0x2000 887#define BGE_RXLP_STATUS 0x2004 888#define BGE_RXLP_SEL_LIST_LOCK 0x2008 889#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 890#define BGE_RXLP_CFG 0x2010 891#define BGE_RXLP_STATS_CTL 0x2014 892#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 893#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 894#define BGE_RXLP_HEAD0 0x2100 895#define BGE_RXLP_TAIL0 0x2104 896#define BGE_RXLP_COUNT0 0x2108 897#define BGE_RXLP_HEAD1 0x2110 898#define BGE_RXLP_TAIL1 0x2114 899#define BGE_RXLP_COUNT1 0x2118 900#define BGE_RXLP_HEAD2 0x2120 901#define BGE_RXLP_TAIL2 0x2124 902#define BGE_RXLP_COUNT2 0x2128 903#define BGE_RXLP_HEAD3 0x2130 904#define BGE_RXLP_TAIL3 0x2134 905#define BGE_RXLP_COUNT3 0x2138 906#define BGE_RXLP_HEAD4 0x2140 907#define BGE_RXLP_TAIL4 0x2144 908#define BGE_RXLP_COUNT4 0x2148 909#define BGE_RXLP_HEAD5 0x2150 910#define BGE_RXLP_TAIL5 0x2154 911#define BGE_RXLP_COUNT5 0x2158 912#define BGE_RXLP_HEAD6 0x2160 913#define BGE_RXLP_TAIL6 0x2164 914#define BGE_RXLP_COUNT6 0x2168 915#define BGE_RXLP_HEAD7 0x2170 916#define BGE_RXLP_TAIL7 0x2174 917#define BGE_RXLP_COUNT7 0x2178 918#define BGE_RXLP_HEAD8 0x2180 919#define BGE_RXLP_TAIL8 0x2184 920#define BGE_RXLP_COUNT8 0x2188 921#define BGE_RXLP_HEAD9 0x2190 922#define BGE_RXLP_TAIL9 0x2194 923#define BGE_RXLP_COUNT9 0x2198 924#define BGE_RXLP_HEAD10 0x21A0 925#define BGE_RXLP_TAIL10 0x21A4 926#define BGE_RXLP_COUNT10 0x21A8 927#define BGE_RXLP_HEAD11 0x21B0 928#define BGE_RXLP_TAIL11 0x21B4 929#define BGE_RXLP_COUNT11 0x21B8 930#define BGE_RXLP_HEAD12 0x21C0 931#define BGE_RXLP_TAIL12 0x21C4 932#define BGE_RXLP_COUNT12 0x21C8 933#define BGE_RXLP_HEAD13 0x21D0 934#define BGE_RXLP_TAIL13 0x21D4 935#define BGE_RXLP_COUNT13 0x21D8 936#define BGE_RXLP_HEAD14 0x21E0 937#define BGE_RXLP_TAIL14 0x21E4 938#define BGE_RXLP_COUNT14 0x21E8 939#define BGE_RXLP_HEAD15 0x21F0 940#define BGE_RXLP_TAIL15 0x21F4 941#define BGE_RXLP_COUNT15 0x21F8 942#define BGE_RXLP_LOCSTAT_COS0 0x2200 943#define BGE_RXLP_LOCSTAT_COS1 0x2204 944#define BGE_RXLP_LOCSTAT_COS2 0x2208 945#define BGE_RXLP_LOCSTAT_COS3 0x220C 946#define BGE_RXLP_LOCSTAT_COS4 0x2210 947#define BGE_RXLP_LOCSTAT_COS5 0x2214 948#define BGE_RXLP_LOCSTAT_COS6 0x2218 949#define BGE_RXLP_LOCSTAT_COS7 0x221C 950#define BGE_RXLP_LOCSTAT_COS8 0x2220 951#define BGE_RXLP_LOCSTAT_COS9 0x2224 952#define BGE_RXLP_LOCSTAT_COS10 0x2228 953#define BGE_RXLP_LOCSTAT_COS11 0x222C 954#define BGE_RXLP_LOCSTAT_COS12 0x2230 955#define BGE_RXLP_LOCSTAT_COS13 0x2234 956#define BGE_RXLP_LOCSTAT_COS14 0x2238 957#define BGE_RXLP_LOCSTAT_COS15 0x223C 958#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 959#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 960#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 961#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 962#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 963#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 964#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 965 966 967/* Receive List Placement mode register */ 968#define BGE_RXLPMODE_RESET 0x00000001 969#define BGE_RXLPMODE_ENABLE 0x00000002 970#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 971#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 972#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 973 974/* Receive List Placement Status register */ 975#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 976#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 977#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 978 979/* 980 * Receive Data and Receive BD Initiator Control Registers 981 */ 982#define BGE_RDBDI_MODE 0x2400 983#define BGE_RDBDI_STATUS 0x2404 984#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 985#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 986#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 987#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 988#define BGE_RX_STD_RCB_HADDR_HI 0x2450 989#define BGE_RX_STD_RCB_HADDR_LO 0x2454 990#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 991#define BGE_RX_STD_RCB_NICADDR 0x245C 992#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 993#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 994#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 995#define BGE_RX_MINI_RCB_NICADDR 0x246C 996#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 997#define BGE_RDBDI_STD_RX_CONS 0x2474 998#define BGE_RDBDI_MINI_RX_CONS 0x2478 999#define BGE_RDBDI_RETURN_PROD0 0x2480 1000#define BGE_RDBDI_RETURN_PROD1 0x2484 1001#define BGE_RDBDI_RETURN_PROD2 0x2488 1002#define BGE_RDBDI_RETURN_PROD3 0x248C 1003#define BGE_RDBDI_RETURN_PROD4 0x2490 1004#define BGE_RDBDI_RETURN_PROD5 0x2494 1005#define BGE_RDBDI_RETURN_PROD6 0x2498 1006#define BGE_RDBDI_RETURN_PROD7 0x249C 1007#define BGE_RDBDI_RETURN_PROD8 0x24A0 1008#define BGE_RDBDI_RETURN_PROD9 0x24A4 1009#define BGE_RDBDI_RETURN_PROD10 0x24A8 1010#define BGE_RDBDI_RETURN_PROD11 0x24AC 1011#define BGE_RDBDI_RETURN_PROD12 0x24B0 1012#define BGE_RDBDI_RETURN_PROD13 0x24B4 1013#define BGE_RDBDI_RETURN_PROD14 0x24B8 1014#define BGE_RDBDI_RETURN_PROD15 0x24BC 1015#define BGE_RDBDI_HWDIAG 0x24C0 1016 1017 1018/* Receive Data and Receive BD Initiator Mode register */ 1019#define BGE_RDBDIMODE_RESET 0x00000001 1020#define BGE_RDBDIMODE_ENABLE 0x00000002 1021#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1022#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1023#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1024 1025/* Receive Data and Receive BD Initiator Status register */ 1026#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1027#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1028#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1029 1030 1031/* 1032 * Receive Data Completion Control registers 1033 */ 1034#define BGE_RDC_MODE 0x2800 1035 1036/* Receive Data Completion Mode register */ 1037#define BGE_RDCMODE_RESET 0x00000001 1038#define BGE_RDCMODE_ENABLE 0x00000002 1039#define BGE_RDCMODE_ATTN 0x00000004 1040 1041/* 1042 * Receive BD Initiator Control registers 1043 */ 1044#define BGE_RBDI_MODE 0x2C00 1045#define BGE_RBDI_STATUS 0x2C04 1046#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1047#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1048#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1049#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1050#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1051#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1052 1053/* Receive BD Initiator Mode register */ 1054#define BGE_RBDIMODE_RESET 0x00000001 1055#define BGE_RBDIMODE_ENABLE 0x00000002 1056#define BGE_RBDIMODE_ATTN 0x00000004 1057 1058/* Receive BD Initiator Status register */ 1059#define BGE_RBDISTAT_ATTN 0x00000004 1060 1061/* 1062 * Receive BD Completion Control registers 1063 */ 1064#define BGE_RBDC_MODE 0x3000 1065#define BGE_RBDC_STATUS 0x3004 1066#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1067#define BGE_RBDC_STD_BD_PROD 0x300C 1068#define BGE_RBDC_MINI_BD_PROD 0x3010 1069 1070/* Receive BD completion mode register */ 1071#define BGE_RBDCMODE_RESET 0x00000001 1072#define BGE_RBDCMODE_ENABLE 0x00000002 1073#define BGE_RBDCMODE_ATTN 0x00000004 1074 1075/* Receive BD completion status register */ 1076#define BGE_RBDCSTAT_ERROR 0x00000004 1077 1078/* 1079 * Receive List Selector Control registers 1080 */ 1081#define BGE_RXLS_MODE 0x3400 1082#define BGE_RXLS_STATUS 0x3404 1083 1084/* Receive List Selector Mode register */ 1085#define BGE_RXLSMODE_RESET 0x00000001 1086#define BGE_RXLSMODE_ENABLE 0x00000002 1087#define BGE_RXLSMODE_ATTN 0x00000004 1088 1089/* Receive List Selector Status register */ 1090#define BGE_RXLSSTAT_ERROR 0x00000004 1091 1092/* 1093 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1094 */ 1095#define BGE_MBCF_MODE 0x3800 1096#define BGE_MBCF_STATUS 0x3804 1097 1098/* Mbuf Cluster Free mode register */ 1099#define BGE_MBCFMODE_RESET 0x00000001 1100#define BGE_MBCFMODE_ENABLE 0x00000002 1101#define BGE_MBCFMODE_ATTN 0x00000004 1102 1103/* Mbuf Cluster Free status register */ 1104#define BGE_MBCFSTAT_ERROR 0x00000004 1105 1106/* 1107 * Host Coalescing Control registers 1108 */ 1109#define BGE_HCC_MODE 0x3C00 1110#define BGE_HCC_STATUS 0x3C04 1111#define BGE_HCC_RX_COAL_TICKS 0x3C08 1112#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1113#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1114#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1115#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1116#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1117#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1118#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1119#define BGE_HCC_STATS_TICKS 0x3C28 1120#define BGE_HCC_STATS_ADDR_HI 0x3C30 1121#define BGE_HCC_STATS_ADDR_LO 0x3C34 1122#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1123#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1124#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1125#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1126#define BGE_FLOW_ATTN 0x3C48 1127#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1128#define BGE_HCC_STD_BD_CONS 0x3C54 1129#define BGE_HCC_MINI_BD_CONS 0x3C58 1130#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1131#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1132#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1133#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1134#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1135#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1136#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1137#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1138#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1139#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1140#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1141#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1142#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1143#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1144#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1145#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1146#define BGE_HCC_TX_BD_CONS0 0x3CC0 1147#define BGE_HCC_TX_BD_CONS1 0x3CC4 1148#define BGE_HCC_TX_BD_CONS2 0x3CC8 1149#define BGE_HCC_TX_BD_CONS3 0x3CCC 1150#define BGE_HCC_TX_BD_CONS4 0x3CD0 1151#define BGE_HCC_TX_BD_CONS5 0x3CD4 1152#define BGE_HCC_TX_BD_CONS6 0x3CD8 1153#define BGE_HCC_TX_BD_CONS7 0x3CDC 1154#define BGE_HCC_TX_BD_CONS8 0x3CE0 1155#define BGE_HCC_TX_BD_CONS9 0x3CE4 1156#define BGE_HCC_TX_BD_CONS10 0x3CE8 1157#define BGE_HCC_TX_BD_CONS11 0x3CEC 1158#define BGE_HCC_TX_BD_CONS12 0x3CF0 1159#define BGE_HCC_TX_BD_CONS13 0x3CF4 1160#define BGE_HCC_TX_BD_CONS14 0x3CF8 1161#define BGE_HCC_TX_BD_CONS15 0x3CFC 1162 1163 1164/* Host coalescing mode register */ 1165#define BGE_HCCMODE_RESET 0x00000001 1166#define BGE_HCCMODE_ENABLE 0x00000002 1167#define BGE_HCCMODE_ATTN 0x00000004 1168#define BGE_HCCMODE_COAL_NOW 0x00000008 1169#define BGE_HCCMODE_MSI_BITS 0x0x000070 1170#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1171 1172#define BGE_STATBLKSZ_FULL 0x00000000 1173#define BGE_STATBLKSZ_64BYTE 0x00000080 1174#define BGE_STATBLKSZ_32BYTE 0x00000100 1175 1176/* Host coalescing status register */ 1177#define BGE_HCCSTAT_ERROR 0x00000004 1178 1179/* Flow attention register */ 1180#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1181#define BGE_FLOWATTN_MEMARB 0x00000080 1182#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1183#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1184#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1185#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1186#define BGE_FLOWATTN_RDBDI 0x00080000 1187#define BGE_FLOWATTN_RXLS 0x00100000 1188#define BGE_FLOWATTN_RXLP 0x00200000 1189#define BGE_FLOWATTN_RBDC 0x00400000 1190#define BGE_FLOWATTN_RBDI 0x00800000 1191#define BGE_FLOWATTN_SDC 0x08000000 1192#define BGE_FLOWATTN_SDI 0x10000000 1193#define BGE_FLOWATTN_SRS 0x20000000 1194#define BGE_FLOWATTN_SBDC 0x40000000 1195#define BGE_FLOWATTN_SBDI 0x80000000 1196 1197/* 1198 * Memory arbiter registers 1199 */ 1200#define BGE_MARB_MODE 0x4000 1201#define BGE_MARB_STATUS 0x4004 1202#define BGE_MARB_TRAPADDR_HI 0x4008 1203#define BGE_MARB_TRAPADDR_LO 0x400C 1204 1205/* Memory arbiter mode register */ 1206#define BGE_MARBMODE_RESET 0x00000001 1207#define BGE_MARBMODE_ENABLE 0x00000002 1208#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1209#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1210#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1211#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1212#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1213#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1214#define BGE_MARBMODE_PCI_TRAP 0x00000100 1215#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1216#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1217#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1218#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1219#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1220#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1221#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1222#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1223#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1224#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1225#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1226#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1227#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1228#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1229#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1230#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1231#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1232 1233/* Memory arbiter status register */ 1234#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1235#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1236#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1237#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1238#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1239#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1240#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1241#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1242#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1243#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1244#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1245#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1246#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1247#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1248#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1249#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1250#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1251#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1252#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1253#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1254#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1255#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1256#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1257#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1258 1259/* 1260 * Buffer manager control registers 1261 */ 1262#define BGE_BMAN_MODE 0x4400 1263#define BGE_BMAN_STATUS 0x4404 1264#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1265#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1266#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1267#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1268#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1269#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1270#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1271#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1272#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1273#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1274#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1275#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1276#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1277#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1278#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1279#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1280#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1281#define BGE_BMAN_HWDIAG_1 0x444C 1282#define BGE_BMAN_HWDIAG_2 0x4450 1283#define BGE_BMAN_HWDIAG_3 0x4454 1284 1285/* Buffer manager mode register */ 1286#define BGE_BMANMODE_RESET 0x00000001 1287#define BGE_BMANMODE_ENABLE 0x00000002 1288#define BGE_BMANMODE_ATTN 0x00000004 1289#define BGE_BMANMODE_TESTMODE 0x00000008 1290#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1291 1292/* Buffer manager status register */ 1293#define BGE_BMANSTAT_ERRO 0x00000004 1294#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1295 1296 1297/* 1298 * Read DMA Control registers 1299 */ 1300#define BGE_RDMA_MODE 0x4800 1301#define BGE_RDMA_STATUS 0x4804 1302 1303/* Read DMA mode register */ 1304#define BGE_RDMAMODE_RESET 0x00000001 1305#define BGE_RDMAMODE_ENABLE 0x00000002 1306#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1307#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1308#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1309#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1310#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1311#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1312#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1313#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1314#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1315 1316/* Read DMA status register */ 1317#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1318#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1319#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1320#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1321#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1322#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1323#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1324#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1325 1326/* 1327 * Write DMA control registers 1328 */ 1329#define BGE_WDMA_MODE 0x4C00 1330#define BGE_WDMA_STATUS 0x4C04 1331 1332/* Write DMA mode register */ 1333#define BGE_WDMAMODE_RESET 0x00000001 1334#define BGE_WDMAMODE_ENABLE 0x00000002 1335#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1336#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1337#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1338#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1339#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1340#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1341#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1342#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1343#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1344 1345/* Write DMA status register */ 1346#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1347#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1348#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1349#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1350#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1351#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1352#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1353#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1354 1355 1356/* 1357 * RX CPU registers 1358 */ 1359#define BGE_RXCPU_MODE 0x5000 1360#define BGE_RXCPU_STATUS 0x5004 1361#define BGE_RXCPU_PC 0x501C 1362 1363/* RX CPU mode register */ 1364#define BGE_RXCPUMODE_RESET 0x00000001 1365#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1366#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1367#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1368#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1369#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1370#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1371#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1372#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1373#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1374#define BGE_RXCPUMODE_HALTCPU 0x00000400 1375#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1376#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1377#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1378 1379/* RX CPU status register */ 1380#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1381#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1382#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1383#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1384#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1385#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1386#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1387#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1388#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1389#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1390#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1391#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1392#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1393#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1394#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1395#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1396#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1397 1398 1399/* 1400 * TX CPU registers 1401 */ 1402#define BGE_TXCPU_MODE 0x5400 1403#define BGE_TXCPU_STATUS 0x5404 1404#define BGE_TXCPU_PC 0x541C 1405 1406/* TX CPU mode register */ 1407#define BGE_TXCPUMODE_RESET 0x00000001 1408#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1409#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1410#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1411#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1412#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1413#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1414#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1415#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1416#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1417#define BGE_TXCPUMODE_HALTCPU 0x00000400 1418#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1419#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1420 1421/* TX CPU status register */ 1422#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1423#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1424#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1425#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1426#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1427#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1428#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1429#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1430#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1431#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1432#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1433#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1434#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1435#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1436#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1437#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1438#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1439 1440 1441/* 1442 * Low priority mailbox registers 1443 */ 1444#define BGE_LPMBX_IRQ0_HI 0x5800 1445#define BGE_LPMBX_IRQ0_LO 0x5804 1446#define BGE_LPMBX_IRQ1_HI 0x5808 1447#define BGE_LPMBX_IRQ1_LO 0x580C 1448#define BGE_LPMBX_IRQ2_HI 0x5810 1449#define BGE_LPMBX_IRQ2_LO 0x5814 1450#define BGE_LPMBX_IRQ3_HI 0x5818 1451#define BGE_LPMBX_IRQ3_LO 0x581C 1452#define BGE_LPMBX_GEN0_HI 0x5820 1453#define BGE_LPMBX_GEN0_LO 0x5824 1454#define BGE_LPMBX_GEN1_HI 0x5828 1455#define BGE_LPMBX_GEN1_LO 0x582C 1456#define BGE_LPMBX_GEN2_HI 0x5830 1457#define BGE_LPMBX_GEN2_LO 0x5834 1458#define BGE_LPMBX_GEN3_HI 0x5828 1459#define BGE_LPMBX_GEN3_LO 0x582C 1460#define BGE_LPMBX_GEN4_HI 0x5840 1461#define BGE_LPMBX_GEN4_LO 0x5844 1462#define BGE_LPMBX_GEN5_HI 0x5848 1463#define BGE_LPMBX_GEN5_LO 0x584C 1464#define BGE_LPMBX_GEN6_HI 0x5850 1465#define BGE_LPMBX_GEN6_LO 0x5854 1466#define BGE_LPMBX_GEN7_HI 0x5858 1467#define BGE_LPMBX_GEN7_LO 0x585C 1468#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1469#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1470#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1471#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1472#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1473#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1474#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1475#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1476#define BGE_LPMBX_RX_CONS0_HI 0x5880 1477#define BGE_LPMBX_RX_CONS0_LO 0x5884 1478#define BGE_LPMBX_RX_CONS1_HI 0x5888 1479#define BGE_LPMBX_RX_CONS1_LO 0x588C 1480#define BGE_LPMBX_RX_CONS2_HI 0x5890 1481#define BGE_LPMBX_RX_CONS2_LO 0x5894 1482#define BGE_LPMBX_RX_CONS3_HI 0x5898 1483#define BGE_LPMBX_RX_CONS3_LO 0x589C 1484#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1485#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1486#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1487#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1488#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1489#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1490#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1491#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1492#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1493#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1494#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1495#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1496#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1497#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1498#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1499#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1500#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1501#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1502#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1503#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1504#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1505#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1506#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1507#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1508#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1509#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1510#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1511#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1512#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1513#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1514#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1515#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1516#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1517#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1518#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1519#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1520#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1521#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1522#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1523#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1524#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1525#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1526#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1527#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1528#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1529#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1530#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1531#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1532#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1533#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1534#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1535#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1536#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1537#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1538#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1539#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1540#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1541#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1542#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1543#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1544#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1545#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1546#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1547#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1548#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1549#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1550#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1551#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1552#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1553#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1554#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1555#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1556#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1557#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1558#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1559#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1560#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1561#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1562#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1563#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1564#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1565#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1566#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1567#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1568#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1569#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1570#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1571#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1572 1573/* 1574 * Flow throw Queue reset register 1575 */ 1576#define BGE_FTQ_RESET 0x5C00 1577 1578#define BGE_FTQRESET_DMAREAD 0x00000002 1579#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1580#define BGE_FTQRESET_DMADONE 0x00000010 1581#define BGE_FTQRESET_SBDC 0x00000020 1582#define BGE_FTQRESET_SDI 0x00000040 1583#define BGE_FTQRESET_WDMA 0x00000080 1584#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1585#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1586#define BGE_FTQRESET_SDC 0x00000400 1587#define BGE_FTQRESET_HCC 0x00000800 1588#define BGE_FTQRESET_TXFIFO 0x00001000 1589#define BGE_FTQRESET_MBC 0x00002000 1590#define BGE_FTQRESET_RBDC 0x00004000 1591#define BGE_FTQRESET_RXLP 0x00008000 1592#define BGE_FTQRESET_RDBDI 0x00010000 1593#define BGE_FTQRESET_RDC 0x00020000 1594#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1595 1596/* 1597 * Message Signaled Interrupt registers 1598 */ 1599#define BGE_MSI_MODE 0x6000 1600#define BGE_MSI_STATUS 0x6004 1601#define BGE_MSI_FIFOACCESS 0x6008 1602 1603/* MSI mode register */ 1604#define BGE_MSIMODE_RESET 0x00000001 1605#define BGE_MSIMODE_ENABLE 0x00000002 1606#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1607#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1608#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1609#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1610#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1611 1612/* MSI status register */ 1613#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1614#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1615#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1616#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1617#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1618 1619 1620/* 1621 * DMA Completion registers 1622 */ 1623#define BGE_DMAC_MODE 0x6400 1624 1625/* DMA Completion mode register */ 1626#define BGE_DMACMODE_RESET 0x00000001 1627#define BGE_DMACMODE_ENABLE 0x00000002 1628 1629 1630/* 1631 * General control registers. 1632 */ 1633#define BGE_MODE_CTL 0x6800 1634#define BGE_MISC_CFG 0x6804 1635#define BGE_MISC_LOCAL_CTL 0x6808 1636#define BGE_EE_ADDR 0x6838 1637#define BGE_EE_DATA 0x683C 1638#define BGE_EE_CTL 0x6840 1639#define BGE_MDI_CTL 0x6844 1640#define BGE_EE_DELAY 0x6848 1641 1642/* Mode control register */ 1643#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1644#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1645#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1646#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1647#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1648#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1649#define BGE_MODECTL_NO_RX_CRC 0x00000400 1650#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1651#define BGE_MODECTL_NO_TX_INTR 0x00002000 1652#define BGE_MODECTL_NO_RX_INTR 0x00004000 1653#define BGE_MODECTL_FORCE_PCI32 0x00008000 1654#define BGE_MODECTL_STACKUP 0x00010000 1655#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1656#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1657#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1658#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1659#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1660#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1661#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1662#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1663#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1664#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1665 1666/* Misc. config register */ 1667#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1668#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1669 1670#define BGE_32BITTIME_66MHZ (0x41 << 1) 1671 1672/* Misc. Local Control */ 1673#define BGE_MLC_INTR_STATE 0x00000001 1674#define BGE_MLC_INTR_CLR 0x00000002 1675#define BGE_MLC_INTR_SET 0x00000004 1676#define BGE_MLC_INTR_ONATTN 0x00000008 1677#define BGE_MLC_MISCIO_IN0 0x00000100 1678#define BGE_MLC_MISCIO_IN1 0x00000200 1679#define BGE_MLC_MISCIO_IN2 0x00000400 1680#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1681#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1682#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1683#define BGE_MLC_MISCIO_OUT0 0x00004000 1684#define BGE_MLC_MISCIO_OUT1 0x00008000 1685#define BGE_MLC_MISCIO_OUT2 0x00010000 1686#define BGE_MLC_EXTRAM_ENB 0x00020000 1687#define BGE_MLC_SRAM_SIZE 0x001C0000 1688#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1689#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1690#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1691#define BGE_MLC_AUTO_EEPROM 0x01000000 1692 1693#define BGE_SSRAMSIZE_256KB 0x00000000 1694#define BGE_SSRAMSIZE_512KB 0x00040000 1695#define BGE_SSRAMSIZE_1MB 0x00080000 1696#define BGE_SSRAMSIZE_2MB 0x000C0000 1697#define BGE_SSRAMSIZE_4MB 0x00100000 1698#define BGE_SSRAMSIZE_8MB 0x00140000 1699#define BGE_SSRAMSIZE_16M 0x00180000 1700 1701/* EEPROM address register */ 1702#define BGE_EEADDR_ADDRESS 0x0000FFFC 1703#define BGE_EEADDR_HALFCLK 0x01FF0000 1704#define BGE_EEADDR_START 0x02000000 1705#define BGE_EEADDR_DEVID 0x1C000000 1706#define BGE_EEADDR_RESET 0x20000000 1707#define BGE_EEADDR_DONE 0x40000000 1708#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1709 1710#define BGE_EEDEVID(x) ((x & 7) << 26) 1711#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1712#define BGE_HALFCLK_384SCL 0x60 1713#define BGE_EE_READCMD \ 1714 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1715 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1716#define BGE_EE_WRCMD \ 1717 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1718 BGE_EEADDR_START|BGE_EEADDR_DONE) 1719 1720/* EEPROM Control register */ 1721#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1722#define BGE_EECTL_CLKOUT 0x00000002 1723#define BGE_EECTL_CLKIN 0x00000004 1724#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1725#define BGE_EECTL_DATAOUT 0x00000010 1726#define BGE_EECTL_DATAIN 0x00000020 1727 1728/* MDI (MII/GMII) access register */ 1729#define BGE_MDI_DATA 0x00000001 1730#define BGE_MDI_DIR 0x00000002 1731#define BGE_MDI_SEL 0x00000004 1732#define BGE_MDI_CLK 0x00000008 1733 1734#define BGE_MEMWIN_START 0x00008000 1735#define BGE_MEMWIN_END 0x0000FFFF 1736 1737 1738#define BGE_MEMWIN_READ(pc, tag, x, val) \ 1739 do { \ 1740 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1741 (0xFFFF0000 & x)); \ 1742 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1743 } while(0) 1744 1745#define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 1746 do { \ 1747 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1748 (0xFFFF0000 & x)); \ 1749 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1750 } while(0) 1751 1752/* 1753 * This magic number is used to prevent PXE restart when we 1754 * issue a software reset. We write this magic number to the 1755 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1756 * code from running. 1757 */ 1758#define BGE_MAGIC_NUMBER 0x4B657654 1759 1760typedef struct { 1761 u_int32_t bge_addr_hi; 1762 u_int32_t bge_addr_lo; 1763} bge_hostaddr; 1764#define BGE_HOSTADDR(x,y) \ 1765 do { \ 1766 (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 1767 if (sizeof(bus_addr_t) == 8) \ 1768 (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 1769 else \ 1770 (x).bge_addr_hi = 0; \ 1771 } while(0) 1772 1773/* Ring control block structure */ 1774struct bge_rcb { 1775 bge_hostaddr bge_hostaddr; 1776 u_int32_t bge_maxlen_flags; 1777 u_int32_t bge_nicaddr; 1778}; 1779 1780#define RCB_WRITE_4(sc, rcb, offset, val) \ 1781 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1782 rcb + offsetof(struct bge_rcb, offset), val) 1783 1784#define RCB_WRITE_2(sc, rcb, offset, val) \ 1785 bus_space_write_2(sc->bge_btag, sc->bge_bhandle, \ 1786 rcb + offsetof(struct bge_rcb, offset), val) 1787 1788#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1789 1790#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1791#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1792 1793struct bge_tx_bd { 1794 bge_hostaddr bge_addr; 1795#if BYTE_ORDER == LITTLE_ENDIAN 1796 u_int16_t bge_flags; 1797 u_int16_t bge_len; 1798 u_int16_t bge_vlan_tag; 1799 u_int16_t bge_rsvd; 1800#else 1801 u_int16_t bge_len; 1802 u_int16_t bge_flags; 1803 u_int16_t bge_rsvd; 1804 u_int16_t bge_vlan_tag; 1805#endif 1806}; 1807 1808#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1809#define BGE_TXBDFLAG_IP_CSUM 0x0002 1810#define BGE_TXBDFLAG_END 0x0004 1811#define BGE_TXBDFLAG_IP_FRAG 0x0008 1812#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1813#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1814#define BGE_TXBDFLAG_COAL_NOW 0x0080 1815#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1816#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1817#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1818#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1819#define BGE_TXBDFLAG_NO_CRC 0x8000 1820 1821#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1822 BGE_SEND_RING_1_TO_4 + \ 1823 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1824 1825struct bge_rx_bd { 1826 bge_hostaddr bge_addr; 1827#if BYTE_ORDER == LITTLE_ENDIAN 1828 u_int16_t bge_len; 1829 u_int16_t bge_idx; 1830 u_int16_t bge_flags; 1831 u_int16_t bge_type; 1832 u_int16_t bge_tcp_udp_csum; 1833 u_int16_t bge_ip_csum; 1834 u_int16_t bge_vlan_tag; 1835 u_int16_t bge_error_flag; 1836#else 1837 u_int16_t bge_idx; 1838 u_int16_t bge_len; 1839 u_int16_t bge_type; 1840 u_int16_t bge_flags; 1841 u_int16_t bge_ip_csum; 1842 u_int16_t bge_tcp_udp_csum; 1843 u_int16_t bge_error_flag; 1844 u_int16_t bge_vlan_tag; 1845#endif 1846 u_int32_t bge_rsvd; 1847 u_int32_t bge_opaque; 1848}; 1849 1850#define BGE_RXBDFLAG_END 0x0004 1851#define BGE_RXBDFLAG_JUMBO_RING 0x0020 1852#define BGE_RXBDFLAG_VLAN_TAG 0x0040 1853#define BGE_RXBDFLAG_ERROR 0x0400 1854#define BGE_RXBDFLAG_MINI_RING 0x0800 1855#define BGE_RXBDFLAG_IP_CSUM 0x1000 1856#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1857#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1858 1859#define BGE_RXERRFLAG_BAD_CRC 0x0001 1860#define BGE_RXERRFLAG_COLL_DETECT 0x0002 1861#define BGE_RXERRFLAG_LINK_LOST 0x0004 1862#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1863#define BGE_RXERRFLAG_MAC_ABORT 0x0010 1864#define BGE_RXERRFLAG_RUNT 0x0020 1865#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1866#define BGE_RXERRFLAG_GIANT 0x0080 1867 1868struct bge_sts_idx { 1869#if BYTE_ORDER == LITTLE_ENDIAN 1870 u_int16_t bge_rx_prod_idx; 1871 u_int16_t bge_tx_cons_idx; 1872#else 1873 u_int16_t bge_tx_cons_idx; 1874 u_int16_t bge_rx_prod_idx; 1875#endif 1876}; 1877 1878struct bge_status_block { 1879 u_int32_t bge_status; 1880 u_int32_t bge_rsvd0; 1881#if BYTE_ORDER == LITTLE_ENDIAN 1882 u_int16_t bge_rx_jumbo_cons_idx; 1883 u_int16_t bge_rx_std_cons_idx; 1884 u_int16_t bge_rx_mini_cons_idx; 1885 u_int16_t bge_rsvd1; 1886#else 1887 u_int16_t bge_rx_std_cons_idx; 1888 u_int16_t bge_rx_jumbo_cons_idx; 1889 u_int16_t bge_rsvd1; 1890 u_int16_t bge_rx_mini_cons_idx; 1891#endif 1892 struct bge_sts_idx bge_idx[16]; 1893}; 1894 1895#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1896#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1897 1898#define BGE_STATFLAG_UPDATED 0x00000001 1899#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1900#define BGE_STATFLAG_ERROR 0x00000004 1901 1902/* 1903 * SysKonnect Subsystem IDs 1904 */ 1905#define SK_SUBSYSID_9D21 0x4421 1906#define SK_SUBSYSID_9D41 0x4441 1907 1908/* 1909 * Offset of MAC address inside EEPROM. 1910 */ 1911#define BGE_EE_MAC_OFFSET 0x7C 1912#define BGE_EE_HWCFG_OFFSET 0xC8 1913 1914#define BGE_HWCFG_VOLTAGE 0x00000003 1915#define BGE_HWCFG_PHYLED_MODE 0x0000000C 1916#define BGE_HWCFG_MEDIA 0x00000030 1917 1918#define BGE_VOLTAGE_1POINT3 0x00000000 1919#define BGE_VOLTAGE_1POINT8 0x00000001 1920 1921#define BGE_PHYLEDMODE_UNSPEC 0x00000000 1922#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 1923#define BGE_PHYLEDMODE_SINGLELED 0x00000008 1924 1925#define BGE_MEDIA_UNSPEC 0x00000000 1926#define BGE_MEDIA_COPPER 0x00000010 1927#define BGE_MEDIA_FIBER 0x00000020 1928 1929#define BGE_PCI_READ_CMD 0x06000000 1930#define BGE_PCI_WRITE_CMD 0x70000000 1931 1932#define BGE_TICKS_PER_SEC 1000000 1933 1934/* 1935 * Ring size constants. 1936 */ 1937#define BGE_EVENT_RING_CNT 256 1938#define BGE_CMD_RING_CNT 64 1939#define BGE_STD_RX_RING_CNT 512 1940#define BGE_JUMBO_RX_RING_CNT 256 1941#define BGE_MINI_RX_RING_CNT 1024 1942#define BGE_RETURN_RING_CNT 1024 1943 1944/* 5705 has smaller return ring size */ 1945#define BGE_RETURN_RING_CNT_5705 512 1946 1947/* 1948 * Possible TX ring sizes. 1949 */ 1950#define BGE_TX_RING_CNT_128 128 1951#define BGE_TX_RING_BASE_128 0x3800 1952 1953#define BGE_TX_RING_CNT_256 256 1954#define BGE_TX_RING_BASE_256 0x3000 1955 1956#define BGE_TX_RING_CNT_512 512 1957#define BGE_TX_RING_BASE_512 0x2000 1958 1959#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 1960#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 1961 1962/* 1963 * Tigon III statistics counters. 1964 */ 1965/* Statistics maintained MAC Receive block. */ 1966struct bge_rx_mac_stats { 1967 bge_hostaddr ifHCInOctets; 1968 bge_hostaddr Reserved1; 1969 bge_hostaddr etherStatsFragments; 1970 bge_hostaddr ifHCInUcastPkts; 1971 bge_hostaddr ifHCInMulticastPkts; 1972 bge_hostaddr ifHCInBroadcastPkts; 1973 bge_hostaddr dot3StatsFCSErrors; 1974 bge_hostaddr dot3StatsAlignmentErrors; 1975 bge_hostaddr xonPauseFramesReceived; 1976 bge_hostaddr xoffPauseFramesReceived; 1977 bge_hostaddr macControlFramesReceived; 1978 bge_hostaddr xoffStateEntered; 1979 bge_hostaddr dot3StatsFramesTooLong; 1980 bge_hostaddr etherStatsJabbers; 1981 bge_hostaddr etherStatsUndersizePkts; 1982 bge_hostaddr inRangeLengthError; 1983 bge_hostaddr outRangeLengthError; 1984 bge_hostaddr etherStatsPkts64Octets; 1985 bge_hostaddr etherStatsPkts65Octetsto127Octets; 1986 bge_hostaddr etherStatsPkts128Octetsto255Octets; 1987 bge_hostaddr etherStatsPkts256Octetsto511Octets; 1988 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 1989 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 1990 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 1991 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 1992 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 1993 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 1994}; 1995 1996/* Statistics maintained MAC Transmit block. */ 1997struct bge_tx_mac_stats { 1998 bge_hostaddr ifHCOutOctets; 1999 bge_hostaddr Reserved2; 2000 bge_hostaddr etherStatsCollisions; 2001 bge_hostaddr outXonSent; 2002 bge_hostaddr outXoffSent; 2003 bge_hostaddr flowControlDone; 2004 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2005 bge_hostaddr dot3StatsSingleCollisionFrames; 2006 bge_hostaddr dot3StatsMultipleCollisionFrames; 2007 bge_hostaddr dot3StatsDeferredTransmissions; 2008 bge_hostaddr Reserved3; 2009 bge_hostaddr dot3StatsExcessiveCollisions; 2010 bge_hostaddr dot3StatsLateCollisions; 2011 bge_hostaddr dot3Collided2Times; 2012 bge_hostaddr dot3Collided3Times; 2013 bge_hostaddr dot3Collided4Times; 2014 bge_hostaddr dot3Collided5Times; 2015 bge_hostaddr dot3Collided6Times; 2016 bge_hostaddr dot3Collided7Times; 2017 bge_hostaddr dot3Collided8Times; 2018 bge_hostaddr dot3Collided9Times; 2019 bge_hostaddr dot3Collided10Times; 2020 bge_hostaddr dot3Collided11Times; 2021 bge_hostaddr dot3Collided12Times; 2022 bge_hostaddr dot3Collided13Times; 2023 bge_hostaddr dot3Collided14Times; 2024 bge_hostaddr dot3Collided15Times; 2025 bge_hostaddr ifHCOutUcastPkts; 2026 bge_hostaddr ifHCOutMulticastPkts; 2027 bge_hostaddr ifHCOutBroadcastPkts; 2028 bge_hostaddr dot3StatsCarrierSenseErrors; 2029 bge_hostaddr ifOutDiscards; 2030 bge_hostaddr ifOutErrors; 2031}; 2032 2033/* Stats counters access through registers */ 2034struct bge_mac_stats_regs { 2035 u_int32_t ifHCOutOctets; 2036 u_int32_t Reserved0; 2037 u_int32_t etherStatsCollisions; 2038 u_int32_t outXonSent; 2039 u_int32_t outXoffSent; 2040 u_int32_t Reserved1; 2041 u_int32_t dot3StatsInternalMacTransmitErrors; 2042 u_int32_t dot3StatsSingleCollisionFrames; 2043 u_int32_t dot3StatsMultipleCollisionFrames; 2044 u_int32_t dot3StatsDeferredTransmissions; 2045 u_int32_t Reserved2; 2046 u_int32_t dot3StatsExcessiveCollisions; 2047 u_int32_t dot3StatsLateCollisions; 2048 u_int32_t Reserved3[14]; 2049 u_int32_t ifHCOutUcastPkts; 2050 u_int32_t ifHCOutMulticastPkts; 2051 u_int32_t ifHCOutBroadcastPkts; 2052 u_int32_t Reserved4[2]; 2053 u_int32_t ifHCInOctets; 2054 u_int32_t Reserved5; 2055 u_int32_t etherStatsFragments; 2056 u_int32_t ifHCInUcastPkts; 2057 u_int32_t ifHCInMulticastPkts; 2058 u_int32_t ifHCInBroadcastPkts; 2059 u_int32_t dot3StatsFCSErrors; 2060 u_int32_t dot3StatsAlignmentErrors; 2061 u_int32_t xonPauseFramesReceived; 2062 u_int32_t xoffPauseFramesReceived; 2063 u_int32_t macControlFramesReceived; 2064 u_int32_t xoffStateEntered; 2065 u_int32_t dot3StatsFramesTooLong; 2066 u_int32_t etherStatsJabbers; 2067 u_int32_t etherStatsUndersizePkts; 2068}; 2069 2070struct bge_stats { 2071 u_int8_t Reserved0[256]; 2072 2073 /* Statistics maintained by Receive MAC. */ 2074 struct bge_rx_mac_stats rxstats; 2075 2076 bge_hostaddr Unused1[37]; 2077 2078 /* Statistics maintained by Transmit MAC. */ 2079 struct bge_tx_mac_stats txstats; 2080 2081 bge_hostaddr Unused2[31]; 2082 2083 /* Statistics maintained by Receive List Placement. */ 2084 bge_hostaddr COSIfHCInPkts[16]; 2085 bge_hostaddr COSFramesDroppedDueToFilters; 2086 bge_hostaddr nicDmaWriteQueueFull; 2087 bge_hostaddr nicDmaWriteHighPriQueueFull; 2088 bge_hostaddr nicNoMoreRxBDs; 2089 bge_hostaddr ifInDiscards; 2090 bge_hostaddr ifInErrors; 2091 bge_hostaddr nicRecvThresholdHit; 2092 2093 bge_hostaddr Unused3[9]; 2094 2095 /* Statistics maintained by Send Data Initiator. */ 2096 bge_hostaddr COSIfHCOutPkts[16]; 2097 bge_hostaddr nicDmaReadQueueFull; 2098 bge_hostaddr nicDmaReadHighPriQueueFull; 2099 bge_hostaddr nicSendDataCompQueueFull; 2100 2101 /* Statistics maintained by Host Coalescing. */ 2102 bge_hostaddr nicRingSetSendProdIndex; 2103 bge_hostaddr nicRingStatusUpdate; 2104 bge_hostaddr nicInterrupts; 2105 bge_hostaddr nicAvoidedInterrupts; 2106 bge_hostaddr nicSendThresholdHit; 2107 2108 u_int8_t Reserved4[320]; 2109}; 2110 2111/* 2112 * Tigon general information block. This resides in host memory 2113 * and contains the status counters, ring control blocks and 2114 * producer pointers. 2115 */ 2116 2117struct bge_gib { 2118 struct bge_stats bge_stats; 2119 struct bge_rcb bge_tx_rcb[16]; 2120 struct bge_rcb bge_std_rx_rcb; 2121 struct bge_rcb bge_jumbo_rx_rcb; 2122 struct bge_rcb bge_mini_rx_rcb; 2123 struct bge_rcb bge_return_rcb; 2124}; 2125 2126/* 2127 * NOTE! On the Alpha, we have an alignment constraint. 2128 * The first thing in the packet is a 14-byte Ethernet header. 2129 * This means that the packet is misaligned. To compensate, 2130 * we actually offset the data 2 bytes into the cluster. This 2131 * alignes the packet after the Ethernet header at a 32-bit 2132 * boundary. 2133 */ 2134 2135#define BGE_PAGE_SIZE PAGE_SIZE 2136#define BGE_MIN_FRAMELEN 60 2137 2138/* 2139 * Other utility macros. 2140 */ 2141#define BGE_INC(x, y) (x) = (x + 1) % y 2142 2143/* 2144 * Vital product data and structures. 2145 */ 2146#define BGE_VPD_FLAG 0x8000 2147 2148/* VPD structures */ 2149struct vpd_res { 2150 u_int8_t vr_id; 2151 u_int8_t vr_len; 2152 u_int8_t vr_pad; 2153}; 2154 2155struct vpd_key { 2156 char vk_key[2]; 2157 u_int8_t vk_len; 2158}; 2159 2160#define VPD_RES_ID 0x82 /* ID string */ 2161#define VPD_RES_READ 0x90 /* start of read only area */ 2162#define VPD_RES_WRITE 0x81 /* start of read/write area */ 2163#define VPD_RES_END 0x78 /* end tag */ 2164 2165 2166/* 2167 * Register access macros. The Tigon always uses memory mapped register 2168 * accesses and all registers must be accessed with 32 bit operations. 2169 */ 2170 2171#define CSR_WRITE_4(sc, reg, val) \ 2172 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2173 2174#define CSR_READ_4(sc, reg) \ 2175 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2176 2177#define BGE_SETBIT(sc, reg, x) \ 2178 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2179#define BGE_CLRBIT(sc, reg, x) \ 2180 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2181 2182#define PCI_SETBIT(pc, tag, reg, x) \ 2183 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 2184#define PCI_CLRBIT(pc, tag, reg, x) \ 2185 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 2186 2187/* 2188 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2189 * values are tuneable. They control the actual amount of buffers 2190 * allocated for the standard, mini and jumbo receive rings. 2191 */ 2192 2193#define BGE_SSLOTS 256 2194#define BGE_MSLOTS 256 2195#define BGE_JSLOTS 384 2196 2197#define BGE_JRAWLEN (ETHER_MAX_LEN_JUMBO + ETHER_ALIGN) 2198#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2199 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2200#define BGE_JPAGESZ PAGE_SIZE 2201#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2202#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2203 2204/* 2205 * Ring structures. Most of these reside in host memory and we tell 2206 * the NIC where they are via the ring control blocks. The exceptions 2207 * are the tx and command rings, which live in NIC memory and which 2208 * we access via the shared memory window. 2209 */ 2210struct bge_ring_data { 2211 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2212 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2213 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2214 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2215 struct bge_status_block bge_status_block; 2216 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2217 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2218 struct bge_gib bge_info; 2219}; 2220 2221#define BGE_RING_DMA_ADDR(sc, offset) \ 2222 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2223 offsetof(struct bge_ring_data, offset)) 2224 2225/* 2226 * Number of DMA segments in a TxCB. Note that this is carefully 2227 * chosen to make the total struct size an even power of two. It's 2228 * critical that no TxCB be split across a page boundary since 2229 * no attempt is made to allocate physically contiguous memory. 2230 * 2231 */ 2232#ifdef __LP64__ 2233#define BGE_NTXSEG 30 2234#else 2235#define BGE_NTXSEG 31 2236#endif 2237 2238/* 2239 * Mbuf pointers. We need these to keep track of the virtual addresses 2240 * of our mbuf chains since we can only convert from physical to virtual, 2241 * not the other way around. 2242 */ 2243struct bge_chain_data { 2244 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2245 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2246 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2247 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2248 bus_dmamap_t bge_tx_map[BGE_TX_RING_CNT]; 2249 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2250 bus_dmamap_t bge_rx_jumbo_map; 2251 /* Stick the jumbo mem management stuff here too. */ 2252 caddr_t bge_jslots[BGE_JSLOTS]; 2253 void *bge_jumbo_buf; 2254}; 2255 2256#define BGE_JUMBO_DMA_ADDR(sc, m) \ 2257 ((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \ 2258 (mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf)) 2259 2260struct bge_type { 2261 u_int16_t bge_vid; 2262 u_int16_t bge_did; 2263 char *bge_name; 2264}; 2265 2266#define BGE_HWREV_TIGON 0x01 2267#define BGE_HWREV_TIGON_II 0x02 2268#define BGE_TIMEOUT 100000 2269#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2270 2271struct bge_jpool_entry { 2272 int slot; 2273 LIST_ENTRY(bge_jpool_entry) jpool_entries; 2274}; 2275 2276struct bge_softc { 2277 struct device bge_dev; 2278 struct arpcom arpcom; /* interface info */ 2279 bus_space_handle_t bge_bhandle; 2280 bus_space_tag_t bge_btag; 2281 void *bge_intrhand; 2282 struct pci_attach_args bge_pa; 2283 struct mii_data bge_mii; 2284 struct ifmedia bge_ifmedia; /* media info */ 2285 u_int8_t bge_extram; /* has external SSRAM */ 2286 u_int8_t bge_tbi; 2287 u_int8_t bge_rx_alignment_bug; 2288 bus_dma_tag_t bge_dmatag; 2289 u_int32_t bge_chipid; 2290 u_int32_t bge_quirks; 2291 u_int8_t bge_no_3_led; 2292 u_int8_t bge_pcie; 2293 struct bge_ring_data *bge_rdata; /* rings */ 2294 struct bge_chain_data bge_cdata; /* mbufs */ 2295 bus_dmamap_t bge_ring_map; 2296 u_int16_t bge_tx_saved_considx; 2297 u_int16_t bge_rx_saved_considx; 2298 u_int16_t bge_ev_saved_considx; 2299 u_int16_t bge_return_ring_cnt; 2300 u_int16_t bge_std; /* current std ring head */ 2301 u_int16_t bge_jumbo; /* current jumo ring head */ 2302 LIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2303 LIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2304 u_int32_t bge_stat_ticks; 2305 u_int32_t bge_rx_coal_ticks; 2306 u_int32_t bge_tx_coal_ticks; 2307 u_int32_t bge_rx_max_coal_bds; 2308 u_int32_t bge_tx_max_coal_bds; 2309 u_int32_t bge_tx_buf_ratio; 2310 int bge_if_flags; 2311 int bge_txcnt; 2312 int bge_link; 2313 struct timeout bge_timeout; 2314 char *bge_vpd_prodname; 2315 char *bge_vpd_readonly; 2316}; 2317