if_bgereg.h revision 1.16
1/* $OpenBSD: if_bgereg.h,v 1.16 2004/12/16 14:30:32 brad Exp $ */ 2/* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bgereg.h,v 1.11 2002/11/14 23:54:50 sam Exp $ 35 */ 36 37/* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65#define BGE_PAGE_ZERO 0x00000000 66#define BGE_PAGE_ZERO_END 0x000000FF 67#define BGE_SEND_RING_RCB 0x00000100 68#define BGE_SEND_RING_RCB_END 0x000001FF 69#define BGE_RX_RETURN_RING_RCB 0x00000200 70#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 71#define BGE_STATS_BLOCK 0x00000300 72#define BGE_STATS_BLOCK_END 0x00000AFF 73#define BGE_STATUS_BLOCK 0x00000B00 74#define BGE_STATUS_BLOCK_END 0x00000B4F 75#define BGE_SOFTWARE_GENCOMM 0x00000B50 76#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 77#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 78#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 79#define BGE_UNMAPPED 0x00001000 80#define BGE_UNMAPPED_END 0x00001FFF 81#define BGE_DMA_DESCRIPTORS 0x00002000 82#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 83#define BGE_SEND_RING_1_TO_4 0x00004000 84#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 85 86/* Mappings for internal memory configuration */ 87#define BGE_STD_RX_RINGS 0x00006000 88#define BGE_STD_RX_RINGS_END 0x00006FFF 89#define BGE_JUMBO_RX_RINGS 0x00007000 90#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 91#define BGE_BUFFPOOL_1 0x00008000 92#define BGE_BUFFPOOL_1_END 0x0000FFFF 93#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 94#define BGE_BUFFPOOL_2_END 0x00017FFF 95#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 96#define BGE_BUFFPOOL_3_END 0x0001FFFF 97 98/* Mappings for external SSRAM configurations */ 99#define BGE_SEND_RING_5_TO_6 0x00006000 100#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 101#define BGE_SEND_RING_7_TO_8 0x00007000 102#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 103#define BGE_SEND_RING_9_TO_16 0x00008000 104#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 105#define BGE_EXT_STD_RX_RINGS 0x0000C000 106#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 107#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 108#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 109#define BGE_MINI_RX_RINGS 0x0000E000 110#define BGE_MINI_RX_RINGS_END 0x0000FFFF 111#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 112#define BGE_AVAIL_REGION1_END 0x00017FFF 113#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 114#define BGE_AVAIL_REGION2_END 0x0001FFFF 115#define BGE_EXT_SSRAM 0x00020000 116#define BGE_EXT_SSRAM_END 0x000FFFFF 117 118 119/* 120 * BCM570x register offsets. These are memory mapped registers 121 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 122 * Each register must be accessed using 32 bit operations. 123 * 124 * All registers are accessed through a 32K shared memory block. 125 * The first group of registers are actually copies of the PCI 126 * configuration space registers. 127 */ 128 129/* 130 * PCI registers defined in the PCI 2.2 spec. 131 */ 132#define BGE_PCI_VID 0x00 133#define BGE_PCI_DID 0x02 134#define BGE_PCI_CMD 0x04 135#define BGE_PCI_STS 0x06 136#define BGE_PCI_REV 0x08 137#define BGE_PCI_CLASS 0x09 138#define BGE_PCI_CACHESZ 0x0C 139#define BGE_PCI_LATTIMER 0x0D 140#define BGE_PCI_HDRTYPE 0x0E 141#define BGE_PCI_BIST 0x0F 142#define BGE_PCI_BAR0 0x10 143#define BGE_PCI_BAR1 0x14 144#define BGE_PCI_SUBSYS 0x2C 145#define BGE_PCI_SUBVID 0x2E 146#define BGE_PCI_ROMBASE 0x30 147#define BGE_PCI_CAPPTR 0x34 148#define BGE_PCI_INTLINE 0x3C 149#define BGE_PCI_INTPIN 0x3D 150#define BGE_PCI_MINGNT 0x3E 151#define BGE_PCI_MAXLAT 0x3F 152#define BGE_PCI_PCIXCAP 0x40 153#define BGE_PCI_NEXTPTR_PM 0x41 154#define BGE_PCI_PCIX_CMD 0x42 155#define BGE_PCI_PCIX_STS 0x44 156#define BGE_PCI_PWRMGMT_CAPID 0x48 157#define BGE_PCI_NEXTPTR_VPD 0x49 158#define BGE_PCI_PWRMGMT_CAPS 0x4A 159#define BGE_PCI_PWRMGMT_CMD 0x4C 160#define BGE_PCI_PWRMGMT_STS 0x4D 161#define BGE_PCI_PWRMGMT_DATA 0x4F 162#define BGE_PCI_VPD_CAPID 0x50 163#define BGE_PCI_NEXTPTR_MSI 0x51 164#define BGE_PCI_VPD_ADDR 0x52 165#define BGE_PCI_VPD_DATA 0x54 166#define BGE_PCI_MSI_CAPID 0x58 167#define BGE_PCI_NEXTPTR_NONE 0x59 168#define BGE_PCI_MSI_CTL 0x5A 169#define BGE_PCI_MSI_ADDR_HI 0x5C 170#define BGE_PCI_MSI_ADDR_LO 0x60 171#define BGE_PCI_MSI_DATA 0x64 172 173/* PCI MSI. ??? */ 174#define BGE_PCIE_CAPID_REG 0xD0 175#define BGE_PCIE_CAPID 0x10 176 177/* 178 * PCI registers specific to the BCM570x family. 179 */ 180#define BGE_PCI_MISC_CTL 0x68 181#define BGE_PCI_DMA_RW_CTL 0x6C 182#define BGE_PCI_PCISTATE 0x70 183#define BGE_PCI_CLKCTL 0x74 184#define BGE_PCI_REG_BASEADDR 0x78 185#define BGE_PCI_MEMWIN_BASEADDR 0x7C 186#define BGE_PCI_REG_DATA 0x80 187#define BGE_PCI_MEMWIN_DATA 0x84 188#define BGE_PCI_MODECTL 0x88 189#define BGE_PCI_MISC_CFG 0x8C 190#define BGE_PCI_MISC_LOCALCTL 0x90 191#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 192#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 193#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 194#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 195#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 196#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 197#define BGE_PCI_ISR_MBX_HI 0xB0 198#define BGE_PCI_ISR_MBX_LO 0xB4 199 200/* PCI Misc. Host control register */ 201#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 202#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 203#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 204#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 205#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 206#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 207#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 208#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 209#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 210 211#define BGE_BIGENDIAN_INIT \ 212 (BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \ 213 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 214 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR) 215 216#define BGE_LITTLEENDIAN_INIT \ 217 (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \ 218 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS) 219 220#define BGE_CHIPID_TIGON_I 0x40000000 221#define BGE_CHIPID_TIGON_II 0x60000000 222#define BGE_CHIPID_BCM5700_A0 0x70000000 223#define BGE_CHIPID_BCM5700_A1 0x70010000 224#define BGE_CHIPID_BCM5700_B0 0x71000000 225#define BGE_CHIPID_BCM5700_B1 0x71020000 226#define BGE_CHIPID_BCM5700_B2 0x71030000 227#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 228#define BGE_CHIPID_BCM5700_C0 0x72000000 229#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 230#define BGE_CHIPID_BCM5701_B0 0x01000000 231#define BGE_CHIPID_BCM5701_B2 0x01020000 232#define BGE_CHIPID_BCM5701_B5 0x01050000 233#define BGE_CHIPID_BCM5703_A0 0x10000000 234#define BGE_CHIPID_BCM5703_A1 0x10010000 235#define BGE_CHIPID_BCM5703_A2 0x10020000 236#define BGE_CHIPID_BCM5703_A3 0x11000000 237#define BGE_CHIPID_BCM5704_A0 0x20000000 238#define BGE_CHIPID_BCM5704_A1 0x20010000 239#define BGE_CHIPID_BCM5704_A2 0x20020000 240#define BGE_CHIPID_BCM5704_A3 0x20030000 241#define BGE_CHIPID_BCM5705_A0 0x30000000 242#define BGE_CHIPID_BCM5705_A1 0x30010000 243#define BGE_CHIPID_BCM5705_A2 0x30020000 244#define BGE_CHIPID_BCM5705_A3 0x30030000 245#define BGE_CHIPID_BCM5750_A0 0x40000000 246#define BGE_CHIPID_BCM5750_A1 0x40010000 247 248/* shorthand one */ 249#define BGE_ASICREV(x) ((x) >> 28) 250#define BGE_ASICREV_BCM5700 0x07 251#define BGE_ASICREV_BCM5701 0x00 252#define BGE_ASICREV_BCM5703 0x01 253#define BGE_ASICREV_BCM5704 0x02 254#define BGE_ASICREV_BCM5705 0x03 255#define BGE_ASICREV_BCM5750 0x04 256 257/* chip revisions */ 258#define BGE_CHIPREV(x) ((x) >> 24) 259#define BGE_CHIPREV_5700_AX 0x70 260#define BGE_CHIPREV_5700_BX 0x71 261#define BGE_CHIPREV_5700_CX 0x72 262#define BGE_CHIPREV_5701_AX 0x00 263 264/* PCI DMA Read/Write Control register */ 265#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 266#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 267#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 268#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 269#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 270#define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 271#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 272#define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 273#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 274#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 275#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 276#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD_SHIFT 24 277#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 278#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD_SHIFT 28 279 280#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 281#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 282#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 283#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 284#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 285#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 286#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 287#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 288 289#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 290#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 291#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 292#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 293#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 294#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 295#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 296#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 297 298/* 299 * PCI state register -- note, this register is read only 300 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 301 * register is set. 302 */ 303#define BGE_PCISTATE_FORCE_RESET 0x00000001 304#define BGE_PCISTATE_INTR_STATE 0x00000002 305#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 306#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 307#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 308#define BGE_PCISTATE_WANT_EXPROM 0x00000020 309#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 310#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 311#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 312 313/* 314 * PCI Clock Control register -- note, this register is read only 315 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 316 * register is set. 317 */ 318#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 319#define BGE_PCICLOCKCTL_M66EN 0x00000080 320#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 321#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 322#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 323#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 324#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 325#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 326#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 327#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 328 329/* 330 * High priority mailbox registers 331 * Each mailbox is 64-bits wide, though we only use the 332 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 333 * first. The NIC will load the mailbox after the lower 32 bit word 334 * has been updated. 335 */ 336#define BGE_MBX_IRQ0_HI 0x0200 337#define BGE_MBX_IRQ0_LO 0x0204 338#define BGE_MBX_IRQ1_HI 0x0208 339#define BGE_MBX_IRQ1_LO 0x020C 340#define BGE_MBX_IRQ2_HI 0x0210 341#define BGE_MBX_IRQ2_LO 0x0214 342#define BGE_MBX_IRQ3_HI 0x0218 343#define BGE_MBX_IRQ3_LO 0x021C 344#define BGE_MBX_GEN0_HI 0x0220 345#define BGE_MBX_GEN0_LO 0x0224 346#define BGE_MBX_GEN1_HI 0x0228 347#define BGE_MBX_GEN1_LO 0x022C 348#define BGE_MBX_GEN2_HI 0x0230 349#define BGE_MBX_GEN2_LO 0x0234 350#define BGE_MBX_GEN3_HI 0x0228 351#define BGE_MBX_GEN3_LO 0x022C 352#define BGE_MBX_GEN4_HI 0x0240 353#define BGE_MBX_GEN4_LO 0x0244 354#define BGE_MBX_GEN5_HI 0x0248 355#define BGE_MBX_GEN5_LO 0x024C 356#define BGE_MBX_GEN6_HI 0x0250 357#define BGE_MBX_GEN6_LO 0x0254 358#define BGE_MBX_GEN7_HI 0x0258 359#define BGE_MBX_GEN7_LO 0x025C 360#define BGE_MBX_RELOAD_STATS_HI 0x0260 361#define BGE_MBX_RELOAD_STATS_LO 0x0264 362#define BGE_MBX_RX_STD_PROD_HI 0x0268 363#define BGE_MBX_RX_STD_PROD_LO 0x026C 364#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 365#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 366#define BGE_MBX_RX_MINI_PROD_HI 0x0278 367#define BGE_MBX_RX_MINI_PROD_LO 0x027C 368#define BGE_MBX_RX_CONS0_HI 0x0280 369#define BGE_MBX_RX_CONS0_LO 0x0284 370#define BGE_MBX_RX_CONS1_HI 0x0288 371#define BGE_MBX_RX_CONS1_LO 0x028C 372#define BGE_MBX_RX_CONS2_HI 0x0290 373#define BGE_MBX_RX_CONS2_LO 0x0294 374#define BGE_MBX_RX_CONS3_HI 0x0298 375#define BGE_MBX_RX_CONS3_LO 0x029C 376#define BGE_MBX_RX_CONS4_HI 0x02A0 377#define BGE_MBX_RX_CONS4_LO 0x02A4 378#define BGE_MBX_RX_CONS5_HI 0x02A8 379#define BGE_MBX_RX_CONS5_LO 0x02AC 380#define BGE_MBX_RX_CONS6_HI 0x02B0 381#define BGE_MBX_RX_CONS6_LO 0x02B4 382#define BGE_MBX_RX_CONS7_HI 0x02B8 383#define BGE_MBX_RX_CONS7_LO 0x02BC 384#define BGE_MBX_RX_CONS8_HI 0x02C0 385#define BGE_MBX_RX_CONS8_LO 0x02C4 386#define BGE_MBX_RX_CONS9_HI 0x02C8 387#define BGE_MBX_RX_CONS9_LO 0x02CC 388#define BGE_MBX_RX_CONS10_HI 0x02D0 389#define BGE_MBX_RX_CONS10_LO 0x02D4 390#define BGE_MBX_RX_CONS11_HI 0x02D8 391#define BGE_MBX_RX_CONS11_LO 0x02DC 392#define BGE_MBX_RX_CONS12_HI 0x02E0 393#define BGE_MBX_RX_CONS12_LO 0x02E4 394#define BGE_MBX_RX_CONS13_HI 0x02E8 395#define BGE_MBX_RX_CONS13_LO 0x02EC 396#define BGE_MBX_RX_CONS14_HI 0x02F0 397#define BGE_MBX_RX_CONS14_LO 0x02F4 398#define BGE_MBX_RX_CONS15_HI 0x02F8 399#define BGE_MBX_RX_CONS15_LO 0x02FC 400#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 401#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 402#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 403#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 404#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 405#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 406#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 407#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 408#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 409#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 410#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 411#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 412#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 413#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 414#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 415#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 416#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 417#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 418#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 419#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 420#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 421#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 422#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 423#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 424#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 425#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 426#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 427#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 428#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 429#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 430#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 431#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 432#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 433#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 434#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 435#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 436#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 437#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 438#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 439#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 440#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 441#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 442#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 443#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 444#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 445#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 446#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 447#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 448#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 449#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 450#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 451#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 452#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 453#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 454#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 455#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 456#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 457#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 458#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 459#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 460#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 461#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 462#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 463#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 464 465#define BGE_TX_RINGS_MAX 4 466#define BGE_TX_RINGS_EXTSSRAM_MAX 16 467#define BGE_RX_RINGS_MAX 16 468 469/* Ethernet MAC control registers */ 470#define BGE_MAC_MODE 0x0400 471#define BGE_MAC_STS 0x0404 472#define BGE_MAC_EVT_ENB 0x0408 473#define BGE_MAC_LED_CTL 0x040C 474#define BGE_MAC_ADDR1_LO 0x0410 475#define BGE_MAC_ADDR1_HI 0x0414 476#define BGE_MAC_ADDR2_LO 0x0418 477#define BGE_MAC_ADDR2_HI 0x041C 478#define BGE_MAC_ADDR3_LO 0x0420 479#define BGE_MAC_ADDR3_HI 0x0424 480#define BGE_MAC_ADDR4_LO 0x0428 481#define BGE_MAC_ADDR4_HI 0x042C 482#define BGE_WOL_PATPTR 0x0430 483#define BGE_WOL_PATCFG 0x0434 484#define BGE_TX_RANDOM_BACKOFF 0x0438 485#define BGE_RX_MTU 0x043C 486#define BGE_GBIT_PCS_TEST 0x0440 487#define BGE_TX_TBI_AUTONEG 0x0444 488#define BGE_RX_TBI_AUTONEG 0x0448 489#define BGE_MI_COMM 0x044C 490#define BGE_MI_STS 0x0450 491#define BGE_MI_MODE 0x0454 492#define BGE_AUTOPOLL_STS 0x0458 493#define BGE_TX_MODE 0x045C 494#define BGE_TX_STS 0x0460 495#define BGE_TX_LENGTHS 0x0464 496#define BGE_RX_MODE 0x0468 497#define BGE_RX_STS 0x046C 498#define BGE_MAR0 0x0470 499#define BGE_MAR1 0x0474 500#define BGE_MAR2 0x0478 501#define BGE_MAR3 0x047C 502#define BGE_RX_BD_RULES_CTL0 0x0480 503#define BGE_RX_BD_RULES_MASKVAL0 0x0484 504#define BGE_RX_BD_RULES_CTL1 0x0488 505#define BGE_RX_BD_RULES_MASKVAL1 0x048C 506#define BGE_RX_BD_RULES_CTL2 0x0490 507#define BGE_RX_BD_RULES_MASKVAL2 0x0494 508#define BGE_RX_BD_RULES_CTL3 0x0498 509#define BGE_RX_BD_RULES_MASKVAL3 0x049C 510#define BGE_RX_BD_RULES_CTL4 0x04A0 511#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 512#define BGE_RX_BD_RULES_CTL5 0x04A8 513#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 514#define BGE_RX_BD_RULES_CTL6 0x04B0 515#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 516#define BGE_RX_BD_RULES_CTL7 0x04B8 517#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 518#define BGE_RX_BD_RULES_CTL8 0x04C0 519#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 520#define BGE_RX_BD_RULES_CTL9 0x04C8 521#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 522#define BGE_RX_BD_RULES_CTL10 0x04D0 523#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 524#define BGE_RX_BD_RULES_CTL11 0x04D8 525#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 526#define BGE_RX_BD_RULES_CTL12 0x04E0 527#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 528#define BGE_RX_BD_RULES_CTL13 0x04E8 529#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 530#define BGE_RX_BD_RULES_CTL14 0x04F0 531#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 532#define BGE_RX_BD_RULES_CTL15 0x04F8 533#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 534#define BGE_RX_RULES_CFG 0x0500 535#define BGE_MAX_RX_FRAME_LOWAT 0x0504 536#define BGE_SERDES_CFG 0x0590 537#define BGE_SERDES_STS 0x0594 538#define BGE_SGDIG_CFG 0x05B0 539#define BGE_SGDIG_STS 0x05B4 540#define BGE_RX_STATS 0x0800 541#define BGE_TX_STATS 0x0880 542 543/* Ethernet MAC Mode register */ 544#define BGE_MACMODE_RESET 0x00000001 545#define BGE_MACMODE_HALF_DUPLEX 0x00000002 546#define BGE_MACMODE_PORTMODE 0x0000000C 547#define BGE_MACMODE_LOOPBACK 0x00000010 548#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 549#define BGE_MACMODE_TX_BURST_ENB 0x00000100 550#define BGE_MACMODE_MAX_DEFER 0x00000200 551#define BGE_MACMODE_LINK_POLARITY 0x00000400 552#define BGE_MACMODE_RX_STATS_ENB 0x00000800 553#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 554#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 555#define BGE_MACMODE_TX_STATS_ENB 0x00004000 556#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 557#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 558#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 559#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 560#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 561#define BGE_MACMODE_MIP_ENB 0x00100000 562#define BGE_MACMODE_TXDMA_ENB 0x00200000 563#define BGE_MACMODE_RXDMA_ENB 0x00400000 564#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 565 566#define BGE_PORTMODE_NONE 0x00000000 567#define BGE_PORTMODE_MII 0x00000004 568#define BGE_PORTMODE_GMII 0x00000008 569#define BGE_PORTMODE_TBI 0x0000000C 570 571/* MAC Status register */ 572#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 573#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 574#define BGE_MACSTAT_RX_CFG 0x00000004 575#define BGE_MACSTAT_CFG_CHANGED 0x00000008 576#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 577#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 578#define BGE_MACSTAT_LINK_CHANGED 0x00001000 579#define BGE_MACSTAT_MI_COMPLETE 0x00400000 580#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 581#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 582#define BGE_MACSTAT_ODI_ERROR 0x02000000 583#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 584#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 585 586/* MAC Event Enable Register */ 587#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 588#define BGE_EVTENB_LINK_CHANGED 0x00001000 589#define BGE_EVTENB_MI_COMPLETE 0x00400000 590#define BGE_EVTENB_MI_INTERRUPT 0x00800000 591#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 592#define BGE_EVTENB_ODI_ERROR 0x02000000 593#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 594#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 595 596/* LED Control Register */ 597#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 598#define BGE_LEDCTL_1000MBPS_LED 0x00000002 599#define BGE_LEDCTL_100MBPS_LED 0x00000004 600#define BGE_LEDCTL_10MBPS_LED 0x00000008 601#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 602#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 603#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 604#define BGE_LEDCTL_1000MBPS_STS 0x00000080 605#define BGE_LEDCTL_100MBPS_STS 0x00000100 606#define BGE_LEDCTL_10MBPS_STS 0x00000200 607#define BGE_LEDCTL_TRADLED_STS 0x00000400 608#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 609#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 610 611/* TX backoff seed register */ 612#define BGE_TX_BACKOFF_SEED_MASK 0x3F 613 614/* Autopoll status register */ 615#define BGE_AUTOPOLLSTS_ERROR 0x00000001 616 617/* Transmit MAC mode register */ 618#define BGE_TXMODE_RESET 0x00000001 619#define BGE_TXMODE_ENABLE 0x00000002 620#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 621#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 622#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 623 624/* Transmit MAC status register */ 625#define BGE_TXSTAT_RX_XOFFED 0x00000001 626#define BGE_TXSTAT_SENT_XOFF 0x00000002 627#define BGE_TXSTAT_SENT_XON 0x00000004 628#define BGE_TXSTAT_LINK_UP 0x00000008 629#define BGE_TXSTAT_ODI_UFLOW 0x00000010 630#define BGE_TXSTAT_ODI_OFLOW 0x00000020 631 632/* Transmit MAC lengths register */ 633#define BGE_TXLEN_SLOTTIME 0x000000FF 634#define BGE_TXLEN_IPG 0x00000F00 635#define BGE_TXLEN_CRS 0x00003000 636 637/* Receive MAC mode register */ 638#define BGE_RXMODE_RESET 0x00000001 639#define BGE_RXMODE_ENABLE 0x00000002 640#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 641#define BGE_RXMODE_RX_GIANTS 0x00000020 642#define BGE_RXMODE_RX_RUNTS 0x00000040 643#define BGE_RXMODE_8022_LENCHECK 0x00000080 644#define BGE_RXMODE_RX_PROMISC 0x00000100 645#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 646#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 647 648/* Receive MAC status register */ 649#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 650#define BGE_RXSTAT_RCVD_XOFF 0x00000002 651#define BGE_RXSTAT_RCVD_XON 0x00000004 652 653/* Receive Rules Control register */ 654#define BGE_RXRULECTL_OFFSET 0x000000FF 655#define BGE_RXRULECTL_CLASS 0x00001F00 656#define BGE_RXRULECTL_HDRTYPE 0x0000E000 657#define BGE_RXRULECTL_COMPARE_OP 0x00030000 658#define BGE_RXRULECTL_MAP 0x01000000 659#define BGE_RXRULECTL_DISCARD 0x02000000 660#define BGE_RXRULECTL_MASK 0x04000000 661#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 662#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 663#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 664#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 665 666/* Receive Rules Mask register */ 667#define BGE_RXRULEMASK_VALUE 0x0000FFFF 668#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 669 670/* SERDES configuration register */ 671#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 672#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 673#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 674#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 675#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 676#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 677#define BGE_SERDESCFG_TXMODE 0x00001000 678#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 679#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 680#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 681#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 682#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 683#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 684#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 685#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 686#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 687 688/* SERDES status register */ 689#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 690#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 691 692/* SGDIG config (not documented) */ 693#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 694#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 695#define BGE_SGDIGCFG_SEND 0x40000000 696#define BGE_SGDIGCFG_AUTO 0x80000000 697 698/* SGDIG status (not documented) */ 699#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 700#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 701#define BGE_SGDIGSTS_DONE 0x00000002 702 703/* MI communication register */ 704#define BGE_MICOMM_DATA 0x0000FFFF 705#define BGE_MICOMM_REG 0x001F0000 706#define BGE_MICOMM_PHY 0x03E00000 707#define BGE_MICOMM_CMD 0x0C000000 708#define BGE_MICOMM_READFAIL 0x10000000 709#define BGE_MICOMM_BUSY 0x20000000 710 711#define BGE_MIREG(x) ((x & 0x1F) << 16) 712#define BGE_MIPHY(x) ((x & 0x1F) << 21) 713#define BGE_MICMD_WRITE 0x04000000 714#define BGE_MICMD_READ 0x08000000 715 716/* MI status register */ 717#define BGE_MISTS_LINK 0x00000001 718#define BGE_MISTS_10MBPS 0x00000002 719 720#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 721#define BGE_MIMODE_AUTOPOLL 0x00000010 722#define BGE_MIMODE_CLKCNT 0x001F0000 723 724 725/* 726 * Send data initiator control registers. 727 */ 728#define BGE_SDI_MODE 0x0C00 729#define BGE_SDI_STATUS 0x0C04 730#define BGE_SDI_STATS_CTL 0x0C08 731#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 732#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 733#define BGE_LOCSTATS_COS0 0x0C80 734#define BGE_LOCSTATS_COS1 0x0C84 735#define BGE_LOCSTATS_COS2 0x0C88 736#define BGE_LOCSTATS_COS3 0x0C8C 737#define BGE_LOCSTATS_COS4 0x0C90 738#define BGE_LOCSTATS_COS5 0x0C84 739#define BGE_LOCSTATS_COS6 0x0C98 740#define BGE_LOCSTATS_COS7 0x0C9C 741#define BGE_LOCSTATS_COS8 0x0CA0 742#define BGE_LOCSTATS_COS9 0x0CA4 743#define BGE_LOCSTATS_COS10 0x0CA8 744#define BGE_LOCSTATS_COS11 0x0CAC 745#define BGE_LOCSTATS_COS12 0x0CB0 746#define BGE_LOCSTATS_COS13 0x0CB4 747#define BGE_LOCSTATS_COS14 0x0CB8 748#define BGE_LOCSTATS_COS15 0x0CBC 749#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 750#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 751#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 752#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 753#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 754#define BGE_LOCSTATS_IRQS 0x0CD4 755#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 756#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 757 758/* Send Data Initiator mode register */ 759#define BGE_SDIMODE_RESET 0x00000001 760#define BGE_SDIMODE_ENABLE 0x00000002 761#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 762 763/* Send Data Initiator stats register */ 764#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 765 766/* Send Data Initiator stats control register */ 767#define BGE_SDISTATSCTL_ENABLE 0x00000001 768#define BGE_SDISTATSCTL_FASTER 0x00000002 769#define BGE_SDISTATSCTL_CLEAR 0x00000004 770#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 771#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 772 773/* 774 * Send Data Completion Control registers 775 */ 776#define BGE_SDC_MODE 0x1000 777#define BGE_SDC_STATUS 0x1004 778 779/* Send Data completion mode register */ 780#define BGE_SDCMODE_RESET 0x00000001 781#define BGE_SDCMODE_ENABLE 0x00000002 782#define BGE_SDCMODE_ATTN 0x00000004 783 784/* Send Data completion status register */ 785#define BGE_SDCSTAT_ATTN 0x00000004 786 787/* 788 * Send BD Ring Selector Control registers 789 */ 790#define BGE_SRS_MODE 0x1400 791#define BGE_SRS_STATUS 0x1404 792#define BGE_SRS_HWDIAG 0x1408 793#define BGE_SRS_LOC_NIC_CONS0 0x1440 794#define BGE_SRS_LOC_NIC_CONS1 0x1444 795#define BGE_SRS_LOC_NIC_CONS2 0x1448 796#define BGE_SRS_LOC_NIC_CONS3 0x144C 797#define BGE_SRS_LOC_NIC_CONS4 0x1450 798#define BGE_SRS_LOC_NIC_CONS5 0x1454 799#define BGE_SRS_LOC_NIC_CONS6 0x1458 800#define BGE_SRS_LOC_NIC_CONS7 0x145C 801#define BGE_SRS_LOC_NIC_CONS8 0x1460 802#define BGE_SRS_LOC_NIC_CONS9 0x1464 803#define BGE_SRS_LOC_NIC_CONS10 0x1468 804#define BGE_SRS_LOC_NIC_CONS11 0x146C 805#define BGE_SRS_LOC_NIC_CONS12 0x1470 806#define BGE_SRS_LOC_NIC_CONS13 0x1474 807#define BGE_SRS_LOC_NIC_CONS14 0x1478 808#define BGE_SRS_LOC_NIC_CONS15 0x147C 809 810/* Send BD Ring Selector Mode register */ 811#define BGE_SRSMODE_RESET 0x00000001 812#define BGE_SRSMODE_ENABLE 0x00000002 813#define BGE_SRSMODE_ATTN 0x00000004 814 815/* Send BD Ring Selector Status register */ 816#define BGE_SRSSTAT_ERROR 0x00000004 817 818/* Send BD Ring Selector HW Diagnostics register */ 819#define BGE_SRSHWDIAG_STATE 0x0000000F 820#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 821#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 822#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 823 824/* 825 * Send BD Initiator Selector Control registers 826 */ 827#define BGE_SBDI_MODE 0x1800 828#define BGE_SBDI_STATUS 0x1804 829#define BGE_SBDI_LOC_NIC_PROD0 0x1808 830#define BGE_SBDI_LOC_NIC_PROD1 0x180C 831#define BGE_SBDI_LOC_NIC_PROD2 0x1810 832#define BGE_SBDI_LOC_NIC_PROD3 0x1814 833#define BGE_SBDI_LOC_NIC_PROD4 0x1818 834#define BGE_SBDI_LOC_NIC_PROD5 0x181C 835#define BGE_SBDI_LOC_NIC_PROD6 0x1820 836#define BGE_SBDI_LOC_NIC_PROD7 0x1824 837#define BGE_SBDI_LOC_NIC_PROD8 0x1828 838#define BGE_SBDI_LOC_NIC_PROD9 0x182C 839#define BGE_SBDI_LOC_NIC_PROD10 0x1830 840#define BGE_SBDI_LOC_NIC_PROD11 0x1834 841#define BGE_SBDI_LOC_NIC_PROD12 0x1838 842#define BGE_SBDI_LOC_NIC_PROD13 0x183C 843#define BGE_SBDI_LOC_NIC_PROD14 0x1840 844#define BGE_SBDI_LOC_NIC_PROD15 0x1844 845 846/* Send BD Initiator Mode register */ 847#define BGE_SBDIMODE_RESET 0x00000001 848#define BGE_SBDIMODE_ENABLE 0x00000002 849#define BGE_SBDIMODE_ATTN 0x00000004 850 851/* Send BD Initiator Status register */ 852#define BGE_SBDISTAT_ERROR 0x00000004 853 854/* 855 * Send BD Completion Control registers 856 */ 857#define BGE_SBDC_MODE 0x1C00 858#define BGE_SBDC_STATUS 0x1C04 859 860/* Send BD Completion Control Mode register */ 861#define BGE_SBDCMODE_RESET 0x00000001 862#define BGE_SBDCMODE_ENABLE 0x00000002 863#define BGE_SBDCMODE_ATTN 0x00000004 864 865/* Send BD Completion Control Status register */ 866#define BGE_SBDCSTAT_ATTN 0x00000004 867 868/* 869 * Receive List Placement Control registers 870 */ 871#define BGE_RXLP_MODE 0x2000 872#define BGE_RXLP_STATUS 0x2004 873#define BGE_RXLP_SEL_LIST_LOCK 0x2008 874#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 875#define BGE_RXLP_CFG 0x2010 876#define BGE_RXLP_STATS_CTL 0x2014 877#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 878#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 879#define BGE_RXLP_HEAD0 0x2100 880#define BGE_RXLP_TAIL0 0x2104 881#define BGE_RXLP_COUNT0 0x2108 882#define BGE_RXLP_HEAD1 0x2110 883#define BGE_RXLP_TAIL1 0x2114 884#define BGE_RXLP_COUNT1 0x2118 885#define BGE_RXLP_HEAD2 0x2120 886#define BGE_RXLP_TAIL2 0x2124 887#define BGE_RXLP_COUNT2 0x2128 888#define BGE_RXLP_HEAD3 0x2130 889#define BGE_RXLP_TAIL3 0x2134 890#define BGE_RXLP_COUNT3 0x2138 891#define BGE_RXLP_HEAD4 0x2140 892#define BGE_RXLP_TAIL4 0x2144 893#define BGE_RXLP_COUNT4 0x2148 894#define BGE_RXLP_HEAD5 0x2150 895#define BGE_RXLP_TAIL5 0x2154 896#define BGE_RXLP_COUNT5 0x2158 897#define BGE_RXLP_HEAD6 0x2160 898#define BGE_RXLP_TAIL6 0x2164 899#define BGE_RXLP_COUNT6 0x2168 900#define BGE_RXLP_HEAD7 0x2170 901#define BGE_RXLP_TAIL7 0x2174 902#define BGE_RXLP_COUNT7 0x2178 903#define BGE_RXLP_HEAD8 0x2180 904#define BGE_RXLP_TAIL8 0x2184 905#define BGE_RXLP_COUNT8 0x2188 906#define BGE_RXLP_HEAD9 0x2190 907#define BGE_RXLP_TAIL9 0x2194 908#define BGE_RXLP_COUNT9 0x2198 909#define BGE_RXLP_HEAD10 0x21A0 910#define BGE_RXLP_TAIL10 0x21A4 911#define BGE_RXLP_COUNT10 0x21A8 912#define BGE_RXLP_HEAD11 0x21B0 913#define BGE_RXLP_TAIL11 0x21B4 914#define BGE_RXLP_COUNT11 0x21B8 915#define BGE_RXLP_HEAD12 0x21C0 916#define BGE_RXLP_TAIL12 0x21C4 917#define BGE_RXLP_COUNT12 0x21C8 918#define BGE_RXLP_HEAD13 0x21D0 919#define BGE_RXLP_TAIL13 0x21D4 920#define BGE_RXLP_COUNT13 0x21D8 921#define BGE_RXLP_HEAD14 0x21E0 922#define BGE_RXLP_TAIL14 0x21E4 923#define BGE_RXLP_COUNT14 0x21E8 924#define BGE_RXLP_HEAD15 0x21F0 925#define BGE_RXLP_TAIL15 0x21F4 926#define BGE_RXLP_COUNT15 0x21F8 927#define BGE_RXLP_LOCSTAT_COS0 0x2200 928#define BGE_RXLP_LOCSTAT_COS1 0x2204 929#define BGE_RXLP_LOCSTAT_COS2 0x2208 930#define BGE_RXLP_LOCSTAT_COS3 0x220C 931#define BGE_RXLP_LOCSTAT_COS4 0x2210 932#define BGE_RXLP_LOCSTAT_COS5 0x2214 933#define BGE_RXLP_LOCSTAT_COS6 0x2218 934#define BGE_RXLP_LOCSTAT_COS7 0x221C 935#define BGE_RXLP_LOCSTAT_COS8 0x2220 936#define BGE_RXLP_LOCSTAT_COS9 0x2224 937#define BGE_RXLP_LOCSTAT_COS10 0x2228 938#define BGE_RXLP_LOCSTAT_COS11 0x222C 939#define BGE_RXLP_LOCSTAT_COS12 0x2230 940#define BGE_RXLP_LOCSTAT_COS13 0x2234 941#define BGE_RXLP_LOCSTAT_COS14 0x2238 942#define BGE_RXLP_LOCSTAT_COS15 0x223C 943#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 944#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 945#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 946#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 947#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 948#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 949#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 950 951 952/* Receive List Placement mode register */ 953#define BGE_RXLPMODE_RESET 0x00000001 954#define BGE_RXLPMODE_ENABLE 0x00000002 955#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 956#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 957#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 958 959/* Receive List Placement Status register */ 960#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 961#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 962#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 963 964/* 965 * Receive Data and Receive BD Initiator Control Registers 966 */ 967#define BGE_RDBDI_MODE 0x2400 968#define BGE_RDBDI_STATUS 0x2404 969#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 970#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 971#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 972#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 973#define BGE_RX_STD_RCB_HADDR_HI 0x2450 974#define BGE_RX_STD_RCB_HADDR_LO 0x2454 975#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 976#define BGE_RX_STD_RCB_NICADDR 0x245C 977#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 978#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 979#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 980#define BGE_RX_MINI_RCB_NICADDR 0x246C 981#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 982#define BGE_RDBDI_STD_RX_CONS 0x2474 983#define BGE_RDBDI_MINI_RX_CONS 0x2478 984#define BGE_RDBDI_RETURN_PROD0 0x2480 985#define BGE_RDBDI_RETURN_PROD1 0x2484 986#define BGE_RDBDI_RETURN_PROD2 0x2488 987#define BGE_RDBDI_RETURN_PROD3 0x248C 988#define BGE_RDBDI_RETURN_PROD4 0x2490 989#define BGE_RDBDI_RETURN_PROD5 0x2494 990#define BGE_RDBDI_RETURN_PROD6 0x2498 991#define BGE_RDBDI_RETURN_PROD7 0x249C 992#define BGE_RDBDI_RETURN_PROD8 0x24A0 993#define BGE_RDBDI_RETURN_PROD9 0x24A4 994#define BGE_RDBDI_RETURN_PROD10 0x24A8 995#define BGE_RDBDI_RETURN_PROD11 0x24AC 996#define BGE_RDBDI_RETURN_PROD12 0x24B0 997#define BGE_RDBDI_RETURN_PROD13 0x24B4 998#define BGE_RDBDI_RETURN_PROD14 0x24B8 999#define BGE_RDBDI_RETURN_PROD15 0x24BC 1000#define BGE_RDBDI_HWDIAG 0x24C0 1001 1002 1003/* Receive Data and Receive BD Initiator Mode register */ 1004#define BGE_RDBDIMODE_RESET 0x00000001 1005#define BGE_RDBDIMODE_ENABLE 0x00000002 1006#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1007#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1008#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1009 1010/* Receive Data and Receive BD Initiator Status register */ 1011#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1012#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1013#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1014 1015 1016/* 1017 * Receive Data Completion Control registers 1018 */ 1019#define BGE_RDC_MODE 0x2800 1020 1021/* Receive Data Completion Mode register */ 1022#define BGE_RDCMODE_RESET 0x00000001 1023#define BGE_RDCMODE_ENABLE 0x00000002 1024#define BGE_RDCMODE_ATTN 0x00000004 1025 1026/* 1027 * Receive BD Initiator Control registers 1028 */ 1029#define BGE_RBDI_MODE 0x2C00 1030#define BGE_RBDI_STATUS 0x2C04 1031#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1032#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1033#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1034#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1035#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1036#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1037 1038/* Receive BD Initiator Mode register */ 1039#define BGE_RBDIMODE_RESET 0x00000001 1040#define BGE_RBDIMODE_ENABLE 0x00000002 1041#define BGE_RBDIMODE_ATTN 0x00000004 1042 1043/* Receive BD Initiator Status register */ 1044#define BGE_RBDISTAT_ATTN 0x00000004 1045 1046/* 1047 * Receive BD Completion Control registers 1048 */ 1049#define BGE_RBDC_MODE 0x3000 1050#define BGE_RBDC_STATUS 0x3004 1051#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1052#define BGE_RBDC_STD_BD_PROD 0x300C 1053#define BGE_RBDC_MINI_BD_PROD 0x3010 1054 1055/* Receive BD completion mode register */ 1056#define BGE_RBDCMODE_RESET 0x00000001 1057#define BGE_RBDCMODE_ENABLE 0x00000002 1058#define BGE_RBDCMODE_ATTN 0x00000004 1059 1060/* Receive BD completion status register */ 1061#define BGE_RBDCSTAT_ERROR 0x00000004 1062 1063/* 1064 * Receive List Selector Control registers 1065 */ 1066#define BGE_RXLS_MODE 0x3400 1067#define BGE_RXLS_STATUS 0x3404 1068 1069/* Receive List Selector Mode register */ 1070#define BGE_RXLSMODE_RESET 0x00000001 1071#define BGE_RXLSMODE_ENABLE 0x00000002 1072#define BGE_RXLSMODE_ATTN 0x00000004 1073 1074/* Receive List Selector Status register */ 1075#define BGE_RXLSSTAT_ERROR 0x00000004 1076 1077/* 1078 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1079 */ 1080#define BGE_MBCF_MODE 0x3800 1081#define BGE_MBCF_STATUS 0x3804 1082 1083/* Mbuf Cluster Free mode register */ 1084#define BGE_MBCFMODE_RESET 0x00000001 1085#define BGE_MBCFMODE_ENABLE 0x00000002 1086#define BGE_MBCFMODE_ATTN 0x00000004 1087 1088/* Mbuf Cluster Free status register */ 1089#define BGE_MBCFSTAT_ERROR 0x00000004 1090 1091/* 1092 * Host Coalescing Control registers 1093 */ 1094#define BGE_HCC_MODE 0x3C00 1095#define BGE_HCC_STATUS 0x3C04 1096#define BGE_HCC_RX_COAL_TICKS 0x3C08 1097#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1098#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1099#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1100#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1101#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1102#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1103#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1104#define BGE_HCC_STATS_TICKS 0x3C28 1105#define BGE_HCC_STATS_ADDR_HI 0x3C30 1106#define BGE_HCC_STATS_ADDR_LO 0x3C34 1107#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1108#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1109#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1110#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1111#define BGE_FLOW_ATTN 0x3C48 1112#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1113#define BGE_HCC_STD_BD_CONS 0x3C54 1114#define BGE_HCC_MINI_BD_CONS 0x3C58 1115#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1116#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1117#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1118#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1119#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1120#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1121#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1122#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1123#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1124#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1125#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1126#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1127#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1128#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1129#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1130#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1131#define BGE_HCC_TX_BD_CONS0 0x3CC0 1132#define BGE_HCC_TX_BD_CONS1 0x3CC4 1133#define BGE_HCC_TX_BD_CONS2 0x3CC8 1134#define BGE_HCC_TX_BD_CONS3 0x3CCC 1135#define BGE_HCC_TX_BD_CONS4 0x3CD0 1136#define BGE_HCC_TX_BD_CONS5 0x3CD4 1137#define BGE_HCC_TX_BD_CONS6 0x3CD8 1138#define BGE_HCC_TX_BD_CONS7 0x3CDC 1139#define BGE_HCC_TX_BD_CONS8 0x3CE0 1140#define BGE_HCC_TX_BD_CONS9 0x3CE4 1141#define BGE_HCC_TX_BD_CONS10 0x3CE8 1142#define BGE_HCC_TX_BD_CONS11 0x3CEC 1143#define BGE_HCC_TX_BD_CONS12 0x3CF0 1144#define BGE_HCC_TX_BD_CONS13 0x3CF4 1145#define BGE_HCC_TX_BD_CONS14 0x3CF8 1146#define BGE_HCC_TX_BD_CONS15 0x3CFC 1147 1148 1149/* Host coalescing mode register */ 1150#define BGE_HCCMODE_RESET 0x00000001 1151#define BGE_HCCMODE_ENABLE 0x00000002 1152#define BGE_HCCMODE_ATTN 0x00000004 1153#define BGE_HCCMODE_COAL_NOW 0x00000008 1154#define BGE_HCCMODE_MSI_BITS 0x0x000070 1155#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1156 1157#define BGE_STATBLKSZ_FULL 0x00000000 1158#define BGE_STATBLKSZ_64BYTE 0x00000080 1159#define BGE_STATBLKSZ_32BYTE 0x00000100 1160 1161/* Host coalescing status register */ 1162#define BGE_HCCSTAT_ERROR 0x00000004 1163 1164/* Flow attention register */ 1165#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1166#define BGE_FLOWATTN_MEMARB 0x00000080 1167#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1168#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1169#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1170#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1171#define BGE_FLOWATTN_RDBDI 0x00080000 1172#define BGE_FLOWATTN_RXLS 0x00100000 1173#define BGE_FLOWATTN_RXLP 0x00200000 1174#define BGE_FLOWATTN_RBDC 0x00400000 1175#define BGE_FLOWATTN_RBDI 0x00800000 1176#define BGE_FLOWATTN_SDC 0x08000000 1177#define BGE_FLOWATTN_SDI 0x10000000 1178#define BGE_FLOWATTN_SRS 0x20000000 1179#define BGE_FLOWATTN_SBDC 0x40000000 1180#define BGE_FLOWATTN_SBDI 0x80000000 1181 1182/* 1183 * Memory arbiter registers 1184 */ 1185#define BGE_MARB_MODE 0x4000 1186#define BGE_MARB_STATUS 0x4004 1187#define BGE_MARB_TRAPADDR_HI 0x4008 1188#define BGE_MARB_TRAPADDR_LO 0x400C 1189 1190/* Memory arbiter mode register */ 1191#define BGE_MARBMODE_RESET 0x00000001 1192#define BGE_MARBMODE_ENABLE 0x00000002 1193#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1194#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1195#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1196#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1197#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1198#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1199#define BGE_MARBMODE_PCI_TRAP 0x00000100 1200#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1201#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1202#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1203#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1204#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1205#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1206#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1207#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1208#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1209#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1210#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1211#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1212#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1213#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1214#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1215#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1216#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1217 1218/* Memory arbiter status register */ 1219#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1220#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1221#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1222#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1223#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1224#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1225#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1226#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1227#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1228#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1229#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1230#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1231#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1232#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1233#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1234#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1235#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1236#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1237#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1238#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1239#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1240#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1241#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1242#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1243 1244/* 1245 * Buffer manager control registers 1246 */ 1247#define BGE_BMAN_MODE 0x4400 1248#define BGE_BMAN_STATUS 0x4404 1249#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1250#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1251#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1252#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1253#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1254#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1255#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1256#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1257#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1258#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1259#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1260#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1261#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1262#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1263#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1264#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1265#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1266#define BGE_BMAN_HWDIAG_1 0x444C 1267#define BGE_BMAN_HWDIAG_2 0x4450 1268#define BGE_BMAN_HWDIAG_3 0x4454 1269 1270/* Buffer manager mode register */ 1271#define BGE_BMANMODE_RESET 0x00000001 1272#define BGE_BMANMODE_ENABLE 0x00000002 1273#define BGE_BMANMODE_ATTN 0x00000004 1274#define BGE_BMANMODE_TESTMODE 0x00000008 1275#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1276 1277/* Buffer manager status register */ 1278#define BGE_BMANSTAT_ERRO 0x00000004 1279#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1280 1281 1282/* 1283 * Read DMA Control registers 1284 */ 1285#define BGE_RDMA_MODE 0x4800 1286#define BGE_RDMA_STATUS 0x4804 1287 1288/* Read DMA mode register */ 1289#define BGE_RDMAMODE_RESET 0x00000001 1290#define BGE_RDMAMODE_ENABLE 0x00000002 1291#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1292#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1293#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1294#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1295#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1296#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1297#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1298#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1299#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1300 1301/* Read DMA status register */ 1302#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1303#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1304#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1305#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1306#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1307#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1308#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1309#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1310 1311/* 1312 * Write DMA control registers 1313 */ 1314#define BGE_WDMA_MODE 0x4C00 1315#define BGE_WDMA_STATUS 0x4C04 1316 1317/* Write DMA mode register */ 1318#define BGE_WDMAMODE_RESET 0x00000001 1319#define BGE_WDMAMODE_ENABLE 0x00000002 1320#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1321#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1322#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1323#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1324#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1325#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1326#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1327#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1328#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1329 1330/* Write DMA status register */ 1331#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1332#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1333#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1334#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1335#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1336#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1337#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1338#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1339 1340 1341/* 1342 * RX CPU registers 1343 */ 1344#define BGE_RXCPU_MODE 0x5000 1345#define BGE_RXCPU_STATUS 0x5004 1346#define BGE_RXCPU_PC 0x501C 1347 1348/* RX CPU mode register */ 1349#define BGE_RXCPUMODE_RESET 0x00000001 1350#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1351#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1352#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1353#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1354#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1355#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1356#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1357#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1358#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1359#define BGE_RXCPUMODE_HALTCPU 0x00000400 1360#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1361#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1362#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1363 1364/* RX CPU status register */ 1365#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1366#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1367#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1368#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1369#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1370#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1371#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1372#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1373#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1374#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1375#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1376#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1377#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1378#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1379#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1380#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1381#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1382 1383 1384/* 1385 * TX CPU registers 1386 */ 1387#define BGE_TXCPU_MODE 0x5400 1388#define BGE_TXCPU_STATUS 0x5404 1389#define BGE_TXCPU_PC 0x541C 1390 1391/* TX CPU mode register */ 1392#define BGE_TXCPUMODE_RESET 0x00000001 1393#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1394#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1395#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1396#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1397#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1398#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1399#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1400#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1401#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1402#define BGE_TXCPUMODE_HALTCPU 0x00000400 1403#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1404#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1405 1406/* TX CPU status register */ 1407#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1408#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1409#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1410#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1411#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1412#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1413#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1414#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1415#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1416#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1417#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1418#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1419#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1420#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1421#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1422#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1423#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1424 1425 1426/* 1427 * Low priority mailbox registers 1428 */ 1429#define BGE_LPMBX_IRQ0_HI 0x5800 1430#define BGE_LPMBX_IRQ0_LO 0x5804 1431#define BGE_LPMBX_IRQ1_HI 0x5808 1432#define BGE_LPMBX_IRQ1_LO 0x580C 1433#define BGE_LPMBX_IRQ2_HI 0x5810 1434#define BGE_LPMBX_IRQ2_LO 0x5814 1435#define BGE_LPMBX_IRQ3_HI 0x5818 1436#define BGE_LPMBX_IRQ3_LO 0x581C 1437#define BGE_LPMBX_GEN0_HI 0x5820 1438#define BGE_LPMBX_GEN0_LO 0x5824 1439#define BGE_LPMBX_GEN1_HI 0x5828 1440#define BGE_LPMBX_GEN1_LO 0x582C 1441#define BGE_LPMBX_GEN2_HI 0x5830 1442#define BGE_LPMBX_GEN2_LO 0x5834 1443#define BGE_LPMBX_GEN3_HI 0x5828 1444#define BGE_LPMBX_GEN3_LO 0x582C 1445#define BGE_LPMBX_GEN4_HI 0x5840 1446#define BGE_LPMBX_GEN4_LO 0x5844 1447#define BGE_LPMBX_GEN5_HI 0x5848 1448#define BGE_LPMBX_GEN5_LO 0x584C 1449#define BGE_LPMBX_GEN6_HI 0x5850 1450#define BGE_LPMBX_GEN6_LO 0x5854 1451#define BGE_LPMBX_GEN7_HI 0x5858 1452#define BGE_LPMBX_GEN7_LO 0x585C 1453#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1454#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1455#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1456#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1457#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1458#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1459#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1460#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1461#define BGE_LPMBX_RX_CONS0_HI 0x5880 1462#define BGE_LPMBX_RX_CONS0_LO 0x5884 1463#define BGE_LPMBX_RX_CONS1_HI 0x5888 1464#define BGE_LPMBX_RX_CONS1_LO 0x588C 1465#define BGE_LPMBX_RX_CONS2_HI 0x5890 1466#define BGE_LPMBX_RX_CONS2_LO 0x5894 1467#define BGE_LPMBX_RX_CONS3_HI 0x5898 1468#define BGE_LPMBX_RX_CONS3_LO 0x589C 1469#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1470#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1471#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1472#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1473#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1474#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1475#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1476#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1477#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1478#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1479#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1480#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1481#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1482#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1483#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1484#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1485#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1486#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1487#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1488#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1489#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1490#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1491#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1492#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1493#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1494#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1495#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1496#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1497#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1498#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1499#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1500#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1501#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1502#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1503#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1504#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1505#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1506#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1507#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1508#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1509#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1510#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1511#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1512#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1513#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1514#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1515#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1516#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1517#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1518#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1519#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1520#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1521#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1522#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1523#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1524#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1525#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1526#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1527#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1528#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1529#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1530#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1531#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1532#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1533#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1534#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1535#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1536#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1537#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1538#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1539#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1540#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1541#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1542#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1543#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1544#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1545#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1546#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1547#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1548#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1549#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1550#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1551#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1552#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1553#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1554#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1555#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1556#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1557 1558/* 1559 * Flow throw Queue reset register 1560 */ 1561#define BGE_FTQ_RESET 0x5C00 1562 1563#define BGE_FTQRESET_DMAREAD 0x00000002 1564#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1565#define BGE_FTQRESET_DMADONE 0x00000010 1566#define BGE_FTQRESET_SBDC 0x00000020 1567#define BGE_FTQRESET_SDI 0x00000040 1568#define BGE_FTQRESET_WDMA 0x00000080 1569#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1570#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1571#define BGE_FTQRESET_SDC 0x00000400 1572#define BGE_FTQRESET_HCC 0x00000800 1573#define BGE_FTQRESET_TXFIFO 0x00001000 1574#define BGE_FTQRESET_MBC 0x00002000 1575#define BGE_FTQRESET_RBDC 0x00004000 1576#define BGE_FTQRESET_RXLP 0x00008000 1577#define BGE_FTQRESET_RDBDI 0x00010000 1578#define BGE_FTQRESET_RDC 0x00020000 1579#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1580 1581/* 1582 * Message Signaled Interrupt registers 1583 */ 1584#define BGE_MSI_MODE 0x6000 1585#define BGE_MSI_STATUS 0x6004 1586#define BGE_MSI_FIFOACCESS 0x6008 1587 1588/* MSI mode register */ 1589#define BGE_MSIMODE_RESET 0x00000001 1590#define BGE_MSIMODE_ENABLE 0x00000002 1591#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1592#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1593#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1594#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1595#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1596 1597/* MSI status register */ 1598#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1599#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1600#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1601#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1602#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1603 1604 1605/* 1606 * DMA Completion registers 1607 */ 1608#define BGE_DMAC_MODE 0x6400 1609 1610/* DMA Completion mode register */ 1611#define BGE_DMACMODE_RESET 0x00000001 1612#define BGE_DMACMODE_ENABLE 0x00000002 1613 1614 1615/* 1616 * General control registers. 1617 */ 1618#define BGE_MODE_CTL 0x6800 1619#define BGE_MISC_CFG 0x6804 1620#define BGE_MISC_LOCAL_CTL 0x6808 1621#define BGE_EE_ADDR 0x6838 1622#define BGE_EE_DATA 0x683C 1623#define BGE_EE_CTL 0x6840 1624#define BGE_MDI_CTL 0x6844 1625#define BGE_EE_DELAY 0x6848 1626 1627/* Mode control register */ 1628#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1629#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1630#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1631#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1632#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1633#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1634#define BGE_MODECTL_NO_RX_CRC 0x00000400 1635#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1636#define BGE_MODECTL_NO_TX_INTR 0x00002000 1637#define BGE_MODECTL_NO_RX_INTR 0x00004000 1638#define BGE_MODECTL_FORCE_PCI32 0x00008000 1639#define BGE_MODECTL_STACKUP 0x00010000 1640#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1641#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1642#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1643#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1644#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1645#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1646#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1647#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1648#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1649#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1650 1651/* Misc. config register */ 1652#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1653#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1654 1655#define BGE_32BITTIME_66MHZ (0x41 << 1) 1656 1657/* Misc. Local Control */ 1658#define BGE_MLC_INTR_STATE 0x00000001 1659#define BGE_MLC_INTR_CLR 0x00000002 1660#define BGE_MLC_INTR_SET 0x00000004 1661#define BGE_MLC_INTR_ONATTN 0x00000008 1662#define BGE_MLC_MISCIO_IN0 0x00000100 1663#define BGE_MLC_MISCIO_IN1 0x00000200 1664#define BGE_MLC_MISCIO_IN2 0x00000400 1665#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1666#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1667#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1668#define BGE_MLC_MISCIO_OUT0 0x00004000 1669#define BGE_MLC_MISCIO_OUT1 0x00008000 1670#define BGE_MLC_MISCIO_OUT2 0x00010000 1671#define BGE_MLC_EXTRAM_ENB 0x00020000 1672#define BGE_MLC_SRAM_SIZE 0x001C0000 1673#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1674#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1675#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1676#define BGE_MLC_AUTO_EEPROM 0x01000000 1677 1678#define BGE_SSRAMSIZE_256KB 0x00000000 1679#define BGE_SSRAMSIZE_512KB 0x00040000 1680#define BGE_SSRAMSIZE_1MB 0x00080000 1681#define BGE_SSRAMSIZE_2MB 0x000C0000 1682#define BGE_SSRAMSIZE_4MB 0x00100000 1683#define BGE_SSRAMSIZE_8MB 0x00140000 1684#define BGE_SSRAMSIZE_16M 0x00180000 1685 1686/* EEPROM address register */ 1687#define BGE_EEADDR_ADDRESS 0x0000FFFC 1688#define BGE_EEADDR_HALFCLK 0x01FF0000 1689#define BGE_EEADDR_START 0x02000000 1690#define BGE_EEADDR_DEVID 0x1C000000 1691#define BGE_EEADDR_RESET 0x20000000 1692#define BGE_EEADDR_DONE 0x40000000 1693#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1694 1695#define BGE_EEDEVID(x) ((x & 7) << 26) 1696#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1697#define BGE_HALFCLK_384SCL 0x60 1698#define BGE_EE_READCMD \ 1699 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1700 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1701#define BGE_EE_WRCMD \ 1702 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1703 BGE_EEADDR_START|BGE_EEADDR_DONE) 1704 1705/* EEPROM Control register */ 1706#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1707#define BGE_EECTL_CLKOUT 0x00000002 1708#define BGE_EECTL_CLKIN 0x00000004 1709#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1710#define BGE_EECTL_DATAOUT 0x00000010 1711#define BGE_EECTL_DATAIN 0x00000020 1712 1713/* MDI (MII/GMII) access register */ 1714#define BGE_MDI_DATA 0x00000001 1715#define BGE_MDI_DIR 0x00000002 1716#define BGE_MDI_SEL 0x00000004 1717#define BGE_MDI_CLK 0x00000008 1718 1719#define BGE_MEMWIN_START 0x00008000 1720#define BGE_MEMWIN_END 0x0000FFFF 1721 1722 1723#define BGE_MEMWIN_READ(pc, tag, x, val) \ 1724 do { \ 1725 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1726 (0xFFFF0000 & x)); \ 1727 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1728 } while(0) 1729 1730#define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 1731 do { \ 1732 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1733 (0xFFFF0000 & x)); \ 1734 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1735 } while(0) 1736 1737/* 1738 * This magic number is used to prevent PXE restart when we 1739 * issue a software reset. We write this magic number to the 1740 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1741 * code from running. 1742 */ 1743#define BGE_MAGIC_NUMBER 0x4B657654 1744 1745typedef struct { 1746 u_int32_t bge_addr_hi; 1747 u_int32_t bge_addr_lo; 1748} bge_hostaddr; 1749#define BGE_HOSTADDR(x,y) \ 1750 do { \ 1751 (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 1752 (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 1753 } while(0) 1754 1755/* Ring control block structure */ 1756struct bge_rcb { 1757 bge_hostaddr bge_hostaddr; 1758 u_int32_t bge_maxlen_flags; 1759 u_int32_t bge_nicaddr; 1760}; 1761 1762#define RCB_WRITE_4(sc, rcb, offset, val) \ 1763 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1764 rcb + offsetof(struct bge_rcb, offset), val) 1765 1766#define RCB_WRITE_2(sc, rcb, offset, val) \ 1767 bus_space_write_2(sc->bge_btag, sc->bge_bhandle, \ 1768 rcb + offsetof(struct bge_rcb, offset), val) 1769 1770#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen << 16) | (flags)) 1771 1772#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1773#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1774 1775struct bge_tx_bd { 1776 bge_hostaddr bge_addr; 1777 u_int16_t bge_flags; 1778 u_int16_t bge_len; 1779 u_int16_t bge_vlan_tag; 1780 u_int16_t bge_rsvd; 1781}; 1782 1783#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1784#define BGE_TXBDFLAG_IP_CSUM 0x0002 1785#define BGE_TXBDFLAG_END 0x0004 1786#define BGE_TXBDFLAG_IP_FRAG 0x0008 1787#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1788#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1789#define BGE_TXBDFLAG_COAL_NOW 0x0080 1790#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1791#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1792#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1793#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1794#define BGE_TXBDFLAG_NO_CRC 0x8000 1795 1796#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1797 BGE_SEND_RING_1_TO_4 + \ 1798 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1799 1800struct bge_rx_bd { 1801 bge_hostaddr bge_addr; 1802 u_int16_t bge_len; 1803 u_int16_t bge_idx; 1804 u_int16_t bge_flags; 1805 u_int16_t bge_type; 1806 u_int16_t bge_tcp_udp_csum; 1807 u_int16_t bge_ip_csum; 1808 u_int16_t bge_vlan_tag; 1809 u_int16_t bge_error_flag; 1810 u_int32_t bge_rsvd; 1811 u_int32_t bge_opaque; 1812}; 1813 1814#define BGE_RXBDFLAG_END 0x0004 1815#define BGE_RXBDFLAG_JUMBO_RING 0x0020 1816#define BGE_RXBDFLAG_VLAN_TAG 0x0040 1817#define BGE_RXBDFLAG_ERROR 0x0400 1818#define BGE_RXBDFLAG_MINI_RING 0x0800 1819#define BGE_RXBDFLAG_IP_CSUM 0x1000 1820#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1821#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1822 1823#define BGE_RXERRFLAG_BAD_CRC 0x0001 1824#define BGE_RXERRFLAG_COLL_DETECT 0x0002 1825#define BGE_RXERRFLAG_LINK_LOST 0x0004 1826#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1827#define BGE_RXERRFLAG_MAC_ABORT 0x0010 1828#define BGE_RXERRFLAG_RUNT 0x0020 1829#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1830#define BGE_RXERRFLAG_GIANT 0x0080 1831 1832struct bge_sts_idx { 1833 u_int16_t bge_rx_prod_idx; 1834 u_int16_t bge_tx_cons_idx; 1835}; 1836 1837struct bge_status_block { 1838 u_int32_t bge_status; 1839 u_int32_t bge_rsvd0; 1840 u_int16_t bge_rx_jumbo_cons_idx; 1841 u_int16_t bge_rx_std_cons_idx; 1842 u_int16_t bge_rx_mini_cons_idx; 1843 u_int16_t bge_rsvd1; 1844 struct bge_sts_idx bge_idx[16]; 1845}; 1846 1847#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1848#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1849 1850#define BGE_STATFLAG_UPDATED 0x00000001 1851#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1852#define BGE_STATFLAG_ERROR 0x00000004 1853 1854/* 1855 * SysKonnect Subsystem IDs 1856 */ 1857#define SK_SUBSYSID_9D21 0x4421 1858#define SK_SUBSYSID_9D41 0x4441 1859 1860/* 1861 * Offset of MAC address inside EEPROM. 1862 */ 1863#define BGE_EE_MAC_OFFSET 0x7C 1864#define BGE_EE_HWCFG_OFFSET 0xC8 1865 1866#define BGE_HWCFG_VOLTAGE 0x00000003 1867#define BGE_HWCFG_PHYLED_MODE 0x0000000C 1868#define BGE_HWCFG_MEDIA 0x00000030 1869 1870#define BGE_VOLTAGE_1POINT3 0x00000000 1871#define BGE_VOLTAGE_1POINT8 0x00000001 1872 1873#define BGE_PHYLEDMODE_UNSPEC 0x00000000 1874#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 1875#define BGE_PHYLEDMODE_SINGLELED 0x00000008 1876 1877#define BGE_MEDIA_UNSPEC 0x00000000 1878#define BGE_MEDIA_COPPER 0x00000010 1879#define BGE_MEDIA_FIBER 0x00000020 1880 1881#define BGE_PCI_READ_CMD 0x06000000 1882#define BGE_PCI_WRITE_CMD 0x70000000 1883 1884#define BGE_TICKS_PER_SEC 1000000 1885 1886/* 1887 * Ring size constants. 1888 */ 1889#define BGE_EVENT_RING_CNT 256 1890#define BGE_CMD_RING_CNT 64 1891#define BGE_STD_RX_RING_CNT 512 1892#define BGE_JUMBO_RX_RING_CNT 256 1893#define BGE_MINI_RX_RING_CNT 1024 1894#define BGE_RETURN_RING_CNT 1024 1895 1896/* 5705 has smaller return ring size */ 1897#define BGE_RETURN_RING_CNT_5705 512 1898 1899/* 1900 * Possible TX ring sizes. 1901 */ 1902#define BGE_TX_RING_CNT_128 128 1903#define BGE_TX_RING_BASE_128 0x3800 1904 1905#define BGE_TX_RING_CNT_256 256 1906#define BGE_TX_RING_BASE_256 0x3000 1907 1908#define BGE_TX_RING_CNT_512 512 1909#define BGE_TX_RING_BASE_512 0x2000 1910 1911#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 1912#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 1913 1914/* 1915 * Tigon III statistics counters. 1916 */ 1917/* Statistics maintained MAC Receive block. */ 1918struct bge_rx_mac_stats { 1919 bge_hostaddr ifHCInOctets; 1920 bge_hostaddr Reserved1; 1921 bge_hostaddr etherStatsFragments; 1922 bge_hostaddr ifHCInUcastPkts; 1923 bge_hostaddr ifHCInMulticastPkts; 1924 bge_hostaddr ifHCInBroadcastPkts; 1925 bge_hostaddr dot3StatsFCSErrors; 1926 bge_hostaddr dot3StatsAlignmentErrors; 1927 bge_hostaddr xonPauseFramesReceived; 1928 bge_hostaddr xoffPauseFramesReceived; 1929 bge_hostaddr macControlFramesReceived; 1930 bge_hostaddr xoffStateEntered; 1931 bge_hostaddr dot3StatsFramesTooLong; 1932 bge_hostaddr etherStatsJabbers; 1933 bge_hostaddr etherStatsUndersizePkts; 1934 bge_hostaddr inRangeLengthError; 1935 bge_hostaddr outRangeLengthError; 1936 bge_hostaddr etherStatsPkts64Octets; 1937 bge_hostaddr etherStatsPkts65Octetsto127Octets; 1938 bge_hostaddr etherStatsPkts128Octetsto255Octets; 1939 bge_hostaddr etherStatsPkts256Octetsto511Octets; 1940 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 1941 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 1942 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 1943 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 1944 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 1945 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 1946}; 1947 1948/* Statistics maintained MAC Transmit block. */ 1949struct bge_tx_mac_stats { 1950 bge_hostaddr ifHCOutOctets; 1951 bge_hostaddr Reserved2; 1952 bge_hostaddr etherStatsCollisions; 1953 bge_hostaddr outXonSent; 1954 bge_hostaddr outXoffSent; 1955 bge_hostaddr flowControlDone; 1956 bge_hostaddr dot3StatsInternalMacTransmitErrors; 1957 bge_hostaddr dot3StatsSingleCollisionFrames; 1958 bge_hostaddr dot3StatsMultipleCollisionFrames; 1959 bge_hostaddr dot3StatsDeferredTransmissions; 1960 bge_hostaddr Reserved3; 1961 bge_hostaddr dot3StatsExcessiveCollisions; 1962 bge_hostaddr dot3StatsLateCollisions; 1963 bge_hostaddr dot3Collided2Times; 1964 bge_hostaddr dot3Collided3Times; 1965 bge_hostaddr dot3Collided4Times; 1966 bge_hostaddr dot3Collided5Times; 1967 bge_hostaddr dot3Collided6Times; 1968 bge_hostaddr dot3Collided7Times; 1969 bge_hostaddr dot3Collided8Times; 1970 bge_hostaddr dot3Collided9Times; 1971 bge_hostaddr dot3Collided10Times; 1972 bge_hostaddr dot3Collided11Times; 1973 bge_hostaddr dot3Collided12Times; 1974 bge_hostaddr dot3Collided13Times; 1975 bge_hostaddr dot3Collided14Times; 1976 bge_hostaddr dot3Collided15Times; 1977 bge_hostaddr ifHCOutUcastPkts; 1978 bge_hostaddr ifHCOutMulticastPkts; 1979 bge_hostaddr ifHCOutBroadcastPkts; 1980 bge_hostaddr dot3StatsCarrierSenseErrors; 1981 bge_hostaddr ifOutDiscards; 1982 bge_hostaddr ifOutErrors; 1983}; 1984 1985/* Stats counters access through registers */ 1986struct bge_mac_stats_regs { 1987 u_int32_t ifHCOutOctets; 1988 u_int32_t Reserved0; 1989 u_int32_t etherStatsCollisions; 1990 u_int32_t outXonSent; 1991 u_int32_t outXoffSent; 1992 u_int32_t Reserved1; 1993 u_int32_t dot3StatsInternalMacTransmitErrors; 1994 u_int32_t dot3StatsSingleCollisionFrames; 1995 u_int32_t dot3StatsMultipleCollisionFrames; 1996 u_int32_t dot3StatsDeferredTransmissions; 1997 u_int32_t Reserved2; 1998 u_int32_t dot3StatsExcessiveCollisions; 1999 u_int32_t dot3StatsLateCollisions; 2000 u_int32_t Reserved3[14]; 2001 u_int32_t ifHCOutUcastPkts; 2002 u_int32_t ifHCOutMulticastPkts; 2003 u_int32_t ifHCOutBroadcastPkts; 2004 u_int32_t Reserved4[2]; 2005 u_int32_t ifHCInOctets; 2006 u_int32_t Reserved5; 2007 u_int32_t etherStatsFragments; 2008 u_int32_t ifHCInUcastPkts; 2009 u_int32_t ifHCInMulticastPkts; 2010 u_int32_t ifHCInBroadcastPkts; 2011 u_int32_t dot3StatsFCSErrors; 2012 u_int32_t dot3StatsAlignmentErrors; 2013 u_int32_t xonPauseFramesReceived; 2014 u_int32_t xoffPauseFramesReceived; 2015 u_int32_t macControlFramesReceived; 2016 u_int32_t xoffStateEntered; 2017 u_int32_t dot3StatsFramesTooLong; 2018 u_int32_t etherStatsJabbers; 2019 u_int32_t etherStatsUndersizePkts; 2020}; 2021 2022struct bge_stats { 2023 u_int8_t Reserved0[256]; 2024 2025 /* Statistics maintained by Receive MAC. */ 2026 struct bge_rx_mac_stats rxstats; 2027 2028 bge_hostaddr Unused1[37]; 2029 2030 /* Statistics maintained by Transmit MAC. */ 2031 struct bge_tx_mac_stats txstats; 2032 2033 bge_hostaddr Unused2[31]; 2034 2035 /* Statistics maintained by Receive List Placement. */ 2036 bge_hostaddr COSIfHCInPkts[16]; 2037 bge_hostaddr COSFramesDroppedDueToFilters; 2038 bge_hostaddr nicDmaWriteQueueFull; 2039 bge_hostaddr nicDmaWriteHighPriQueueFull; 2040 bge_hostaddr nicNoMoreRxBDs; 2041 bge_hostaddr ifInDiscards; 2042 bge_hostaddr ifInErrors; 2043 bge_hostaddr nicRecvThresholdHit; 2044 2045 bge_hostaddr Unused3[9]; 2046 2047 /* Statistics maintained by Send Data Initiator. */ 2048 bge_hostaddr COSIfHCOutPkts[16]; 2049 bge_hostaddr nicDmaReadQueueFull; 2050 bge_hostaddr nicDmaReadHighPriQueueFull; 2051 bge_hostaddr nicSendDataCompQueueFull; 2052 2053 /* Statistics maintained by Host Coalescing. */ 2054 bge_hostaddr nicRingSetSendProdIndex; 2055 bge_hostaddr nicRingStatusUpdate; 2056 bge_hostaddr nicInterrupts; 2057 bge_hostaddr nicAvoidedInterrupts; 2058 bge_hostaddr nicSendThresholdHit; 2059 2060 u_int8_t Reserved4[320]; 2061}; 2062 2063/* 2064 * Tigon general information block. This resides in host memory 2065 * and contains the status counters, ring control blocks and 2066 * producer pointers. 2067 */ 2068 2069struct bge_gib { 2070 struct bge_stats bge_stats; 2071 struct bge_rcb bge_tx_rcb[16]; 2072 struct bge_rcb bge_std_rx_rcb; 2073 struct bge_rcb bge_jumbo_rx_rcb; 2074 struct bge_rcb bge_mini_rx_rcb; 2075 struct bge_rcb bge_return_rcb; 2076}; 2077 2078/* 2079 * NOTE! On the Alpha, we have an alignment constraint. 2080 * The first thing in the packet is a 14-byte Ethernet header. 2081 * This means that the packet is misaligned. To compensate, 2082 * we actually offset the data 2 bytes into the cluster. This 2083 * alignes the packet after the Ethernet header at a 32-bit 2084 * boundary. 2085 */ 2086 2087#define BGE_PAGE_SIZE PAGE_SIZE 2088#define BGE_MIN_FRAMELEN 60 2089 2090/* 2091 * Other utility macros. 2092 */ 2093#define BGE_INC(x, y) (x) = (x + 1) % y 2094 2095/* 2096 * Vital product data and structures. 2097 */ 2098#define BGE_VPD_FLAG 0x8000 2099 2100/* VPD structures */ 2101struct vpd_res { 2102 u_int8_t vr_id; 2103 u_int8_t vr_len; 2104 u_int8_t vr_pad; 2105}; 2106 2107struct vpd_key { 2108 char vk_key[2]; 2109 u_int8_t vk_len; 2110}; 2111 2112#define VPD_RES_ID 0x82 /* ID string */ 2113#define VPD_RES_READ 0x90 /* start of read only area */ 2114#define VPD_RES_WRITE 0x81 /* start of read/write area */ 2115#define VPD_RES_END 0x78 /* end tag */ 2116 2117 2118/* 2119 * Register access macros. The Tigon always uses memory mapped register 2120 * accesses and all registers must be accessed with 32 bit operations. 2121 */ 2122 2123#define CSR_WRITE_4(sc, reg, val) \ 2124 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2125 2126#define CSR_READ_4(sc, reg) \ 2127 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2128 2129#define BGE_SETBIT(sc, reg, x) \ 2130 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2131#define BGE_CLRBIT(sc, reg, x) \ 2132 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2133 2134#define PCI_SETBIT(pc, tag, reg, x) \ 2135 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 2136#define PCI_CLRBIT(pc, tag, reg, x) \ 2137 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 2138 2139/* 2140 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2141 * values are tuneable. They control the actual amount of buffers 2142 * allocated for the standard, mini and jumbo receive rings. 2143 */ 2144 2145#define BGE_SSLOTS 256 2146#define BGE_MSLOTS 256 2147#define BGE_JSLOTS 384 2148 2149#define BGE_JRAWLEN (ETHER_MAX_LEN_JUMBO + ETHER_ALIGN) 2150#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2151 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2152#define BGE_JPAGESZ PAGE_SIZE 2153#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2154#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2155 2156/* 2157 * Ring structures. Most of these reside in host memory and we tell 2158 * the NIC where they are via the ring control blocks. The exceptions 2159 * are the tx and command rings, which live in NIC memory and which 2160 * we access via the shared memory window. 2161 */ 2162struct bge_ring_data { 2163 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2164 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2165 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2166 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2167 struct bge_status_block bge_status_block; 2168 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2169 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2170 struct bge_gib bge_info; 2171}; 2172 2173#define BGE_RING_DMA_ADDR(sc, offset) \ 2174 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2175 offsetof(struct bge_ring_data, offset)) 2176 2177/* 2178 * Number of DMA segments in a TxCB. Note that this is carefully 2179 * chosen to make the total struct size an even power of two. It's 2180 * critical that no TxCB be split across a page boundry since 2181 * no attempt is made to allocate physically contiguous memory. 2182 * 2183 */ 2184#ifdef __LP64__ 2185#define BGE_NTXSEG 30 2186#else 2187#define BGE_NTXSEG 31 2188#endif 2189 2190/* 2191 * Mbuf pointers. We need these to keep track of the virtual addresses 2192 * of our mbuf chains since we can only convert from physical to virtual, 2193 * not the other way around. 2194 */ 2195struct bge_chain_data { 2196 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2197 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2198 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2199 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2200 bus_dmamap_t bge_tx_map[BGE_TX_RING_CNT]; 2201 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2202 bus_dmamap_t bge_rx_jumbo_map; 2203 /* Stick the jumbo mem management stuff here too. */ 2204 caddr_t bge_jslots[BGE_JSLOTS]; 2205 void *bge_jumbo_buf; 2206}; 2207 2208#define BGE_JUMBO_DMA_ADDR(sc, m) \ 2209 ((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \ 2210 (mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf)) 2211 2212struct bge_type { 2213 u_int16_t bge_vid; 2214 u_int16_t bge_did; 2215 char *bge_name; 2216}; 2217 2218#define BGE_HWREV_TIGON 0x01 2219#define BGE_HWREV_TIGON_II 0x02 2220#define BGE_TIMEOUT 100000 2221#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2222 2223struct bge_jpool_entry { 2224 int slot; 2225 LIST_ENTRY(bge_jpool_entry) jpool_entries; 2226}; 2227 2228struct bge_bcom_hack { 2229 int reg; 2230 int val; 2231}; 2232 2233struct bge_softc { 2234 struct device bge_dev; 2235 struct arpcom arpcom; /* interface info */ 2236 bus_space_handle_t bge_bhandle; 2237 bus_space_tag_t bge_btag; 2238 void *bge_intrhand; 2239 struct pci_attach_args bge_pa; 2240 struct mii_data bge_mii; 2241 struct ifmedia bge_ifmedia; /* media info */ 2242 u_int8_t bge_extram; /* has external SSRAM */ 2243 u_int8_t bge_tbi; 2244 u_int8_t bge_rx_alignment_bug; 2245 bus_dma_tag_t bge_dmatag; 2246 u_int32_t bge_chipid; 2247 u_int32_t bge_quirks; 2248 u_int8_t bge_no_3_led; 2249 u_int8_t bge_pcie; 2250 struct bge_ring_data *bge_rdata; /* rings */ 2251 struct bge_chain_data bge_cdata; /* mbufs */ 2252 bus_dmamap_t bge_ring_map; 2253 u_int16_t bge_tx_saved_considx; 2254 u_int16_t bge_rx_saved_considx; 2255 u_int16_t bge_ev_saved_considx; 2256 u_int16_t bge_return_ring_cnt; 2257 u_int16_t bge_std; /* current std ring head */ 2258 u_int16_t bge_jumbo; /* current jumo ring head */ 2259 LIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2260 LIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2261 u_int32_t bge_stat_ticks; 2262 u_int32_t bge_rx_coal_ticks; 2263 u_int32_t bge_tx_coal_ticks; 2264 u_int32_t bge_rx_max_coal_bds; 2265 u_int32_t bge_tx_max_coal_bds; 2266 u_int32_t bge_tx_buf_ratio; 2267 int bge_if_flags; 2268 int bge_txcnt; 2269 int bge_link; 2270 struct timeout bge_timeout; 2271 char *bge_vpd_prodname; 2272 char *bge_vpd_readonly; 2273}; 2274