if_bgereg.h revision 1.132
1/* $OpenBSD: if_bgereg.h,v 1.132 2021/04/19 17:03:49 kettenis Exp $ */ 2 3/* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bgereg.h,v 1.11 2002/11/14 23:54:50 sam Exp $ 36 */ 37 38/* 39 * BCM570x memory map. The internal memory layout varies somewhat 40 * depending on whether or not we have external SSRAM attached. 41 * The BCM5700 can have up to 16MB of external memory. The BCM5701 42 * is apparently not designed to use external SSRAM. The mappings 43 * up to the first 4 send rings are the same for both internal and 44 * external memory configurations. Note that mini RX ring space is 45 * only available with external SSRAM configurations, which means 46 * the mini RX ring is not supported on the BCM5701. 47 * 48 * The NIC's memory can be accessed by the host in one of 3 ways: 49 * 50 * 1) Indirect register access. The REG_BASEADDR and REG_DATA 51 * registers in PCI config space can be used to read any 32-bit 52 * address within the NIC's memory. 53 * 54 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 55 * space can be used in conjunction with the memory window in the 56 * device register space at offset 0x8000 to read any 32K chunk 57 * of NIC memory. 58 * 59 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 60 * set, the device I/O mapping consumes 32MB of host address space, 61 * allowing all of the registers and internal NIC memory to be 62 * accessed directly. NIC memory addresses are offset by 0x01000000. 63 * Flat mode consumes so much host address space that it is not 64 * recommended. 65 */ 66#define BGE_PAGE_ZERO 0x00000000 67#define BGE_PAGE_ZERO_END 0x000000FF 68#define BGE_SEND_RING_RCB 0x00000100 69#define BGE_SEND_RING_RCB_END 0x000001FF 70#define BGE_RX_RETURN_RING_RCB 0x00000200 71#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 72#define BGE_STATS_BLOCK 0x00000300 73#define BGE_STATS_BLOCK_END 0x00000AFF 74#define BGE_STATUS_BLOCK 0x00000B00 75#define BGE_STATUS_BLOCK_END 0x00000B4F 76#define BGE_SOFTWARE_GENCOMM 0x00000B50 77#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 78#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 79#define BGE_SOFTWARE_GENCOMM_VER 0x00000B5C 80#define BGE_VER_SHIFT 16 81#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 82#define BGE_FW_PAUSE 0x00000002 83#define BGE_SOFTWARE_GENCOMM_NICCFG2 0x00000D38 84#define BGE_SOFTWARE_GENCOMM_NICCFG3 0x00000D3C 85#define BGE_SOFTWARE_GENCOMM_NICCFG4 0x00000D60 86#define BGE_NICCFG4_GMII_MODE 0x00000002 87#define BGE_NICCFG4_RGMII_STD_IBND_DISABLE 0x00000004 88#define BGE_NICCFG4_RGMII_EXT_IBND_RX_EN 0x00000008 89#define BGE_NICCFG4_RGMII_EXT_IBND_TX_EN 0x00000010 90#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 91#define BGE_UNMAPPED 0x00001000 92#define BGE_UNMAPPED_END 0x00001FFF 93#define BGE_DMA_DESCRIPTORS 0x00002000 94#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 95#define BGE_SEND_RING_5717 0x00004000 96#define BGE_SEND_RING_1_TO_4 0x00004000 97#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 98 99/* Mappings for internal memory configuration */ 100#define BGE_STD_RX_RINGS 0x00006000 101#define BGE_STD_RX_RINGS_END 0x00006FFF 102#define BGE_JUMBO_RX_RINGS 0x00007000 103#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 104#define BGE_BUFFPOOL_1 0x00008000 105#define BGE_BUFFPOOL_1_END 0x0000FFFF 106#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 107#define BGE_BUFFPOOL_2_END 0x00017FFF 108#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 109#define BGE_BUFFPOOL_3_END 0x0001FFFF 110#define BGE_STD_RX_RINGS_5717 0x00040000 111#define BGE_JUMBO_RX_RINGS_5717 0x00044400 112 113/* Mappings for external SSRAM configurations */ 114#define BGE_SEND_RING_5_TO_6 0x00006000 115#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 116#define BGE_SEND_RING_7_TO_8 0x00007000 117#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 118#define BGE_SEND_RING_9_TO_16 0x00008000 119#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 120#define BGE_EXT_STD_RX_RINGS 0x0000C000 121#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 122#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 123#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 124#define BGE_MINI_RX_RINGS 0x0000E000 125#define BGE_MINI_RX_RINGS_END 0x0000FFFF 126#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 127#define BGE_AVAIL_REGION1_END 0x00017FFF 128#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 129#define BGE_AVAIL_REGION2_END 0x0001FFFF 130#define BGE_EXT_SSRAM 0x00020000 131#define BGE_EXT_SSRAM_END 0x000FFFFF 132 133 134/* 135 * BCM570x register offsets. These are memory mapped registers 136 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 137 * Each register must be accessed using 32 bit operations. 138 * 139 * All registers are accessed through a 32K shared memory block. 140 * The first group of registers are actually copies of the PCI 141 * configuration space registers. 142 */ 143 144/* 145 * PCI registers defined in the PCI 2.2 spec. 146 */ 147#define BGE_PCI_VID 0x00 148#define BGE_PCI_DID 0x02 149#define BGE_PCI_CMD 0x04 150#define BGE_PCI_STS 0x06 151#define BGE_PCI_REV 0x08 152#define BGE_PCI_CLASS 0x09 153#define BGE_PCI_CACHESZ 0x0C 154#define BGE_PCI_LATTIMER 0x0D 155#define BGE_PCI_HDRTYPE 0x0E 156#define BGE_PCI_BIST 0x0F 157#define BGE_PCI_BAR0 0x10 158#define BGE_PCI_BAR1 0x14 159#define BGE_PCI_BAR2 0x18 160#define BGE_PCI_SUBSYS 0x2C 161#define BGE_PCI_SUBVID 0x2E 162#define BGE_PCI_ROMBASE 0x30 163#define BGE_PCI_CAPPTR 0x34 164#define BGE_PCI_INTLINE 0x3C 165#define BGE_PCI_INTPIN 0x3D 166#define BGE_PCI_MINGNT 0x3E 167#define BGE_PCI_MAXLAT 0x3F 168#define BGE_PCI_PCIXCAP 0x40 169#define BGE_PCI_NEXTPTR_PM 0x41 170#define BGE_PCI_PCIX_CMD 0x42 171#define BGE_PCI_PCIX_STS 0x44 172#define BGE_PCI_PWRMGMT_CAPID 0x48 173#define BGE_PCI_NEXTPTR_VPD 0x49 174#define BGE_PCI_PWRMGMT_CAPS 0x4A 175#define BGE_PCI_PWRMGMT_CMD 0x4C 176#define BGE_PCI_PWRMGMT_STS 0x4D 177#define BGE_PCI_PWRMGMT_DATA 0x4F 178#define BGE_PCI_VPD_CAPID 0x50 179#define BGE_PCI_NEXTPTR_MSI 0x51 180#define BGE_PCI_VPD_ADDR 0x52 181#define BGE_PCI_VPD_DATA 0x54 182#define BGE_PCI_MSI_CAPID 0x58 183#define BGE_PCI_NEXTPTR_NONE 0x59 184#define BGE_PCI_MSI_CTL 0x5A 185#define BGE_PCI_MSI_ADDR_HI 0x5C 186#define BGE_PCI_MSI_ADDR_LO 0x60 187#define BGE_PCI_MSI_DATA 0x64 188 189/* PCI MSI. ??? */ 190#define BGE_PCIE_CAPID_REG 0xD0 191#define BGE_PCIE_CAPID 0x10 192 193/* 194 * PCI registers specific to the BCM570x family. 195 */ 196#define BGE_PCI_MISC_CTL 0x68 197#define BGE_PCI_DMA_RW_CTL 0x6C 198#define BGE_PCI_PCISTATE 0x70 199#define BGE_PCI_CLKCTL 0x74 200#define BGE_PCI_REG_BASEADDR 0x78 201#define BGE_PCI_MEMWIN_BASEADDR 0x7C 202#define BGE_PCI_REG_DATA 0x80 203#define BGE_PCI_MEMWIN_DATA 0x84 204#define BGE_PCI_MODECTL 0x88 205#define BGE_PCI_MISC_CFG 0x8C 206#define BGE_PCI_MISC_LOCALCTL 0x90 207#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 208#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 209#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 210#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 211#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 212#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 213#define BGE_PCI_ISR_MBX_HI 0xB0 214#define BGE_PCI_ISR_MBX_LO 0xB4 215#define BGE_PCI_PRODID_ASICREV 0xBC 216#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 217#define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 218 219/* PCI Misc. Host control register */ 220#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 221#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 222#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 223#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 224#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 225#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 226#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 227#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 228#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 229#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 230#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 231 232#if BYTE_ORDER == LITTLE_ENDIAN 233#define BGE_DMA_SWAP_OPTIONS \ 234 BGE_MODECTL_WORDSWAP_NONFRAME| \ 235 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 236#else 237#define BGE_DMA_SWAP_OPTIONS \ 238 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 239 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 240#endif 241 242#define BGE_INIT \ 243 (BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 244 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 245 246#define BGE_CHIPID_BCM5700_A0 0x7000 247#define BGE_CHIPID_BCM5700_A1 0x7001 248#define BGE_CHIPID_BCM5700_B0 0x7100 249#define BGE_CHIPID_BCM5700_B1 0x7101 250#define BGE_CHIPID_BCM5700_B2 0x7102 251#define BGE_CHIPID_BCM5700_B3 0x7103 252#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 253#define BGE_CHIPID_BCM5700_C0 0x7200 254#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 255#define BGE_CHIPID_BCM5701_B0 0x0100 256#define BGE_CHIPID_BCM5701_B2 0x0102 257#define BGE_CHIPID_BCM5701_B5 0x0105 258#define BGE_CHIPID_BCM5703_A0 0x1000 259#define BGE_CHIPID_BCM5703_A1 0x1001 260#define BGE_CHIPID_BCM5703_A2 0x1002 261#define BGE_CHIPID_BCM5703_A3 0x1003 262#define BGE_CHIPID_BCM5703_B0 0x1100 263#define BGE_CHIPID_BCM5704_A0 0x2000 264#define BGE_CHIPID_BCM5704_A1 0x2001 265#define BGE_CHIPID_BCM5704_A2 0x2002 266#define BGE_CHIPID_BCM5704_A3 0x2003 267#define BGE_CHIPID_BCM5704_B0 0x2100 268#define BGE_CHIPID_BCM5705_A0 0x3000 269#define BGE_CHIPID_BCM5705_A1 0x3001 270#define BGE_CHIPID_BCM5705_A2 0x3002 271#define BGE_CHIPID_BCM5705_A3 0x3003 272#define BGE_CHIPID_BCM5750_A0 0x4000 273#define BGE_CHIPID_BCM5750_A1 0x4001 274#define BGE_CHIPID_BCM5750_A3 0x4003 275#define BGE_CHIPID_BCM5750_B0 0x4010 276#define BGE_CHIPID_BCM5750_B1 0x4101 277#define BGE_CHIPID_BCM5750_C0 0x4200 278#define BGE_CHIPID_BCM5750_C1 0x4201 279#define BGE_CHIPID_BCM5750_C2 0x4202 280#define BGE_CHIPID_BCM5714_A0 0x5000 281#define BGE_CHIPID_BCM5752_A0 0x6000 282#define BGE_CHIPID_BCM5752_A1 0x6001 283#define BGE_CHIPID_BCM5752_A2 0x6002 284#define BGE_CHIPID_BCM5714_B0 0x8000 285#define BGE_CHIPID_BCM5714_B3 0x8003 286#define BGE_CHIPID_BCM5715_A0 0x9000 287#define BGE_CHIPID_BCM5715_A1 0x9001 288#define BGE_CHIPID_BCM5715_A3 0x9003 289#define BGE_CHIPID_BCM5755_A0 0xa000 290#define BGE_CHIPID_BCM5755_A1 0xa001 291#define BGE_CHIPID_BCM5755_A2 0xa002 292#define BGE_CHIPID_BCM5755_C0 0xa200 293#define BGE_CHIPID_BCM5787_A0 0xb000 294#define BGE_CHIPID_BCM5787_A1 0xb001 295#define BGE_CHIPID_BCM5787_A2 0xb002 296#define BGE_CHIPID_BCM5761_A0 0x5761000 297#define BGE_CHIPID_BCM5761_A1 0x5761100 298#define BGE_CHIPID_BCM5784_A0 0x5784000 299#define BGE_CHIPID_BCM5784_A1 0x5784100 300#define BGE_CHIPID_BCM5906_A0 0xc000 301#define BGE_CHIPID_BCM5906_A1 0xc001 302#define BGE_CHIPID_BCM5906_A2 0xc002 303#define BGE_CHIPID_BCM57780_A0 0x57780000 304#define BGE_CHIPID_BCM57780_A1 0x57780001 305#define BGE_CHIPID_BCM5717_A0 0x05717000 306#define BGE_CHIPID_BCM5717_B0 0x05717100 307#define BGE_CHIPID_BCM5719_A0 0x05719000 308#define BGE_CHIPID_BCM5719_A1 0x05719001 309#define BGE_CHIPID_BCM5720_A0 0x05720000 310#define BGE_CHIPID_BCM5762_A0 0x05762000 311#define BGE_CHIPID_BCM57765_A0 0x57785000 312#define BGE_CHIPID_BCM57765_B0 0x57785100 313#define BGE_CHIPID_BCM57766_A0 0x57766000 314#define BGE_CHIPID_BCM57766_A1 0x57766001 315 316/* shorthand one */ 317#define BGE_ASICREV(x) ((x) >> 12) 318#define BGE_ASICREV_BCM5700 0x07 319#define BGE_ASICREV_BCM5701 0x00 320#define BGE_ASICREV_BCM5703 0x01 321#define BGE_ASICREV_BCM5704 0x02 322#define BGE_ASICREV_BCM5705 0x03 323#define BGE_ASICREV_BCM5750 0x04 324#define BGE_ASICREV_BCM5714_A0 0x05 /* 5714, 5715 */ 325#define BGE_ASICREV_BCM5752 0x06 326#define BGE_ASICREV_BCM5780 0x08 327#define BGE_ASICREV_BCM5714 0x09 /* 5714, 5715 */ 328#define BGE_ASICREV_BCM5755 0x0a 329#define BGE_ASICREV_BCM5787 0x0b 330#define BGE_ASICREV_BCM5906 0x0c 331#define BGE_ASICREV_USE_PRODID_REG 0x0f 332#define BGE_ASICREV_BCM5717 0x5717 333#define BGE_ASICREV_BCM5719 0x5719 334#define BGE_ASICREV_BCM5720 0x5720 335#define BGE_ASICREV_BCM5761 0x5761 336#define BGE_ASICREV_BCM5762 0x5762 337#define BGE_ASICREV_BCM5784 0x5784 338#define BGE_ASICREV_BCM5785 0x5785 339#define BGE_ASICREV_BCM57765 0x57785 340#define BGE_ASICREV_BCM57766 0x57766 341#define BGE_ASICREV_BCM57780 0x57780 342 343/* chip revisions */ 344#define BGE_CHIPREV(x) ((x) >> 8) 345#define BGE_CHIPREV_5700_AX 0x70 346#define BGE_CHIPREV_5700_BX 0x71 347#define BGE_CHIPREV_5700_CX 0x72 348#define BGE_CHIPREV_5701_AX 0x00 349#define BGE_CHIPREV_5703_AX 0x10 350#define BGE_CHIPREV_5704_AX 0x20 351#define BGE_CHIPREV_5704_BX 0x21 352#define BGE_CHIPREV_5750_AX 0x40 353#define BGE_CHIPREV_5750_BX 0x41 354#define BGE_CHIPREV_5717_AX 0x57170 355#define BGE_CHIPREV_5717_BX 0x57171 356#define BGE_CHIPREV_5761_AX 0x57611 357#define BGE_CHIPREV_57765_AX 0x577850 358#define BGE_CHIPREV_5784_AX 0x57841 359 360/* PCI DMA Read/Write Control register */ 361#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 362#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 363#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 364#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 365#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 366#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 367#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 368#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 369#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 370#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 371#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 372#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 373#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 374 375#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 376#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 377#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 378#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 379 380#define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 381#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 382 383#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 384#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 385#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 386#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 387#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 388#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 389#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 390#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 391 392#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 393#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 394#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 395#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 396#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 397#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 398#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 399#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 400 401/* 402 * PCI state register -- note, this register is read only 403 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 404 * register is set. 405 */ 406#define BGE_PCISTATE_FORCE_RESET 0x00000001 407#define BGE_PCISTATE_INTR_NOT_ACTIVE 0x00000002 408#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 409#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 410#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 411#define BGE_PCISTATE_ROM_ENABLE 0x00000020 412#define BGE_PCISTATE_ROM_RETRY_ENABLE 0x00000040 413#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 414#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 415#define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000 416#define BGE_PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 417#define BGE_PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 418#define BGE_PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 419 420/* 421 * The following bits in PCI state register are reserved. 422 * If we check that the register values reverts on reset, 423 * do not check these bits. On some 5704C (rev A3) and some 424 * Altima chips, these bits do not revert until much later 425 * in the bge driver's bge_reset() chip-reset state machine. 426 */ 427#define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 428 429/* 430 * PCI Clock Control register -- note, this register is read only 431 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 432 * register is set. 433 */ 434#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 435#define BGE_PCICLOCKCTL_M66EN 0x00000080 436#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 437#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 438#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 439#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 440#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 441#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 442#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 443#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 444 445/* 446 * High priority mailbox registers 447 * Each mailbox is 64-bits wide, though we only use the 448 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 449 * first. The NIC will load the mailbox after the lower 32 bit word 450 * has been updated. 451 */ 452#define BGE_MBX_IRQ0_HI 0x0200 453#define BGE_MBX_IRQ0_LO 0x0204 454#define BGE_MBX_IRQ1_HI 0x0208 455#define BGE_MBX_IRQ1_LO 0x020C 456#define BGE_MBX_IRQ2_HI 0x0210 457#define BGE_MBX_IRQ2_LO 0x0214 458#define BGE_MBX_IRQ3_HI 0x0218 459#define BGE_MBX_IRQ3_LO 0x021C 460#define BGE_MBX_GEN0_HI 0x0220 461#define BGE_MBX_GEN0_LO 0x0224 462#define BGE_MBX_GEN1_HI 0x0228 463#define BGE_MBX_GEN1_LO 0x022C 464#define BGE_MBX_GEN2_HI 0x0230 465#define BGE_MBX_GEN2_LO 0x0234 466#define BGE_MBX_GEN3_HI 0x0228 467#define BGE_MBX_GEN3_LO 0x022C 468#define BGE_MBX_GEN4_HI 0x0240 469#define BGE_MBX_GEN4_LO 0x0244 470#define BGE_MBX_GEN5_HI 0x0248 471#define BGE_MBX_GEN5_LO 0x024C 472#define BGE_MBX_GEN6_HI 0x0250 473#define BGE_MBX_GEN6_LO 0x0254 474#define BGE_MBX_GEN7_HI 0x0258 475#define BGE_MBX_GEN7_LO 0x025C 476#define BGE_MBX_RELOAD_STATS_HI 0x0260 477#define BGE_MBX_RELOAD_STATS_LO 0x0264 478#define BGE_MBX_RX_STD_PROD_HI 0x0268 479#define BGE_MBX_RX_STD_PROD_LO 0x026C 480#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 481#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 482#define BGE_MBX_RX_MINI_PROD_HI 0x0278 483#define BGE_MBX_RX_MINI_PROD_LO 0x027C 484#define BGE_MBX_RX_CONS0_HI 0x0280 485#define BGE_MBX_RX_CONS0_LO 0x0284 486#define BGE_MBX_RX_CONS1_HI 0x0288 487#define BGE_MBX_RX_CONS1_LO 0x028C 488#define BGE_MBX_RX_CONS2_HI 0x0290 489#define BGE_MBX_RX_CONS2_LO 0x0294 490#define BGE_MBX_RX_CONS3_HI 0x0298 491#define BGE_MBX_RX_CONS3_LO 0x029C 492#define BGE_MBX_RX_CONS4_HI 0x02A0 493#define BGE_MBX_RX_CONS4_LO 0x02A4 494#define BGE_MBX_RX_CONS5_HI 0x02A8 495#define BGE_MBX_RX_CONS5_LO 0x02AC 496#define BGE_MBX_RX_CONS6_HI 0x02B0 497#define BGE_MBX_RX_CONS6_LO 0x02B4 498#define BGE_MBX_RX_CONS7_HI 0x02B8 499#define BGE_MBX_RX_CONS7_LO 0x02BC 500#define BGE_MBX_RX_CONS8_HI 0x02C0 501#define BGE_MBX_RX_CONS8_LO 0x02C4 502#define BGE_MBX_RX_CONS9_HI 0x02C8 503#define BGE_MBX_RX_CONS9_LO 0x02CC 504#define BGE_MBX_RX_CONS10_HI 0x02D0 505#define BGE_MBX_RX_CONS10_LO 0x02D4 506#define BGE_MBX_RX_CONS11_HI 0x02D8 507#define BGE_MBX_RX_CONS11_LO 0x02DC 508#define BGE_MBX_RX_CONS12_HI 0x02E0 509#define BGE_MBX_RX_CONS12_LO 0x02E4 510#define BGE_MBX_RX_CONS13_HI 0x02E8 511#define BGE_MBX_RX_CONS13_LO 0x02EC 512#define BGE_MBX_RX_CONS14_HI 0x02F0 513#define BGE_MBX_RX_CONS14_LO 0x02F4 514#define BGE_MBX_RX_CONS15_HI 0x02F8 515#define BGE_MBX_RX_CONS15_LO 0x02FC 516#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 517#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 518#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 519#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 520#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 521#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 522#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 523#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 524#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 525#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 526#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 527#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 528#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 529#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 530#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 531#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 532#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 533#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 534#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 535#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 536#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 537#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 538#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 539#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 540#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 541#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 542#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 543#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 544#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 545#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 546#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 547#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 548#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 549#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 550#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 551#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 552#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 553#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 554#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 555#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 556#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 557#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 558#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 559#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 560#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 561#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 562#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 563#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 564#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 565#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 566#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 567#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 568#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 569#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 570#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 571#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 572#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 573#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 574#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 575#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 576#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 577#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 578#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 579#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 580 581#define BGE_TX_RINGS_MAX 4 582#define BGE_TX_RINGS_EXTSSRAM_MAX 16 583#define BGE_RX_RINGS_MAX 16 584 585/* Ethernet MAC control registers */ 586#define BGE_MAC_MODE 0x0400 587#define BGE_MAC_STS 0x0404 588#define BGE_MAC_EVT_ENB 0x0408 589#define BGE_MAC_LED_CTL 0x040C 590#define BGE_MAC_ADDR1_LO 0x0410 591#define BGE_MAC_ADDR1_HI 0x0414 592#define BGE_MAC_ADDR2_LO 0x0418 593#define BGE_MAC_ADDR2_HI 0x041C 594#define BGE_MAC_ADDR3_LO 0x0420 595#define BGE_MAC_ADDR3_HI 0x0424 596#define BGE_MAC_ADDR4_LO 0x0428 597#define BGE_MAC_ADDR4_HI 0x042C 598#define BGE_WOL_PATPTR 0x0430 599#define BGE_WOL_PATCFG 0x0434 600#define BGE_TX_RANDOM_BACKOFF 0x0438 601#define BGE_RX_MTU 0x043C 602#define BGE_GBIT_PCS_TEST 0x0440 603#define BGE_TX_TBI_AUTONEG 0x0444 604#define BGE_RX_TBI_AUTONEG 0x0448 605#define BGE_MI_COMM 0x044C 606#define BGE_MI_STS 0x0450 607#define BGE_MI_MODE 0x0454 608#define BGE_AUTOPOLL_STS 0x0458 609#define BGE_TX_MODE 0x045C 610#define BGE_TX_STS 0x0460 611#define BGE_TX_LENGTHS 0x0464 612#define BGE_RX_MODE 0x0468 613#define BGE_RX_STS 0x046C 614#define BGE_MAR0 0x0470 615#define BGE_MAR1 0x0474 616#define BGE_MAR2 0x0478 617#define BGE_MAR3 0x047C 618#define BGE_RX_BD_RULES_CTL0 0x0480 619#define BGE_RX_BD_RULES_MASKVAL0 0x0484 620#define BGE_RX_BD_RULES_CTL1 0x0488 621#define BGE_RX_BD_RULES_MASKVAL1 0x048C 622#define BGE_RX_BD_RULES_CTL2 0x0490 623#define BGE_RX_BD_RULES_MASKVAL2 0x0494 624#define BGE_RX_BD_RULES_CTL3 0x0498 625#define BGE_RX_BD_RULES_MASKVAL3 0x049C 626#define BGE_RX_BD_RULES_CTL4 0x04A0 627#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 628#define BGE_RX_BD_RULES_CTL5 0x04A8 629#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 630#define BGE_RX_BD_RULES_CTL6 0x04B0 631#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 632#define BGE_RX_BD_RULES_CTL7 0x04B8 633#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 634#define BGE_RX_BD_RULES_CTL8 0x04C0 635#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 636#define BGE_RX_BD_RULES_CTL9 0x04C8 637#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 638#define BGE_RX_BD_RULES_CTL10 0x04D0 639#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 640#define BGE_RX_BD_RULES_CTL11 0x04D8 641#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 642#define BGE_RX_BD_RULES_CTL12 0x04E0 643#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 644#define BGE_RX_BD_RULES_CTL13 0x04E8 645#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 646#define BGE_RX_BD_RULES_CTL14 0x04F0 647#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 648#define BGE_RX_BD_RULES_CTL15 0x04F8 649#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 650#define BGE_RX_RULES_CFG 0x0500 651#define BGE_MAX_RX_FRAME_LOWAT 0x0504 652#define BGE_SERDES_CFG 0x0590 653#define BGE_SERDES_STS 0x0594 654#define BGE_PHYCFG1 0x05A0 655#define BGE_PHYCFG2 0x05A4 656#define BGE_EXT_RGMII_MODE 0x05A8 657#define BGE_SGDIG_CFG 0x05B0 658#define BGE_SGDIG_STS 0x05B4 659#define BGE_MAC_STATS 0x0800 660 661/* Ethernet MAC Mode register */ 662#define BGE_MACMODE_RESET 0x00000001 663#define BGE_MACMODE_HALF_DUPLEX 0x00000002 664#define BGE_MACMODE_PORTMODE 0x0000000C 665#define BGE_MACMODE_LOOPBACK 0x00000010 666#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 667#define BGE_MACMODE_TX_BURST_ENB 0x00000100 668#define BGE_MACMODE_MAX_DEFER 0x00000200 669#define BGE_MACMODE_LINK_POLARITY 0x00000400 670#define BGE_MACMODE_RX_STATS_ENB 0x00000800 671#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 672#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 673#define BGE_MACMODE_TX_STATS_ENB 0x00004000 674#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 675#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 676#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 677#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 678#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 679#define BGE_MACMODE_MIP_ENB 0x00100000 680#define BGE_MACMODE_TXDMA_ENB 0x00200000 681#define BGE_MACMODE_RXDMA_ENB 0x00400000 682#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 683#define BGE_MACMODE_APE_RX_EN 0x08000000 684#define BGE_MACMODE_APE_TX_EN 0x10000000 685 686#define BGE_PORTMODE_NONE 0x00000000 687#define BGE_PORTMODE_MII 0x00000004 688#define BGE_PORTMODE_GMII 0x00000008 689#define BGE_PORTMODE_TBI 0x0000000C 690 691/* MAC Status register */ 692#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 693#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 694#define BGE_MACSTAT_RX_CFG 0x00000004 695#define BGE_MACSTAT_CFG_CHANGED 0x00000008 696#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 697#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 698#define BGE_MACSTAT_LINK_CHANGED 0x00001000 699#define BGE_MACSTAT_MI_COMPLETE 0x00400000 700#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 701#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 702#define BGE_MACSTAT_ODI_ERROR 0x02000000 703#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 704#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 705 706/* MAC Event Enable Register */ 707#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 708#define BGE_EVTENB_LINK_CHANGED 0x00001000 709#define BGE_EVTENB_MI_COMPLETE 0x00400000 710#define BGE_EVTENB_MI_INTERRUPT 0x00800000 711#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 712#define BGE_EVTENB_ODI_ERROR 0x02000000 713#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 714#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 715 716/* LED Control Register */ 717#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 718#define BGE_LEDCTL_1000MBPS_LED 0x00000002 719#define BGE_LEDCTL_100MBPS_LED 0x00000004 720#define BGE_LEDCTL_10MBPS_LED 0x00000008 721#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 722#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 723#define BGE_LEDCTL_TRAFLED_BLINK_2 0x00000040 724#define BGE_LEDCTL_1000MBPS_STS 0x00000080 725#define BGE_LEDCTL_100MBPS_STS 0x00000100 726#define BGE_LEDCTL_10MBPS_STS 0x00000200 727#define BGE_LEDCTL_TRADLED_STS 0x00000400 728#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 729#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 730 731/* TX backoff seed register */ 732#define BGE_TX_BACKOFF_SEED_MASK 0x3FF 733 734/* Autopoll status register */ 735#define BGE_AUTOPOLLSTS_ERROR 0x00000001 736 737/* Transmit MAC mode register */ 738#define BGE_TXMODE_RESET 0x00000001 739#define BGE_TXMODE_ENABLE 0x00000002 740#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 741#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 742#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 743#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 744#define BGE_TXMODE_JMB_FRM_LEN 0x00400000 745#define BGE_TXMODE_CNT_DN_MODE 0x00800000 746 747/* Transmit MAC status register */ 748#define BGE_TXSTAT_RX_XOFFED 0x00000001 749#define BGE_TXSTAT_SENT_XOFF 0x00000002 750#define BGE_TXSTAT_SENT_XON 0x00000004 751#define BGE_TXSTAT_LINK_UP 0x00000008 752#define BGE_TXSTAT_ODI_UFLOW 0x00000010 753#define BGE_TXSTAT_ODI_OFLOW 0x00000020 754 755/* Transmit MAC lengths register */ 756#define BGE_TXLEN_SLOTTIME 0x000000FF 757#define BGE_TXLEN_IPG 0x00000F00 758#define BGE_TXLEN_CRS 0x00003000 759#define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000 760#define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000 761 762/* Receive MAC mode register */ 763#define BGE_RXMODE_RESET 0x00000001 764#define BGE_RXMODE_ENABLE 0x00000002 765#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 766#define BGE_RXMODE_RX_GIANTS 0x00000020 767#define BGE_RXMODE_RX_RUNTS 0x00000040 768#define BGE_RXMODE_8022_LENCHECK 0x00000080 769#define BGE_RXMODE_RX_PROMISC 0x00000100 770#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 771#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 772#define BGE_RXMODE_IPV6_ENABLE 0x01000000 773#define BGE_RXMODE_IPV4_FRAG_FIX 0x02000000 774 775/* Receive MAC status register */ 776#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 777#define BGE_RXSTAT_RCVD_XOFF 0x00000002 778#define BGE_RXSTAT_RCVD_XON 0x00000004 779 780/* Receive Rules Control register */ 781#define BGE_RXRULECTL_OFFSET 0x000000FF 782#define BGE_RXRULECTL_CLASS 0x00001F00 783#define BGE_RXRULECTL_HDRTYPE 0x0000E000 784#define BGE_RXRULECTL_COMPARE_OP 0x00030000 785#define BGE_RXRULECTL_MAP 0x01000000 786#define BGE_RXRULECTL_DISCARD 0x02000000 787#define BGE_RXRULECTL_MASK 0x04000000 788#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 789#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 790#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 791#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 792 793/* Receive Rules Mask register */ 794#define BGE_RXRULEMASK_VALUE 0x0000FFFF 795#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 796 797/* SERDES configuration register */ 798#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 799#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 800#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 801#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 802#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 803#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 804#define BGE_SERDESCFG_TXMODE 0x00001000 805#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 806#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 807#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 808#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 809#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 810#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 811#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125MHz clock */ 812#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 813#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 814 815/* SERDES status register */ 816#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 817#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 818 819/* PHYCFG1 config */ 820#define BGE_PHYCFG1_RGMII_INT 0x00000001 821#define BGE_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000 822#define BGE_PHYCFG1_RGMII_SND_STAT_EN 0x04000000 823#define BGE_PHYCFG1_TXC_DRV 0x20000000 824 825/* PHYCFG2 config */ 826#define BGE_PHYCFG2_INBAND_ENABLE 0x00000001 827#define BGE_PHYCFG2_EMODE_MASK_MASK 0x000001c0 828#define BGE_PHYCFG2_EMODE_MASK_AC131 0x000000c0 829#define BGE_PHYCFG2_EMODE_MASK_50610 0x00000100 830#define BGE_PHYCFG2_EMODE_MASK_RT8211 0x00000000 831#define BGE_PHYCFG2_EMODE_MASK_RT8201 0x000001c0 832#define BGE_PHYCFG2_EMODE_COMP_MASK 0x00000e00 833#define BGE_PHYCFG2_EMODE_COMP_AC131 0x00000600 834#define BGE_PHYCFG2_EMODE_COMP_50610 0x00000400 835#define BGE_PHYCFG2_EMODE_COMP_RT8211 0x00000800 836#define BGE_PHYCFG2_EMODE_COMP_RT8201 0x00000000 837#define BGE_PHYCFG2_FMODE_MASK_MASK 0x00007000 838#define BGE_PHYCFG2_FMODE_MASK_AC131 0x00006000 839#define BGE_PHYCFG2_FMODE_MASK_50610 0x00004000 840#define BGE_PHYCFG2_FMODE_MASK_RT8211 0x00000000 841#define BGE_PHYCFG2_FMODE_MASK_RT8201 0x00007000 842#define BGE_PHYCFG2_FMODE_COMP_MASK 0x00038000 843#define BGE_PHYCFG2_FMODE_COMP_AC131 0x00030000 844#define BGE_PHYCFG2_FMODE_COMP_50610 0x00008000 845#define BGE_PHYCFG2_FMODE_COMP_RT8211 0x00038000 846#define BGE_PHYCFG2_FMODE_COMP_RT8201 0x00000000 847#define BGE_PHYCFG2_GMODE_MASK_MASK 0x001c0000 848#define BGE_PHYCFG2_GMODE_MASK_AC131 0x001c0000 849#define BGE_PHYCFG2_GMODE_MASK_50610 0x00100000 850#define BGE_PHYCFG2_GMODE_MASK_RT8211 0x00000000 851#define BGE_PHYCFG2_GMODE_MASK_RT8201 0x001c0000 852#define BGE_PHYCFG2_GMODE_COMP_MASK 0x00e00000 853#define BGE_PHYCFG2_GMODE_COMP_AC131 0x00e00000 854#define BGE_PHYCFG2_GMODE_COMP_50610 0x00000000 855#define BGE_PHYCFG2_GMODE_COMP_RT8211 0x00200000 856#define BGE_PHYCFG2_GMODE_COMP_RT8201 0x00000000 857#define BGE_PHYCFG2_ACT_MASK_MASK 0x03000000 858#define BGE_PHYCFG2_ACT_MASK_AC131 0x03000000 859#define BGE_PHYCFG2_ACT_MASK_50610 0x01000000 860#define BGE_PHYCFG2_ACT_MASK_RT8211 0x03000000 861#define BGE_PHYCFG2_ACT_MASK_RT8201 0x01000000 862#define BGE_PHYCFG2_ACT_COMP_MASK 0x0c000000 863#define BGE_PHYCFG2_ACT_COMP_AC131 0x00000000 864#define BGE_PHYCFG2_ACT_COMP_50610 0x00000000 865#define BGE_PHYCFG2_ACT_COMP_RT8211 0x00000000 866#define BGE_PHYCFG2_ACT_COMP_RT8201 0x08000000 867#define BGE_PHYCFG2_QUAL_MASK_MASK 0x30000000 868#define BGE_PHYCFG2_QUAL_MASK_AC131 0x30000000 869#define BGE_PHYCFG2_QUAL_MASK_50610 0x30000000 870#define BGE_PHYCFG2_QUAL_MASK_RT8211 0x30000000 871#define BGE_PHYCFG2_QUAL_MASK_RT8201 0x30000000 872#define BGE_PHYCFG2_QUAL_COMP_MASK 0xc0000000 873#define BGE_PHYCFG2_QUAL_COMP_AC131 0x00000000 874#define BGE_PHYCFG2_QUAL_COMP_50610 0x00000000 875#define BGE_PHYCFG2_QUAL_COMP_RT8211 0x00000000 876#define BGE_PHYCFG2_QUAL_COMP_RT8201 0x00000000 877#define BGE_PHYCFG2_50610_LED_MODES \ 878 (BGE_PHYCFG2_EMODE_MASK_50610 | \ 879 BGE_PHYCFG2_EMODE_COMP_50610 | \ 880 BGE_PHYCFG2_FMODE_MASK_50610 | \ 881 BGE_PHYCFG2_FMODE_COMP_50610 | \ 882 BGE_PHYCFG2_GMODE_MASK_50610 | \ 883 BGE_PHYCFG2_GMODE_COMP_50610 | \ 884 BGE_PHYCFG2_ACT_MASK_50610 | \ 885 BGE_PHYCFG2_ACT_COMP_50610 | \ 886 BGE_PHYCFG2_QUAL_MASK_50610 | \ 887 BGE_PHYCFG2_QUAL_COMP_50610) 888#define BGE_PHYCFG2_AC131_LED_MODES \ 889 (BGE_PHYCFG2_EMODE_MASK_AC131 | \ 890 BGE_PHYCFG2_EMODE_COMP_AC131 | \ 891 BGE_PHYCFG2_FMODE_MASK_AC131 | \ 892 BGE_PHYCFG2_FMODE_COMP_AC131 | \ 893 BGE_PHYCFG2_GMODE_MASK_AC131 | \ 894 BGE_PHYCFG2_GMODE_COMP_AC131 | \ 895 BGE_PHYCFG2_ACT_MASK_AC131 | \ 896 BGE_PHYCFG2_ACT_COMP_AC131 | \ 897 BGE_PHYCFG2_QUAL_MASK_AC131 | \ 898 BGE_PHYCFG2_QUAL_COMP_AC131) 899#define BGE_PHYCFG2_RTL8211C_LED_MODES \ 900 (BGE_PHYCFG2_EMODE_MASK_RT8211 | \ 901 BGE_PHYCFG2_EMODE_COMP_RT8211 | \ 902 BGE_PHYCFG2_FMODE_MASK_RT8211 | \ 903 BGE_PHYCFG2_FMODE_COMP_RT8211 | \ 904 BGE_PHYCFG2_GMODE_MASK_RT8211 | \ 905 BGE_PHYCFG2_GMODE_COMP_RT8211 | \ 906 BGE_PHYCFG2_ACT_MASK_RT8211 | \ 907 BGE_PHYCFG2_ACT_COMP_RT8211 | \ 908 BGE_PHYCFG2_QUAL_MASK_RT8211 | \ 909 BGE_PHYCFG2_QUAL_COMP_RT8211) 910#define BGE_PHYCFG2_RTL8201E_LED_MODES \ 911 (BGE_PHYCFG2_EMODE_MASK_RT8201 | \ 912 BGE_PHYCFG2_EMODE_COMP_RT8201 | \ 913 BGE_PHYCFG2_FMODE_MASK_RT8201 | \ 914 BGE_PHYCFG2_FMODE_COMP_RT8201 | \ 915 BGE_PHYCFG2_GMODE_MASK_RT8201 | \ 916 BGE_PHYCFG2_GMODE_COMP_RT8201 | \ 917 BGE_PHYCFG2_ACT_MASK_RT8201 | \ 918 BGE_PHYCFG2_ACT_COMP_RT8201 | \ 919 BGE_PHYCFG2_QUAL_MASK_RT8201 | \ 920 BGE_PHYCFG2_QUAL_COMP_RT8201) 921 922/* EXT_RGMII_MODE config */ 923#define BGE_RGMII_MODE_TX_ENABLE 0x00000001 924#define BGE_RGMII_MODE_TX_LOWPWR 0x00000002 925#define BGE_RGMII_MODE_TX_RESET 0x00000004 926#define BGE_RGMII_MODE_RX_INT_B 0x00000100 927#define BGE_RGMII_MODE_RX_QUALITY 0x00000200 928#define BGE_RGMII_MODE_RX_ACTIVITY 0x00000400 929#define BGE_RGMII_MODE_RX_ENG_DET 0x00000800 930 931/* SGDIG config (not documented) */ 932#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 933#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 934#define BGE_SGDIGCFG_SEND 0x40000000 935#define BGE_SGDIGCFG_AUTO 0x80000000 936 937/* SGDIG status (not documented) */ 938#define BGE_SGDIGSTS_DONE 0x00000002 939#define BGE_SGDIGSTS_IS_SERDES 0x00000100 940#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 941#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 942 943/* MI communication register */ 944#define BGE_MICOMM_DATA 0x0000FFFF 945#define BGE_MICOMM_REG 0x001F0000 946#define BGE_MICOMM_PHY 0x03E00000 947#define BGE_MICOMM_CMD 0x0C000000 948#define BGE_MICOMM_READFAIL 0x10000000 949#define BGE_MICOMM_BUSY 0x20000000 950 951#define BGE_MIREG(x) ((x & 0x1F) << 16) 952#define BGE_MIPHY(x) ((x & 0x1F) << 21) 953#define BGE_MICMD_WRITE 0x04000000 954#define BGE_MICMD_READ 0x08000000 955 956/* MI status register */ 957#define BGE_MISTS_LINK 0x00000001 958#define BGE_MISTS_10MBPS 0x00000002 959 960#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 961#define BGE_MIMODE_AUTOPOLL 0x00000010 962#define BGE_MIMODE_CLKCNT 0x001F0000 963#define BGE_MIMODE_500KHZ_CONST 0x00008000 964#define BGE_MIMODE_BASE 0x000C0000 965#define BGE_MIMODE_PHYADDR(x) ((x & 0x1F) << 5) 966 967/* 968 * Send data initiator control registers. 969 */ 970#define BGE_SDI_MODE 0x0C00 971#define BGE_SDI_STATUS 0x0C04 972#define BGE_SDI_STATS_CTL 0x0C08 973#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 974#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 975#define BGE_ISO_PKT_TX 0x0C20 976#define BGE_LOCSTATS_COS0 0x0C80 977#define BGE_LOCSTATS_COS1 0x0C84 978#define BGE_LOCSTATS_COS2 0x0C88 979#define BGE_LOCSTATS_COS3 0x0C8C 980#define BGE_LOCSTATS_COS4 0x0C90 981#define BGE_LOCSTATS_COS5 0x0C84 982#define BGE_LOCSTATS_COS6 0x0C98 983#define BGE_LOCSTATS_COS7 0x0C9C 984#define BGE_LOCSTATS_COS8 0x0CA0 985#define BGE_LOCSTATS_COS9 0x0CA4 986#define BGE_LOCSTATS_COS10 0x0CA8 987#define BGE_LOCSTATS_COS11 0x0CAC 988#define BGE_LOCSTATS_COS12 0x0CB0 989#define BGE_LOCSTATS_COS13 0x0CB4 990#define BGE_LOCSTATS_COS14 0x0CB8 991#define BGE_LOCSTATS_COS15 0x0CBC 992#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 993#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 994#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 995#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 996#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 997#define BGE_LOCSTATS_IRQS 0x0CD4 998#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 999#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 1000 1001/* Send Data Initiator mode register */ 1002#define BGE_SDIMODE_RESET 0x00000001 1003#define BGE_SDIMODE_ENABLE 0x00000002 1004#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 1005 1006/* Send Data Initiator stats register */ 1007#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 1008 1009/* Send Data Initiator stats control register */ 1010#define BGE_SDISTATSCTL_ENABLE 0x00000001 1011#define BGE_SDISTATSCTL_FASTER 0x00000002 1012#define BGE_SDISTATSCTL_CLEAR 0x00000004 1013#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 1014#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 1015 1016/* 1017 * Send Data Completion Control registers 1018 */ 1019#define BGE_SDC_MODE 0x1000 1020#define BGE_SDC_STATUS 0x1004 1021 1022/* Send Data completion mode register */ 1023#define BGE_SDCMODE_RESET 0x00000001 1024#define BGE_SDCMODE_ENABLE 0x00000002 1025#define BGE_SDCMODE_ATTN 0x00000004 1026#define BGE_SDCMODE_CDELAY 0x00000010 1027 1028/* Send Data completion status register */ 1029#define BGE_SDCSTAT_ATTN 0x00000004 1030 1031/* 1032 * Send BD Ring Selector Control registers 1033 */ 1034#define BGE_SRS_MODE 0x1400 1035#define BGE_SRS_STATUS 0x1404 1036#define BGE_SRS_HWDIAG 0x1408 1037#define BGE_SRS_LOC_NIC_CONS0 0x1440 1038#define BGE_SRS_LOC_NIC_CONS1 0x1444 1039#define BGE_SRS_LOC_NIC_CONS2 0x1448 1040#define BGE_SRS_LOC_NIC_CONS3 0x144C 1041#define BGE_SRS_LOC_NIC_CONS4 0x1450 1042#define BGE_SRS_LOC_NIC_CONS5 0x1454 1043#define BGE_SRS_LOC_NIC_CONS6 0x1458 1044#define BGE_SRS_LOC_NIC_CONS7 0x145C 1045#define BGE_SRS_LOC_NIC_CONS8 0x1460 1046#define BGE_SRS_LOC_NIC_CONS9 0x1464 1047#define BGE_SRS_LOC_NIC_CONS10 0x1468 1048#define BGE_SRS_LOC_NIC_CONS11 0x146C 1049#define BGE_SRS_LOC_NIC_CONS12 0x1470 1050#define BGE_SRS_LOC_NIC_CONS13 0x1474 1051#define BGE_SRS_LOC_NIC_CONS14 0x1478 1052#define BGE_SRS_LOC_NIC_CONS15 0x147C 1053 1054/* Send BD Ring Selector Mode register */ 1055#define BGE_SRSMODE_RESET 0x00000001 1056#define BGE_SRSMODE_ENABLE 0x00000002 1057#define BGE_SRSMODE_ATTN 0x00000004 1058 1059/* Send BD Ring Selector Status register */ 1060#define BGE_SRSSTAT_ERROR 0x00000004 1061 1062/* Send BD Ring Selector HW Diagnostics register */ 1063#define BGE_SRSHWDIAG_STATE 0x0000000F 1064#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 1065#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 1066#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 1067 1068/* 1069 * Send BD Initiator Selector Control registers 1070 */ 1071#define BGE_SBDI_MODE 0x1800 1072#define BGE_SBDI_STATUS 0x1804 1073#define BGE_SBDI_LOC_NIC_PROD0 0x1808 1074#define BGE_SBDI_LOC_NIC_PROD1 0x180C 1075#define BGE_SBDI_LOC_NIC_PROD2 0x1810 1076#define BGE_SBDI_LOC_NIC_PROD3 0x1814 1077#define BGE_SBDI_LOC_NIC_PROD4 0x1818 1078#define BGE_SBDI_LOC_NIC_PROD5 0x181C 1079#define BGE_SBDI_LOC_NIC_PROD6 0x1820 1080#define BGE_SBDI_LOC_NIC_PROD7 0x1824 1081#define BGE_SBDI_LOC_NIC_PROD8 0x1828 1082#define BGE_SBDI_LOC_NIC_PROD9 0x182C 1083#define BGE_SBDI_LOC_NIC_PROD10 0x1830 1084#define BGE_SBDI_LOC_NIC_PROD11 0x1834 1085#define BGE_SBDI_LOC_NIC_PROD12 0x1838 1086#define BGE_SBDI_LOC_NIC_PROD13 0x183C 1087#define BGE_SBDI_LOC_NIC_PROD14 0x1840 1088#define BGE_SBDI_LOC_NIC_PROD15 0x1844 1089 1090/* Send BD Initiator Mode register */ 1091#define BGE_SBDIMODE_RESET 0x00000001 1092#define BGE_SBDIMODE_ENABLE 0x00000002 1093#define BGE_SBDIMODE_ATTN 0x00000004 1094 1095/* Send BD Initiator Status register */ 1096#define BGE_SBDISTAT_ERROR 0x00000004 1097 1098/* 1099 * Send BD Completion Control registers 1100 */ 1101#define BGE_SBDC_MODE 0x1C00 1102#define BGE_SBDC_STATUS 0x1C04 1103 1104/* Send BD Completion Control Mode register */ 1105#define BGE_SBDCMODE_RESET 0x00000001 1106#define BGE_SBDCMODE_ENABLE 0x00000002 1107#define BGE_SBDCMODE_ATTN 0x00000004 1108 1109/* Send BD Completion Control Status register */ 1110#define BGE_SBDCSTAT_ATTN 0x00000004 1111 1112/* 1113 * Receive List Placement Control registers 1114 */ 1115#define BGE_RXLP_MODE 0x2000 1116#define BGE_RXLP_STATUS 0x2004 1117#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1118#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1119#define BGE_RXLP_CFG 0x2010 1120#define BGE_RXLP_STATS_CTL 0x2014 1121#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1122#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1123#define BGE_RXLP_HEAD0 0x2100 1124#define BGE_RXLP_TAIL0 0x2104 1125#define BGE_RXLP_COUNT0 0x2108 1126#define BGE_RXLP_HEAD1 0x2110 1127#define BGE_RXLP_TAIL1 0x2114 1128#define BGE_RXLP_COUNT1 0x2118 1129#define BGE_RXLP_HEAD2 0x2120 1130#define BGE_RXLP_TAIL2 0x2124 1131#define BGE_RXLP_COUNT2 0x2128 1132#define BGE_RXLP_HEAD3 0x2130 1133#define BGE_RXLP_TAIL3 0x2134 1134#define BGE_RXLP_COUNT3 0x2138 1135#define BGE_RXLP_HEAD4 0x2140 1136#define BGE_RXLP_TAIL4 0x2144 1137#define BGE_RXLP_COUNT4 0x2148 1138#define BGE_RXLP_HEAD5 0x2150 1139#define BGE_RXLP_TAIL5 0x2154 1140#define BGE_RXLP_COUNT5 0x2158 1141#define BGE_RXLP_HEAD6 0x2160 1142#define BGE_RXLP_TAIL6 0x2164 1143#define BGE_RXLP_COUNT6 0x2168 1144#define BGE_RXLP_HEAD7 0x2170 1145#define BGE_RXLP_TAIL7 0x2174 1146#define BGE_RXLP_COUNT7 0x2178 1147#define BGE_RXLP_HEAD8 0x2180 1148#define BGE_RXLP_TAIL8 0x2184 1149#define BGE_RXLP_COUNT8 0x2188 1150#define BGE_RXLP_HEAD9 0x2190 1151#define BGE_RXLP_TAIL9 0x2194 1152#define BGE_RXLP_COUNT9 0x2198 1153#define BGE_RXLP_HEAD10 0x21A0 1154#define BGE_RXLP_TAIL10 0x21A4 1155#define BGE_RXLP_COUNT10 0x21A8 1156#define BGE_RXLP_HEAD11 0x21B0 1157#define BGE_RXLP_TAIL11 0x21B4 1158#define BGE_RXLP_COUNT11 0x21B8 1159#define BGE_RXLP_HEAD12 0x21C0 1160#define BGE_RXLP_TAIL12 0x21C4 1161#define BGE_RXLP_COUNT12 0x21C8 1162#define BGE_RXLP_HEAD13 0x21D0 1163#define BGE_RXLP_TAIL13 0x21D4 1164#define BGE_RXLP_COUNT13 0x21D8 1165#define BGE_RXLP_HEAD14 0x21E0 1166#define BGE_RXLP_TAIL14 0x21E4 1167#define BGE_RXLP_COUNT14 0x21E8 1168#define BGE_RXLP_HEAD15 0x21F0 1169#define BGE_RXLP_TAIL15 0x21F4 1170#define BGE_RXLP_COUNT15 0x21F8 1171#define BGE_RXLP_LOCSTAT_COS0 0x2200 1172#define BGE_RXLP_LOCSTAT_COS1 0x2204 1173#define BGE_RXLP_LOCSTAT_COS2 0x2208 1174#define BGE_RXLP_LOCSTAT_COS3 0x220C 1175#define BGE_RXLP_LOCSTAT_COS4 0x2210 1176#define BGE_RXLP_LOCSTAT_COS5 0x2214 1177#define BGE_RXLP_LOCSTAT_COS6 0x2218 1178#define BGE_RXLP_LOCSTAT_COS7 0x221C 1179#define BGE_RXLP_LOCSTAT_COS8 0x2220 1180#define BGE_RXLP_LOCSTAT_COS9 0x2224 1181#define BGE_RXLP_LOCSTAT_COS10 0x2228 1182#define BGE_RXLP_LOCSTAT_COS11 0x222C 1183#define BGE_RXLP_LOCSTAT_COS12 0x2230 1184#define BGE_RXLP_LOCSTAT_COS13 0x2234 1185#define BGE_RXLP_LOCSTAT_COS14 0x2238 1186#define BGE_RXLP_LOCSTAT_COS15 0x223C 1187#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1188#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1189#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1190#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1191#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1192#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1193#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1194 1195 1196/* Receive List Placement mode register */ 1197#define BGE_RXLPMODE_RESET 0x00000001 1198#define BGE_RXLPMODE_ENABLE 0x00000002 1199#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1200#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1201#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1202 1203/* Receive List Placement Status register */ 1204#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1205#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1206#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1207 1208/* 1209 * Receive Data and Receive BD Initiator Control Registers 1210 */ 1211#define BGE_RDBDI_MODE 0x2400 1212#define BGE_RDBDI_STATUS 0x2404 1213#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1214#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1215#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1216#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1217#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1218#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1219#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1220#define BGE_RX_STD_RCB_NICADDR 0x245C 1221#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1222#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1223#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1224#define BGE_RX_MINI_RCB_NICADDR 0x246C 1225#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1226#define BGE_RDBDI_STD_RX_CONS 0x2474 1227#define BGE_RDBDI_MINI_RX_CONS 0x2478 1228#define BGE_RDBDI_RETURN_PROD0 0x2480 1229#define BGE_RDBDI_RETURN_PROD1 0x2484 1230#define BGE_RDBDI_RETURN_PROD2 0x2488 1231#define BGE_RDBDI_RETURN_PROD3 0x248C 1232#define BGE_RDBDI_RETURN_PROD4 0x2490 1233#define BGE_RDBDI_RETURN_PROD5 0x2494 1234#define BGE_RDBDI_RETURN_PROD6 0x2498 1235#define BGE_RDBDI_RETURN_PROD7 0x249C 1236#define BGE_RDBDI_RETURN_PROD8 0x24A0 1237#define BGE_RDBDI_RETURN_PROD9 0x24A4 1238#define BGE_RDBDI_RETURN_PROD10 0x24A8 1239#define BGE_RDBDI_RETURN_PROD11 0x24AC 1240#define BGE_RDBDI_RETURN_PROD12 0x24B0 1241#define BGE_RDBDI_RETURN_PROD13 0x24B4 1242#define BGE_RDBDI_RETURN_PROD14 0x24B8 1243#define BGE_RDBDI_RETURN_PROD15 0x24BC 1244#define BGE_RDBDI_HWDIAG 0x24C0 1245 1246 1247/* Receive Data and Receive BD Initiator Mode register */ 1248#define BGE_RDBDIMODE_RESET 0x00000001 1249#define BGE_RDBDIMODE_ENABLE 0x00000002 1250#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1251#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1252#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1253 1254/* Receive Data and Receive BD Initiator Status register */ 1255#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1256#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1257#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1258 1259 1260/* 1261 * Receive Data Completion Control registers 1262 */ 1263#define BGE_RDC_MODE 0x2800 1264 1265/* Receive Data Completion Mode register */ 1266#define BGE_RDCMODE_RESET 0x00000001 1267#define BGE_RDCMODE_ENABLE 0x00000002 1268#define BGE_RDCMODE_ATTN 0x00000004 1269 1270/* 1271 * Receive BD Initiator Control registers 1272 */ 1273#define BGE_RBDI_MODE 0x2C00 1274#define BGE_RBDI_STATUS 0x2C04 1275#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1276#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1277#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1278#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1279#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1280#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1281 1282#define BGE_STD_REPL_LWM 0x2D00 1283#define BGE_JUMBO_REPL_LWM 0x2D04 1284 1285/* Receive BD Initiator Mode register */ 1286#define BGE_RBDIMODE_RESET 0x00000001 1287#define BGE_RBDIMODE_ENABLE 0x00000002 1288#define BGE_RBDIMODE_ATTN 0x00000004 1289 1290/* Receive BD Initiator Status register */ 1291#define BGE_RBDISTAT_ATTN 0x00000004 1292 1293/* 1294 * Receive BD Completion Control registers 1295 */ 1296#define BGE_RBDC_MODE 0x3000 1297#define BGE_RBDC_STATUS 0x3004 1298#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1299#define BGE_RBDC_STD_BD_PROD 0x300C 1300#define BGE_RBDC_MINI_BD_PROD 0x3010 1301 1302/* Receive BD completion mode register */ 1303#define BGE_RBDCMODE_RESET 0x00000001 1304#define BGE_RBDCMODE_ENABLE 0x00000002 1305#define BGE_RBDCMODE_ATTN 0x00000004 1306 1307/* Receive BD completion status register */ 1308#define BGE_RBDCSTAT_ERROR 0x00000004 1309 1310/* 1311 * Receive List Selector Control registers 1312 */ 1313#define BGE_RXLS_MODE 0x3400 1314#define BGE_RXLS_STATUS 0x3404 1315 1316/* Receive List Selector Mode register */ 1317#define BGE_RXLSMODE_RESET 0x00000001 1318#define BGE_RXLSMODE_ENABLE 0x00000002 1319#define BGE_RXLSMODE_ATTN 0x00000004 1320 1321/* Receive List Selector Status register */ 1322#define BGE_RXLSSTAT_ERROR 0x00000004 1323 1324#define BGE_CPMU_CTRL 0x3600 1325#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1326#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1327#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1328#define BGE_CPMU_HST_ACC 0x361C 1329#define BGE_CPMU_CLCK_ORIDE 0x3624 1330#define BGE_CPMU_CLCK_STAT 0x3630 1331#define BGE_CPMU_MUTEX_REQ 0x365C 1332#define BGE_CPMU_MUTEX_GNT 0x3660 1333#define BGE_CPMU_PHY_STRAP 0x3664 1334#define BGE_CPMU_PADRNG_CTL 0x3668 1335 1336/* Central Power Management Unit (CPMU) register */ 1337#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1338#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1339#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1340#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1341 1342/* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1343#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1344#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1345 1346/* Link Speed 1000MB Power Mode Clock Policy register */ 1347#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1348#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1349#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1350 1351/* Link Aware Power Mode Clock Policy register */ 1352#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1353#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1354 1355#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1356#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1357 1358/* Clock Speed Override Policy register */ 1359#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1360 1361/* CPMU Clock Status register */ 1362#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1363#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1364#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1365#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1366 1367/* CPMU Mutex Request register */ 1368#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1369#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1370 1371/* CPMU GPHY Strap register */ 1372#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1373 1374/* CPMU Padring Control register */ 1375#define BGE_CPMU_PADRNG_CTL_RDIV2 0x00040000 1376 1377/* 1378 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1379 */ 1380#define BGE_MBCF_MODE 0x3800 1381#define BGE_MBCF_STATUS 0x3804 1382 1383/* Mbuf Cluster Free mode register */ 1384#define BGE_MBCFMODE_RESET 0x00000001 1385#define BGE_MBCFMODE_ENABLE 0x00000002 1386#define BGE_MBCFMODE_ATTN 0x00000004 1387 1388/* Mbuf Cluster Free status register */ 1389#define BGE_MBCFSTAT_ERROR 0x00000004 1390 1391/* 1392 * Host Coalescing Control registers 1393 */ 1394#define BGE_HCC_MODE 0x3C00 1395#define BGE_HCC_STATUS 0x3C04 1396#define BGE_HCC_RX_COAL_TICKS 0x3C08 1397#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1398#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1399#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1400#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1401#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1402#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1403#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1404#define BGE_HCC_STATS_TICKS 0x3C28 1405#define BGE_HCC_STATS_ADDR_HI 0x3C30 1406#define BGE_HCC_STATS_ADDR_LO 0x3C34 1407#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1408#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1409#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1410#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1411#define BGE_FLOW_ATTN 0x3C48 1412#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1413#define BGE_HCC_STD_BD_CONS 0x3C54 1414#define BGE_HCC_MINI_BD_CONS 0x3C58 1415#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1416#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1417#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1418#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1419#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1420#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1421#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1422#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1423#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1424#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1425#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1426#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1427#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1428#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1429#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1430#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1431#define BGE_HCC_TX_BD_CONS0 0x3CC0 1432#define BGE_HCC_TX_BD_CONS1 0x3CC4 1433#define BGE_HCC_TX_BD_CONS2 0x3CC8 1434#define BGE_HCC_TX_BD_CONS3 0x3CCC 1435#define BGE_HCC_TX_BD_CONS4 0x3CD0 1436#define BGE_HCC_TX_BD_CONS5 0x3CD4 1437#define BGE_HCC_TX_BD_CONS6 0x3CD8 1438#define BGE_HCC_TX_BD_CONS7 0x3CDC 1439#define BGE_HCC_TX_BD_CONS8 0x3CE0 1440#define BGE_HCC_TX_BD_CONS9 0x3CE4 1441#define BGE_HCC_TX_BD_CONS10 0x3CE8 1442#define BGE_HCC_TX_BD_CONS11 0x3CEC 1443#define BGE_HCC_TX_BD_CONS12 0x3CF0 1444#define BGE_HCC_TX_BD_CONS13 0x3CF4 1445#define BGE_HCC_TX_BD_CONS14 0x3CF8 1446#define BGE_HCC_TX_BD_CONS15 0x3CFC 1447 1448 1449/* Host coalescing mode register */ 1450#define BGE_HCCMODE_RESET 0x00000001 1451#define BGE_HCCMODE_ENABLE 0x00000002 1452#define BGE_HCCMODE_ATTN 0x00000004 1453#define BGE_HCCMODE_COAL_NOW 0x00000008 1454#define BGE_HCCMODE_MSI_BITS 0x00000070 1455#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1456 1457#define BGE_STATBLKSZ_FULL 0x00000000 1458#define BGE_STATBLKSZ_64BYTE 0x00000080 1459#define BGE_STATBLKSZ_32BYTE 0x00000100 1460 1461/* Host coalescing status register */ 1462#define BGE_HCCSTAT_ERROR 0x00000004 1463 1464/* Flow attention register */ 1465#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1466#define BGE_FLOWATTN_MEMARB 0x00000080 1467#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1468#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1469#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1470#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1471#define BGE_FLOWATTN_RDBDI 0x00080000 1472#define BGE_FLOWATTN_RXLS 0x00100000 1473#define BGE_FLOWATTN_RXLP 0x00200000 1474#define BGE_FLOWATTN_RBDC 0x00400000 1475#define BGE_FLOWATTN_RBDI 0x00800000 1476#define BGE_FLOWATTN_SDC 0x08000000 1477#define BGE_FLOWATTN_SDI 0x10000000 1478#define BGE_FLOWATTN_SRS 0x20000000 1479#define BGE_FLOWATTN_SBDC 0x40000000 1480#define BGE_FLOWATTN_SBDI 0x80000000 1481 1482/* 1483 * Memory arbiter registers 1484 */ 1485#define BGE_MARB_MODE 0x4000 1486#define BGE_MARB_STATUS 0x4004 1487#define BGE_MARB_TRAPADDR_HI 0x4008 1488#define BGE_MARB_TRAPADDR_LO 0x400C 1489 1490/* Memory arbiter mode register */ 1491#define BGE_MARBMODE_RESET 0x00000001 1492#define BGE_MARBMODE_ENABLE 0x00000002 1493#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1494#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1495#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1496#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1497#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1498#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1499#define BGE_MARBMODE_PCI_TRAP 0x00000100 1500#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1501#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1502#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1503#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1504#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1505#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1506#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1507#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1508#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1509#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1510#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1511#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1512#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1513#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1514#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1515#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1516#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1517 1518/* Memory arbiter status register */ 1519#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1520#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1521#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1522#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1523#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1524#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1525#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1526#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1527#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1528#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1529#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1530#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1531#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1532#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1533#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1534#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1535#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1536#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1537#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1538#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1539#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1540#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1541#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1542#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1543 1544/* 1545 * Buffer manager control registers 1546 */ 1547#define BGE_BMAN_MODE 0x4400 1548#define BGE_BMAN_STATUS 0x4404 1549#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1550#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1551#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1552#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1553#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1554#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1555#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1556#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1557#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1558#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1559#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1560#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1561#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1562#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1563#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1564#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1565#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1566#define BGE_BMAN_HWDIAG_1 0x444C 1567#define BGE_BMAN_HWDIAG_2 0x4450 1568#define BGE_BMAN_HWDIAG_3 0x4454 1569 1570/* Buffer manager mode register */ 1571#define BGE_BMANMODE_RESET 0x00000001 1572#define BGE_BMANMODE_ENABLE 0x00000002 1573#define BGE_BMANMODE_ATTN 0x00000004 1574#define BGE_BMANMODE_TESTMODE 0x00000008 1575#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1576#define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000 1577 1578/* Buffer manager status register */ 1579#define BGE_BMANSTAT_ERRO 0x00000004 1580#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1581 1582 1583/* 1584 * Read DMA Control registers 1585 */ 1586#define BGE_RDMA_MODE 0x4800 1587#define BGE_RDMA_STATUS 0x4804 1588#define BGE_RDMA_RSRVCTRL_REG2 0x4890 1589#define BGE_RDMA_LSO_CRPTEN_CTRL_REG2 0x48A0 1590#define BGE_RDMA_RSRVCTRL 0x4900 1591#define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 1592 1593/* Read DMA mode register */ 1594#define BGE_RDMAMODE_RESET 0x00000001 1595#define BGE_RDMAMODE_ENABLE 0x00000002 1596#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1597#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1598#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1599#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1600#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1601#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1602#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1603#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1604#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1605#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1606#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1607#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1608#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1609#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1610#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1611#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1612#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1613#define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000 1614 1615/* Read DMA status register */ 1616#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1617#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1618#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1619#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1620#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1621#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1622#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1623#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1624 1625/* Read DMA Reserved Control register */ 1626#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1627#define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00 1628#define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000 1629#define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1630#define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0 1631#define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000 1632#define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000 1633 1634#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000 1635#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1636#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 1637#define BGE_RDMA_TX_LENGTH_WA_5719 0x02000000 1638#define BGE_RDMA_TX_LENGTH_WA_5720 0x00200000 1639 1640/* BD Read DMA Mode register */ 1641#define BGE_RDMA_BD_MODE 0x4A00 1642/* BD Read DMA Mode status register */ 1643#define BGE_RDMA_BD_STATUS 0x4A04 1644 1645#define BGE_RDMA_BD_MODE_RESET 0x00000001 1646#define BGE_RDMA_BD_MODE_ENABLE 0x00000002 1647 1648/* Non-LSO Read DMA Mode register */ 1649#define BGE_RDMA_NON_LSO_MODE 0x4B00 1650/* Non-LSO Read DMA Mode status register */ 1651#define BGE_RDMA_NON_LSO_STATUS 0x4B04 1652 1653#define BGE_RDMA_NON_LSO_MODE_RESET 0x00000001 1654#define BGE_RDMA_NON_LSO_MODE_ENABLE 0x00000002 1655 1656#define BGE_RDMA_LENGTH 0x4BE0 1657#define BGE_NUM_RDMA_CHANNELS 4 1658 1659/* 1660 * Write DMA control registers 1661 */ 1662#define BGE_WDMA_MODE 0x4C00 1663#define BGE_WDMA_STATUS 0x4C04 1664 1665/* Write DMA mode register */ 1666#define BGE_WDMAMODE_RESET 0x00000001 1667#define BGE_WDMAMODE_ENABLE 0x00000002 1668#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1669#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1670#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1671#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1672#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1673#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1674#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1675#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1676#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1677#define BGE_WDMAMODE_RX_ACCEL 0x00000400 1678#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1679#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1680 1681/* Write DMA status register */ 1682#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1683#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1684#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1685#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1686#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1687#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1688#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1689#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1690 1691 1692/* 1693 * RX CPU registers 1694 */ 1695#define BGE_RXCPU_MODE 0x5000 1696#define BGE_RXCPU_STATUS 0x5004 1697#define BGE_RXCPU_PC 0x501C 1698 1699/* RX CPU mode register */ 1700#define BGE_RXCPUMODE_RESET 0x00000001 1701#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1702#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1703#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1704#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1705#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1706#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1707#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1708#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1709#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1710#define BGE_RXCPUMODE_HALTCPU 0x00000400 1711#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1712#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1713#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1714 1715/* RX CPU status register */ 1716#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1717#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1718#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1719#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1720#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1721#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1722#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1723#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1724#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1725#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1726#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1727#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1728#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1729#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1730#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1731#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1732#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1733 1734 1735/* 1736 * V? CPU registers 1737 */ 1738#define BGE_VCPU_STATUS 0x5100 1739#define BGE_VCPU_EXT_CTRL 0x6890 1740 1741#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1742#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1743 1744#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1745#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1746 1747/* 1748 * TX CPU registers 1749 */ 1750#define BGE_TXCPU_MODE 0x5400 1751#define BGE_TXCPU_STATUS 0x5404 1752#define BGE_TXCPU_PC 0x541C 1753 1754/* TX CPU mode register */ 1755#define BGE_TXCPUMODE_RESET 0x00000001 1756#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1757#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1758#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1759#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1760#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1761#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1762#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1763#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1764#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1765#define BGE_TXCPUMODE_HALTCPU 0x00000400 1766#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1767#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1768 1769/* TX CPU status register */ 1770#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1771#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1772#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1773#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1774#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1775#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1776#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1777#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1778#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1779#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1780#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1781#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1782#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1783#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1784#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1785#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1786#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1787 1788 1789/* 1790 * Low priority mailbox registers 1791 */ 1792#define BGE_LPMBX_IRQ0_HI 0x5800 1793#define BGE_LPMBX_IRQ0_LO 0x5804 1794#define BGE_LPMBX_IRQ1_HI 0x5808 1795#define BGE_LPMBX_IRQ1_LO 0x580C 1796#define BGE_LPMBX_IRQ2_HI 0x5810 1797#define BGE_LPMBX_IRQ2_LO 0x5814 1798#define BGE_LPMBX_IRQ3_HI 0x5818 1799#define BGE_LPMBX_IRQ3_LO 0x581C 1800#define BGE_LPMBX_GEN0_HI 0x5820 1801#define BGE_LPMBX_GEN0_LO 0x5824 1802#define BGE_LPMBX_GEN1_HI 0x5828 1803#define BGE_LPMBX_GEN1_LO 0x582C 1804#define BGE_LPMBX_GEN2_HI 0x5830 1805#define BGE_LPMBX_GEN2_LO 0x5834 1806#define BGE_LPMBX_GEN3_HI 0x5828 1807#define BGE_LPMBX_GEN3_LO 0x582C 1808#define BGE_LPMBX_GEN4_HI 0x5840 1809#define BGE_LPMBX_GEN4_LO 0x5844 1810#define BGE_LPMBX_GEN5_HI 0x5848 1811#define BGE_LPMBX_GEN5_LO 0x584C 1812#define BGE_LPMBX_GEN6_HI 0x5850 1813#define BGE_LPMBX_GEN6_LO 0x5854 1814#define BGE_LPMBX_GEN7_HI 0x5858 1815#define BGE_LPMBX_GEN7_LO 0x585C 1816#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1817#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1818#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1819#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1820#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1821#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1822#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1823#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1824#define BGE_LPMBX_RX_CONS0_HI 0x5880 1825#define BGE_LPMBX_RX_CONS0_LO 0x5884 1826#define BGE_LPMBX_RX_CONS1_HI 0x5888 1827#define BGE_LPMBX_RX_CONS1_LO 0x588C 1828#define BGE_LPMBX_RX_CONS2_HI 0x5890 1829#define BGE_LPMBX_RX_CONS2_LO 0x5894 1830#define BGE_LPMBX_RX_CONS3_HI 0x5898 1831#define BGE_LPMBX_RX_CONS3_LO 0x589C 1832#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1833#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1834#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1835#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1836#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1837#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1838#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1839#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1840#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1841#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1842#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1843#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1844#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1845#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1846#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1847#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1848#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1849#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1850#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1851#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1852#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1853#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1854#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1855#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1856#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1857#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1858#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1859#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1860#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1861#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1862#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1863#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1864#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1865#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1866#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1867#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1868#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1869#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1870#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1871#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1872#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1873#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1874#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1875#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1876#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1877#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1878#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1879#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1880#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1881#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1882#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1883#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1884#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1885#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1886#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1887#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1888#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1889#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1890#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1891#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1892#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1893#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1894#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1895#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1896#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1897#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1898#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1899#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1900#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1901#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1902#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1903#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1904#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1905#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1906#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1907#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1908#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1909#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1910#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1911#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1912#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1913#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1914#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1915#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1916#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1917#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1918#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1919#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1920 1921/* 1922 * Flow throw Queue reset register 1923 */ 1924#define BGE_FTQ_RESET 0x5C00 1925 1926#define BGE_FTQRESET_DMAREAD 0x00000002 1927#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1928#define BGE_FTQRESET_DMADONE 0x00000010 1929#define BGE_FTQRESET_SBDC 0x00000020 1930#define BGE_FTQRESET_SDI 0x00000040 1931#define BGE_FTQRESET_WDMA 0x00000080 1932#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1933#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1934#define BGE_FTQRESET_SDC 0x00000400 1935#define BGE_FTQRESET_HCC 0x00000800 1936#define BGE_FTQRESET_TXFIFO 0x00001000 1937#define BGE_FTQRESET_MBC 0x00002000 1938#define BGE_FTQRESET_RBDC 0x00004000 1939#define BGE_FTQRESET_RXLP 0x00008000 1940#define BGE_FTQRESET_RDBDI 0x00010000 1941#define BGE_FTQRESET_RDC 0x00020000 1942#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1943 1944/* 1945 * Message Signaled Interrupt registers 1946 */ 1947#define BGE_MSI_MODE 0x6000 1948#define BGE_MSI_STATUS 0x6004 1949#define BGE_MSI_FIFOACCESS 0x6008 1950 1951/* MSI mode register */ 1952#define BGE_MSIMODE_RESET 0x00000001 1953#define BGE_MSIMODE_ENABLE 0x00000002 1954#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1955#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1956#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1957#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1958#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 1959 1960/* MSI status register */ 1961#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1962#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1963#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1964#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1965#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1966 1967 1968/* 1969 * DMA Completion registers 1970 */ 1971#define BGE_DMAC_MODE 0x6400 1972 1973/* DMA Completion mode register */ 1974#define BGE_DMACMODE_RESET 0x00000001 1975#define BGE_DMACMODE_ENABLE 0x00000002 1976 1977 1978/* 1979 * General control registers. 1980 */ 1981#define BGE_MODE_CTL 0x6800 1982#define BGE_MISC_CFG 0x6804 1983#define BGE_MISC_LOCAL_CTL 0x6808 1984#define BGE_RX_CPU_EVENT 0x6810 1985#define BGE_TX_CPU_EVENT 0x6820 1986#define BGE_EE_ADDR 0x6838 1987#define BGE_EE_DATA 0x683C 1988#define BGE_EE_CTL 0x6840 1989#define BGE_MDI_CTL 0x6844 1990#define BGE_EE_DELAY 0x6848 1991#define BGE_FASTBOOT_PC 0x6894 1992 1993#define BGE_RX_CPU_DRV_EVENT 0x00004000 1994 1995/* 1996 * NVRAM Control registers 1997 */ 1998 1999#define BGE_NVRAM_CMD 0x7000 2000#define BGE_NVRAM_STAT 0x7004 2001#define BGE_NVRAM_WRDATA 0x7008 2002#define BGE_NVRAM_ADDR 0x700c 2003#define BGE_NVRAM_RDDATA 0x7010 2004#define BGE_NVRAM_CFG1 0x7014 2005#define BGE_NVRAM_CFG2 0x7018 2006#define BGE_NVRAM_CFG3 0x701c 2007#define BGE_NVRAM_SWARB 0x7020 2008#define BGE_NVRAM_ACCESS 0x7024 2009#define BGE_NVRAM_WRITE1 0x7028 2010 2011 2012#define BGE_NVRAMCMD_RESET 0x00000001 2013#define BGE_NVRAMCMD_DONE 0x00000008 2014#define BGE_NVRAMCMD_START 0x00000010 2015#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 2016#define BGE_NVRAMCMD_ERASE 0x00000040 2017#define BGE_NVRAMCMD_FIRST 0x00000080 2018#define BGE_NVRAMCMD_LAST 0x00000100 2019 2020#define BGE_NVRAM_READCMD \ 2021 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 2022 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 2023#define BGE_NVRAM_WRITECMD \ 2024 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 2025 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 2026 2027#define BGE_NVRAMSWARB_SET0 0x00000001 2028#define BGE_NVRAMSWARB_SET1 0x00000002 2029#define BGE_NVRAMSWARB_SET2 0x00000003 2030#define BGE_NVRAMSWARB_SET3 0x00000004 2031#define BGE_NVRAMSWARB_CLR0 0x00000010 2032#define BGE_NVRAMSWARB_CLR1 0x00000020 2033#define BGE_NVRAMSWARB_CLR2 0x00000040 2034#define BGE_NVRAMSWARB_CLR3 0x00000080 2035#define BGE_NVRAMSWARB_GNT0 0x00000100 2036#define BGE_NVRAMSWARB_GNT1 0x00000200 2037#define BGE_NVRAMSWARB_GNT2 0x00000400 2038#define BGE_NVRAMSWARB_GNT3 0x00000800 2039#define BGE_NVRAMSWARB_REQ0 0x00001000 2040#define BGE_NVRAMSWARB_REQ1 0x00002000 2041#define BGE_NVRAMSWARB_REQ2 0x00004000 2042#define BGE_NVRAMSWARB_REQ3 0x00008000 2043 2044#define BGE_NVRAMACC_ENABLE 0x00000001 2045#define BGE_NVRAMACC_WRENABLE 0x00000002 2046 2047/* 2048 * TLP Control Register 2049 * Applicable to BCM5721 and BCM5751 only 2050 */ 2051#define BGE_TLP_CONTROL_REG 0x7c00 2052#define BGE_TLP_DATA_FIFO_PROTECT 0x02000000 2053 2054/* 2055 * PHY Test Control Register 2056 * Applicable to BCM5721 and BCM5751 only 2057 */ 2058#define BGE_PHY_TEST_CTRL_REG 0x7e2c 2059#define BGE_PHY_PCIE_SCRAM_MODE 0x0020 2060#define BGE_PHY_PCIE_LTASS_MODE 0x0040 2061 2062/* Mode control register */ 2063#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 2064#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 2065#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 2066#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 2067#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 2068#define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040 2069#define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080 2070#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 2071#define BGE_MODECTL_NO_RX_CRC 0x00000400 2072#define BGE_MODECTL_RX_BADFRAMES 0x00000800 2073#define BGE_MODECTL_NO_TX_INTR 0x00002000 2074#define BGE_MODECTL_NO_RX_INTR 0x00004000 2075#define BGE_MODECTL_FORCE_PCI32 0x00008000 2076#define BGE_MODECTL_B2HRX_ENABLE 0x00008000 2077#define BGE_MODECTL_STACKUP 0x00010000 2078#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 2079#define BGE_MODECTL_HTX2B_ENABLE 0x00040000 2080#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 2081#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 2082#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 2083#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 2084#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 2085#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 2086#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 2087#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 2088#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 2089 2090/* Misc. config register */ 2091#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 2092#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 2093#define BGE_MISCCFG_BOARD_ID_MASK 0x0001E000 2094#define BGE_MISCCFG_BOARD_ID_5704 0x00000000 2095#define BGE_MISCCFG_BOARD_ID_5704CIOBE 0x00004000 2096#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 2097#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 2098#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 2099#define BGE_MISCCFG_KEEP_GPHY_POWER 0x04000000 2100 2101#define BGE_32BITTIME_66MHZ (0x41 << 1) 2102 2103/* Misc. Local Control */ 2104#define BGE_MLC_INTR_STATE 0x00000001 2105#define BGE_MLC_INTR_CLR 0x00000002 2106#define BGE_MLC_INTR_SET 0x00000004 2107#define BGE_MLC_INTR_ONATTN 0x00000008 2108#define BGE_MLC_MISCIO_IN0 0x00000100 2109#define BGE_MLC_MISCIO_IN1 0x00000200 2110#define BGE_MLC_MISCIO_IN2 0x00000400 2111#define BGE_MLC_MISCIO_OUTEN0 0x00000800 2112#define BGE_MLC_MISCIO_OUTEN1 0x00001000 2113#define BGE_MLC_MISCIO_OUTEN2 0x00002000 2114#define BGE_MLC_MISCIO_OUT0 0x00004000 2115#define BGE_MLC_MISCIO_OUT1 0x00008000 2116#define BGE_MLC_MISCIO_OUT2 0x00010000 2117#define BGE_MLC_EXTRAM_ENB 0x00020000 2118#define BGE_MLC_SRAM_SIZE 0x001C0000 2119#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 2120#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 2121#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 2122#define BGE_MLC_AUTO_EEPROM 0x01000000 2123 2124#define BGE_SSRAMSIZE_256KB 0x00000000 2125#define BGE_SSRAMSIZE_512KB 0x00040000 2126#define BGE_SSRAMSIZE_1MB 0x00080000 2127#define BGE_SSRAMSIZE_2MB 0x000C0000 2128#define BGE_SSRAMSIZE_4MB 0x00100000 2129#define BGE_SSRAMSIZE_8MB 0x00140000 2130#define BGE_SSRAMSIZE_16M 0x00180000 2131 2132/* EEPROM address register */ 2133#define BGE_EEADDR_ADDRESS 0x0000FFFC 2134#define BGE_EEADDR_HALFCLK 0x01FF0000 2135#define BGE_EEADDR_START 0x02000000 2136#define BGE_EEADDR_DEVID 0x1C000000 2137#define BGE_EEADDR_RESET 0x20000000 2138#define BGE_EEADDR_DONE 0x40000000 2139#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 2140 2141#define BGE_EEDEVID(x) ((x & 7) << 26) 2142#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2143#define BGE_HALFCLK_384SCL 0x60 2144#define BGE_EE_READCMD \ 2145 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2146 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 2147#define BGE_EE_WRCMD \ 2148 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2149 BGE_EEADDR_START|BGE_EEADDR_DONE) 2150 2151/* EEPROM Control register */ 2152#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2153#define BGE_EECTL_CLKOUT 0x00000002 2154#define BGE_EECTL_CLKIN 0x00000004 2155#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2156#define BGE_EECTL_DATAOUT 0x00000010 2157#define BGE_EECTL_DATAIN 0x00000020 2158 2159/* MDI (MII/GMII) access register */ 2160#define BGE_MDI_DATA 0x00000001 2161#define BGE_MDI_DIR 0x00000002 2162#define BGE_MDI_SEL 0x00000004 2163#define BGE_MDI_CLK 0x00000008 2164 2165#define BGE_MEMWIN_START 0x00008000 2166#define BGE_MEMWIN_END 0x0000FFFF 2167 2168/* BAR1 (APE) Register Definitions */ 2169 2170#define BGE_APE_GPIO_MSG 0x0008 2171#define BGE_APE_EVENT 0x000C 2172#define BGE_APE_LOCK_REQ 0x002C 2173#define BGE_APE_LOCK_GRANT 0x004C 2174 2175#define BGE_APE_GPIO_MSG_SHIFT 4 2176 2177#define BGE_APE_EVENT_1 0x00000001 2178 2179#define BGE_APE_LOCK_REQ_DRIVER0 0x00001000 2180 2181#define BGE_APE_LOCK_GRANT_DRIVER0 0x00001000 2182 2183/* APE Shared Memory block (writable by APE only) */ 2184#define BGE_APE_SEG_SIG 0x4000 2185#define BGE_APE_FW_STATUS 0x400C 2186#define BGE_APE_FW_FEATURES 0x4010 2187#define BGE_APE_FW_BEHAVIOR 0x4014 2188#define BGE_APE_FW_VERSION 0x4018 2189#define BGE_APE_FW_HEARTBEAT_INTERVAL 0x4024 2190#define BGE_APE_FW_HEARTBEAT 0x4028 2191#define BGE_APE_FW_ERROR_FLAGS 0x4074 2192 2193#define BGE_APE_SEG_SIG_MAGIC 0x41504521 2194 2195#define BGE_APE_FW_STATUS_READY 0x00000100 2196 2197#define BGE_APE_FW_FEATURE_DASH 0x00000001 2198#define BGE_APE_FW_FEATURE_NCSI 0x00000002 2199 2200#define BGE_APE_FW_VERSION_MAJMSK 0xFF000000 2201#define BGE_APE_FW_VERSION_MAJSFT 24 2202#define BGE_APE_FW_VERSION_MINMSK 0x00FF0000 2203#define BGE_APE_FW_VERSION_MINSFT 16 2204#define BGE_APE_FW_VERSION_REVMSK 0x0000FF00 2205#define BGE_APE_FW_VERSION_REVSFT 8 2206#define BGE_APE_FW_VERSION_BLDMSK 0x000000FF 2207 2208/* Host Shared Memory block (writable by host only) */ 2209#define BGE_APE_HOST_SEG_SIG 0x4200 2210#define BGE_APE_HOST_SEG_LEN 0x4204 2211#define BGE_APE_HOST_INIT_COUNT 0x4208 2212#define BGE_APE_HOST_DRIVER_ID 0x420C 2213#define BGE_APE_HOST_BEHAVIOR 0x4210 2214#define BGE_APE_HOST_HEARTBEAT_INT_MS 0x4214 2215#define BGE_APE_HOST_HEARTBEAT_COUNT 0x4218 2216#define BGE_APE_HOST_DRVR_STATE 0x421C 2217#define BGE_APE_HOST_WOL_SPEED 0x4224 2218 2219#define BGE_APE_HOST_SEG_SIG_MAGIC 0x484F5354 2220 2221#define BGE_APE_HOST_SEG_LEN_MAGIC 0x00000020 2222 2223#define BGE_APE_HOST_DRIVER_ID_FBSD 0xF6000000 2224#define BGE_APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2225 (BGE_APE_HOST_DRIVER_ID_FBSD | \ 2226 ((maj) & 0xffd) << 16 | ((min) & 0xff) << 8) 2227 2228#define BGE_APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2229 2230#define BGE_APE_HOST_HEARTBEAT_INT_DISABLE 0 2231#define BGE_APE_HOST_HEARTBEAT_INT_5SEC 5000 2232 2233#define BGE_APE_HOST_DRVR_STATE_START 0x00000001 2234#define BGE_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2235#define BGE_APE_HOST_DRVR_STATE_WOL 0x00000003 2236#define BGE_APE_HOST_DRVR_STATE_SUSPEND 0x00000004 2237 2238#define BGE_APE_HOST_WOL_SPEED_AUTO 0x00008000 2239 2240#define BGE_APE_EVENT_STATUS 0x4300 2241 2242#define BGE_APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2243#define BGE_APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2244#define BGE_APE_EVENT_STATUS_STATE_START 0x00010000 2245#define BGE_APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2246#define BGE_APE_EVENT_STATUS_STATE_WOL 0x00030000 2247#define BGE_APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2248#define BGE_APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2249 2250#define BGE_APE_DEBUG_LOG 0x4E00 2251#define BGE_APE_DEBUG_LOG_LEN 0x0100 2252 2253#define BGE_APE_PER_LOCK_REQ 0x8400 2254#define BGE_APE_PER_LOCK_GRANT 0x8420 2255 2256#define BGE_APE_LOCK_PER_REQ_DRIVER0 0x00001000 2257#define BGE_APE_LOCK_PER_REQ_DRIVER1 0x00000002 2258#define BGE_APE_LOCK_PER_REQ_DRIVER2 0x00000004 2259#define BGE_APE_LOCK_PER_REQ_DRIVER3 0x00000008 2260 2261#define BGE_APE_PER_LOCK_GRANT_DRIVER0 0x00001000 2262#define BGE_APE_PER_LOCK_GRANT_DRIVER1 0x00000002 2263#define BGE_APE_PER_LOCK_GRANT_DRIVER2 0x00000004 2264#define BGE_APE_PER_LOCK_GRANT_DRIVER3 0x00000008 2265 2266/* APE Mutex Resources */ 2267#define BGE_APE_LOCK_PHY0 0 2268#define BGE_APE_LOCK_GRC 1 2269#define BGE_APE_LOCK_PHY1 2 2270#define BGE_APE_LOCK_PHY2 3 2271#define BGE_APE_LOCK_MEM 4 2272#define BGE_APE_LOCK_PHY3 5 2273#define BGE_APE_LOCK_GPIO 7 2274 2275#define BGE_MEMWIN_READ(pc, tag, x, val) \ 2276 do { \ 2277 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 2278 (0xFFFF8000 & x)); \ 2279 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0x7FFF)); \ 2280 } while(0) 2281 2282#define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 2283 do { \ 2284 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 2285 (0xFFFF8000 & x)); \ 2286 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0x7FFF), val); \ 2287 } while(0) 2288 2289/* 2290 * This magic number is written to the firmware mailbox at 0xb50 2291 * before a software reset is issued. After the internal firmware 2292 * has completed its initialization it will write the opposite of 2293 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 2294 * driver to synchronize with the firmware. 2295 */ 2296#define BGE_MAGIC_NUMBER 0x4B657654 2297 2298typedef struct { 2299 u_int32_t bge_addr_hi; 2300 u_int32_t bge_addr_lo; 2301} bge_hostaddr; 2302#define BGE_HOSTADDR(x,y) \ 2303 do { \ 2304 (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 2305 if (sizeof(bus_addr_t) == 8) \ 2306 (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 2307 else \ 2308 (x).bge_addr_hi = 0; \ 2309 } while(0) 2310 2311/* Ring control block structure */ 2312struct bge_rcb { 2313 bge_hostaddr bge_hostaddr; 2314 u_int32_t bge_maxlen_flags; 2315 u_int32_t bge_nicaddr; 2316}; 2317 2318#define RCB_WRITE_4(sc, rcb, offset, val) \ 2319 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 2320 rcb + offsetof(struct bge_rcb, offset), val) 2321 2322#define RCB_WRITE_2(sc, rcb, offset, val) \ 2323 bus_space_write_2(sc->bge_btag, sc->bge_bhandle, \ 2324 rcb + offsetof(struct bge_rcb, offset), val) 2325 2326#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 2327 2328#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2329#define BGE_RCB_FLAG_RING_DISABLED 0x0002 2330 2331struct bge_tx_bd { 2332 bge_hostaddr bge_addr; 2333#if BYTE_ORDER == LITTLE_ENDIAN 2334 u_int16_t bge_flags; 2335 u_int16_t bge_len; 2336 u_int16_t bge_vlan_tag; 2337 u_int16_t bge_rsvd; 2338#else 2339 u_int16_t bge_len; 2340 u_int16_t bge_flags; 2341 u_int16_t bge_rsvd; 2342 u_int16_t bge_vlan_tag; 2343#endif 2344}; 2345 2346#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2347#define BGE_TXBDFLAG_IP_CSUM 0x0002 2348#define BGE_TXBDFLAG_END 0x0004 2349#define BGE_TXBDFLAG_IP_FRAG 0x0008 2350#define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */ 2351#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2352#define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 /* 5717 */ 2353#define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */ 2354#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2355#define BGE_TXBDFLAG_COAL_NOW 0x0080 2356#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2357#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2358#define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 /* 5717 */ 2359#define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 /* 5717 */ 2360#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2361#define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 /* 5717 */ 2362#define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 /* 5717 */ 2363#define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 /* 5717 */ 2364#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2365#define BGE_TXBDFLAG_NO_CRC 0x8000 2366 2367#define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */ 2368/* Bits [1:0] of the MSS header length. */ 2369#define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */ 2370 2371#define BGE_NIC_TXRING_ADDR(ringno, size) \ 2372 BGE_SEND_RING_1_TO_4 + \ 2373 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2374 2375struct bge_rx_bd { 2376 bge_hostaddr bge_addr; 2377#if BYTE_ORDER == LITTLE_ENDIAN 2378 u_int16_t bge_len; 2379 u_int16_t bge_idx; 2380 u_int16_t bge_flags; 2381 u_int16_t bge_type; 2382 u_int16_t bge_tcp_udp_csum; 2383 u_int16_t bge_ip_csum; 2384 u_int16_t bge_vlan_tag; 2385 u_int16_t bge_error_flag; 2386#else 2387 u_int16_t bge_idx; 2388 u_int16_t bge_len; 2389 u_int16_t bge_type; 2390 u_int16_t bge_flags; 2391 u_int16_t bge_ip_csum; 2392 u_int16_t bge_tcp_udp_csum; 2393 u_int16_t bge_error_flag; 2394 u_int16_t bge_vlan_tag; 2395#endif 2396 u_int32_t bge_rsvd; 2397 u_int32_t bge_opaque; 2398}; 2399 2400struct bge_ext_rx_bd { 2401 bge_hostaddr bge_addr1; 2402 bge_hostaddr bge_addr2; 2403 bge_hostaddr bge_addr3; 2404#if BYTE_ORDER == LITTLE_ENDIAN 2405 u_int16_t bge_len2; 2406 u_int16_t bge_len1; 2407 u_int16_t bge_rsvd; 2408 u_int16_t bge_len3; 2409#else 2410 u_int16_t bge_len1; 2411 u_int16_t bge_len2; 2412 u_int16_t bge_len3; 2413 u_int16_t bge_rsvd; 2414#endif 2415 struct bge_rx_bd bge_bd; 2416}; 2417 2418#define BGE_RXBDFLAG_END 0x0004 2419#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2420#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2421#define BGE_RXBDFLAG_ERROR 0x0400 2422#define BGE_RXBDFLAG_MINI_RING 0x0800 2423#define BGE_RXBDFLAG_IP_CSUM 0x1000 2424#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2425#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2426#define BGE_RXBDFLAG_IPV6 0x8000 2427 2428#define BGE_RXERRFLAG_BAD_CRC 0x0001 2429#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2430#define BGE_RXERRFLAG_LINK_LOST 0x0004 2431#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2432#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2433#define BGE_RXERRFLAG_RUNT 0x0020 2434#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2435#define BGE_RXERRFLAG_GIANT 0x0080 2436#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ 2437 2438struct bge_sts_idx { 2439#if BYTE_ORDER == LITTLE_ENDIAN 2440 u_int16_t bge_rx_prod_idx; 2441 u_int16_t bge_tx_cons_idx; 2442#else 2443 u_int16_t bge_tx_cons_idx; 2444 u_int16_t bge_rx_prod_idx; 2445#endif 2446}; 2447 2448struct bge_status_block { 2449 u_int32_t bge_status; 2450 u_int32_t bge_status_tag; 2451#if BYTE_ORDER == LITTLE_ENDIAN 2452 u_int16_t bge_rx_jumbo_cons_idx; 2453 u_int16_t bge_rx_std_cons_idx; 2454 u_int16_t bge_rx_mini_cons_idx; 2455 u_int16_t bge_rsvd1; 2456#else 2457 u_int16_t bge_rx_std_cons_idx; 2458 u_int16_t bge_rx_jumbo_cons_idx; 2459 u_int16_t bge_rsvd1; 2460 u_int16_t bge_rx_mini_cons_idx; 2461#endif 2462 struct bge_sts_idx bge_idx[16]; 2463}; 2464 2465#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 2466#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 2467 2468#define BGE_STATFLAG_UPDATED 0x00000001 2469#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2470#define BGE_STATFLAG_ERROR 0x00000004 2471 2472/* 2473 * SysKonnect Subsystem IDs 2474 */ 2475#define SK_SUBSYSID_9D41 0x4441 2476 2477/* 2478 * Dell PCI vendor ID 2479 */ 2480#define DELL_VENDORID 0x1028 2481 2482/* 2483 * Offset of MAC address inside EEPROM. 2484 */ 2485#define BGE_EE_MAC_OFFSET 0x7C 2486#define BGE_EE_MAC_OFFSET_5906 0x10 2487#define BGE_EE_HWCFG_OFFSET 0xC8 2488 2489#define BGE_HWCFG_VOLTAGE 0x00000003 2490#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2491#define BGE_HWCFG_MEDIA 0x00000030 2492#define BGE_HWCFG_ASF 0x00000080 2493 2494#define BGE_VOLTAGE_1POINT3 0x00000000 2495#define BGE_VOLTAGE_1POINT8 0x00000001 2496 2497#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2498#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2499#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2500 2501#define BGE_MEDIA_UNSPEC 0x00000000 2502#define BGE_MEDIA_COPPER 0x00000010 2503#define BGE_MEDIA_FIBER 0x00000020 2504 2505#define BGE_TICKS_PER_SEC 1000000 2506 2507/* 2508 * Ring size constants. 2509 */ 2510#define BGE_EVENT_RING_CNT 256 2511#define BGE_CMD_RING_CNT 64 2512#define BGE_STD_RX_RING_CNT 512 2513#define BGE_JUMBO_RX_RING_CNT 256 2514#define BGE_MINI_RX_RING_CNT 1024 2515#define BGE_RETURN_RING_CNT 1024 2516 2517/* 5705 has smaller return ring size */ 2518#define BGE_RETURN_RING_CNT_5705 512 2519 2520/* 2521 * Possible TX ring sizes. 2522 */ 2523#define BGE_TX_RING_CNT_128 128 2524#define BGE_TX_RING_BASE_128 0x3800 2525 2526#define BGE_TX_RING_CNT_256 256 2527#define BGE_TX_RING_BASE_256 0x3000 2528 2529#define BGE_TX_RING_CNT_512 512 2530#define BGE_TX_RING_BASE_512 0x2000 2531 2532#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2533#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2534 2535/* 2536 * Tigon III statistics counters. 2537 */ 2538/* Statistics maintained MAC Receive block. */ 2539struct bge_rx_mac_stats { 2540 bge_hostaddr ifHCInOctets; 2541 bge_hostaddr Reserved1; 2542 bge_hostaddr etherStatsFragments; 2543 bge_hostaddr ifHCInUcastPkts; 2544 bge_hostaddr ifHCInMulticastPkts; 2545 bge_hostaddr ifHCInBroadcastPkts; 2546 bge_hostaddr dot3StatsFCSErrors; 2547 bge_hostaddr dot3StatsAlignmentErrors; 2548 bge_hostaddr xonPauseFramesReceived; 2549 bge_hostaddr xoffPauseFramesReceived; 2550 bge_hostaddr macControlFramesReceived; 2551 bge_hostaddr xoffStateEntered; 2552 bge_hostaddr dot3StatsFramesTooLong; 2553 bge_hostaddr etherStatsJabbers; 2554 bge_hostaddr etherStatsUndersizePkts; 2555 bge_hostaddr inRangeLengthError; 2556 bge_hostaddr outRangeLengthError; 2557 bge_hostaddr etherStatsPkts64Octets; 2558 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2559 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2560 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2561 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2562 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2563 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2564 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2565 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2566 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2567}; 2568 2569/* Statistics maintained MAC Transmit block. */ 2570struct bge_tx_mac_stats { 2571 bge_hostaddr ifHCOutOctets; 2572 bge_hostaddr Reserved2; 2573 bge_hostaddr etherStatsCollisions; 2574 bge_hostaddr outXonSent; 2575 bge_hostaddr outXoffSent; 2576 bge_hostaddr flowControlDone; 2577 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2578 bge_hostaddr dot3StatsSingleCollisionFrames; 2579 bge_hostaddr dot3StatsMultipleCollisionFrames; 2580 bge_hostaddr dot3StatsDeferredTransmissions; 2581 bge_hostaddr Reserved3; 2582 bge_hostaddr dot3StatsExcessiveCollisions; 2583 bge_hostaddr dot3StatsLateCollisions; 2584 bge_hostaddr dot3Collided2Times; 2585 bge_hostaddr dot3Collided3Times; 2586 bge_hostaddr dot3Collided4Times; 2587 bge_hostaddr dot3Collided5Times; 2588 bge_hostaddr dot3Collided6Times; 2589 bge_hostaddr dot3Collided7Times; 2590 bge_hostaddr dot3Collided8Times; 2591 bge_hostaddr dot3Collided9Times; 2592 bge_hostaddr dot3Collided10Times; 2593 bge_hostaddr dot3Collided11Times; 2594 bge_hostaddr dot3Collided12Times; 2595 bge_hostaddr dot3Collided13Times; 2596 bge_hostaddr dot3Collided14Times; 2597 bge_hostaddr dot3Collided15Times; 2598 bge_hostaddr ifHCOutUcastPkts; 2599 bge_hostaddr ifHCOutMulticastPkts; 2600 bge_hostaddr ifHCOutBroadcastPkts; 2601 bge_hostaddr dot3StatsCarrierSenseErrors; 2602 bge_hostaddr ifOutDiscards; 2603 bge_hostaddr ifOutErrors; 2604}; 2605 2606/* Stats counters access through registers */ 2607struct bge_mac_stats_regs { 2608 u_int32_t ifHCOutOctets; 2609 u_int32_t Reserved0; 2610 u_int32_t etherStatsCollisions; 2611 u_int32_t outXonSent; 2612 u_int32_t outXoffSent; 2613 u_int32_t Reserved1; 2614 u_int32_t dot3StatsInternalMacTransmitErrors; 2615 u_int32_t dot3StatsSingleCollisionFrames; 2616 u_int32_t dot3StatsMultipleCollisionFrames; 2617 u_int32_t dot3StatsDeferredTransmissions; 2618 u_int32_t Reserved2; 2619 u_int32_t dot3StatsExcessiveCollisions; 2620 u_int32_t dot3StatsLateCollisions; 2621 u_int32_t Reserved3[14]; 2622 u_int32_t ifHCOutUcastPkts; 2623 u_int32_t ifHCOutMulticastPkts; 2624 u_int32_t ifHCOutBroadcastPkts; 2625 u_int32_t Reserved4[2]; 2626 u_int32_t ifHCInOctets; 2627 u_int32_t Reserved5; 2628 u_int32_t etherStatsFragments; 2629 u_int32_t ifHCInUcastPkts; 2630 u_int32_t ifHCInMulticastPkts; 2631 u_int32_t ifHCInBroadcastPkts; 2632 u_int32_t dot3StatsFCSErrors; 2633 u_int32_t dot3StatsAlignmentErrors; 2634 u_int32_t xonPauseFramesReceived; 2635 u_int32_t xoffPauseFramesReceived; 2636 u_int32_t macControlFramesReceived; 2637 u_int32_t xoffStateEntered; 2638 u_int32_t dot3StatsFramesTooLong; 2639 u_int32_t etherStatsJabbers; 2640 u_int32_t etherStatsUndersizePkts; 2641}; 2642 2643struct bge_stats { 2644 u_int8_t Reserved0[256]; 2645 2646 /* Statistics maintained by Receive MAC. */ 2647 struct bge_rx_mac_stats rxstats; 2648 2649 bge_hostaddr Unused1[37]; 2650 2651 /* Statistics maintained by Transmit MAC. */ 2652 struct bge_tx_mac_stats txstats; 2653 2654 bge_hostaddr Unused2[31]; 2655 2656 /* Statistics maintained by Receive List Placement. */ 2657 bge_hostaddr COSIfHCInPkts[16]; 2658 bge_hostaddr COSFramesDroppedDueToFilters; 2659 bge_hostaddr nicDmaWriteQueueFull; 2660 bge_hostaddr nicDmaWriteHighPriQueueFull; 2661 bge_hostaddr nicNoMoreRxBDs; 2662 bge_hostaddr ifInDiscards; 2663 bge_hostaddr ifInErrors; 2664 bge_hostaddr nicRecvThresholdHit; 2665 2666 bge_hostaddr Unused3[9]; 2667 2668 /* Statistics maintained by Send Data Initiator. */ 2669 bge_hostaddr COSIfHCOutPkts[16]; 2670 bge_hostaddr nicDmaReadQueueFull; 2671 bge_hostaddr nicDmaReadHighPriQueueFull; 2672 bge_hostaddr nicSendDataCompQueueFull; 2673 2674 /* Statistics maintained by Host Coalescing. */ 2675 bge_hostaddr nicRingSetSendProdIndex; 2676 bge_hostaddr nicRingStatusUpdate; 2677 bge_hostaddr nicInterrupts; 2678 bge_hostaddr nicAvoidedInterrupts; 2679 bge_hostaddr nicSendThresholdHit; 2680 2681 u_int8_t Reserved4[320]; 2682}; 2683 2684/* 2685 * Tigon general information block. This resides in host memory 2686 * and contains the status counters, ring control blocks and 2687 * producer pointers. 2688 */ 2689 2690struct bge_gib { 2691 struct bge_stats bge_stats; 2692 struct bge_rcb bge_tx_rcb[16]; 2693 struct bge_rcb bge_std_rx_rcb; 2694 struct bge_rcb bge_jumbo_rx_rcb; 2695 struct bge_rcb bge_mini_rx_rcb; 2696 struct bge_rcb bge_return_rcb; 2697}; 2698 2699/* 2700 * NOTE! On the Alpha, we have an alignment constraint. 2701 * The first thing in the packet is a 14-byte Ethernet header. 2702 * This means that the packet is misaligned. To compensate, 2703 * we actually offset the data 2 bytes into the cluster. This 2704 * aligns the packet after the Ethernet header to a 32-bit 2705 * boundary. 2706 */ 2707 2708#define BGE_JUMBO_FRAMELEN 9022 2709#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 2710#define BGE_PAGE_SIZE PAGE_SIZE 2711 2712/* 2713 * Other utility macros. 2714 */ 2715#define BGE_INC(x, y) (x) = (x + 1) % y 2716 2717/* 2718 * Vital product data and structures. 2719 */ 2720#define BGE_VPD_FLAG 0x8000 2721 2722#define VPD_RES_ID 0x82 /* ID string */ 2723#define VPD_RES_READ 0x90 /* start of read only area */ 2724#define VPD_RES_WRITE 0x81 /* start of read/write area */ 2725#define VPD_RES_END 0x78 /* end tag */ 2726 2727/* 2728 * Register access macros. The Tigon always uses memory mapped register 2729 * accesses and all registers must be accessed with 32 bit operations. 2730 */ 2731 2732#define CSR_WRITE_4(sc, reg, val) \ 2733 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2734 2735#define CSR_READ_4(sc, reg) \ 2736 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2737 2738#define BGE_SETBIT(sc, reg, x) \ 2739 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2740#define BGE_CLRBIT(sc, reg, x) \ 2741 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2742 2743/* BAR2 APE register access macros. */ 2744#define APE_WRITE_4(sc, reg, val) \ 2745 bus_space_write_4(sc->bge_apetag, sc->bge_apehandle, reg, val) 2746 2747#define APE_READ_4(sc, reg) \ 2748 bus_space_read_4(sc->bge_apetag, sc->bge_apehandle, reg) 2749 2750#define APE_SETBIT(sc, reg, x) \ 2751 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x))) 2752#define APE_CLRBIT(sc, reg, x) \ 2753 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x))) 2754 2755#define PCI_SETBIT(pc, tag, reg, x) \ 2756 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 2757#define PCI_CLRBIT(pc, tag, reg, x) \ 2758 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 2759 2760/* 2761 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2762 * values are tuneable. They control the actual amount of buffers 2763 * allocated for the standard, mini and jumbo receive rings. 2764 */ 2765 2766#define BGE_SSLOTS 256 2767#define BGE_MSLOTS 256 2768#define BGE_JSLOTS 384 2769 2770#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2771#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2772 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2773 2774/* 2775 * Ring structures. Most of these reside in host memory and we tell 2776 * the NIC where they are via the ring control blocks. The exceptions 2777 * are the tx and command rings, which live in NIC memory and which 2778 * we access via the shared memory window. 2779 */ 2780struct bge_ring_data { 2781 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2782 struct bge_ext_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2783 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2784 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2785 struct bge_status_block bge_status_block; 2786 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2787 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2788 struct bge_gib bge_info; 2789}; 2790 2791#define BGE_RING_DMA_ADDR(sc, offset) \ 2792 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2793 offsetof(struct bge_ring_data, offset)) 2794 2795/* 2796 * Number of DMA segments in a TxCB. Note that this is carefully 2797 * chosen to make the total struct size an even power of two. It's 2798 * critical that no TxCB be split across a page boundary since 2799 * no attempt is made to allocate physically contiguous memory. 2800 * 2801 */ 2802#ifdef __LP64__ 2803#define BGE_NTXSEG 30 2804#else 2805#define BGE_NTXSEG 31 2806#endif 2807 2808#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2809 2810#define BGE_STATS_SZ sizeof (struct bge_stats) 2811 2812/* 2813 * Mbuf pointers. We need these to keep track of the virtual addresses 2814 * of our mbuf chains since we can only convert from physical to virtual, 2815 * not the other way around. 2816 */ 2817struct bge_chain_data { 2818 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2819 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2820 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2821 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2822 bus_dmamap_t bge_tx_map[BGE_TX_RING_CNT]; 2823 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2824 bus_dmamap_t bge_rx_jumbo_map[BGE_JUMBO_RX_RING_CNT]; 2825}; 2826 2827struct bge_type { 2828 u_int16_t bge_vid; 2829 u_int16_t bge_did; 2830 char *bge_name; 2831}; 2832 2833#define BGE_TIMEOUT 100000 2834#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2835 2836#define ASF_ENABLE 1 2837#define ASF_NEW_HANDSHAKE 2 2838#define ASF_STACKUP 4 2839 2840struct bge_softc { 2841 struct device bge_dev; 2842 struct arpcom arpcom; /* interface info */ 2843 bus_space_handle_t bge_bhandle; 2844 bus_space_tag_t bge_btag; 2845 bus_size_t bge_bsize; 2846 bus_space_handle_t bge_apehandle; 2847 bus_space_tag_t bge_apetag; 2848 bus_size_t bge_apesize; 2849 void *bge_intrhand; 2850 struct pci_attach_args bge_pa; 2851 struct mii_data bge_mii; 2852 struct ifmedia bge_ifmedia; /* media info */ 2853 u_int32_t bge_expcap; 2854 u_int32_t bge_msicap; 2855 u_int32_t bge_mps; 2856 u_int32_t bge_expmrq; 2857 u_int32_t bge_lasttag; 2858 u_int32_t bge_flags; 2859#define BGE_TXRING_VALID 0x00000001 2860#define BGE_RXRING_VALID 0x00000002 2861#define BGE_JUMBO_RXRING_VALID 0x00000004 2862#define BGE_RX_ALIGNBUG 0x00000008 2863#define BGE_PCIX 0x00000010 2864#define BGE_PCIE 0x00000020 2865#define BGE_ASF_MODE 0x00000040 2866#define BGE_NO_EEPROM 0x00000080 2867#define BGE_JUMBO_CAPABLE 0x00000100 2868#define BGE_FIBER_TBI 0x00000200 2869#define BGE_FIBER_MII 0x00000400 2870#define BGE_IS_5788 0x00000800 2871#define BGE_5705_PLUS 0x00001000 2872#define BGE_575X_PLUS 0x00002000 2873#define BGE_5755_PLUS 0x00004000 2874#define BGE_5714_FAMILY 0x00008000 2875#define BGE_5700_FAMILY 0x00010000 2876#define BGE_5717_PLUS 0x00020000 2877#define BGE_57765_PLUS 0x00040000 2878#define BGE_APE 0x00080000 2879#define BGE_CPMU_PRESENT 0x00100000 2880#define BGE_TAGGED_STATUS 0x00200000 2881#define BGE_MSI 0x00400000 2882#define BGE_RDMA_BUG 0x00800000 2883#define BGE_JUMBO_RING 0x01000000 2884#define BGE_JUMBO_STD 0x02000000 2885#define BGE_JUMBO_FRAME 0x04000000 2886 2887 u_int32_t bge_phy_flags; 2888#define BGE_PHY_NO_3LED 0x00000001 2889#define BGE_PHY_10_100_ONLY 0x00000002 2890#define BGE_PHY_CRC_BUG 0x00000004 2891#define BGE_PHY_ADC_BUG 0x00000008 2892#define BGE_PHY_5704_A0_BUG 0x00008010 2893#define BGE_PHY_JITTER_BUG 0x00000020 2894#define BGE_PHY_BER_BUG 0x00000040 2895#define BGE_PHY_ADJUST_TRIM 0x00000080 2896#define BGE_PHY_NO_WIRESPEED 0x00000100 2897 2898 bus_dma_tag_t bge_dmatag; 2899 u_int32_t bge_mfw_flags; /* Management F/W flags */ 2900#define BGE_MFW_ON_RXCPU 0x00000001 2901#define BGE_MFW_ON_APE 0x00000002 2902#define BGE_MFW_TYPE_NCSI 0x00000004 2903#define BGE_MFW_TYPE_DASH 0x00000008 2904 int bge_phy_ape_lock; 2905 int bge_phy_addr; 2906 u_int32_t bge_chipid; 2907 struct bge_ring_data *bge_rdata; /* rings */ 2908 struct bge_chain_data bge_cdata; /* mbufs */ 2909 bus_dmamap_t bge_ring_map; 2910 bus_dma_segment_t bge_ring_seg; 2911 int bge_ring_nseg; 2912 u_int16_t bge_tx_saved_considx; 2913 u_int16_t bge_rx_saved_considx; 2914 u_int16_t bge_ev_saved_considx; 2915 u_int16_t bge_return_ring_cnt; 2916 u_int32_t bge_tx_prodidx; 2917 struct if_rxring bge_std_ring; 2918 u_int16_t bge_std; /* current std ring head */ 2919 int bge_rx_std_len; 2920 struct if_rxring bge_jumbo_ring; 2921 u_int16_t bge_jumbo; /* current jumo ring head */ 2922 u_int32_t bge_stat_ticks; 2923 u_int32_t bge_rx_coal_ticks; 2924 u_int32_t bge_tx_coal_ticks; 2925 u_int32_t bge_rx_max_coal_bds; 2926 u_int32_t bge_tx_max_coal_bds; 2927 u_int32_t bge_tx_buf_ratio; 2928 u_int32_t bge_sts; 2929#define BGE_STS_LINK 0x00000001 /* MAC link status */ 2930#define BGE_STS_LINK_EVT 0x00000002 /* pending link event */ 2931#define BGE_STS_AUTOPOLL 0x00000004 /* PHY auto-polling */ 2932#define BGE_STS_BIT(sc, x) ((sc)->bge_sts & (x)) 2933#define BGE_STS_SETBIT(sc, x) ((sc)->bge_sts |= (x)) 2934#define BGE_STS_CLRBIT(sc, x) ((sc)->bge_sts &= ~(x)) 2935 uint64_t bge_flowflags; 2936 int bge_txcnt; 2937 struct timeout bge_timeout; 2938 struct timeout bge_rxtimeout; 2939 struct timeout bge_rxtimeout_jumbo; 2940 u_int32_t bge_rx_discards; 2941 u_int32_t bge_tx_discards; 2942 u_int32_t bge_rx_inerrors; 2943 u_int32_t bge_rx_overruns; 2944 u_int32_t bge_tx_collisions; 2945 bus_dmamap_t bge_txdma[BGE_TX_RING_CNT]; 2946}; 2947