if_bgereg.h revision 1.130
1/* $OpenBSD: if_bgereg.h,v 1.130 2015/11/29 20:19:35 kettenis Exp $ */ 2 3/* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bgereg.h,v 1.11 2002/11/14 23:54:50 sam Exp $ 36 */ 37 38/* 39 * BCM570x memory map. The internal memory layout varies somewhat 40 * depending on whether or not we have external SSRAM attached. 41 * The BCM5700 can have up to 16MB of external memory. The BCM5701 42 * is apparently not designed to use external SSRAM. The mappings 43 * up to the first 4 send rings are the same for both internal and 44 * external memory configurations. Note that mini RX ring space is 45 * only available with external SSRAM configurations, which means 46 * the mini RX ring is not supported on the BCM5701. 47 * 48 * The NIC's memory can be accessed by the host in one of 3 ways: 49 * 50 * 1) Indirect register access. The REG_BASEADDR and REG_DATA 51 * registers in PCI config space can be used to read any 32-bit 52 * address within the NIC's memory. 53 * 54 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 55 * space can be used in conjunction with the memory window in the 56 * device register space at offset 0x8000 to read any 32K chunk 57 * of NIC memory. 58 * 59 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 60 * set, the device I/O mapping consumes 32MB of host address space, 61 * allowing all of the registers and internal NIC memory to be 62 * accessed directly. NIC memory addresses are offset by 0x01000000. 63 * Flat mode consumes so much host address space that it is not 64 * recommended. 65 */ 66#define BGE_PAGE_ZERO 0x00000000 67#define BGE_PAGE_ZERO_END 0x000000FF 68#define BGE_SEND_RING_RCB 0x00000100 69#define BGE_SEND_RING_RCB_END 0x000001FF 70#define BGE_RX_RETURN_RING_RCB 0x00000200 71#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 72#define BGE_STATS_BLOCK 0x00000300 73#define BGE_STATS_BLOCK_END 0x00000AFF 74#define BGE_STATUS_BLOCK 0x00000B00 75#define BGE_STATUS_BLOCK_END 0x00000B4F 76#define BGE_SOFTWARE_GENCOMM 0x00000B50 77#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 78#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 79#define BGE_SOFTWARE_GENCOMM_VER 0x00000B5C 80#define BGE_VER_SHIFT 16 81#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 82#define BGE_FW_PAUSE 0x00000002 83#define BGE_SOFTWARE_GENCOMM_NICCFG2 0x00000D38 84#define BGE_SOFTWARE_GENCOMM_NICCFG3 0x00000D3C 85#define BGE_SOFTWARE_GENCOMM_NICCFG4 0x00000D60 86#define BGE_NICCFG4_GMII_MODE 0x00000002 87#define BGE_NICCFG4_RGMII_STD_IBND_DISABLE 0x00000004 88#define BGE_NICCFG4_RGMII_EXT_IBND_RX_EN 0x00000008 89#define BGE_NICCFG4_RGMII_EXT_IBND_TX_EN 0x00000010 90#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 91#define BGE_UNMAPPED 0x00001000 92#define BGE_UNMAPPED_END 0x00001FFF 93#define BGE_DMA_DESCRIPTORS 0x00002000 94#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 95#define BGE_SEND_RING_5717 0x00004000 96#define BGE_SEND_RING_1_TO_4 0x00004000 97#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 98 99/* Mappings for internal memory configuration */ 100#define BGE_STD_RX_RINGS 0x00006000 101#define BGE_STD_RX_RINGS_END 0x00006FFF 102#define BGE_JUMBO_RX_RINGS 0x00007000 103#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 104#define BGE_BUFFPOOL_1 0x00008000 105#define BGE_BUFFPOOL_1_END 0x0000FFFF 106#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 107#define BGE_BUFFPOOL_2_END 0x00017FFF 108#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 109#define BGE_BUFFPOOL_3_END 0x0001FFFF 110#define BGE_STD_RX_RINGS_5717 0x00040000 111#define BGE_JUMBO_RX_RINGS_5717 0x00044400 112 113/* Mappings for external SSRAM configurations */ 114#define BGE_SEND_RING_5_TO_6 0x00006000 115#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 116#define BGE_SEND_RING_7_TO_8 0x00007000 117#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 118#define BGE_SEND_RING_9_TO_16 0x00008000 119#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 120#define BGE_EXT_STD_RX_RINGS 0x0000C000 121#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 122#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 123#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 124#define BGE_MINI_RX_RINGS 0x0000E000 125#define BGE_MINI_RX_RINGS_END 0x0000FFFF 126#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 127#define BGE_AVAIL_REGION1_END 0x00017FFF 128#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 129#define BGE_AVAIL_REGION2_END 0x0001FFFF 130#define BGE_EXT_SSRAM 0x00020000 131#define BGE_EXT_SSRAM_END 0x000FFFFF 132 133 134/* 135 * BCM570x register offsets. These are memory mapped registers 136 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 137 * Each register must be accessed using 32 bit operations. 138 * 139 * All registers are accessed through a 32K shared memory block. 140 * The first group of registers are actually copies of the PCI 141 * configuration space registers. 142 */ 143 144/* 145 * PCI registers defined in the PCI 2.2 spec. 146 */ 147#define BGE_PCI_VID 0x00 148#define BGE_PCI_DID 0x02 149#define BGE_PCI_CMD 0x04 150#define BGE_PCI_STS 0x06 151#define BGE_PCI_REV 0x08 152#define BGE_PCI_CLASS 0x09 153#define BGE_PCI_CACHESZ 0x0C 154#define BGE_PCI_LATTIMER 0x0D 155#define BGE_PCI_HDRTYPE 0x0E 156#define BGE_PCI_BIST 0x0F 157#define BGE_PCI_BAR0 0x10 158#define BGE_PCI_BAR1 0x14 159#define BGE_PCI_BAR2 0x18 160#define BGE_PCI_SUBSYS 0x2C 161#define BGE_PCI_SUBVID 0x2E 162#define BGE_PCI_ROMBASE 0x30 163#define BGE_PCI_CAPPTR 0x34 164#define BGE_PCI_INTLINE 0x3C 165#define BGE_PCI_INTPIN 0x3D 166#define BGE_PCI_MINGNT 0x3E 167#define BGE_PCI_MAXLAT 0x3F 168#define BGE_PCI_PCIXCAP 0x40 169#define BGE_PCI_NEXTPTR_PM 0x41 170#define BGE_PCI_PCIX_CMD 0x42 171#define BGE_PCI_PCIX_STS 0x44 172#define BGE_PCI_PWRMGMT_CAPID 0x48 173#define BGE_PCI_NEXTPTR_VPD 0x49 174#define BGE_PCI_PWRMGMT_CAPS 0x4A 175#define BGE_PCI_PWRMGMT_CMD 0x4C 176#define BGE_PCI_PWRMGMT_STS 0x4D 177#define BGE_PCI_PWRMGMT_DATA 0x4F 178#define BGE_PCI_VPD_CAPID 0x50 179#define BGE_PCI_NEXTPTR_MSI 0x51 180#define BGE_PCI_VPD_ADDR 0x52 181#define BGE_PCI_VPD_DATA 0x54 182#define BGE_PCI_MSI_CAPID 0x58 183#define BGE_PCI_NEXTPTR_NONE 0x59 184#define BGE_PCI_MSI_CTL 0x5A 185#define BGE_PCI_MSI_ADDR_HI 0x5C 186#define BGE_PCI_MSI_ADDR_LO 0x60 187#define BGE_PCI_MSI_DATA 0x64 188 189/* PCI MSI. ??? */ 190#define BGE_PCIE_CAPID_REG 0xD0 191#define BGE_PCIE_CAPID 0x10 192 193/* 194 * PCI registers specific to the BCM570x family. 195 */ 196#define BGE_PCI_MISC_CTL 0x68 197#define BGE_PCI_DMA_RW_CTL 0x6C 198#define BGE_PCI_PCISTATE 0x70 199#define BGE_PCI_CLKCTL 0x74 200#define BGE_PCI_REG_BASEADDR 0x78 201#define BGE_PCI_MEMWIN_BASEADDR 0x7C 202#define BGE_PCI_REG_DATA 0x80 203#define BGE_PCI_MEMWIN_DATA 0x84 204#define BGE_PCI_MODECTL 0x88 205#define BGE_PCI_MISC_CFG 0x8C 206#define BGE_PCI_MISC_LOCALCTL 0x90 207#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 208#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 209#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 210#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 211#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 212#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 213#define BGE_PCI_ISR_MBX_HI 0xB0 214#define BGE_PCI_ISR_MBX_LO 0xB4 215#define BGE_PCI_PRODID_ASICREV 0xBC 216#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 217#define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 218 219/* PCI Misc. Host control register */ 220#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 221#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 222#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 223#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 224#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 225#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 226#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 227#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 228#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 229#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 230#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 231 232#if BYTE_ORDER == LITTLE_ENDIAN 233#define BGE_DMA_SWAP_OPTIONS \ 234 BGE_MODECTL_WORDSWAP_NONFRAME| \ 235 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 236#else 237#define BGE_DMA_SWAP_OPTIONS \ 238 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 239 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 240#endif 241 242#define BGE_INIT \ 243 (BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 244 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 245 246#define BGE_CHIPID_BCM5700_A0 0x7000 247#define BGE_CHIPID_BCM5700_A1 0x7001 248#define BGE_CHIPID_BCM5700_B0 0x7100 249#define BGE_CHIPID_BCM5700_B1 0x7101 250#define BGE_CHIPID_BCM5700_B2 0x7102 251#define BGE_CHIPID_BCM5700_B3 0x7103 252#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 253#define BGE_CHIPID_BCM5700_C0 0x7200 254#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 255#define BGE_CHIPID_BCM5701_B0 0x0100 256#define BGE_CHIPID_BCM5701_B2 0x0102 257#define BGE_CHIPID_BCM5701_B5 0x0105 258#define BGE_CHIPID_BCM5703_A0 0x1000 259#define BGE_CHIPID_BCM5703_A1 0x1001 260#define BGE_CHIPID_BCM5703_A2 0x1002 261#define BGE_CHIPID_BCM5703_A3 0x1003 262#define BGE_CHIPID_BCM5703_B0 0x1100 263#define BGE_CHIPID_BCM5704_A0 0x2000 264#define BGE_CHIPID_BCM5704_A1 0x2001 265#define BGE_CHIPID_BCM5704_A2 0x2002 266#define BGE_CHIPID_BCM5704_A3 0x2003 267#define BGE_CHIPID_BCM5704_B0 0x2100 268#define BGE_CHIPID_BCM5705_A0 0x3000 269#define BGE_CHIPID_BCM5705_A1 0x3001 270#define BGE_CHIPID_BCM5705_A2 0x3002 271#define BGE_CHIPID_BCM5705_A3 0x3003 272#define BGE_CHIPID_BCM5750_A0 0x4000 273#define BGE_CHIPID_BCM5750_A1 0x4001 274#define BGE_CHIPID_BCM5750_A3 0x4003 275#define BGE_CHIPID_BCM5750_B0 0x4010 276#define BGE_CHIPID_BCM5750_B1 0x4101 277#define BGE_CHIPID_BCM5750_C0 0x4200 278#define BGE_CHIPID_BCM5750_C1 0x4201 279#define BGE_CHIPID_BCM5750_C2 0x4202 280#define BGE_CHIPID_BCM5714_A0 0x5000 281#define BGE_CHIPID_BCM5752_A0 0x6000 282#define BGE_CHIPID_BCM5752_A1 0x6001 283#define BGE_CHIPID_BCM5752_A2 0x6002 284#define BGE_CHIPID_BCM5714_B0 0x8000 285#define BGE_CHIPID_BCM5714_B3 0x8003 286#define BGE_CHIPID_BCM5715_A0 0x9000 287#define BGE_CHIPID_BCM5715_A1 0x9001 288#define BGE_CHIPID_BCM5715_A3 0x9003 289#define BGE_CHIPID_BCM5755_A0 0xa000 290#define BGE_CHIPID_BCM5755_A1 0xa001 291#define BGE_CHIPID_BCM5755_A2 0xa002 292#define BGE_CHIPID_BCM5755_C0 0xa200 293#define BGE_CHIPID_BCM5787_A0 0xb000 294#define BGE_CHIPID_BCM5787_A1 0xb001 295#define BGE_CHIPID_BCM5787_A2 0xb002 296#define BGE_CHIPID_BCM5761_A0 0x5761000 297#define BGE_CHIPID_BCM5761_A1 0x5761100 298#define BGE_CHIPID_BCM5784_A0 0x5784000 299#define BGE_CHIPID_BCM5784_A1 0x5784100 300#define BGE_CHIPID_BCM5906_A0 0xc000 301#define BGE_CHIPID_BCM5906_A1 0xc001 302#define BGE_CHIPID_BCM5906_A2 0xc002 303#define BGE_CHIPID_BCM57780_A0 0x57780000 304#define BGE_CHIPID_BCM57780_A1 0x57780001 305#define BGE_CHIPID_BCM5717_A0 0x05717000 306#define BGE_CHIPID_BCM5717_B0 0x05717100 307#define BGE_CHIPID_BCM5719_A0 0x05719000 308#define BGE_CHIPID_BCM5720_A0 0x05720000 309#define BGE_CHIPID_BCM5762_A0 0x05762000 310#define BGE_CHIPID_BCM57765_A0 0x57785000 311#define BGE_CHIPID_BCM57765_B0 0x57785100 312 313/* shorthand one */ 314#define BGE_ASICREV(x) ((x) >> 12) 315#define BGE_ASICREV_BCM5700 0x07 316#define BGE_ASICREV_BCM5701 0x00 317#define BGE_ASICREV_BCM5703 0x01 318#define BGE_ASICREV_BCM5704 0x02 319#define BGE_ASICREV_BCM5705 0x03 320#define BGE_ASICREV_BCM5750 0x04 321#define BGE_ASICREV_BCM5714_A0 0x05 /* 5714, 5715 */ 322#define BGE_ASICREV_BCM5752 0x06 323#define BGE_ASICREV_BCM5780 0x08 324#define BGE_ASICREV_BCM5714 0x09 /* 5714, 5715 */ 325#define BGE_ASICREV_BCM5755 0x0a 326#define BGE_ASICREV_BCM5787 0x0b 327#define BGE_ASICREV_BCM5906 0x0c 328#define BGE_ASICREV_USE_PRODID_REG 0x0f 329#define BGE_ASICREV_BCM5717 0x5717 330#define BGE_ASICREV_BCM5719 0x5719 331#define BGE_ASICREV_BCM5720 0x5720 332#define BGE_ASICREV_BCM5761 0x5761 333#define BGE_ASICREV_BCM5762 0x5762 334#define BGE_ASICREV_BCM5784 0x5784 335#define BGE_ASICREV_BCM5785 0x5785 336#define BGE_ASICREV_BCM57765 0x57785 337#define BGE_ASICREV_BCM57766 0x57766 338#define BGE_ASICREV_BCM57780 0x57780 339 340/* chip revisions */ 341#define BGE_CHIPREV(x) ((x) >> 8) 342#define BGE_CHIPREV_5700_AX 0x70 343#define BGE_CHIPREV_5700_BX 0x71 344#define BGE_CHIPREV_5700_CX 0x72 345#define BGE_CHIPREV_5701_AX 0x00 346#define BGE_CHIPREV_5703_AX 0x10 347#define BGE_CHIPREV_5704_AX 0x20 348#define BGE_CHIPREV_5704_BX 0x21 349#define BGE_CHIPREV_5750_AX 0x40 350#define BGE_CHIPREV_5750_BX 0x41 351#define BGE_CHIPREV_5717_AX 0x57170 352#define BGE_CHIPREV_5717_BX 0x57171 353#define BGE_CHIPREV_5761_AX 0x57611 354#define BGE_CHIPREV_57765_AX 0x577850 355#define BGE_CHIPREV_5784_AX 0x57841 356 357/* PCI DMA Read/Write Control register */ 358#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 359#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 360#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 361#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 362#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 363#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 364#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 365#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 366#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 367#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 368#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 369#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 370#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 371 372#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 373#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 374#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 375#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 376 377#define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 378#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 379 380#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 381#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 382#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 383#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 384#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 385#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 386#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 387#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 388 389#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 390#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 391#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 392#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 393#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 394#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 395#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 396#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 397 398/* 399 * PCI state register -- note, this register is read only 400 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 401 * register is set. 402 */ 403#define BGE_PCISTATE_FORCE_RESET 0x00000001 404#define BGE_PCISTATE_INTR_NOT_ACTIVE 0x00000002 405#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 406#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 407#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 408#define BGE_PCISTATE_ROM_ENABLE 0x00000020 409#define BGE_PCISTATE_ROM_RETRY_ENABLE 0x00000040 410#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 411#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 412#define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000 413#define BGE_PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 414#define BGE_PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 415#define BGE_PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 416 417/* 418 * The following bits in PCI state register are reserved. 419 * If we check that the register values reverts on reset, 420 * do not check these bits. On some 5704C (rev A3) and some 421 * Altima chips, these bits do not revert until much later 422 * in the bge driver's bge_reset() chip-reset state machine. 423 */ 424#define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 425 426/* 427 * PCI Clock Control register -- note, this register is read only 428 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 429 * register is set. 430 */ 431#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 432#define BGE_PCICLOCKCTL_M66EN 0x00000080 433#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 434#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 435#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 436#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 437#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 438#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 439#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 440#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 441 442/* 443 * High priority mailbox registers 444 * Each mailbox is 64-bits wide, though we only use the 445 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 446 * first. The NIC will load the mailbox after the lower 32 bit word 447 * has been updated. 448 */ 449#define BGE_MBX_IRQ0_HI 0x0200 450#define BGE_MBX_IRQ0_LO 0x0204 451#define BGE_MBX_IRQ1_HI 0x0208 452#define BGE_MBX_IRQ1_LO 0x020C 453#define BGE_MBX_IRQ2_HI 0x0210 454#define BGE_MBX_IRQ2_LO 0x0214 455#define BGE_MBX_IRQ3_HI 0x0218 456#define BGE_MBX_IRQ3_LO 0x021C 457#define BGE_MBX_GEN0_HI 0x0220 458#define BGE_MBX_GEN0_LO 0x0224 459#define BGE_MBX_GEN1_HI 0x0228 460#define BGE_MBX_GEN1_LO 0x022C 461#define BGE_MBX_GEN2_HI 0x0230 462#define BGE_MBX_GEN2_LO 0x0234 463#define BGE_MBX_GEN3_HI 0x0228 464#define BGE_MBX_GEN3_LO 0x022C 465#define BGE_MBX_GEN4_HI 0x0240 466#define BGE_MBX_GEN4_LO 0x0244 467#define BGE_MBX_GEN5_HI 0x0248 468#define BGE_MBX_GEN5_LO 0x024C 469#define BGE_MBX_GEN6_HI 0x0250 470#define BGE_MBX_GEN6_LO 0x0254 471#define BGE_MBX_GEN7_HI 0x0258 472#define BGE_MBX_GEN7_LO 0x025C 473#define BGE_MBX_RELOAD_STATS_HI 0x0260 474#define BGE_MBX_RELOAD_STATS_LO 0x0264 475#define BGE_MBX_RX_STD_PROD_HI 0x0268 476#define BGE_MBX_RX_STD_PROD_LO 0x026C 477#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 478#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 479#define BGE_MBX_RX_MINI_PROD_HI 0x0278 480#define BGE_MBX_RX_MINI_PROD_LO 0x027C 481#define BGE_MBX_RX_CONS0_HI 0x0280 482#define BGE_MBX_RX_CONS0_LO 0x0284 483#define BGE_MBX_RX_CONS1_HI 0x0288 484#define BGE_MBX_RX_CONS1_LO 0x028C 485#define BGE_MBX_RX_CONS2_HI 0x0290 486#define BGE_MBX_RX_CONS2_LO 0x0294 487#define BGE_MBX_RX_CONS3_HI 0x0298 488#define BGE_MBX_RX_CONS3_LO 0x029C 489#define BGE_MBX_RX_CONS4_HI 0x02A0 490#define BGE_MBX_RX_CONS4_LO 0x02A4 491#define BGE_MBX_RX_CONS5_HI 0x02A8 492#define BGE_MBX_RX_CONS5_LO 0x02AC 493#define BGE_MBX_RX_CONS6_HI 0x02B0 494#define BGE_MBX_RX_CONS6_LO 0x02B4 495#define BGE_MBX_RX_CONS7_HI 0x02B8 496#define BGE_MBX_RX_CONS7_LO 0x02BC 497#define BGE_MBX_RX_CONS8_HI 0x02C0 498#define BGE_MBX_RX_CONS8_LO 0x02C4 499#define BGE_MBX_RX_CONS9_HI 0x02C8 500#define BGE_MBX_RX_CONS9_LO 0x02CC 501#define BGE_MBX_RX_CONS10_HI 0x02D0 502#define BGE_MBX_RX_CONS10_LO 0x02D4 503#define BGE_MBX_RX_CONS11_HI 0x02D8 504#define BGE_MBX_RX_CONS11_LO 0x02DC 505#define BGE_MBX_RX_CONS12_HI 0x02E0 506#define BGE_MBX_RX_CONS12_LO 0x02E4 507#define BGE_MBX_RX_CONS13_HI 0x02E8 508#define BGE_MBX_RX_CONS13_LO 0x02EC 509#define BGE_MBX_RX_CONS14_HI 0x02F0 510#define BGE_MBX_RX_CONS14_LO 0x02F4 511#define BGE_MBX_RX_CONS15_HI 0x02F8 512#define BGE_MBX_RX_CONS15_LO 0x02FC 513#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 514#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 515#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 516#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 517#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 518#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 519#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 520#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 521#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 522#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 523#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 524#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 525#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 526#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 527#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 528#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 529#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 530#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 531#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 532#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 533#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 534#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 535#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 536#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 537#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 538#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 539#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 540#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 541#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 542#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 543#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 544#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 545#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 546#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 547#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 548#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 549#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 550#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 551#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 552#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 553#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 554#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 555#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 556#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 557#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 558#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 559#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 560#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 561#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 562#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 563#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 564#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 565#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 566#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 567#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 568#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 569#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 570#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 571#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 572#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 573#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 574#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 575#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 576#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 577 578#define BGE_TX_RINGS_MAX 4 579#define BGE_TX_RINGS_EXTSSRAM_MAX 16 580#define BGE_RX_RINGS_MAX 16 581 582/* Ethernet MAC control registers */ 583#define BGE_MAC_MODE 0x0400 584#define BGE_MAC_STS 0x0404 585#define BGE_MAC_EVT_ENB 0x0408 586#define BGE_MAC_LED_CTL 0x040C 587#define BGE_MAC_ADDR1_LO 0x0410 588#define BGE_MAC_ADDR1_HI 0x0414 589#define BGE_MAC_ADDR2_LO 0x0418 590#define BGE_MAC_ADDR2_HI 0x041C 591#define BGE_MAC_ADDR3_LO 0x0420 592#define BGE_MAC_ADDR3_HI 0x0424 593#define BGE_MAC_ADDR4_LO 0x0428 594#define BGE_MAC_ADDR4_HI 0x042C 595#define BGE_WOL_PATPTR 0x0430 596#define BGE_WOL_PATCFG 0x0434 597#define BGE_TX_RANDOM_BACKOFF 0x0438 598#define BGE_RX_MTU 0x043C 599#define BGE_GBIT_PCS_TEST 0x0440 600#define BGE_TX_TBI_AUTONEG 0x0444 601#define BGE_RX_TBI_AUTONEG 0x0448 602#define BGE_MI_COMM 0x044C 603#define BGE_MI_STS 0x0450 604#define BGE_MI_MODE 0x0454 605#define BGE_AUTOPOLL_STS 0x0458 606#define BGE_TX_MODE 0x045C 607#define BGE_TX_STS 0x0460 608#define BGE_TX_LENGTHS 0x0464 609#define BGE_RX_MODE 0x0468 610#define BGE_RX_STS 0x046C 611#define BGE_MAR0 0x0470 612#define BGE_MAR1 0x0474 613#define BGE_MAR2 0x0478 614#define BGE_MAR3 0x047C 615#define BGE_RX_BD_RULES_CTL0 0x0480 616#define BGE_RX_BD_RULES_MASKVAL0 0x0484 617#define BGE_RX_BD_RULES_CTL1 0x0488 618#define BGE_RX_BD_RULES_MASKVAL1 0x048C 619#define BGE_RX_BD_RULES_CTL2 0x0490 620#define BGE_RX_BD_RULES_MASKVAL2 0x0494 621#define BGE_RX_BD_RULES_CTL3 0x0498 622#define BGE_RX_BD_RULES_MASKVAL3 0x049C 623#define BGE_RX_BD_RULES_CTL4 0x04A0 624#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 625#define BGE_RX_BD_RULES_CTL5 0x04A8 626#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 627#define BGE_RX_BD_RULES_CTL6 0x04B0 628#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 629#define BGE_RX_BD_RULES_CTL7 0x04B8 630#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 631#define BGE_RX_BD_RULES_CTL8 0x04C0 632#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 633#define BGE_RX_BD_RULES_CTL9 0x04C8 634#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 635#define BGE_RX_BD_RULES_CTL10 0x04D0 636#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 637#define BGE_RX_BD_RULES_CTL11 0x04D8 638#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 639#define BGE_RX_BD_RULES_CTL12 0x04E0 640#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 641#define BGE_RX_BD_RULES_CTL13 0x04E8 642#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 643#define BGE_RX_BD_RULES_CTL14 0x04F0 644#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 645#define BGE_RX_BD_RULES_CTL15 0x04F8 646#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 647#define BGE_RX_RULES_CFG 0x0500 648#define BGE_MAX_RX_FRAME_LOWAT 0x0504 649#define BGE_SERDES_CFG 0x0590 650#define BGE_SERDES_STS 0x0594 651#define BGE_PHYCFG1 0x05A0 652#define BGE_PHYCFG2 0x05A4 653#define BGE_EXT_RGMII_MODE 0x05A8 654#define BGE_SGDIG_CFG 0x05B0 655#define BGE_SGDIG_STS 0x05B4 656#define BGE_MAC_STATS 0x0800 657 658/* Ethernet MAC Mode register */ 659#define BGE_MACMODE_RESET 0x00000001 660#define BGE_MACMODE_HALF_DUPLEX 0x00000002 661#define BGE_MACMODE_PORTMODE 0x0000000C 662#define BGE_MACMODE_LOOPBACK 0x00000010 663#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 664#define BGE_MACMODE_TX_BURST_ENB 0x00000100 665#define BGE_MACMODE_MAX_DEFER 0x00000200 666#define BGE_MACMODE_LINK_POLARITY 0x00000400 667#define BGE_MACMODE_RX_STATS_ENB 0x00000800 668#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 669#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 670#define BGE_MACMODE_TX_STATS_ENB 0x00004000 671#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 672#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 673#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 674#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 675#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 676#define BGE_MACMODE_MIP_ENB 0x00100000 677#define BGE_MACMODE_TXDMA_ENB 0x00200000 678#define BGE_MACMODE_RXDMA_ENB 0x00400000 679#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 680#define BGE_MACMODE_APE_RX_EN 0x08000000 681#define BGE_MACMODE_APE_TX_EN 0x10000000 682 683#define BGE_PORTMODE_NONE 0x00000000 684#define BGE_PORTMODE_MII 0x00000004 685#define BGE_PORTMODE_GMII 0x00000008 686#define BGE_PORTMODE_TBI 0x0000000C 687 688/* MAC Status register */ 689#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 690#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 691#define BGE_MACSTAT_RX_CFG 0x00000004 692#define BGE_MACSTAT_CFG_CHANGED 0x00000008 693#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 694#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 695#define BGE_MACSTAT_LINK_CHANGED 0x00001000 696#define BGE_MACSTAT_MI_COMPLETE 0x00400000 697#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 698#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 699#define BGE_MACSTAT_ODI_ERROR 0x02000000 700#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 701#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 702 703/* MAC Event Enable Register */ 704#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 705#define BGE_EVTENB_LINK_CHANGED 0x00001000 706#define BGE_EVTENB_MI_COMPLETE 0x00400000 707#define BGE_EVTENB_MI_INTERRUPT 0x00800000 708#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 709#define BGE_EVTENB_ODI_ERROR 0x02000000 710#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 711#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 712 713/* LED Control Register */ 714#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 715#define BGE_LEDCTL_1000MBPS_LED 0x00000002 716#define BGE_LEDCTL_100MBPS_LED 0x00000004 717#define BGE_LEDCTL_10MBPS_LED 0x00000008 718#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 719#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 720#define BGE_LEDCTL_TRAFLED_BLINK_2 0x00000040 721#define BGE_LEDCTL_1000MBPS_STS 0x00000080 722#define BGE_LEDCTL_100MBPS_STS 0x00000100 723#define BGE_LEDCTL_10MBPS_STS 0x00000200 724#define BGE_LEDCTL_TRADLED_STS 0x00000400 725#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 726#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 727 728/* TX backoff seed register */ 729#define BGE_TX_BACKOFF_SEED_MASK 0x3FF 730 731/* Autopoll status register */ 732#define BGE_AUTOPOLLSTS_ERROR 0x00000001 733 734/* Transmit MAC mode register */ 735#define BGE_TXMODE_RESET 0x00000001 736#define BGE_TXMODE_ENABLE 0x00000002 737#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 738#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 739#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 740#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 741#define BGE_TXMODE_JMB_FRM_LEN 0x00400000 742#define BGE_TXMODE_CNT_DN_MODE 0x00800000 743 744/* Transmit MAC status register */ 745#define BGE_TXSTAT_RX_XOFFED 0x00000001 746#define BGE_TXSTAT_SENT_XOFF 0x00000002 747#define BGE_TXSTAT_SENT_XON 0x00000004 748#define BGE_TXSTAT_LINK_UP 0x00000008 749#define BGE_TXSTAT_ODI_UFLOW 0x00000010 750#define BGE_TXSTAT_ODI_OFLOW 0x00000020 751 752/* Transmit MAC lengths register */ 753#define BGE_TXLEN_SLOTTIME 0x000000FF 754#define BGE_TXLEN_IPG 0x00000F00 755#define BGE_TXLEN_CRS 0x00003000 756#define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000 757#define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000 758 759/* Receive MAC mode register */ 760#define BGE_RXMODE_RESET 0x00000001 761#define BGE_RXMODE_ENABLE 0x00000002 762#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 763#define BGE_RXMODE_RX_GIANTS 0x00000020 764#define BGE_RXMODE_RX_RUNTS 0x00000040 765#define BGE_RXMODE_8022_LENCHECK 0x00000080 766#define BGE_RXMODE_RX_PROMISC 0x00000100 767#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 768#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 769#define BGE_RXMODE_IPV6_ENABLE 0x01000000 770#define BGE_RXMODE_IPV4_FRAG_FIX 0x02000000 771 772/* Receive MAC status register */ 773#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 774#define BGE_RXSTAT_RCVD_XOFF 0x00000002 775#define BGE_RXSTAT_RCVD_XON 0x00000004 776 777/* Receive Rules Control register */ 778#define BGE_RXRULECTL_OFFSET 0x000000FF 779#define BGE_RXRULECTL_CLASS 0x00001F00 780#define BGE_RXRULECTL_HDRTYPE 0x0000E000 781#define BGE_RXRULECTL_COMPARE_OP 0x00030000 782#define BGE_RXRULECTL_MAP 0x01000000 783#define BGE_RXRULECTL_DISCARD 0x02000000 784#define BGE_RXRULECTL_MASK 0x04000000 785#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 786#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 787#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 788#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 789 790/* Receive Rules Mask register */ 791#define BGE_RXRULEMASK_VALUE 0x0000FFFF 792#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 793 794/* SERDES configuration register */ 795#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 796#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 797#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 798#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 799#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 800#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 801#define BGE_SERDESCFG_TXMODE 0x00001000 802#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 803#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 804#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 805#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 806#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 807#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 808#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125MHz clock */ 809#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 810#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 811 812/* SERDES status register */ 813#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 814#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 815 816/* PHYCFG1 config */ 817#define BGE_PHYCFG1_RGMII_INT 0x00000001 818#define BGE_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000 819#define BGE_PHYCFG1_RGMII_SND_STAT_EN 0x04000000 820#define BGE_PHYCFG1_TXC_DRV 0x20000000 821 822/* PHYCFG2 config */ 823#define BGE_PHYCFG2_INBAND_ENABLE 0x00000001 824#define BGE_PHYCFG2_EMODE_MASK_MASK 0x000001c0 825#define BGE_PHYCFG2_EMODE_MASK_AC131 0x000000c0 826#define BGE_PHYCFG2_EMODE_MASK_50610 0x00000100 827#define BGE_PHYCFG2_EMODE_MASK_RT8211 0x00000000 828#define BGE_PHYCFG2_EMODE_MASK_RT8201 0x000001c0 829#define BGE_PHYCFG2_EMODE_COMP_MASK 0x00000e00 830#define BGE_PHYCFG2_EMODE_COMP_AC131 0x00000600 831#define BGE_PHYCFG2_EMODE_COMP_50610 0x00000400 832#define BGE_PHYCFG2_EMODE_COMP_RT8211 0x00000800 833#define BGE_PHYCFG2_EMODE_COMP_RT8201 0x00000000 834#define BGE_PHYCFG2_FMODE_MASK_MASK 0x00007000 835#define BGE_PHYCFG2_FMODE_MASK_AC131 0x00006000 836#define BGE_PHYCFG2_FMODE_MASK_50610 0x00004000 837#define BGE_PHYCFG2_FMODE_MASK_RT8211 0x00000000 838#define BGE_PHYCFG2_FMODE_MASK_RT8201 0x00007000 839#define BGE_PHYCFG2_FMODE_COMP_MASK 0x00038000 840#define BGE_PHYCFG2_FMODE_COMP_AC131 0x00030000 841#define BGE_PHYCFG2_FMODE_COMP_50610 0x00008000 842#define BGE_PHYCFG2_FMODE_COMP_RT8211 0x00038000 843#define BGE_PHYCFG2_FMODE_COMP_RT8201 0x00000000 844#define BGE_PHYCFG2_GMODE_MASK_MASK 0x001c0000 845#define BGE_PHYCFG2_GMODE_MASK_AC131 0x001c0000 846#define BGE_PHYCFG2_GMODE_MASK_50610 0x00100000 847#define BGE_PHYCFG2_GMODE_MASK_RT8211 0x00000000 848#define BGE_PHYCFG2_GMODE_MASK_RT8201 0x001c0000 849#define BGE_PHYCFG2_GMODE_COMP_MASK 0x00e00000 850#define BGE_PHYCFG2_GMODE_COMP_AC131 0x00e00000 851#define BGE_PHYCFG2_GMODE_COMP_50610 0x00000000 852#define BGE_PHYCFG2_GMODE_COMP_RT8211 0x00200000 853#define BGE_PHYCFG2_GMODE_COMP_RT8201 0x00000000 854#define BGE_PHYCFG2_ACT_MASK_MASK 0x03000000 855#define BGE_PHYCFG2_ACT_MASK_AC131 0x03000000 856#define BGE_PHYCFG2_ACT_MASK_50610 0x01000000 857#define BGE_PHYCFG2_ACT_MASK_RT8211 0x03000000 858#define BGE_PHYCFG2_ACT_MASK_RT8201 0x01000000 859#define BGE_PHYCFG2_ACT_COMP_MASK 0x0c000000 860#define BGE_PHYCFG2_ACT_COMP_AC131 0x00000000 861#define BGE_PHYCFG2_ACT_COMP_50610 0x00000000 862#define BGE_PHYCFG2_ACT_COMP_RT8211 0x00000000 863#define BGE_PHYCFG2_ACT_COMP_RT8201 0x08000000 864#define BGE_PHYCFG2_QUAL_MASK_MASK 0x30000000 865#define BGE_PHYCFG2_QUAL_MASK_AC131 0x30000000 866#define BGE_PHYCFG2_QUAL_MASK_50610 0x30000000 867#define BGE_PHYCFG2_QUAL_MASK_RT8211 0x30000000 868#define BGE_PHYCFG2_QUAL_MASK_RT8201 0x30000000 869#define BGE_PHYCFG2_QUAL_COMP_MASK 0xc0000000 870#define BGE_PHYCFG2_QUAL_COMP_AC131 0x00000000 871#define BGE_PHYCFG2_QUAL_COMP_50610 0x00000000 872#define BGE_PHYCFG2_QUAL_COMP_RT8211 0x00000000 873#define BGE_PHYCFG2_QUAL_COMP_RT8201 0x00000000 874#define BGE_PHYCFG2_50610_LED_MODES \ 875 (BGE_PHYCFG2_EMODE_MASK_50610 | \ 876 BGE_PHYCFG2_EMODE_COMP_50610 | \ 877 BGE_PHYCFG2_FMODE_MASK_50610 | \ 878 BGE_PHYCFG2_FMODE_COMP_50610 | \ 879 BGE_PHYCFG2_GMODE_MASK_50610 | \ 880 BGE_PHYCFG2_GMODE_COMP_50610 | \ 881 BGE_PHYCFG2_ACT_MASK_50610 | \ 882 BGE_PHYCFG2_ACT_COMP_50610 | \ 883 BGE_PHYCFG2_QUAL_MASK_50610 | \ 884 BGE_PHYCFG2_QUAL_COMP_50610) 885#define BGE_PHYCFG2_AC131_LED_MODES \ 886 (BGE_PHYCFG2_EMODE_MASK_AC131 | \ 887 BGE_PHYCFG2_EMODE_COMP_AC131 | \ 888 BGE_PHYCFG2_FMODE_MASK_AC131 | \ 889 BGE_PHYCFG2_FMODE_COMP_AC131 | \ 890 BGE_PHYCFG2_GMODE_MASK_AC131 | \ 891 BGE_PHYCFG2_GMODE_COMP_AC131 | \ 892 BGE_PHYCFG2_ACT_MASK_AC131 | \ 893 BGE_PHYCFG2_ACT_COMP_AC131 | \ 894 BGE_PHYCFG2_QUAL_MASK_AC131 | \ 895 BGE_PHYCFG2_QUAL_COMP_AC131) 896#define BGE_PHYCFG2_RTL8211C_LED_MODES \ 897 (BGE_PHYCFG2_EMODE_MASK_RT8211 | \ 898 BGE_PHYCFG2_EMODE_COMP_RT8211 | \ 899 BGE_PHYCFG2_FMODE_MASK_RT8211 | \ 900 BGE_PHYCFG2_FMODE_COMP_RT8211 | \ 901 BGE_PHYCFG2_GMODE_MASK_RT8211 | \ 902 BGE_PHYCFG2_GMODE_COMP_RT8211 | \ 903 BGE_PHYCFG2_ACT_MASK_RT8211 | \ 904 BGE_PHYCFG2_ACT_COMP_RT8211 | \ 905 BGE_PHYCFG2_QUAL_MASK_RT8211 | \ 906 BGE_PHYCFG2_QUAL_COMP_RT8211) 907#define BGE_PHYCFG2_RTL8201E_LED_MODES \ 908 (BGE_PHYCFG2_EMODE_MASK_RT8201 | \ 909 BGE_PHYCFG2_EMODE_COMP_RT8201 | \ 910 BGE_PHYCFG2_FMODE_MASK_RT8201 | \ 911 BGE_PHYCFG2_FMODE_COMP_RT8201 | \ 912 BGE_PHYCFG2_GMODE_MASK_RT8201 | \ 913 BGE_PHYCFG2_GMODE_COMP_RT8201 | \ 914 BGE_PHYCFG2_ACT_MASK_RT8201 | \ 915 BGE_PHYCFG2_ACT_COMP_RT8201 | \ 916 BGE_PHYCFG2_QUAL_MASK_RT8201 | \ 917 BGE_PHYCFG2_QUAL_COMP_RT8201) 918 919/* EXT_RGMII_MODE config */ 920#define BGE_RGMII_MODE_TX_ENABLE 0x00000001 921#define BGE_RGMII_MODE_TX_LOWPWR 0x00000002 922#define BGE_RGMII_MODE_TX_RESET 0x00000004 923#define BGE_RGMII_MODE_RX_INT_B 0x00000100 924#define BGE_RGMII_MODE_RX_QUALITY 0x00000200 925#define BGE_RGMII_MODE_RX_ACTIVITY 0x00000400 926#define BGE_RGMII_MODE_RX_ENG_DET 0x00000800 927 928/* SGDIG config (not documented) */ 929#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 930#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 931#define BGE_SGDIGCFG_SEND 0x40000000 932#define BGE_SGDIGCFG_AUTO 0x80000000 933 934/* SGDIG status (not documented) */ 935#define BGE_SGDIGSTS_DONE 0x00000002 936#define BGE_SGDIGSTS_IS_SERDES 0x00000100 937#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 938#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 939 940/* MI communication register */ 941#define BGE_MICOMM_DATA 0x0000FFFF 942#define BGE_MICOMM_REG 0x001F0000 943#define BGE_MICOMM_PHY 0x03E00000 944#define BGE_MICOMM_CMD 0x0C000000 945#define BGE_MICOMM_READFAIL 0x10000000 946#define BGE_MICOMM_BUSY 0x20000000 947 948#define BGE_MIREG(x) ((x & 0x1F) << 16) 949#define BGE_MIPHY(x) ((x & 0x1F) << 21) 950#define BGE_MICMD_WRITE 0x04000000 951#define BGE_MICMD_READ 0x08000000 952 953/* MI status register */ 954#define BGE_MISTS_LINK 0x00000001 955#define BGE_MISTS_10MBPS 0x00000002 956 957#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 958#define BGE_MIMODE_AUTOPOLL 0x00000010 959#define BGE_MIMODE_CLKCNT 0x001F0000 960#define BGE_MIMODE_500KHZ_CONST 0x00008000 961#define BGE_MIMODE_BASE 0x000C0000 962#define BGE_MIMODE_PHYADDR(x) ((x & 0x1F) << 5) 963 964/* 965 * Send data initiator control registers. 966 */ 967#define BGE_SDI_MODE 0x0C00 968#define BGE_SDI_STATUS 0x0C04 969#define BGE_SDI_STATS_CTL 0x0C08 970#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 971#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 972#define BGE_ISO_PKT_TX 0x0C20 973#define BGE_LOCSTATS_COS0 0x0C80 974#define BGE_LOCSTATS_COS1 0x0C84 975#define BGE_LOCSTATS_COS2 0x0C88 976#define BGE_LOCSTATS_COS3 0x0C8C 977#define BGE_LOCSTATS_COS4 0x0C90 978#define BGE_LOCSTATS_COS5 0x0C84 979#define BGE_LOCSTATS_COS6 0x0C98 980#define BGE_LOCSTATS_COS7 0x0C9C 981#define BGE_LOCSTATS_COS8 0x0CA0 982#define BGE_LOCSTATS_COS9 0x0CA4 983#define BGE_LOCSTATS_COS10 0x0CA8 984#define BGE_LOCSTATS_COS11 0x0CAC 985#define BGE_LOCSTATS_COS12 0x0CB0 986#define BGE_LOCSTATS_COS13 0x0CB4 987#define BGE_LOCSTATS_COS14 0x0CB8 988#define BGE_LOCSTATS_COS15 0x0CBC 989#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 990#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 991#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 992#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 993#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 994#define BGE_LOCSTATS_IRQS 0x0CD4 995#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 996#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 997 998/* Send Data Initiator mode register */ 999#define BGE_SDIMODE_RESET 0x00000001 1000#define BGE_SDIMODE_ENABLE 0x00000002 1001#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 1002 1003/* Send Data Initiator stats register */ 1004#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 1005 1006/* Send Data Initiator stats control register */ 1007#define BGE_SDISTATSCTL_ENABLE 0x00000001 1008#define BGE_SDISTATSCTL_FASTER 0x00000002 1009#define BGE_SDISTATSCTL_CLEAR 0x00000004 1010#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 1011#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 1012 1013/* 1014 * Send Data Completion Control registers 1015 */ 1016#define BGE_SDC_MODE 0x1000 1017#define BGE_SDC_STATUS 0x1004 1018 1019/* Send Data completion mode register */ 1020#define BGE_SDCMODE_RESET 0x00000001 1021#define BGE_SDCMODE_ENABLE 0x00000002 1022#define BGE_SDCMODE_ATTN 0x00000004 1023#define BGE_SDCMODE_CDELAY 0x00000010 1024 1025/* Send Data completion status register */ 1026#define BGE_SDCSTAT_ATTN 0x00000004 1027 1028/* 1029 * Send BD Ring Selector Control registers 1030 */ 1031#define BGE_SRS_MODE 0x1400 1032#define BGE_SRS_STATUS 0x1404 1033#define BGE_SRS_HWDIAG 0x1408 1034#define BGE_SRS_LOC_NIC_CONS0 0x1440 1035#define BGE_SRS_LOC_NIC_CONS1 0x1444 1036#define BGE_SRS_LOC_NIC_CONS2 0x1448 1037#define BGE_SRS_LOC_NIC_CONS3 0x144C 1038#define BGE_SRS_LOC_NIC_CONS4 0x1450 1039#define BGE_SRS_LOC_NIC_CONS5 0x1454 1040#define BGE_SRS_LOC_NIC_CONS6 0x1458 1041#define BGE_SRS_LOC_NIC_CONS7 0x145C 1042#define BGE_SRS_LOC_NIC_CONS8 0x1460 1043#define BGE_SRS_LOC_NIC_CONS9 0x1464 1044#define BGE_SRS_LOC_NIC_CONS10 0x1468 1045#define BGE_SRS_LOC_NIC_CONS11 0x146C 1046#define BGE_SRS_LOC_NIC_CONS12 0x1470 1047#define BGE_SRS_LOC_NIC_CONS13 0x1474 1048#define BGE_SRS_LOC_NIC_CONS14 0x1478 1049#define BGE_SRS_LOC_NIC_CONS15 0x147C 1050 1051/* Send BD Ring Selector Mode register */ 1052#define BGE_SRSMODE_RESET 0x00000001 1053#define BGE_SRSMODE_ENABLE 0x00000002 1054#define BGE_SRSMODE_ATTN 0x00000004 1055 1056/* Send BD Ring Selector Status register */ 1057#define BGE_SRSSTAT_ERROR 0x00000004 1058 1059/* Send BD Ring Selector HW Diagnostics register */ 1060#define BGE_SRSHWDIAG_STATE 0x0000000F 1061#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 1062#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 1063#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 1064 1065/* 1066 * Send BD Initiator Selector Control registers 1067 */ 1068#define BGE_SBDI_MODE 0x1800 1069#define BGE_SBDI_STATUS 0x1804 1070#define BGE_SBDI_LOC_NIC_PROD0 0x1808 1071#define BGE_SBDI_LOC_NIC_PROD1 0x180C 1072#define BGE_SBDI_LOC_NIC_PROD2 0x1810 1073#define BGE_SBDI_LOC_NIC_PROD3 0x1814 1074#define BGE_SBDI_LOC_NIC_PROD4 0x1818 1075#define BGE_SBDI_LOC_NIC_PROD5 0x181C 1076#define BGE_SBDI_LOC_NIC_PROD6 0x1820 1077#define BGE_SBDI_LOC_NIC_PROD7 0x1824 1078#define BGE_SBDI_LOC_NIC_PROD8 0x1828 1079#define BGE_SBDI_LOC_NIC_PROD9 0x182C 1080#define BGE_SBDI_LOC_NIC_PROD10 0x1830 1081#define BGE_SBDI_LOC_NIC_PROD11 0x1834 1082#define BGE_SBDI_LOC_NIC_PROD12 0x1838 1083#define BGE_SBDI_LOC_NIC_PROD13 0x183C 1084#define BGE_SBDI_LOC_NIC_PROD14 0x1840 1085#define BGE_SBDI_LOC_NIC_PROD15 0x1844 1086 1087/* Send BD Initiator Mode register */ 1088#define BGE_SBDIMODE_RESET 0x00000001 1089#define BGE_SBDIMODE_ENABLE 0x00000002 1090#define BGE_SBDIMODE_ATTN 0x00000004 1091 1092/* Send BD Initiator Status register */ 1093#define BGE_SBDISTAT_ERROR 0x00000004 1094 1095/* 1096 * Send BD Completion Control registers 1097 */ 1098#define BGE_SBDC_MODE 0x1C00 1099#define BGE_SBDC_STATUS 0x1C04 1100 1101/* Send BD Completion Control Mode register */ 1102#define BGE_SBDCMODE_RESET 0x00000001 1103#define BGE_SBDCMODE_ENABLE 0x00000002 1104#define BGE_SBDCMODE_ATTN 0x00000004 1105 1106/* Send BD Completion Control Status register */ 1107#define BGE_SBDCSTAT_ATTN 0x00000004 1108 1109/* 1110 * Receive List Placement Control registers 1111 */ 1112#define BGE_RXLP_MODE 0x2000 1113#define BGE_RXLP_STATUS 0x2004 1114#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1115#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1116#define BGE_RXLP_CFG 0x2010 1117#define BGE_RXLP_STATS_CTL 0x2014 1118#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1119#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1120#define BGE_RXLP_HEAD0 0x2100 1121#define BGE_RXLP_TAIL0 0x2104 1122#define BGE_RXLP_COUNT0 0x2108 1123#define BGE_RXLP_HEAD1 0x2110 1124#define BGE_RXLP_TAIL1 0x2114 1125#define BGE_RXLP_COUNT1 0x2118 1126#define BGE_RXLP_HEAD2 0x2120 1127#define BGE_RXLP_TAIL2 0x2124 1128#define BGE_RXLP_COUNT2 0x2128 1129#define BGE_RXLP_HEAD3 0x2130 1130#define BGE_RXLP_TAIL3 0x2134 1131#define BGE_RXLP_COUNT3 0x2138 1132#define BGE_RXLP_HEAD4 0x2140 1133#define BGE_RXLP_TAIL4 0x2144 1134#define BGE_RXLP_COUNT4 0x2148 1135#define BGE_RXLP_HEAD5 0x2150 1136#define BGE_RXLP_TAIL5 0x2154 1137#define BGE_RXLP_COUNT5 0x2158 1138#define BGE_RXLP_HEAD6 0x2160 1139#define BGE_RXLP_TAIL6 0x2164 1140#define BGE_RXLP_COUNT6 0x2168 1141#define BGE_RXLP_HEAD7 0x2170 1142#define BGE_RXLP_TAIL7 0x2174 1143#define BGE_RXLP_COUNT7 0x2178 1144#define BGE_RXLP_HEAD8 0x2180 1145#define BGE_RXLP_TAIL8 0x2184 1146#define BGE_RXLP_COUNT8 0x2188 1147#define BGE_RXLP_HEAD9 0x2190 1148#define BGE_RXLP_TAIL9 0x2194 1149#define BGE_RXLP_COUNT9 0x2198 1150#define BGE_RXLP_HEAD10 0x21A0 1151#define BGE_RXLP_TAIL10 0x21A4 1152#define BGE_RXLP_COUNT10 0x21A8 1153#define BGE_RXLP_HEAD11 0x21B0 1154#define BGE_RXLP_TAIL11 0x21B4 1155#define BGE_RXLP_COUNT11 0x21B8 1156#define BGE_RXLP_HEAD12 0x21C0 1157#define BGE_RXLP_TAIL12 0x21C4 1158#define BGE_RXLP_COUNT12 0x21C8 1159#define BGE_RXLP_HEAD13 0x21D0 1160#define BGE_RXLP_TAIL13 0x21D4 1161#define BGE_RXLP_COUNT13 0x21D8 1162#define BGE_RXLP_HEAD14 0x21E0 1163#define BGE_RXLP_TAIL14 0x21E4 1164#define BGE_RXLP_COUNT14 0x21E8 1165#define BGE_RXLP_HEAD15 0x21F0 1166#define BGE_RXLP_TAIL15 0x21F4 1167#define BGE_RXLP_COUNT15 0x21F8 1168#define BGE_RXLP_LOCSTAT_COS0 0x2200 1169#define BGE_RXLP_LOCSTAT_COS1 0x2204 1170#define BGE_RXLP_LOCSTAT_COS2 0x2208 1171#define BGE_RXLP_LOCSTAT_COS3 0x220C 1172#define BGE_RXLP_LOCSTAT_COS4 0x2210 1173#define BGE_RXLP_LOCSTAT_COS5 0x2214 1174#define BGE_RXLP_LOCSTAT_COS6 0x2218 1175#define BGE_RXLP_LOCSTAT_COS7 0x221C 1176#define BGE_RXLP_LOCSTAT_COS8 0x2220 1177#define BGE_RXLP_LOCSTAT_COS9 0x2224 1178#define BGE_RXLP_LOCSTAT_COS10 0x2228 1179#define BGE_RXLP_LOCSTAT_COS11 0x222C 1180#define BGE_RXLP_LOCSTAT_COS12 0x2230 1181#define BGE_RXLP_LOCSTAT_COS13 0x2234 1182#define BGE_RXLP_LOCSTAT_COS14 0x2238 1183#define BGE_RXLP_LOCSTAT_COS15 0x223C 1184#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1185#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1186#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1187#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1188#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1189#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1190#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1191 1192 1193/* Receive List Placement mode register */ 1194#define BGE_RXLPMODE_RESET 0x00000001 1195#define BGE_RXLPMODE_ENABLE 0x00000002 1196#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1197#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1198#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1199 1200/* Receive List Placement Status register */ 1201#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1202#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1203#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1204 1205/* 1206 * Receive Data and Receive BD Initiator Control Registers 1207 */ 1208#define BGE_RDBDI_MODE 0x2400 1209#define BGE_RDBDI_STATUS 0x2404 1210#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1211#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1212#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1213#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1214#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1215#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1216#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1217#define BGE_RX_STD_RCB_NICADDR 0x245C 1218#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1219#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1220#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1221#define BGE_RX_MINI_RCB_NICADDR 0x246C 1222#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1223#define BGE_RDBDI_STD_RX_CONS 0x2474 1224#define BGE_RDBDI_MINI_RX_CONS 0x2478 1225#define BGE_RDBDI_RETURN_PROD0 0x2480 1226#define BGE_RDBDI_RETURN_PROD1 0x2484 1227#define BGE_RDBDI_RETURN_PROD2 0x2488 1228#define BGE_RDBDI_RETURN_PROD3 0x248C 1229#define BGE_RDBDI_RETURN_PROD4 0x2490 1230#define BGE_RDBDI_RETURN_PROD5 0x2494 1231#define BGE_RDBDI_RETURN_PROD6 0x2498 1232#define BGE_RDBDI_RETURN_PROD7 0x249C 1233#define BGE_RDBDI_RETURN_PROD8 0x24A0 1234#define BGE_RDBDI_RETURN_PROD9 0x24A4 1235#define BGE_RDBDI_RETURN_PROD10 0x24A8 1236#define BGE_RDBDI_RETURN_PROD11 0x24AC 1237#define BGE_RDBDI_RETURN_PROD12 0x24B0 1238#define BGE_RDBDI_RETURN_PROD13 0x24B4 1239#define BGE_RDBDI_RETURN_PROD14 0x24B8 1240#define BGE_RDBDI_RETURN_PROD15 0x24BC 1241#define BGE_RDBDI_HWDIAG 0x24C0 1242 1243 1244/* Receive Data and Receive BD Initiator Mode register */ 1245#define BGE_RDBDIMODE_RESET 0x00000001 1246#define BGE_RDBDIMODE_ENABLE 0x00000002 1247#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1248#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1249#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1250 1251/* Receive Data and Receive BD Initiator Status register */ 1252#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1253#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1254#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1255 1256 1257/* 1258 * Receive Data Completion Control registers 1259 */ 1260#define BGE_RDC_MODE 0x2800 1261 1262/* Receive Data Completion Mode register */ 1263#define BGE_RDCMODE_RESET 0x00000001 1264#define BGE_RDCMODE_ENABLE 0x00000002 1265#define BGE_RDCMODE_ATTN 0x00000004 1266 1267/* 1268 * Receive BD Initiator Control registers 1269 */ 1270#define BGE_RBDI_MODE 0x2C00 1271#define BGE_RBDI_STATUS 0x2C04 1272#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1273#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1274#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1275#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1276#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1277#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1278 1279#define BGE_STD_REPL_LWM 0x2D00 1280#define BGE_JUMBO_REPL_LWM 0x2D04 1281 1282/* Receive BD Initiator Mode register */ 1283#define BGE_RBDIMODE_RESET 0x00000001 1284#define BGE_RBDIMODE_ENABLE 0x00000002 1285#define BGE_RBDIMODE_ATTN 0x00000004 1286 1287/* Receive BD Initiator Status register */ 1288#define BGE_RBDISTAT_ATTN 0x00000004 1289 1290/* 1291 * Receive BD Completion Control registers 1292 */ 1293#define BGE_RBDC_MODE 0x3000 1294#define BGE_RBDC_STATUS 0x3004 1295#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1296#define BGE_RBDC_STD_BD_PROD 0x300C 1297#define BGE_RBDC_MINI_BD_PROD 0x3010 1298 1299/* Receive BD completion mode register */ 1300#define BGE_RBDCMODE_RESET 0x00000001 1301#define BGE_RBDCMODE_ENABLE 0x00000002 1302#define BGE_RBDCMODE_ATTN 0x00000004 1303 1304/* Receive BD completion status register */ 1305#define BGE_RBDCSTAT_ERROR 0x00000004 1306 1307/* 1308 * Receive List Selector Control registers 1309 */ 1310#define BGE_RXLS_MODE 0x3400 1311#define BGE_RXLS_STATUS 0x3404 1312 1313/* Receive List Selector Mode register */ 1314#define BGE_RXLSMODE_RESET 0x00000001 1315#define BGE_RXLSMODE_ENABLE 0x00000002 1316#define BGE_RXLSMODE_ATTN 0x00000004 1317 1318/* Receive List Selector Status register */ 1319#define BGE_RXLSSTAT_ERROR 0x00000004 1320 1321#define BGE_CPMU_CTRL 0x3600 1322#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1323#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1324#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1325#define BGE_CPMU_HST_ACC 0x361C 1326#define BGE_CPMU_CLCK_ORIDE 0x3624 1327#define BGE_CPMU_CLCK_STAT 0x3630 1328#define BGE_CPMU_MUTEX_REQ 0x365C 1329#define BGE_CPMU_MUTEX_GNT 0x3660 1330#define BGE_CPMU_PHY_STRAP 0x3664 1331#define BGE_CPMU_PADRNG_CTL 0x3668 1332 1333/* Central Power Management Unit (CPMU) register */ 1334#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1335#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1336#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1337#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1338 1339/* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1340#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1341#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1342 1343/* Link Speed 1000MB Power Mode Clock Policy register */ 1344#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1345#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1346#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1347 1348/* Link Aware Power Mode Clock Policy register */ 1349#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1350#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1351 1352#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1353#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1354 1355/* Clock Speed Override Policy register */ 1356#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1357 1358/* CPMU Clock Status register */ 1359#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1360#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1361#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1362#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1363 1364/* CPMU Mutex Request register */ 1365#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1366#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1367 1368/* CPMU GPHY Strap register */ 1369#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1370 1371/* CPMU Padring Control register */ 1372#define BGE_CPMU_PADRNG_CTL_RDIV2 0x00040000 1373 1374/* 1375 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1376 */ 1377#define BGE_MBCF_MODE 0x3800 1378#define BGE_MBCF_STATUS 0x3804 1379 1380/* Mbuf Cluster Free mode register */ 1381#define BGE_MBCFMODE_RESET 0x00000001 1382#define BGE_MBCFMODE_ENABLE 0x00000002 1383#define BGE_MBCFMODE_ATTN 0x00000004 1384 1385/* Mbuf Cluster Free status register */ 1386#define BGE_MBCFSTAT_ERROR 0x00000004 1387 1388/* 1389 * Host Coalescing Control registers 1390 */ 1391#define BGE_HCC_MODE 0x3C00 1392#define BGE_HCC_STATUS 0x3C04 1393#define BGE_HCC_RX_COAL_TICKS 0x3C08 1394#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1395#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1396#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1397#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1398#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1399#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1400#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1401#define BGE_HCC_STATS_TICKS 0x3C28 1402#define BGE_HCC_STATS_ADDR_HI 0x3C30 1403#define BGE_HCC_STATS_ADDR_LO 0x3C34 1404#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1405#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1406#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1407#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1408#define BGE_FLOW_ATTN 0x3C48 1409#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1410#define BGE_HCC_STD_BD_CONS 0x3C54 1411#define BGE_HCC_MINI_BD_CONS 0x3C58 1412#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1413#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1414#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1415#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1416#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1417#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1418#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1419#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1420#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1421#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1422#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1423#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1424#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1425#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1426#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1427#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1428#define BGE_HCC_TX_BD_CONS0 0x3CC0 1429#define BGE_HCC_TX_BD_CONS1 0x3CC4 1430#define BGE_HCC_TX_BD_CONS2 0x3CC8 1431#define BGE_HCC_TX_BD_CONS3 0x3CCC 1432#define BGE_HCC_TX_BD_CONS4 0x3CD0 1433#define BGE_HCC_TX_BD_CONS5 0x3CD4 1434#define BGE_HCC_TX_BD_CONS6 0x3CD8 1435#define BGE_HCC_TX_BD_CONS7 0x3CDC 1436#define BGE_HCC_TX_BD_CONS8 0x3CE0 1437#define BGE_HCC_TX_BD_CONS9 0x3CE4 1438#define BGE_HCC_TX_BD_CONS10 0x3CE8 1439#define BGE_HCC_TX_BD_CONS11 0x3CEC 1440#define BGE_HCC_TX_BD_CONS12 0x3CF0 1441#define BGE_HCC_TX_BD_CONS13 0x3CF4 1442#define BGE_HCC_TX_BD_CONS14 0x3CF8 1443#define BGE_HCC_TX_BD_CONS15 0x3CFC 1444 1445 1446/* Host coalescing mode register */ 1447#define BGE_HCCMODE_RESET 0x00000001 1448#define BGE_HCCMODE_ENABLE 0x00000002 1449#define BGE_HCCMODE_ATTN 0x00000004 1450#define BGE_HCCMODE_COAL_NOW 0x00000008 1451#define BGE_HCCMODE_MSI_BITS 0x00000070 1452#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1453 1454#define BGE_STATBLKSZ_FULL 0x00000000 1455#define BGE_STATBLKSZ_64BYTE 0x00000080 1456#define BGE_STATBLKSZ_32BYTE 0x00000100 1457 1458/* Host coalescing status register */ 1459#define BGE_HCCSTAT_ERROR 0x00000004 1460 1461/* Flow attention register */ 1462#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1463#define BGE_FLOWATTN_MEMARB 0x00000080 1464#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1465#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1466#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1467#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1468#define BGE_FLOWATTN_RDBDI 0x00080000 1469#define BGE_FLOWATTN_RXLS 0x00100000 1470#define BGE_FLOWATTN_RXLP 0x00200000 1471#define BGE_FLOWATTN_RBDC 0x00400000 1472#define BGE_FLOWATTN_RBDI 0x00800000 1473#define BGE_FLOWATTN_SDC 0x08000000 1474#define BGE_FLOWATTN_SDI 0x10000000 1475#define BGE_FLOWATTN_SRS 0x20000000 1476#define BGE_FLOWATTN_SBDC 0x40000000 1477#define BGE_FLOWATTN_SBDI 0x80000000 1478 1479/* 1480 * Memory arbiter registers 1481 */ 1482#define BGE_MARB_MODE 0x4000 1483#define BGE_MARB_STATUS 0x4004 1484#define BGE_MARB_TRAPADDR_HI 0x4008 1485#define BGE_MARB_TRAPADDR_LO 0x400C 1486 1487/* Memory arbiter mode register */ 1488#define BGE_MARBMODE_RESET 0x00000001 1489#define BGE_MARBMODE_ENABLE 0x00000002 1490#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1491#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1492#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1493#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1494#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1495#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1496#define BGE_MARBMODE_PCI_TRAP 0x00000100 1497#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1498#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1499#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1500#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1501#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1502#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1503#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1504#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1505#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1506#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1507#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1508#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1509#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1510#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1511#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1512#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1513#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1514 1515/* Memory arbiter status register */ 1516#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1517#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1518#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1519#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1520#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1521#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1522#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1523#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1524#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1525#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1526#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1527#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1528#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1529#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1530#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1531#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1532#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1533#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1534#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1535#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1536#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1537#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1538#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1539#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1540 1541/* 1542 * Buffer manager control registers 1543 */ 1544#define BGE_BMAN_MODE 0x4400 1545#define BGE_BMAN_STATUS 0x4404 1546#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1547#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1548#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1549#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1550#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1551#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1552#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1553#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1554#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1555#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1556#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1557#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1558#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1559#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1560#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1561#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1562#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1563#define BGE_BMAN_HWDIAG_1 0x444C 1564#define BGE_BMAN_HWDIAG_2 0x4450 1565#define BGE_BMAN_HWDIAG_3 0x4454 1566 1567/* Buffer manager mode register */ 1568#define BGE_BMANMODE_RESET 0x00000001 1569#define BGE_BMANMODE_ENABLE 0x00000002 1570#define BGE_BMANMODE_ATTN 0x00000004 1571#define BGE_BMANMODE_TESTMODE 0x00000008 1572#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1573#define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000 1574 1575/* Buffer manager status register */ 1576#define BGE_BMANSTAT_ERRO 0x00000004 1577#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1578 1579 1580/* 1581 * Read DMA Control registers 1582 */ 1583#define BGE_RDMA_MODE 0x4800 1584#define BGE_RDMA_STATUS 0x4804 1585#define BGE_RDMA_RSRVCTRL_REG2 0x4890 1586#define BGE_RDMA_LSO_CRPTEN_CTRL_REG2 0x48A0 1587#define BGE_RDMA_RSRVCTRL 0x4900 1588#define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 1589 1590/* Read DMA mode register */ 1591#define BGE_RDMAMODE_RESET 0x00000001 1592#define BGE_RDMAMODE_ENABLE 0x00000002 1593#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1594#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1595#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1596#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1597#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1598#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1599#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1600#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1601#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1602#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1603#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1604#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1605#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1606#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1607#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1608#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1609#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1610#define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000 1611 1612/* Read DMA status register */ 1613#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1614#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1615#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1616#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1617#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1618#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1619#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1620#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1621 1622/* Read DMA Reserved Control register */ 1623#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1624#define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00 1625#define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000 1626#define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1627#define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0 1628#define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000 1629#define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000 1630 1631#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000 1632#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1633#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 1634#define BGE_RDMA_TX_LENGTH_WA_5719 0x02000000 1635#define BGE_RDMA_TX_LENGTH_WA_5720 0x00200000 1636 1637/* BD Read DMA Mode register */ 1638#define BGE_RDMA_BD_MODE 0x4A00 1639/* BD Read DMA Mode status register */ 1640#define BGE_RDMA_BD_STATUS 0x4A04 1641 1642#define BGE_RDMA_BD_MODE_RESET 0x00000001 1643#define BGE_RDMA_BD_MODE_ENABLE 0x00000002 1644 1645/* Non-LSO Read DMA Mode register */ 1646#define BGE_RDMA_NON_LSO_MODE 0x4B00 1647/* Non-LSO Read DMA Mode status register */ 1648#define BGE_RDMA_NON_LSO_STATUS 0x4B04 1649 1650#define BGE_RDMA_NON_LSO_MODE_RESET 0x00000001 1651#define BGE_RDMA_NON_LSO_MODE_ENABLE 0x00000002 1652 1653#define BGE_RDMA_LENGTH 0x4BE0 1654#define BGE_NUM_RDMA_CHANNELS 4 1655 1656/* 1657 * Write DMA control registers 1658 */ 1659#define BGE_WDMA_MODE 0x4C00 1660#define BGE_WDMA_STATUS 0x4C04 1661 1662/* Write DMA mode register */ 1663#define BGE_WDMAMODE_RESET 0x00000001 1664#define BGE_WDMAMODE_ENABLE 0x00000002 1665#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1666#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1667#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1668#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1669#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1670#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1671#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1672#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1673#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1674#define BGE_WDMAMODE_RX_ACCEL 0x00000400 1675#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1676#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1677 1678/* Write DMA status register */ 1679#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1680#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1681#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1682#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1683#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1684#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1685#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1686#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1687 1688 1689/* 1690 * RX CPU registers 1691 */ 1692#define BGE_RXCPU_MODE 0x5000 1693#define BGE_RXCPU_STATUS 0x5004 1694#define BGE_RXCPU_PC 0x501C 1695 1696/* RX CPU mode register */ 1697#define BGE_RXCPUMODE_RESET 0x00000001 1698#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1699#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1700#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1701#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1702#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1703#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1704#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1705#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1706#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1707#define BGE_RXCPUMODE_HALTCPU 0x00000400 1708#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1709#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1710#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1711 1712/* RX CPU status register */ 1713#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1714#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1715#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1716#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1717#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1718#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1719#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1720#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1721#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1722#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1723#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1724#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1725#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1726#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1727#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1728#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1729#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1730 1731 1732/* 1733 * V? CPU registers 1734 */ 1735#define BGE_VCPU_STATUS 0x5100 1736#define BGE_VCPU_EXT_CTRL 0x6890 1737 1738#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1739#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1740 1741#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1742#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1743 1744/* 1745 * TX CPU registers 1746 */ 1747#define BGE_TXCPU_MODE 0x5400 1748#define BGE_TXCPU_STATUS 0x5404 1749#define BGE_TXCPU_PC 0x541C 1750 1751/* TX CPU mode register */ 1752#define BGE_TXCPUMODE_RESET 0x00000001 1753#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1754#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1755#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1756#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1757#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1758#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1759#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1760#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1761#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1762#define BGE_TXCPUMODE_HALTCPU 0x00000400 1763#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1764#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1765 1766/* TX CPU status register */ 1767#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1768#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1769#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1770#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1771#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1772#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1773#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1774#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1775#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1776#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1777#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1778#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1779#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1780#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1781#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1782#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1783#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1784 1785 1786/* 1787 * Low priority mailbox registers 1788 */ 1789#define BGE_LPMBX_IRQ0_HI 0x5800 1790#define BGE_LPMBX_IRQ0_LO 0x5804 1791#define BGE_LPMBX_IRQ1_HI 0x5808 1792#define BGE_LPMBX_IRQ1_LO 0x580C 1793#define BGE_LPMBX_IRQ2_HI 0x5810 1794#define BGE_LPMBX_IRQ2_LO 0x5814 1795#define BGE_LPMBX_IRQ3_HI 0x5818 1796#define BGE_LPMBX_IRQ3_LO 0x581C 1797#define BGE_LPMBX_GEN0_HI 0x5820 1798#define BGE_LPMBX_GEN0_LO 0x5824 1799#define BGE_LPMBX_GEN1_HI 0x5828 1800#define BGE_LPMBX_GEN1_LO 0x582C 1801#define BGE_LPMBX_GEN2_HI 0x5830 1802#define BGE_LPMBX_GEN2_LO 0x5834 1803#define BGE_LPMBX_GEN3_HI 0x5828 1804#define BGE_LPMBX_GEN3_LO 0x582C 1805#define BGE_LPMBX_GEN4_HI 0x5840 1806#define BGE_LPMBX_GEN4_LO 0x5844 1807#define BGE_LPMBX_GEN5_HI 0x5848 1808#define BGE_LPMBX_GEN5_LO 0x584C 1809#define BGE_LPMBX_GEN6_HI 0x5850 1810#define BGE_LPMBX_GEN6_LO 0x5854 1811#define BGE_LPMBX_GEN7_HI 0x5858 1812#define BGE_LPMBX_GEN7_LO 0x585C 1813#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1814#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1815#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1816#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1817#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1818#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1819#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1820#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1821#define BGE_LPMBX_RX_CONS0_HI 0x5880 1822#define BGE_LPMBX_RX_CONS0_LO 0x5884 1823#define BGE_LPMBX_RX_CONS1_HI 0x5888 1824#define BGE_LPMBX_RX_CONS1_LO 0x588C 1825#define BGE_LPMBX_RX_CONS2_HI 0x5890 1826#define BGE_LPMBX_RX_CONS2_LO 0x5894 1827#define BGE_LPMBX_RX_CONS3_HI 0x5898 1828#define BGE_LPMBX_RX_CONS3_LO 0x589C 1829#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1830#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1831#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1832#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1833#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1834#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1835#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1836#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1837#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1838#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1839#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1840#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1841#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1842#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1843#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1844#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1845#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1846#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1847#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1848#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1849#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1850#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1851#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1852#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1853#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1854#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1855#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1856#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1857#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1858#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1859#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1860#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1861#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1862#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1863#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1864#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1865#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1866#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1867#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1868#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1869#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1870#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1871#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1872#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1873#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1874#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1875#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1876#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1877#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1878#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1879#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1880#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1881#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1882#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1883#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1884#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1885#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1886#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1887#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1888#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1889#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1890#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1891#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1892#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1893#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1894#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1895#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1896#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1897#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1898#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1899#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1900#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1901#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1902#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1903#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1904#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1905#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1906#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1907#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1908#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1909#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1910#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1911#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1912#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1913#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1914#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1915#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1916#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1917 1918/* 1919 * Flow throw Queue reset register 1920 */ 1921#define BGE_FTQ_RESET 0x5C00 1922 1923#define BGE_FTQRESET_DMAREAD 0x00000002 1924#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1925#define BGE_FTQRESET_DMADONE 0x00000010 1926#define BGE_FTQRESET_SBDC 0x00000020 1927#define BGE_FTQRESET_SDI 0x00000040 1928#define BGE_FTQRESET_WDMA 0x00000080 1929#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1930#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1931#define BGE_FTQRESET_SDC 0x00000400 1932#define BGE_FTQRESET_HCC 0x00000800 1933#define BGE_FTQRESET_TXFIFO 0x00001000 1934#define BGE_FTQRESET_MBC 0x00002000 1935#define BGE_FTQRESET_RBDC 0x00004000 1936#define BGE_FTQRESET_RXLP 0x00008000 1937#define BGE_FTQRESET_RDBDI 0x00010000 1938#define BGE_FTQRESET_RDC 0x00020000 1939#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1940 1941/* 1942 * Message Signaled Interrupt registers 1943 */ 1944#define BGE_MSI_MODE 0x6000 1945#define BGE_MSI_STATUS 0x6004 1946#define BGE_MSI_FIFOACCESS 0x6008 1947 1948/* MSI mode register */ 1949#define BGE_MSIMODE_RESET 0x00000001 1950#define BGE_MSIMODE_ENABLE 0x00000002 1951#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1952#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1953#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1954#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1955#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 1956 1957/* MSI status register */ 1958#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1959#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1960#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1961#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1962#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1963 1964 1965/* 1966 * DMA Completion registers 1967 */ 1968#define BGE_DMAC_MODE 0x6400 1969 1970/* DMA Completion mode register */ 1971#define BGE_DMACMODE_RESET 0x00000001 1972#define BGE_DMACMODE_ENABLE 0x00000002 1973 1974 1975/* 1976 * General control registers. 1977 */ 1978#define BGE_MODE_CTL 0x6800 1979#define BGE_MISC_CFG 0x6804 1980#define BGE_MISC_LOCAL_CTL 0x6808 1981#define BGE_RX_CPU_EVENT 0x6810 1982#define BGE_TX_CPU_EVENT 0x6820 1983#define BGE_EE_ADDR 0x6838 1984#define BGE_EE_DATA 0x683C 1985#define BGE_EE_CTL 0x6840 1986#define BGE_MDI_CTL 0x6844 1987#define BGE_EE_DELAY 0x6848 1988#define BGE_FASTBOOT_PC 0x6894 1989 1990#define BGE_RX_CPU_DRV_EVENT 0x00004000 1991 1992/* 1993 * NVRAM Control registers 1994 */ 1995 1996#define BGE_NVRAM_CMD 0x7000 1997#define BGE_NVRAM_STAT 0x7004 1998#define BGE_NVRAM_WRDATA 0x7008 1999#define BGE_NVRAM_ADDR 0x700c 2000#define BGE_NVRAM_RDDATA 0x7010 2001#define BGE_NVRAM_CFG1 0x7014 2002#define BGE_NVRAM_CFG2 0x7018 2003#define BGE_NVRAM_CFG3 0x701c 2004#define BGE_NVRAM_SWARB 0x7020 2005#define BGE_NVRAM_ACCESS 0x7024 2006#define BGE_NVRAM_WRITE1 0x7028 2007 2008 2009#define BGE_NVRAMCMD_RESET 0x00000001 2010#define BGE_NVRAMCMD_DONE 0x00000008 2011#define BGE_NVRAMCMD_START 0x00000010 2012#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 2013#define BGE_NVRAMCMD_ERASE 0x00000040 2014#define BGE_NVRAMCMD_FIRST 0x00000080 2015#define BGE_NVRAMCMD_LAST 0x00000100 2016 2017#define BGE_NVRAM_READCMD \ 2018 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 2019 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 2020#define BGE_NVRAM_WRITECMD \ 2021 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 2022 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 2023 2024#define BGE_NVRAMSWARB_SET0 0x00000001 2025#define BGE_NVRAMSWARB_SET1 0x00000002 2026#define BGE_NVRAMSWARB_SET2 0x00000003 2027#define BGE_NVRAMSWARB_SET3 0x00000004 2028#define BGE_NVRAMSWARB_CLR0 0x00000010 2029#define BGE_NVRAMSWARB_CLR1 0x00000020 2030#define BGE_NVRAMSWARB_CLR2 0x00000040 2031#define BGE_NVRAMSWARB_CLR3 0x00000080 2032#define BGE_NVRAMSWARB_GNT0 0x00000100 2033#define BGE_NVRAMSWARB_GNT1 0x00000200 2034#define BGE_NVRAMSWARB_GNT2 0x00000400 2035#define BGE_NVRAMSWARB_GNT3 0x00000800 2036#define BGE_NVRAMSWARB_REQ0 0x00001000 2037#define BGE_NVRAMSWARB_REQ1 0x00002000 2038#define BGE_NVRAMSWARB_REQ2 0x00004000 2039#define BGE_NVRAMSWARB_REQ3 0x00008000 2040 2041#define BGE_NVRAMACC_ENABLE 0x00000001 2042#define BGE_NVRAMACC_WRENABLE 0x00000002 2043 2044/* 2045 * TLP Control Register 2046 * Applicable to BCM5721 and BCM5751 only 2047 */ 2048#define BGE_TLP_CONTROL_REG 0x7c00 2049#define BGE_TLP_DATA_FIFO_PROTECT 0x02000000 2050 2051/* 2052 * PHY Test Control Register 2053 * Applicable to BCM5721 and BCM5751 only 2054 */ 2055#define BGE_PHY_TEST_CTRL_REG 0x7e2c 2056#define BGE_PHY_PCIE_SCRAM_MODE 0x0020 2057#define BGE_PHY_PCIE_LTASS_MODE 0x0040 2058 2059/* Mode control register */ 2060#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 2061#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 2062#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 2063#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 2064#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 2065#define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040 2066#define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080 2067#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 2068#define BGE_MODECTL_NO_RX_CRC 0x00000400 2069#define BGE_MODECTL_RX_BADFRAMES 0x00000800 2070#define BGE_MODECTL_NO_TX_INTR 0x00002000 2071#define BGE_MODECTL_NO_RX_INTR 0x00004000 2072#define BGE_MODECTL_FORCE_PCI32 0x00008000 2073#define BGE_MODECTL_B2HRX_ENABLE 0x00008000 2074#define BGE_MODECTL_STACKUP 0x00010000 2075#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 2076#define BGE_MODECTL_HTX2B_ENABLE 0x00040000 2077#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 2078#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 2079#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 2080#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 2081#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 2082#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 2083#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 2084#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 2085#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 2086 2087/* Misc. config register */ 2088#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 2089#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 2090#define BGE_MISCCFG_BOARD_ID_MASK 0x0001E000 2091#define BGE_MISCCFG_BOARD_ID_5704 0x00000000 2092#define BGE_MISCCFG_BOARD_ID_5704CIOBE 0x00004000 2093#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 2094#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 2095#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 2096#define BGE_MISCCFG_KEEP_GPHY_POWER 0x04000000 2097 2098#define BGE_32BITTIME_66MHZ (0x41 << 1) 2099 2100/* Misc. Local Control */ 2101#define BGE_MLC_INTR_STATE 0x00000001 2102#define BGE_MLC_INTR_CLR 0x00000002 2103#define BGE_MLC_INTR_SET 0x00000004 2104#define BGE_MLC_INTR_ONATTN 0x00000008 2105#define BGE_MLC_MISCIO_IN0 0x00000100 2106#define BGE_MLC_MISCIO_IN1 0x00000200 2107#define BGE_MLC_MISCIO_IN2 0x00000400 2108#define BGE_MLC_MISCIO_OUTEN0 0x00000800 2109#define BGE_MLC_MISCIO_OUTEN1 0x00001000 2110#define BGE_MLC_MISCIO_OUTEN2 0x00002000 2111#define BGE_MLC_MISCIO_OUT0 0x00004000 2112#define BGE_MLC_MISCIO_OUT1 0x00008000 2113#define BGE_MLC_MISCIO_OUT2 0x00010000 2114#define BGE_MLC_EXTRAM_ENB 0x00020000 2115#define BGE_MLC_SRAM_SIZE 0x001C0000 2116#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 2117#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 2118#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 2119#define BGE_MLC_AUTO_EEPROM 0x01000000 2120 2121#define BGE_SSRAMSIZE_256KB 0x00000000 2122#define BGE_SSRAMSIZE_512KB 0x00040000 2123#define BGE_SSRAMSIZE_1MB 0x00080000 2124#define BGE_SSRAMSIZE_2MB 0x000C0000 2125#define BGE_SSRAMSIZE_4MB 0x00100000 2126#define BGE_SSRAMSIZE_8MB 0x00140000 2127#define BGE_SSRAMSIZE_16M 0x00180000 2128 2129/* EEPROM address register */ 2130#define BGE_EEADDR_ADDRESS 0x0000FFFC 2131#define BGE_EEADDR_HALFCLK 0x01FF0000 2132#define BGE_EEADDR_START 0x02000000 2133#define BGE_EEADDR_DEVID 0x1C000000 2134#define BGE_EEADDR_RESET 0x20000000 2135#define BGE_EEADDR_DONE 0x40000000 2136#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 2137 2138#define BGE_EEDEVID(x) ((x & 7) << 26) 2139#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2140#define BGE_HALFCLK_384SCL 0x60 2141#define BGE_EE_READCMD \ 2142 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2143 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 2144#define BGE_EE_WRCMD \ 2145 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2146 BGE_EEADDR_START|BGE_EEADDR_DONE) 2147 2148/* EEPROM Control register */ 2149#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2150#define BGE_EECTL_CLKOUT 0x00000002 2151#define BGE_EECTL_CLKIN 0x00000004 2152#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2153#define BGE_EECTL_DATAOUT 0x00000010 2154#define BGE_EECTL_DATAIN 0x00000020 2155 2156/* MDI (MII/GMII) access register */ 2157#define BGE_MDI_DATA 0x00000001 2158#define BGE_MDI_DIR 0x00000002 2159#define BGE_MDI_SEL 0x00000004 2160#define BGE_MDI_CLK 0x00000008 2161 2162#define BGE_MEMWIN_START 0x00008000 2163#define BGE_MEMWIN_END 0x0000FFFF 2164 2165/* BAR1 (APE) Register Definitions */ 2166 2167#define BGE_APE_GPIO_MSG 0x0008 2168#define BGE_APE_EVENT 0x000C 2169#define BGE_APE_LOCK_REQ 0x002C 2170#define BGE_APE_LOCK_GRANT 0x004C 2171 2172#define BGE_APE_GPIO_MSG_SHIFT 4 2173 2174#define BGE_APE_EVENT_1 0x00000001 2175 2176#define BGE_APE_LOCK_REQ_DRIVER0 0x00001000 2177 2178#define BGE_APE_LOCK_GRANT_DRIVER0 0x00001000 2179 2180/* APE Shared Memory block (writable by APE only) */ 2181#define BGE_APE_SEG_SIG 0x4000 2182#define BGE_APE_FW_STATUS 0x400C 2183#define BGE_APE_FW_FEATURES 0x4010 2184#define BGE_APE_FW_BEHAVIOR 0x4014 2185#define BGE_APE_FW_VERSION 0x4018 2186#define BGE_APE_FW_HEARTBEAT_INTERVAL 0x4024 2187#define BGE_APE_FW_HEARTBEAT 0x4028 2188#define BGE_APE_FW_ERROR_FLAGS 0x4074 2189 2190#define BGE_APE_SEG_SIG_MAGIC 0x41504521 2191 2192#define BGE_APE_FW_STATUS_READY 0x00000100 2193 2194#define BGE_APE_FW_FEATURE_DASH 0x00000001 2195#define BGE_APE_FW_FEATURE_NCSI 0x00000002 2196 2197#define BGE_APE_FW_VERSION_MAJMSK 0xFF000000 2198#define BGE_APE_FW_VERSION_MAJSFT 24 2199#define BGE_APE_FW_VERSION_MINMSK 0x00FF0000 2200#define BGE_APE_FW_VERSION_MINSFT 16 2201#define BGE_APE_FW_VERSION_REVMSK 0x0000FF00 2202#define BGE_APE_FW_VERSION_REVSFT 8 2203#define BGE_APE_FW_VERSION_BLDMSK 0x000000FF 2204 2205/* Host Shared Memory block (writable by host only) */ 2206#define BGE_APE_HOST_SEG_SIG 0x4200 2207#define BGE_APE_HOST_SEG_LEN 0x4204 2208#define BGE_APE_HOST_INIT_COUNT 0x4208 2209#define BGE_APE_HOST_DRIVER_ID 0x420C 2210#define BGE_APE_HOST_BEHAVIOR 0x4210 2211#define BGE_APE_HOST_HEARTBEAT_INT_MS 0x4214 2212#define BGE_APE_HOST_HEARTBEAT_COUNT 0x4218 2213#define BGE_APE_HOST_DRVR_STATE 0x421C 2214#define BGE_APE_HOST_WOL_SPEED 0x4224 2215 2216#define BGE_APE_HOST_SEG_SIG_MAGIC 0x484F5354 2217 2218#define BGE_APE_HOST_SEG_LEN_MAGIC 0x00000020 2219 2220#define BGE_APE_HOST_DRIVER_ID_FBSD 0xF6000000 2221#define BGE_APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2222 (BGE_APE_HOST_DRIVER_ID_FBSD | \ 2223 ((maj) & 0xffd) << 16 | ((min) & 0xff) << 8) 2224 2225#define BGE_APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2226 2227#define BGE_APE_HOST_HEARTBEAT_INT_DISABLE 0 2228#define BGE_APE_HOST_HEARTBEAT_INT_5SEC 5000 2229 2230#define BGE_APE_HOST_DRVR_STATE_START 0x00000001 2231#define BGE_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2232#define BGE_APE_HOST_DRVR_STATE_WOL 0x00000003 2233#define BGE_APE_HOST_DRVR_STATE_SUSPEND 0x00000004 2234 2235#define BGE_APE_HOST_WOL_SPEED_AUTO 0x00008000 2236 2237#define BGE_APE_EVENT_STATUS 0x4300 2238 2239#define BGE_APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2240#define BGE_APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2241#define BGE_APE_EVENT_STATUS_STATE_START 0x00010000 2242#define BGE_APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2243#define BGE_APE_EVENT_STATUS_STATE_WOL 0x00030000 2244#define BGE_APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2245#define BGE_APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2246 2247#define BGE_APE_DEBUG_LOG 0x4E00 2248#define BGE_APE_DEBUG_LOG_LEN 0x0100 2249 2250#define BGE_APE_PER_LOCK_REQ 0x8400 2251#define BGE_APE_PER_LOCK_GRANT 0x8420 2252 2253#define BGE_APE_LOCK_PER_REQ_DRIVER0 0x00001000 2254#define BGE_APE_LOCK_PER_REQ_DRIVER1 0x00000002 2255#define BGE_APE_LOCK_PER_REQ_DRIVER2 0x00000004 2256#define BGE_APE_LOCK_PER_REQ_DRIVER3 0x00000008 2257 2258#define BGE_APE_PER_LOCK_GRANT_DRIVER0 0x00001000 2259#define BGE_APE_PER_LOCK_GRANT_DRIVER1 0x00000002 2260#define BGE_APE_PER_LOCK_GRANT_DRIVER2 0x00000004 2261#define BGE_APE_PER_LOCK_GRANT_DRIVER3 0x00000008 2262 2263/* APE Mutex Resources */ 2264#define BGE_APE_LOCK_PHY0 0 2265#define BGE_APE_LOCK_GRC 1 2266#define BGE_APE_LOCK_PHY1 2 2267#define BGE_APE_LOCK_PHY2 3 2268#define BGE_APE_LOCK_MEM 4 2269#define BGE_APE_LOCK_PHY3 5 2270#define BGE_APE_LOCK_GPIO 7 2271 2272#define BGE_MEMWIN_READ(pc, tag, x, val) \ 2273 do { \ 2274 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 2275 (0xFFFF8000 & x)); \ 2276 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0x7FFF)); \ 2277 } while(0) 2278 2279#define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 2280 do { \ 2281 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 2282 (0xFFFF8000 & x)); \ 2283 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0x7FFF), val); \ 2284 } while(0) 2285 2286/* 2287 * This magic number is written to the firmware mailbox at 0xb50 2288 * before a software reset is issued. After the internal firmware 2289 * has completed its initialization it will write the opposite of 2290 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 2291 * driver to synchronize with the firmware. 2292 */ 2293#define BGE_MAGIC_NUMBER 0x4B657654 2294 2295typedef struct { 2296 u_int32_t bge_addr_hi; 2297 u_int32_t bge_addr_lo; 2298} bge_hostaddr; 2299#define BGE_HOSTADDR(x,y) \ 2300 do { \ 2301 (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 2302 if (sizeof(bus_addr_t) == 8) \ 2303 (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 2304 else \ 2305 (x).bge_addr_hi = 0; \ 2306 } while(0) 2307 2308/* Ring control block structure */ 2309struct bge_rcb { 2310 bge_hostaddr bge_hostaddr; 2311 u_int32_t bge_maxlen_flags; 2312 u_int32_t bge_nicaddr; 2313}; 2314 2315#define RCB_WRITE_4(sc, rcb, offset, val) \ 2316 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 2317 rcb + offsetof(struct bge_rcb, offset), val) 2318 2319#define RCB_WRITE_2(sc, rcb, offset, val) \ 2320 bus_space_write_2(sc->bge_btag, sc->bge_bhandle, \ 2321 rcb + offsetof(struct bge_rcb, offset), val) 2322 2323#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 2324 2325#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2326#define BGE_RCB_FLAG_RING_DISABLED 0x0002 2327 2328struct bge_tx_bd { 2329 bge_hostaddr bge_addr; 2330#if BYTE_ORDER == LITTLE_ENDIAN 2331 u_int16_t bge_flags; 2332 u_int16_t bge_len; 2333 u_int16_t bge_vlan_tag; 2334 u_int16_t bge_rsvd; 2335#else 2336 u_int16_t bge_len; 2337 u_int16_t bge_flags; 2338 u_int16_t bge_rsvd; 2339 u_int16_t bge_vlan_tag; 2340#endif 2341}; 2342 2343#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2344#define BGE_TXBDFLAG_IP_CSUM 0x0002 2345#define BGE_TXBDFLAG_END 0x0004 2346#define BGE_TXBDFLAG_IP_FRAG 0x0008 2347#define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */ 2348#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2349#define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 /* 5717 */ 2350#define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */ 2351#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2352#define BGE_TXBDFLAG_COAL_NOW 0x0080 2353#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2354#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2355#define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 /* 5717 */ 2356#define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 /* 5717 */ 2357#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2358#define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 /* 5717 */ 2359#define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 /* 5717 */ 2360#define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 /* 5717 */ 2361#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2362#define BGE_TXBDFLAG_NO_CRC 0x8000 2363 2364#define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */ 2365/* Bits [1:0] of the MSS header length. */ 2366#define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */ 2367 2368#define BGE_NIC_TXRING_ADDR(ringno, size) \ 2369 BGE_SEND_RING_1_TO_4 + \ 2370 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2371 2372struct bge_rx_bd { 2373 bge_hostaddr bge_addr; 2374#if BYTE_ORDER == LITTLE_ENDIAN 2375 u_int16_t bge_len; 2376 u_int16_t bge_idx; 2377 u_int16_t bge_flags; 2378 u_int16_t bge_type; 2379 u_int16_t bge_tcp_udp_csum; 2380 u_int16_t bge_ip_csum; 2381 u_int16_t bge_vlan_tag; 2382 u_int16_t bge_error_flag; 2383#else 2384 u_int16_t bge_idx; 2385 u_int16_t bge_len; 2386 u_int16_t bge_type; 2387 u_int16_t bge_flags; 2388 u_int16_t bge_ip_csum; 2389 u_int16_t bge_tcp_udp_csum; 2390 u_int16_t bge_error_flag; 2391 u_int16_t bge_vlan_tag; 2392#endif 2393 u_int32_t bge_rsvd; 2394 u_int32_t bge_opaque; 2395}; 2396 2397struct bge_ext_rx_bd { 2398 bge_hostaddr bge_addr1; 2399 bge_hostaddr bge_addr2; 2400 bge_hostaddr bge_addr3; 2401#if BYTE_ORDER == LITTLE_ENDIAN 2402 u_int16_t bge_len2; 2403 u_int16_t bge_len1; 2404 u_int16_t bge_rsvd; 2405 u_int16_t bge_len3; 2406#else 2407 u_int16_t bge_len1; 2408 u_int16_t bge_len2; 2409 u_int16_t bge_len3; 2410 u_int16_t bge_rsvd; 2411#endif 2412 struct bge_rx_bd bge_bd; 2413}; 2414 2415#define BGE_RXBDFLAG_END 0x0004 2416#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2417#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2418#define BGE_RXBDFLAG_ERROR 0x0400 2419#define BGE_RXBDFLAG_MINI_RING 0x0800 2420#define BGE_RXBDFLAG_IP_CSUM 0x1000 2421#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2422#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2423#define BGE_RXBDFLAG_IPV6 0x8000 2424 2425#define BGE_RXERRFLAG_BAD_CRC 0x0001 2426#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2427#define BGE_RXERRFLAG_LINK_LOST 0x0004 2428#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2429#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2430#define BGE_RXERRFLAG_RUNT 0x0020 2431#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2432#define BGE_RXERRFLAG_GIANT 0x0080 2433#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ 2434 2435struct bge_sts_idx { 2436#if BYTE_ORDER == LITTLE_ENDIAN 2437 u_int16_t bge_rx_prod_idx; 2438 u_int16_t bge_tx_cons_idx; 2439#else 2440 u_int16_t bge_tx_cons_idx; 2441 u_int16_t bge_rx_prod_idx; 2442#endif 2443}; 2444 2445struct bge_status_block { 2446 u_int32_t bge_status; 2447 u_int32_t bge_status_tag; 2448#if BYTE_ORDER == LITTLE_ENDIAN 2449 u_int16_t bge_rx_jumbo_cons_idx; 2450 u_int16_t bge_rx_std_cons_idx; 2451 u_int16_t bge_rx_mini_cons_idx; 2452 u_int16_t bge_rsvd1; 2453#else 2454 u_int16_t bge_rx_std_cons_idx; 2455 u_int16_t bge_rx_jumbo_cons_idx; 2456 u_int16_t bge_rsvd1; 2457 u_int16_t bge_rx_mini_cons_idx; 2458#endif 2459 struct bge_sts_idx bge_idx[16]; 2460}; 2461 2462#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 2463#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 2464 2465#define BGE_STATFLAG_UPDATED 0x00000001 2466#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2467#define BGE_STATFLAG_ERROR 0x00000004 2468 2469/* 2470 * SysKonnect Subsystem IDs 2471 */ 2472#define SK_SUBSYSID_9D41 0x4441 2473 2474/* 2475 * Dell PCI vendor ID 2476 */ 2477#define DELL_VENDORID 0x1028 2478 2479/* 2480 * Offset of MAC address inside EEPROM. 2481 */ 2482#define BGE_EE_MAC_OFFSET 0x7C 2483#define BGE_EE_MAC_OFFSET_5906 0x10 2484#define BGE_EE_HWCFG_OFFSET 0xC8 2485 2486#define BGE_HWCFG_VOLTAGE 0x00000003 2487#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2488#define BGE_HWCFG_MEDIA 0x00000030 2489#define BGE_HWCFG_ASF 0x00000080 2490 2491#define BGE_VOLTAGE_1POINT3 0x00000000 2492#define BGE_VOLTAGE_1POINT8 0x00000001 2493 2494#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2495#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2496#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2497 2498#define BGE_MEDIA_UNSPEC 0x00000000 2499#define BGE_MEDIA_COPPER 0x00000010 2500#define BGE_MEDIA_FIBER 0x00000020 2501 2502#define BGE_TICKS_PER_SEC 1000000 2503 2504/* 2505 * Ring size constants. 2506 */ 2507#define BGE_EVENT_RING_CNT 256 2508#define BGE_CMD_RING_CNT 64 2509#define BGE_STD_RX_RING_CNT 512 2510#define BGE_JUMBO_RX_RING_CNT 256 2511#define BGE_MINI_RX_RING_CNT 1024 2512#define BGE_RETURN_RING_CNT 1024 2513 2514/* 5705 has smaller return ring size */ 2515#define BGE_RETURN_RING_CNT_5705 512 2516 2517/* 2518 * Possible TX ring sizes. 2519 */ 2520#define BGE_TX_RING_CNT_128 128 2521#define BGE_TX_RING_BASE_128 0x3800 2522 2523#define BGE_TX_RING_CNT_256 256 2524#define BGE_TX_RING_BASE_256 0x3000 2525 2526#define BGE_TX_RING_CNT_512 512 2527#define BGE_TX_RING_BASE_512 0x2000 2528 2529#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2530#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2531 2532/* 2533 * Tigon III statistics counters. 2534 */ 2535/* Statistics maintained MAC Receive block. */ 2536struct bge_rx_mac_stats { 2537 bge_hostaddr ifHCInOctets; 2538 bge_hostaddr Reserved1; 2539 bge_hostaddr etherStatsFragments; 2540 bge_hostaddr ifHCInUcastPkts; 2541 bge_hostaddr ifHCInMulticastPkts; 2542 bge_hostaddr ifHCInBroadcastPkts; 2543 bge_hostaddr dot3StatsFCSErrors; 2544 bge_hostaddr dot3StatsAlignmentErrors; 2545 bge_hostaddr xonPauseFramesReceived; 2546 bge_hostaddr xoffPauseFramesReceived; 2547 bge_hostaddr macControlFramesReceived; 2548 bge_hostaddr xoffStateEntered; 2549 bge_hostaddr dot3StatsFramesTooLong; 2550 bge_hostaddr etherStatsJabbers; 2551 bge_hostaddr etherStatsUndersizePkts; 2552 bge_hostaddr inRangeLengthError; 2553 bge_hostaddr outRangeLengthError; 2554 bge_hostaddr etherStatsPkts64Octets; 2555 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2556 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2557 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2558 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2559 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2560 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2561 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2562 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2563 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2564}; 2565 2566/* Statistics maintained MAC Transmit block. */ 2567struct bge_tx_mac_stats { 2568 bge_hostaddr ifHCOutOctets; 2569 bge_hostaddr Reserved2; 2570 bge_hostaddr etherStatsCollisions; 2571 bge_hostaddr outXonSent; 2572 bge_hostaddr outXoffSent; 2573 bge_hostaddr flowControlDone; 2574 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2575 bge_hostaddr dot3StatsSingleCollisionFrames; 2576 bge_hostaddr dot3StatsMultipleCollisionFrames; 2577 bge_hostaddr dot3StatsDeferredTransmissions; 2578 bge_hostaddr Reserved3; 2579 bge_hostaddr dot3StatsExcessiveCollisions; 2580 bge_hostaddr dot3StatsLateCollisions; 2581 bge_hostaddr dot3Collided2Times; 2582 bge_hostaddr dot3Collided3Times; 2583 bge_hostaddr dot3Collided4Times; 2584 bge_hostaddr dot3Collided5Times; 2585 bge_hostaddr dot3Collided6Times; 2586 bge_hostaddr dot3Collided7Times; 2587 bge_hostaddr dot3Collided8Times; 2588 bge_hostaddr dot3Collided9Times; 2589 bge_hostaddr dot3Collided10Times; 2590 bge_hostaddr dot3Collided11Times; 2591 bge_hostaddr dot3Collided12Times; 2592 bge_hostaddr dot3Collided13Times; 2593 bge_hostaddr dot3Collided14Times; 2594 bge_hostaddr dot3Collided15Times; 2595 bge_hostaddr ifHCOutUcastPkts; 2596 bge_hostaddr ifHCOutMulticastPkts; 2597 bge_hostaddr ifHCOutBroadcastPkts; 2598 bge_hostaddr dot3StatsCarrierSenseErrors; 2599 bge_hostaddr ifOutDiscards; 2600 bge_hostaddr ifOutErrors; 2601}; 2602 2603/* Stats counters access through registers */ 2604struct bge_mac_stats_regs { 2605 u_int32_t ifHCOutOctets; 2606 u_int32_t Reserved0; 2607 u_int32_t etherStatsCollisions; 2608 u_int32_t outXonSent; 2609 u_int32_t outXoffSent; 2610 u_int32_t Reserved1; 2611 u_int32_t dot3StatsInternalMacTransmitErrors; 2612 u_int32_t dot3StatsSingleCollisionFrames; 2613 u_int32_t dot3StatsMultipleCollisionFrames; 2614 u_int32_t dot3StatsDeferredTransmissions; 2615 u_int32_t Reserved2; 2616 u_int32_t dot3StatsExcessiveCollisions; 2617 u_int32_t dot3StatsLateCollisions; 2618 u_int32_t Reserved3[14]; 2619 u_int32_t ifHCOutUcastPkts; 2620 u_int32_t ifHCOutMulticastPkts; 2621 u_int32_t ifHCOutBroadcastPkts; 2622 u_int32_t Reserved4[2]; 2623 u_int32_t ifHCInOctets; 2624 u_int32_t Reserved5; 2625 u_int32_t etherStatsFragments; 2626 u_int32_t ifHCInUcastPkts; 2627 u_int32_t ifHCInMulticastPkts; 2628 u_int32_t ifHCInBroadcastPkts; 2629 u_int32_t dot3StatsFCSErrors; 2630 u_int32_t dot3StatsAlignmentErrors; 2631 u_int32_t xonPauseFramesReceived; 2632 u_int32_t xoffPauseFramesReceived; 2633 u_int32_t macControlFramesReceived; 2634 u_int32_t xoffStateEntered; 2635 u_int32_t dot3StatsFramesTooLong; 2636 u_int32_t etherStatsJabbers; 2637 u_int32_t etherStatsUndersizePkts; 2638}; 2639 2640struct bge_stats { 2641 u_int8_t Reserved0[256]; 2642 2643 /* Statistics maintained by Receive MAC. */ 2644 struct bge_rx_mac_stats rxstats; 2645 2646 bge_hostaddr Unused1[37]; 2647 2648 /* Statistics maintained by Transmit MAC. */ 2649 struct bge_tx_mac_stats txstats; 2650 2651 bge_hostaddr Unused2[31]; 2652 2653 /* Statistics maintained by Receive List Placement. */ 2654 bge_hostaddr COSIfHCInPkts[16]; 2655 bge_hostaddr COSFramesDroppedDueToFilters; 2656 bge_hostaddr nicDmaWriteQueueFull; 2657 bge_hostaddr nicDmaWriteHighPriQueueFull; 2658 bge_hostaddr nicNoMoreRxBDs; 2659 bge_hostaddr ifInDiscards; 2660 bge_hostaddr ifInErrors; 2661 bge_hostaddr nicRecvThresholdHit; 2662 2663 bge_hostaddr Unused3[9]; 2664 2665 /* Statistics maintained by Send Data Initiator. */ 2666 bge_hostaddr COSIfHCOutPkts[16]; 2667 bge_hostaddr nicDmaReadQueueFull; 2668 bge_hostaddr nicDmaReadHighPriQueueFull; 2669 bge_hostaddr nicSendDataCompQueueFull; 2670 2671 /* Statistics maintained by Host Coalescing. */ 2672 bge_hostaddr nicRingSetSendProdIndex; 2673 bge_hostaddr nicRingStatusUpdate; 2674 bge_hostaddr nicInterrupts; 2675 bge_hostaddr nicAvoidedInterrupts; 2676 bge_hostaddr nicSendThresholdHit; 2677 2678 u_int8_t Reserved4[320]; 2679}; 2680 2681/* 2682 * Tigon general information block. This resides in host memory 2683 * and contains the status counters, ring control blocks and 2684 * producer pointers. 2685 */ 2686 2687struct bge_gib { 2688 struct bge_stats bge_stats; 2689 struct bge_rcb bge_tx_rcb[16]; 2690 struct bge_rcb bge_std_rx_rcb; 2691 struct bge_rcb bge_jumbo_rx_rcb; 2692 struct bge_rcb bge_mini_rx_rcb; 2693 struct bge_rcb bge_return_rcb; 2694}; 2695 2696/* 2697 * NOTE! On the Alpha, we have an alignment constraint. 2698 * The first thing in the packet is a 14-byte Ethernet header. 2699 * This means that the packet is misaligned. To compensate, 2700 * we actually offset the data 2 bytes into the cluster. This 2701 * aligns the packet after the Ethernet header to a 32-bit 2702 * boundary. 2703 */ 2704 2705#define BGE_JUMBO_FRAMELEN 9022 2706#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 2707#define BGE_PAGE_SIZE PAGE_SIZE 2708 2709/* 2710 * Other utility macros. 2711 */ 2712#define BGE_INC(x, y) (x) = (x + 1) % y 2713 2714/* 2715 * Vital product data and structures. 2716 */ 2717#define BGE_VPD_FLAG 0x8000 2718 2719#define VPD_RES_ID 0x82 /* ID string */ 2720#define VPD_RES_READ 0x90 /* start of read only area */ 2721#define VPD_RES_WRITE 0x81 /* start of read/write area */ 2722#define VPD_RES_END 0x78 /* end tag */ 2723 2724/* 2725 * Register access macros. The Tigon always uses memory mapped register 2726 * accesses and all registers must be accessed with 32 bit operations. 2727 */ 2728 2729#define CSR_WRITE_4(sc, reg, val) \ 2730 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2731 2732#define CSR_READ_4(sc, reg) \ 2733 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2734 2735#define BGE_SETBIT(sc, reg, x) \ 2736 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2737#define BGE_CLRBIT(sc, reg, x) \ 2738 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2739 2740/* BAR2 APE register access macros. */ 2741#define APE_WRITE_4(sc, reg, val) \ 2742 bus_space_write_4(sc->bge_apetag, sc->bge_apehandle, reg, val) 2743 2744#define APE_READ_4(sc, reg) \ 2745 bus_space_read_4(sc->bge_apetag, sc->bge_apehandle, reg) 2746 2747#define APE_SETBIT(sc, reg, x) \ 2748 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x))) 2749#define APE_CLRBIT(sc, reg, x) \ 2750 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x))) 2751 2752#define PCI_SETBIT(pc, tag, reg, x) \ 2753 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 2754#define PCI_CLRBIT(pc, tag, reg, x) \ 2755 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 2756 2757/* 2758 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2759 * values are tuneable. They control the actual amount of buffers 2760 * allocated for the standard, mini and jumbo receive rings. 2761 */ 2762 2763#define BGE_SSLOTS 256 2764#define BGE_MSLOTS 256 2765#define BGE_JSLOTS 384 2766 2767#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2768#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2769 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2770 2771/* 2772 * Ring structures. Most of these reside in host memory and we tell 2773 * the NIC where they are via the ring control blocks. The exceptions 2774 * are the tx and command rings, which live in NIC memory and which 2775 * we access via the shared memory window. 2776 */ 2777struct bge_ring_data { 2778 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2779 struct bge_ext_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2780 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2781 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2782 struct bge_status_block bge_status_block; 2783 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2784 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2785 struct bge_gib bge_info; 2786}; 2787 2788#define BGE_RING_DMA_ADDR(sc, offset) \ 2789 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2790 offsetof(struct bge_ring_data, offset)) 2791 2792/* 2793 * Number of DMA segments in a TxCB. Note that this is carefully 2794 * chosen to make the total struct size an even power of two. It's 2795 * critical that no TxCB be split across a page boundary since 2796 * no attempt is made to allocate physically contiguous memory. 2797 * 2798 */ 2799#ifdef __LP64__ 2800#define BGE_NTXSEG 30 2801#else 2802#define BGE_NTXSEG 31 2803#endif 2804 2805#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2806 2807#define BGE_STATS_SZ sizeof (struct bge_stats) 2808 2809/* 2810 * Mbuf pointers. We need these to keep track of the virtual addresses 2811 * of our mbuf chains since we can only convert from physical to virtual, 2812 * not the other way around. 2813 */ 2814struct bge_chain_data { 2815 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2816 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2817 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2818 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2819 bus_dmamap_t bge_tx_map[BGE_TX_RING_CNT]; 2820 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2821 bus_dmamap_t bge_rx_jumbo_map[BGE_JUMBO_RX_RING_CNT]; 2822}; 2823 2824struct bge_type { 2825 u_int16_t bge_vid; 2826 u_int16_t bge_did; 2827 char *bge_name; 2828}; 2829 2830#define BGE_TIMEOUT 100000 2831#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2832 2833#define ASF_ENABLE 1 2834#define ASF_NEW_HANDSHAKE 2 2835#define ASF_STACKUP 4 2836 2837struct bge_softc { 2838 struct device bge_dev; 2839 struct arpcom arpcom; /* interface info */ 2840 bus_space_handle_t bge_bhandle; 2841 bus_space_tag_t bge_btag; 2842 bus_size_t bge_bsize; 2843 bus_space_handle_t bge_apehandle; 2844 bus_space_tag_t bge_apetag; 2845 bus_size_t bge_apesize; 2846 void *bge_intrhand; 2847 struct pci_attach_args bge_pa; 2848 struct mii_data bge_mii; 2849 struct ifmedia bge_ifmedia; /* media info */ 2850 u_int32_t bge_expcap; 2851 u_int32_t bge_msicap; 2852 u_int32_t bge_mps; 2853 u_int32_t bge_expmrq; 2854 u_int32_t bge_lasttag; 2855 u_int32_t bge_flags; 2856#define BGE_TXRING_VALID 0x00000001 2857#define BGE_RXRING_VALID 0x00000002 2858#define BGE_JUMBO_RXRING_VALID 0x00000004 2859#define BGE_RX_ALIGNBUG 0x00000008 2860#define BGE_PCIX 0x00000010 2861#define BGE_PCIE 0x00000020 2862#define BGE_ASF_MODE 0x00000040 2863#define BGE_NO_EEPROM 0x00000080 2864#define BGE_JUMBO_CAPABLE 0x00000100 2865#define BGE_FIBER_TBI 0x00000200 2866#define BGE_FIBER_MII 0x00000400 2867#define BGE_IS_5788 0x00000800 2868#define BGE_5705_PLUS 0x00001000 2869#define BGE_575X_PLUS 0x00002000 2870#define BGE_5755_PLUS 0x00004000 2871#define BGE_5714_FAMILY 0x00008000 2872#define BGE_5700_FAMILY 0x00010000 2873#define BGE_5717_PLUS 0x00020000 2874#define BGE_57765_PLUS 0x00040000 2875#define BGE_APE 0x00080000 2876#define BGE_CPMU_PRESENT 0x00100000 2877#define BGE_TAGGED_STATUS 0x00200000 2878#define BGE_MSI 0x00400000 2879#define BGE_RDMA_BUG 0x00800000 2880#define BGE_JUMBO_RING 0x01000000 2881#define BGE_JUMBO_STD 0x02000000 2882#define BGE_JUMBO_FRAME 0x04000000 2883 2884 u_int32_t bge_phy_flags; 2885#define BGE_PHY_NO_3LED 0x00000001 2886#define BGE_PHY_10_100_ONLY 0x00000002 2887#define BGE_PHY_CRC_BUG 0x00000004 2888#define BGE_PHY_ADC_BUG 0x00000008 2889#define BGE_PHY_5704_A0_BUG 0x00008010 2890#define BGE_PHY_JITTER_BUG 0x00000020 2891#define BGE_PHY_BER_BUG 0x00000040 2892#define BGE_PHY_ADJUST_TRIM 0x00000080 2893#define BGE_PHY_NO_WIRESPEED 0x00000100 2894 2895 bus_dma_tag_t bge_dmatag; 2896 u_int32_t bge_mfw_flags; /* Management F/W flags */ 2897#define BGE_MFW_ON_RXCPU 0x00000001 2898#define BGE_MFW_ON_APE 0x00000002 2899#define BGE_MFW_TYPE_NCSI 0x00000004 2900#define BGE_MFW_TYPE_DASH 0x00000008 2901 int bge_phy_ape_lock; 2902 int bge_phy_addr; 2903 u_int32_t bge_chipid; 2904 struct bge_ring_data *bge_rdata; /* rings */ 2905 struct bge_chain_data bge_cdata; /* mbufs */ 2906 bus_dmamap_t bge_ring_map; 2907 bus_dma_segment_t bge_ring_seg; 2908 int bge_ring_nseg; 2909 u_int16_t bge_tx_saved_considx; 2910 u_int16_t bge_rx_saved_considx; 2911 u_int16_t bge_ev_saved_considx; 2912 u_int16_t bge_return_ring_cnt; 2913 u_int32_t bge_tx_prodidx; 2914 struct if_rxring bge_std_ring; 2915 u_int16_t bge_std; /* current std ring head */ 2916 int bge_rx_std_len; 2917 struct if_rxring bge_jumbo_ring; 2918 u_int16_t bge_jumbo; /* current jumo ring head */ 2919 u_int32_t bge_stat_ticks; 2920 u_int32_t bge_rx_coal_ticks; 2921 u_int32_t bge_tx_coal_ticks; 2922 u_int32_t bge_rx_max_coal_bds; 2923 u_int32_t bge_tx_max_coal_bds; 2924 u_int32_t bge_tx_buf_ratio; 2925 u_int32_t bge_sts; 2926#define BGE_STS_LINK 0x00000001 /* MAC link status */ 2927#define BGE_STS_LINK_EVT 0x00000002 /* pending link event */ 2928#define BGE_STS_AUTOPOLL 0x00000004 /* PHY auto-polling */ 2929#define BGE_STS_BIT(sc, x) ((sc)->bge_sts & (x)) 2930#define BGE_STS_SETBIT(sc, x) ((sc)->bge_sts |= (x)) 2931#define BGE_STS_CLRBIT(sc, x) ((sc)->bge_sts &= ~(x)) 2932 uint64_t bge_flowflags; 2933 int bge_txcnt; 2934 struct timeout bge_timeout; 2935 struct timeout bge_rxtimeout; 2936 struct timeout bge_rxtimeout_jumbo; 2937 u_int32_t bge_rx_discards; 2938 u_int32_t bge_tx_discards; 2939 u_int32_t bge_rx_inerrors; 2940 u_int32_t bge_rx_overruns; 2941 u_int32_t bge_tx_collisions; 2942 bus_dmamap_t bge_txdma[BGE_TX_RING_CNT]; 2943}; 2944