if_bgereg.h revision 1.112
1/* $OpenBSD: if_bgereg.h,v 1.112 2013/02/09 23:39:38 brad Exp $ */ 2 3/* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bgereg.h,v 1.11 2002/11/14 23:54:50 sam Exp $ 36 */ 37 38/* 39 * BCM570x memory map. The internal memory layout varies somewhat 40 * depending on whether or not we have external SSRAM attached. 41 * The BCM5700 can have up to 16MB of external memory. The BCM5701 42 * is apparently not designed to use external SSRAM. The mappings 43 * up to the first 4 send rings are the same for both internal and 44 * external memory configurations. Note that mini RX ring space is 45 * only available with external SSRAM configurations, which means 46 * the mini RX ring is not supported on the BCM5701. 47 * 48 * The NIC's memory can be accessed by the host in one of 3 ways: 49 * 50 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 51 * registers in PCI config space can be used to read any 32-bit 52 * address within the NIC's memory. 53 * 54 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 55 * space can be used in conjunction with the memory window in the 56 * device register space at offset 0x8000 to read any 32K chunk 57 * of NIC memory. 58 * 59 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 60 * set, the device I/O mapping consumes 32MB of host address space, 61 * allowing all of the registers and internal NIC memory to be 62 * accessed directly. NIC memory addresses are offset by 0x01000000. 63 * Flat mode consumes so much host address space that it is not 64 * recommended. 65 */ 66#define BGE_PAGE_ZERO 0x00000000 67#define BGE_PAGE_ZERO_END 0x000000FF 68#define BGE_SEND_RING_RCB 0x00000100 69#define BGE_SEND_RING_RCB_END 0x000001FF 70#define BGE_RX_RETURN_RING_RCB 0x00000200 71#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 72#define BGE_STATS_BLOCK 0x00000300 73#define BGE_STATS_BLOCK_END 0x00000AFF 74#define BGE_STATUS_BLOCK 0x00000B00 75#define BGE_STATUS_BLOCK_END 0x00000B4F 76#define BGE_SOFTWARE_GENCOMM 0x00000B50 77#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 78#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 79#define BGE_SOFTWARE_GENCOMM_VER 0x00000B5C 80#define BGE_VER_SHIFT 16 81#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 82#define BGE_FW_PAUSE 0x00000002 83#define BGE_SOFTWARE_GENCOMM_NICCFG2 0x00000D38 84#define BGE_SOFTWARE_GENCOMM_NICCFG3 0x00000D3C 85#define BGE_SOFTWARE_GENCOMM_NICCFG4 0x00000D60 86#define BGE_NICCFG4_GMII_MODE 0x00000002 87#define BGE_NICCFG4_RGMII_STD_IBND_DISABLE 0x00000004 88#define BGE_NICCFG4_RGMII_EXT_IBND_RX_EN 0x00000008 89#define BGE_NICCFG4_RGMII_EXT_IBND_TX_EN 0x00000010 90#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 91#define BGE_UNMAPPED 0x00001000 92#define BGE_UNMAPPED_END 0x00001FFF 93#define BGE_DMA_DESCRIPTORS 0x00002000 94#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 95#define BGE_SEND_RING_5717 0x00004000 96#define BGE_SEND_RING_1_TO_4 0x00004000 97#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 98 99/* Mappings for internal memory configuration */ 100#define BGE_STD_RX_RINGS 0x00006000 101#define BGE_STD_RX_RINGS_END 0x00006FFF 102#define BGE_JUMBO_RX_RINGS 0x00007000 103#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 104#define BGE_BUFFPOOL_1 0x00008000 105#define BGE_BUFFPOOL_1_END 0x0000FFFF 106#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 107#define BGE_BUFFPOOL_2_END 0x00017FFF 108#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 109#define BGE_BUFFPOOL_3_END 0x0001FFFF 110#define BGE_STD_RX_RINGS_5717 0x00040000 111#define BGE_JUMBO_RX_RINGS_5717 0x00044400 112 113/* Mappings for external SSRAM configurations */ 114#define BGE_SEND_RING_5_TO_6 0x00006000 115#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 116#define BGE_SEND_RING_7_TO_8 0x00007000 117#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 118#define BGE_SEND_RING_9_TO_16 0x00008000 119#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 120#define BGE_EXT_STD_RX_RINGS 0x0000C000 121#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 122#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 123#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 124#define BGE_MINI_RX_RINGS 0x0000E000 125#define BGE_MINI_RX_RINGS_END 0x0000FFFF 126#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 127#define BGE_AVAIL_REGION1_END 0x00017FFF 128#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 129#define BGE_AVAIL_REGION2_END 0x0001FFFF 130#define BGE_EXT_SSRAM 0x00020000 131#define BGE_EXT_SSRAM_END 0x000FFFFF 132 133 134/* 135 * BCM570x register offsets. These are memory mapped registers 136 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 137 * Each register must be accessed using 32 bit operations. 138 * 139 * All registers are accessed through a 32K shared memory block. 140 * The first group of registers are actually copies of the PCI 141 * configuration space registers. 142 */ 143 144/* 145 * PCI registers defined in the PCI 2.2 spec. 146 */ 147#define BGE_PCI_VID 0x00 148#define BGE_PCI_DID 0x02 149#define BGE_PCI_CMD 0x04 150#define BGE_PCI_STS 0x06 151#define BGE_PCI_REV 0x08 152#define BGE_PCI_CLASS 0x09 153#define BGE_PCI_CACHESZ 0x0C 154#define BGE_PCI_LATTIMER 0x0D 155#define BGE_PCI_HDRTYPE 0x0E 156#define BGE_PCI_BIST 0x0F 157#define BGE_PCI_BAR0 0x10 158#define BGE_PCI_BAR1 0x14 159#define BGE_PCI_SUBSYS 0x2C 160#define BGE_PCI_SUBVID 0x2E 161#define BGE_PCI_ROMBASE 0x30 162#define BGE_PCI_CAPPTR 0x34 163#define BGE_PCI_INTLINE 0x3C 164#define BGE_PCI_INTPIN 0x3D 165#define BGE_PCI_MINGNT 0x3E 166#define BGE_PCI_MAXLAT 0x3F 167#define BGE_PCI_PCIXCAP 0x40 168#define BGE_PCI_NEXTPTR_PM 0x41 169#define BGE_PCI_PCIX_CMD 0x42 170#define BGE_PCI_PCIX_STS 0x44 171#define BGE_PCI_PWRMGMT_CAPID 0x48 172#define BGE_PCI_NEXTPTR_VPD 0x49 173#define BGE_PCI_PWRMGMT_CAPS 0x4A 174#define BGE_PCI_PWRMGMT_CMD 0x4C 175#define BGE_PCI_PWRMGMT_STS 0x4D 176#define BGE_PCI_PWRMGMT_DATA 0x4F 177#define BGE_PCI_VPD_CAPID 0x50 178#define BGE_PCI_NEXTPTR_MSI 0x51 179#define BGE_PCI_VPD_ADDR 0x52 180#define BGE_PCI_VPD_DATA 0x54 181#define BGE_PCI_MSI_CAPID 0x58 182#define BGE_PCI_NEXTPTR_NONE 0x59 183#define BGE_PCI_MSI_CTL 0x5A 184#define BGE_PCI_MSI_ADDR_HI 0x5C 185#define BGE_PCI_MSI_ADDR_LO 0x60 186#define BGE_PCI_MSI_DATA 0x64 187 188/* PCI MSI. ??? */ 189#define BGE_PCIE_CAPID_REG 0xD0 190#define BGE_PCIE_CAPID 0x10 191 192/* 193 * PCI registers specific to the BCM570x family. 194 */ 195#define BGE_PCI_MISC_CTL 0x68 196#define BGE_PCI_DMA_RW_CTL 0x6C 197#define BGE_PCI_PCISTATE 0x70 198#define BGE_PCI_CLKCTL 0x74 199#define BGE_PCI_REG_BASEADDR 0x78 200#define BGE_PCI_MEMWIN_BASEADDR 0x7C 201#define BGE_PCI_REG_DATA 0x80 202#define BGE_PCI_MEMWIN_DATA 0x84 203#define BGE_PCI_MODECTL 0x88 204#define BGE_PCI_MISC_CFG 0x8C 205#define BGE_PCI_MISC_LOCALCTL 0x90 206#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 207#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 208#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 209#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 210#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 211#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 212#define BGE_PCI_ISR_MBX_HI 0xB0 213#define BGE_PCI_ISR_MBX_LO 0xB4 214#define BGE_PCI_PRODID_ASICREV 0xBC 215#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 216#define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 217 218/* XXX: 219 * Used in PCI-Express code for 575x chips. 220 * Should be replaced with checking for a PCI config-space 221 * capability for PCI-Express, and PCI-Express standard 222 * offsets into that capability block. 223 */ 224#define BGE_PCI_CONF_DEV_CTRL 0xD8 225#define BGE_PCI_CONF_DEV_STUS 0xDA 226 227/* PCI Misc. Host control register */ 228#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 229#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 230#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 231#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 232#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 233#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 234#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 235#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 236#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 237#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 238 239#if BYTE_ORDER == LITTLE_ENDIAN 240#define BGE_DMA_SWAP_OPTIONS \ 241 BGE_MODECTL_WORDSWAP_NONFRAME| \ 242 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 243#else 244#define BGE_DMA_SWAP_OPTIONS \ 245 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 246 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 247#endif 248 249#define BGE_INIT \ 250 (BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 251 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 252 253#define BGE_CHIPID_BCM5700_A0 0x7000 254#define BGE_CHIPID_BCM5700_A1 0x7001 255#define BGE_CHIPID_BCM5700_B0 0x7100 256#define BGE_CHIPID_BCM5700_B1 0x7101 257#define BGE_CHIPID_BCM5700_B2 0x7102 258#define BGE_CHIPID_BCM5700_B3 0x7103 259#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 260#define BGE_CHIPID_BCM5700_C0 0x7200 261#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 262#define BGE_CHIPID_BCM5701_B0 0x0100 263#define BGE_CHIPID_BCM5701_B2 0x0102 264#define BGE_CHIPID_BCM5701_B5 0x0105 265#define BGE_CHIPID_BCM5703_A0 0x1000 266#define BGE_CHIPID_BCM5703_A1 0x1001 267#define BGE_CHIPID_BCM5703_A2 0x1002 268#define BGE_CHIPID_BCM5703_A3 0x1003 269#define BGE_CHIPID_BCM5703_B0 0x1100 270#define BGE_CHIPID_BCM5704_A0 0x2000 271#define BGE_CHIPID_BCM5704_A1 0x2001 272#define BGE_CHIPID_BCM5704_A2 0x2002 273#define BGE_CHIPID_BCM5704_A3 0x2003 274#define BGE_CHIPID_BCM5704_B0 0x2100 275#define BGE_CHIPID_BCM5705_A0 0x3000 276#define BGE_CHIPID_BCM5705_A1 0x3001 277#define BGE_CHIPID_BCM5705_A2 0x3002 278#define BGE_CHIPID_BCM5705_A3 0x3003 279#define BGE_CHIPID_BCM5750_A0 0x4000 280#define BGE_CHIPID_BCM5750_A1 0x4001 281#define BGE_CHIPID_BCM5750_A3 0x4003 282#define BGE_CHIPID_BCM5750_B0 0x4010 283#define BGE_CHIPID_BCM5750_B1 0x4101 284#define BGE_CHIPID_BCM5750_C0 0x4200 285#define BGE_CHIPID_BCM5750_C1 0x4201 286#define BGE_CHIPID_BCM5750_C2 0x4202 287#define BGE_CHIPID_BCM5714_A0 0x5000 288#define BGE_CHIPID_BCM5752_A0 0x6000 289#define BGE_CHIPID_BCM5752_A1 0x6001 290#define BGE_CHIPID_BCM5752_A2 0x6002 291#define BGE_CHIPID_BCM5714_B0 0x8000 292#define BGE_CHIPID_BCM5714_B3 0x8003 293#define BGE_CHIPID_BCM5715_A0 0x9000 294#define BGE_CHIPID_BCM5715_A1 0x9001 295#define BGE_CHIPID_BCM5715_A3 0x9003 296#define BGE_CHIPID_BCM5755_A0 0xa000 297#define BGE_CHIPID_BCM5755_A1 0xa001 298#define BGE_CHIPID_BCM5755_A2 0xa002 299#define BGE_CHIPID_BCM5755_C0 0xa200 300#define BGE_CHIPID_BCM5787_A0 0xb000 301#define BGE_CHIPID_BCM5787_A1 0xb001 302#define BGE_CHIPID_BCM5787_A2 0xb002 303#define BGE_CHIPID_BCM5761_A0 0x5761000 304#define BGE_CHIPID_BCM5761_A1 0x5761100 305#define BGE_CHIPID_BCM5784_A0 0x5784000 306#define BGE_CHIPID_BCM5784_A1 0x5784100 307#define BGE_CHIPID_BCM5906_A0 0xc000 308#define BGE_CHIPID_BCM5906_A1 0xc001 309#define BGE_CHIPID_BCM5906_A2 0xc002 310#define BGE_CHIPID_BCM57780_A0 0x57780000 311#define BGE_CHIPID_BCM57780_A1 0x57780001 312#define BGE_CHIPID_BCM5717_A0 0x05717000 313#define BGE_CHIPID_BCM5717_B0 0x05717100 314#define BGE_CHIPID_BCM5719_A0 0x05719000 315#define BGE_CHIPID_BCM5720_A0 0x05720000 316#define BGE_CHIPID_BCM57765_A0 0x57785000 317#define BGE_CHIPID_BCM57765_B0 0x57785100 318 319/* shorthand one */ 320#define BGE_ASICREV(x) ((x) >> 12) 321#define BGE_ASICREV_BCM5700 0x07 322#define BGE_ASICREV_BCM5701 0x00 323#define BGE_ASICREV_BCM5703 0x01 324#define BGE_ASICREV_BCM5704 0x02 325#define BGE_ASICREV_BCM5705 0x03 326#define BGE_ASICREV_BCM5750 0x04 327#define BGE_ASICREV_BCM5714_A0 0x05 /* 5714, 5715 */ 328#define BGE_ASICREV_BCM5752 0x06 329#define BGE_ASICREV_BCM5780 0x08 330#define BGE_ASICREV_BCM5714 0x09 /* 5714, 5715 */ 331#define BGE_ASICREV_BCM5755 0x0a 332#define BGE_ASICREV_BCM5787 0x0b 333#define BGE_ASICREV_BCM5906 0x0c 334#define BGE_ASICREV_USE_PRODID_REG 0x0f 335#define BGE_ASICREV_BCM5717 0x5717 336#define BGE_ASICREV_BCM5719 0x5719 337#define BGE_ASICREV_BCM5720 0x5720 338#define BGE_ASICREV_BCM5761 0x5761 339#define BGE_ASICREV_BCM5784 0x5784 340#define BGE_ASICREV_BCM5785 0x5785 341#define BGE_ASICREV_BCM57765 0x57785 342#define BGE_ASICREV_BCM57766 0x57766 343#define BGE_ASICREV_BCM57780 0x57780 344 345/* chip revisions */ 346#define BGE_CHIPREV(x) ((x) >> 8) 347#define BGE_CHIPREV_5700_AX 0x70 348#define BGE_CHIPREV_5700_BX 0x71 349#define BGE_CHIPREV_5700_CX 0x72 350#define BGE_CHIPREV_5701_AX 0x00 351#define BGE_CHIPREV_5703_AX 0x10 352#define BGE_CHIPREV_5704_AX 0x20 353#define BGE_CHIPREV_5704_BX 0x21 354#define BGE_CHIPREV_5750_AX 0x40 355#define BGE_CHIPREV_5750_BX 0x41 356#define BGE_CHIPREV_5717_AX 0x57170 357#define BGE_CHIPREV_5717_BX 0x57171 358#define BGE_CHIPREV_5761_AX 0x57611 359#define BGE_CHIPREV_5784_AX 0x57841 360 361/* PCI DMA Read/Write Control register */ 362#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 363#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 364#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 365#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 366#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 367#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 368#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 369#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 370#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 371#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 372#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 373#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 374#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 375 376#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 377#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 378#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 379#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 380 381#define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 382#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 383 384#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 385#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 386#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 387#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 388#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 389#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 390#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 391#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 392 393#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 394#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 395#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 396#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 397#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 398#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 399#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 400#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 401 402/* 403 * PCI state register -- note, this register is read only 404 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 405 * register is set. 406 */ 407#define BGE_PCISTATE_FORCE_RESET 0x00000001 408#define BGE_PCISTATE_INTR_NOT_ACTIVE 0x00000002 409#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 410#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 411#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 412#define BGE_PCISTATE_WANT_EXPROM 0x00000020 413#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 414#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 415#define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000 416#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 417 418/* 419 * The following bits in PCI state register are reserved. 420 * If we check that the register values reverts on reset, 421 * do not check these bits. On some 5704C (rev A3) and some 422 * Altima chips, these bits do not revert until much later 423 * in the bge driver's bge_reset() chip-reset state machine. 424 */ 425#define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 426 427/* 428 * PCI Clock Control register -- note, this register is read only 429 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 430 * register is set. 431 */ 432#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 433#define BGE_PCICLOCKCTL_M66EN 0x00000080 434#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 435#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 436#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 437#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 438#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 439#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 440#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 441#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 442 443/* 444 * High priority mailbox registers 445 * Each mailbox is 64-bits wide, though we only use the 446 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 447 * first. The NIC will load the mailbox after the lower 32 bit word 448 * has been updated. 449 */ 450#define BGE_MBX_IRQ0_HI 0x0200 451#define BGE_MBX_IRQ0_LO 0x0204 452#define BGE_MBX_IRQ1_HI 0x0208 453#define BGE_MBX_IRQ1_LO 0x020C 454#define BGE_MBX_IRQ2_HI 0x0210 455#define BGE_MBX_IRQ2_LO 0x0214 456#define BGE_MBX_IRQ3_HI 0x0218 457#define BGE_MBX_IRQ3_LO 0x021C 458#define BGE_MBX_GEN0_HI 0x0220 459#define BGE_MBX_GEN0_LO 0x0224 460#define BGE_MBX_GEN1_HI 0x0228 461#define BGE_MBX_GEN1_LO 0x022C 462#define BGE_MBX_GEN2_HI 0x0230 463#define BGE_MBX_GEN2_LO 0x0234 464#define BGE_MBX_GEN3_HI 0x0228 465#define BGE_MBX_GEN3_LO 0x022C 466#define BGE_MBX_GEN4_HI 0x0240 467#define BGE_MBX_GEN4_LO 0x0244 468#define BGE_MBX_GEN5_HI 0x0248 469#define BGE_MBX_GEN5_LO 0x024C 470#define BGE_MBX_GEN6_HI 0x0250 471#define BGE_MBX_GEN6_LO 0x0254 472#define BGE_MBX_GEN7_HI 0x0258 473#define BGE_MBX_GEN7_LO 0x025C 474#define BGE_MBX_RELOAD_STATS_HI 0x0260 475#define BGE_MBX_RELOAD_STATS_LO 0x0264 476#define BGE_MBX_RX_STD_PROD_HI 0x0268 477#define BGE_MBX_RX_STD_PROD_LO 0x026C 478#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 479#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 480#define BGE_MBX_RX_MINI_PROD_HI 0x0278 481#define BGE_MBX_RX_MINI_PROD_LO 0x027C 482#define BGE_MBX_RX_CONS0_HI 0x0280 483#define BGE_MBX_RX_CONS0_LO 0x0284 484#define BGE_MBX_RX_CONS1_HI 0x0288 485#define BGE_MBX_RX_CONS1_LO 0x028C 486#define BGE_MBX_RX_CONS2_HI 0x0290 487#define BGE_MBX_RX_CONS2_LO 0x0294 488#define BGE_MBX_RX_CONS3_HI 0x0298 489#define BGE_MBX_RX_CONS3_LO 0x029C 490#define BGE_MBX_RX_CONS4_HI 0x02A0 491#define BGE_MBX_RX_CONS4_LO 0x02A4 492#define BGE_MBX_RX_CONS5_HI 0x02A8 493#define BGE_MBX_RX_CONS5_LO 0x02AC 494#define BGE_MBX_RX_CONS6_HI 0x02B0 495#define BGE_MBX_RX_CONS6_LO 0x02B4 496#define BGE_MBX_RX_CONS7_HI 0x02B8 497#define BGE_MBX_RX_CONS7_LO 0x02BC 498#define BGE_MBX_RX_CONS8_HI 0x02C0 499#define BGE_MBX_RX_CONS8_LO 0x02C4 500#define BGE_MBX_RX_CONS9_HI 0x02C8 501#define BGE_MBX_RX_CONS9_LO 0x02CC 502#define BGE_MBX_RX_CONS10_HI 0x02D0 503#define BGE_MBX_RX_CONS10_LO 0x02D4 504#define BGE_MBX_RX_CONS11_HI 0x02D8 505#define BGE_MBX_RX_CONS11_LO 0x02DC 506#define BGE_MBX_RX_CONS12_HI 0x02E0 507#define BGE_MBX_RX_CONS12_LO 0x02E4 508#define BGE_MBX_RX_CONS13_HI 0x02E8 509#define BGE_MBX_RX_CONS13_LO 0x02EC 510#define BGE_MBX_RX_CONS14_HI 0x02F0 511#define BGE_MBX_RX_CONS14_LO 0x02F4 512#define BGE_MBX_RX_CONS15_HI 0x02F8 513#define BGE_MBX_RX_CONS15_LO 0x02FC 514#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 515#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 516#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 517#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 518#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 519#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 520#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 521#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 522#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 523#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 524#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 525#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 526#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 527#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 528#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 529#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 530#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 531#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 532#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 533#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 534#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 535#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 536#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 537#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 538#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 539#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 540#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 541#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 542#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 543#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 544#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 545#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 546#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 547#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 548#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 549#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 550#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 551#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 552#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 553#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 554#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 555#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 556#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 557#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 558#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 559#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 560#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 561#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 562#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 563#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 564#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 565#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 566#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 567#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 568#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 569#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 570#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 571#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 572#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 573#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 574#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 575#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 576#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 577#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 578 579#define BGE_TX_RINGS_MAX 4 580#define BGE_TX_RINGS_EXTSSRAM_MAX 16 581#define BGE_RX_RINGS_MAX 16 582 583/* Ethernet MAC control registers */ 584#define BGE_MAC_MODE 0x0400 585#define BGE_MAC_STS 0x0404 586#define BGE_MAC_EVT_ENB 0x0408 587#define BGE_MAC_LED_CTL 0x040C 588#define BGE_MAC_ADDR1_LO 0x0410 589#define BGE_MAC_ADDR1_HI 0x0414 590#define BGE_MAC_ADDR2_LO 0x0418 591#define BGE_MAC_ADDR2_HI 0x041C 592#define BGE_MAC_ADDR3_LO 0x0420 593#define BGE_MAC_ADDR3_HI 0x0424 594#define BGE_MAC_ADDR4_LO 0x0428 595#define BGE_MAC_ADDR4_HI 0x042C 596#define BGE_WOL_PATPTR 0x0430 597#define BGE_WOL_PATCFG 0x0434 598#define BGE_TX_RANDOM_BACKOFF 0x0438 599#define BGE_RX_MTU 0x043C 600#define BGE_GBIT_PCS_TEST 0x0440 601#define BGE_TX_TBI_AUTONEG 0x0444 602#define BGE_RX_TBI_AUTONEG 0x0448 603#define BGE_MI_COMM 0x044C 604#define BGE_MI_STS 0x0450 605#define BGE_MI_MODE 0x0454 606#define BGE_AUTOPOLL_STS 0x0458 607#define BGE_TX_MODE 0x045C 608#define BGE_TX_STS 0x0460 609#define BGE_TX_LENGTHS 0x0464 610#define BGE_RX_MODE 0x0468 611#define BGE_RX_STS 0x046C 612#define BGE_MAR0 0x0470 613#define BGE_MAR1 0x0474 614#define BGE_MAR2 0x0478 615#define BGE_MAR3 0x047C 616#define BGE_RX_BD_RULES_CTL0 0x0480 617#define BGE_RX_BD_RULES_MASKVAL0 0x0484 618#define BGE_RX_BD_RULES_CTL1 0x0488 619#define BGE_RX_BD_RULES_MASKVAL1 0x048C 620#define BGE_RX_BD_RULES_CTL2 0x0490 621#define BGE_RX_BD_RULES_MASKVAL2 0x0494 622#define BGE_RX_BD_RULES_CTL3 0x0498 623#define BGE_RX_BD_RULES_MASKVAL3 0x049C 624#define BGE_RX_BD_RULES_CTL4 0x04A0 625#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 626#define BGE_RX_BD_RULES_CTL5 0x04A8 627#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 628#define BGE_RX_BD_RULES_CTL6 0x04B0 629#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 630#define BGE_RX_BD_RULES_CTL7 0x04B8 631#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 632#define BGE_RX_BD_RULES_CTL8 0x04C0 633#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 634#define BGE_RX_BD_RULES_CTL9 0x04C8 635#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 636#define BGE_RX_BD_RULES_CTL10 0x04D0 637#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 638#define BGE_RX_BD_RULES_CTL11 0x04D8 639#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 640#define BGE_RX_BD_RULES_CTL12 0x04E0 641#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 642#define BGE_RX_BD_RULES_CTL13 0x04E8 643#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 644#define BGE_RX_BD_RULES_CTL14 0x04F0 645#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 646#define BGE_RX_BD_RULES_CTL15 0x04F8 647#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 648#define BGE_RX_RULES_CFG 0x0500 649#define BGE_MAX_RX_FRAME_LOWAT 0x0504 650#define BGE_SERDES_CFG 0x0590 651#define BGE_SERDES_STS 0x0594 652#define BGE_PHYCFG1 0x05A0 653#define BGE_PHYCFG2 0x05A4 654#define BGE_EXT_RGMII_MODE 0x05A8 655#define BGE_SGDIG_CFG 0x05B0 656#define BGE_SGDIG_STS 0x05B4 657#define BGE_MAC_STATS 0x0800 658 659/* Ethernet MAC Mode register */ 660#define BGE_MACMODE_RESET 0x00000001 661#define BGE_MACMODE_HALF_DUPLEX 0x00000002 662#define BGE_MACMODE_PORTMODE 0x0000000C 663#define BGE_MACMODE_LOOPBACK 0x00000010 664#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 665#define BGE_MACMODE_TX_BURST_ENB 0x00000100 666#define BGE_MACMODE_MAX_DEFER 0x00000200 667#define BGE_MACMODE_LINK_POLARITY 0x00000400 668#define BGE_MACMODE_RX_STATS_ENB 0x00000800 669#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 670#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 671#define BGE_MACMODE_TX_STATS_ENB 0x00004000 672#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 673#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 674#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 675#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 676#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 677#define BGE_MACMODE_MIP_ENB 0x00100000 678#define BGE_MACMODE_TXDMA_ENB 0x00200000 679#define BGE_MACMODE_RXDMA_ENB 0x00400000 680#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 681 682#define BGE_PORTMODE_NONE 0x00000000 683#define BGE_PORTMODE_MII 0x00000004 684#define BGE_PORTMODE_GMII 0x00000008 685#define BGE_PORTMODE_TBI 0x0000000C 686 687/* MAC Status register */ 688#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 689#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 690#define BGE_MACSTAT_RX_CFG 0x00000004 691#define BGE_MACSTAT_CFG_CHANGED 0x00000008 692#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 693#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 694#define BGE_MACSTAT_LINK_CHANGED 0x00001000 695#define BGE_MACSTAT_MI_COMPLETE 0x00400000 696#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 697#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 698#define BGE_MACSTAT_ODI_ERROR 0x02000000 699#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 700#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 701 702/* MAC Event Enable Register */ 703#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 704#define BGE_EVTENB_LINK_CHANGED 0x00001000 705#define BGE_EVTENB_MI_COMPLETE 0x00400000 706#define BGE_EVTENB_MI_INTERRUPT 0x00800000 707#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 708#define BGE_EVTENB_ODI_ERROR 0x02000000 709#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 710#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 711 712/* LED Control Register */ 713#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 714#define BGE_LEDCTL_1000MBPS_LED 0x00000002 715#define BGE_LEDCTL_100MBPS_LED 0x00000004 716#define BGE_LEDCTL_10MBPS_LED 0x00000008 717#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 718#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 719#define BGE_LEDCTL_TRAFLED_BLINK_2 0x00000040 720#define BGE_LEDCTL_1000MBPS_STS 0x00000080 721#define BGE_LEDCTL_100MBPS_STS 0x00000100 722#define BGE_LEDCTL_10MBPS_STS 0x00000200 723#define BGE_LEDCTL_TRADLED_STS 0x00000400 724#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 725#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 726 727/* TX backoff seed register */ 728#define BGE_TX_BACKOFF_SEED_MASK 0x3F 729 730/* Autopoll status register */ 731#define BGE_AUTOPOLLSTS_ERROR 0x00000001 732 733/* Transmit MAC mode register */ 734#define BGE_TXMODE_RESET 0x00000001 735#define BGE_TXMODE_ENABLE 0x00000002 736#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 737#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 738#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 739#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 740#define BGE_TXMODE_JMB_FRM_LEN 0x00400000 741#define BGE_TXMODE_CNT_DN_MODE 0x00800000 742 743/* Transmit MAC status register */ 744#define BGE_TXSTAT_RX_XOFFED 0x00000001 745#define BGE_TXSTAT_SENT_XOFF 0x00000002 746#define BGE_TXSTAT_SENT_XON 0x00000004 747#define BGE_TXSTAT_LINK_UP 0x00000008 748#define BGE_TXSTAT_ODI_UFLOW 0x00000010 749#define BGE_TXSTAT_ODI_OFLOW 0x00000020 750 751/* Transmit MAC lengths register */ 752#define BGE_TXLEN_SLOTTIME 0x000000FF 753#define BGE_TXLEN_IPG 0x00000F00 754#define BGE_TXLEN_CRS 0x00003000 755#define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000 756#define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000 757 758/* Receive MAC mode register */ 759#define BGE_RXMODE_RESET 0x00000001 760#define BGE_RXMODE_ENABLE 0x00000002 761#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 762#define BGE_RXMODE_RX_GIANTS 0x00000020 763#define BGE_RXMODE_RX_RUNTS 0x00000040 764#define BGE_RXMODE_8022_LENCHECK 0x00000080 765#define BGE_RXMODE_RX_PROMISC 0x00000100 766#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 767#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 768#define BGE_RXMODE_RX_IPV6_CSUM_ENABLE 0x01000000 769 770/* Receive MAC status register */ 771#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 772#define BGE_RXSTAT_RCVD_XOFF 0x00000002 773#define BGE_RXSTAT_RCVD_XON 0x00000004 774 775/* Receive Rules Control register */ 776#define BGE_RXRULECTL_OFFSET 0x000000FF 777#define BGE_RXRULECTL_CLASS 0x00001F00 778#define BGE_RXRULECTL_HDRTYPE 0x0000E000 779#define BGE_RXRULECTL_COMPARE_OP 0x00030000 780#define BGE_RXRULECTL_MAP 0x01000000 781#define BGE_RXRULECTL_DISCARD 0x02000000 782#define BGE_RXRULECTL_MASK 0x04000000 783#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 784#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 785#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 786#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 787 788/* Receive Rules Mask register */ 789#define BGE_RXRULEMASK_VALUE 0x0000FFFF 790#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 791 792/* SERDES configuration register */ 793#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 794#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 795#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 796#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 797#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 798#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 799#define BGE_SERDESCFG_TXMODE 0x00001000 800#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 801#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 802#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 803#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 804#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 805#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 806#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125MHz clock */ 807#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 808#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 809 810/* SERDES status register */ 811#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 812#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 813 814/* PHYCFG1 config */ 815#define BGE_PHYCFG1_RGMII_INT 0x00000001 816#define BGE_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000 817#define BGE_PHYCFG1_RGMII_SND_STAT_EN 0x04000000 818#define BGE_PHYCFG1_TXC_DRV 0x20000000 819 820/* PHYCFG2 config */ 821#define BGE_PHYCFG2_INBAND_ENABLE 0x00000001 822#define BGE_PHYCFG2_EMODE_MASK_MASK 0x000001c0 823#define BGE_PHYCFG2_EMODE_MASK_AC131 0x000000c0 824#define BGE_PHYCFG2_EMODE_MASK_50610 0x00000100 825#define BGE_PHYCFG2_EMODE_MASK_RT8211 0x00000000 826#define BGE_PHYCFG2_EMODE_MASK_RT8201 0x000001c0 827#define BGE_PHYCFG2_EMODE_COMP_MASK 0x00000e00 828#define BGE_PHYCFG2_EMODE_COMP_AC131 0x00000600 829#define BGE_PHYCFG2_EMODE_COMP_50610 0x00000400 830#define BGE_PHYCFG2_EMODE_COMP_RT8211 0x00000800 831#define BGE_PHYCFG2_EMODE_COMP_RT8201 0x00000000 832#define BGE_PHYCFG2_FMODE_MASK_MASK 0x00007000 833#define BGE_PHYCFG2_FMODE_MASK_AC131 0x00006000 834#define BGE_PHYCFG2_FMODE_MASK_50610 0x00004000 835#define BGE_PHYCFG2_FMODE_MASK_RT8211 0x00000000 836#define BGE_PHYCFG2_FMODE_MASK_RT8201 0x00007000 837#define BGE_PHYCFG2_FMODE_COMP_MASK 0x00038000 838#define BGE_PHYCFG2_FMODE_COMP_AC131 0x00030000 839#define BGE_PHYCFG2_FMODE_COMP_50610 0x00008000 840#define BGE_PHYCFG2_FMODE_COMP_RT8211 0x00038000 841#define BGE_PHYCFG2_FMODE_COMP_RT8201 0x00000000 842#define BGE_PHYCFG2_GMODE_MASK_MASK 0x001c0000 843#define BGE_PHYCFG2_GMODE_MASK_AC131 0x001c0000 844#define BGE_PHYCFG2_GMODE_MASK_50610 0x00100000 845#define BGE_PHYCFG2_GMODE_MASK_RT8211 0x00000000 846#define BGE_PHYCFG2_GMODE_MASK_RT8201 0x001c0000 847#define BGE_PHYCFG2_GMODE_COMP_MASK 0x00e00000 848#define BGE_PHYCFG2_GMODE_COMP_AC131 0x00e00000 849#define BGE_PHYCFG2_GMODE_COMP_50610 0x00000000 850#define BGE_PHYCFG2_GMODE_COMP_RT8211 0x00200000 851#define BGE_PHYCFG2_GMODE_COMP_RT8201 0x00000000 852#define BGE_PHYCFG2_ACT_MASK_MASK 0x03000000 853#define BGE_PHYCFG2_ACT_MASK_AC131 0x03000000 854#define BGE_PHYCFG2_ACT_MASK_50610 0x01000000 855#define BGE_PHYCFG2_ACT_MASK_RT8211 0x03000000 856#define BGE_PHYCFG2_ACT_MASK_RT8201 0x01000000 857#define BGE_PHYCFG2_ACT_COMP_MASK 0x0c000000 858#define BGE_PHYCFG2_ACT_COMP_AC131 0x00000000 859#define BGE_PHYCFG2_ACT_COMP_50610 0x00000000 860#define BGE_PHYCFG2_ACT_COMP_RT8211 0x00000000 861#define BGE_PHYCFG2_ACT_COMP_RT8201 0x08000000 862#define BGE_PHYCFG2_QUAL_MASK_MASK 0x30000000 863#define BGE_PHYCFG2_QUAL_MASK_AC131 0x30000000 864#define BGE_PHYCFG2_QUAL_MASK_50610 0x30000000 865#define BGE_PHYCFG2_QUAL_MASK_RT8211 0x30000000 866#define BGE_PHYCFG2_QUAL_MASK_RT8201 0x30000000 867#define BGE_PHYCFG2_QUAL_COMP_MASK 0xc0000000 868#define BGE_PHYCFG2_QUAL_COMP_AC131 0x00000000 869#define BGE_PHYCFG2_QUAL_COMP_50610 0x00000000 870#define BGE_PHYCFG2_QUAL_COMP_RT8211 0x00000000 871#define BGE_PHYCFG2_QUAL_COMP_RT8201 0x00000000 872#define BGE_PHYCFG2_50610_LED_MODES \ 873 (BGE_PHYCFG2_EMODE_MASK_50610 | \ 874 BGE_PHYCFG2_EMODE_COMP_50610 | \ 875 BGE_PHYCFG2_FMODE_MASK_50610 | \ 876 BGE_PHYCFG2_FMODE_COMP_50610 | \ 877 BGE_PHYCFG2_GMODE_MASK_50610 | \ 878 BGE_PHYCFG2_GMODE_COMP_50610 | \ 879 BGE_PHYCFG2_ACT_MASK_50610 | \ 880 BGE_PHYCFG2_ACT_COMP_50610 | \ 881 BGE_PHYCFG2_QUAL_MASK_50610 | \ 882 BGE_PHYCFG2_QUAL_COMP_50610) 883#define BGE_PHYCFG2_AC131_LED_MODES \ 884 (BGE_PHYCFG2_EMODE_MASK_AC131 | \ 885 BGE_PHYCFG2_EMODE_COMP_AC131 | \ 886 BGE_PHYCFG2_FMODE_MASK_AC131 | \ 887 BGE_PHYCFG2_FMODE_COMP_AC131 | \ 888 BGE_PHYCFG2_GMODE_MASK_AC131 | \ 889 BGE_PHYCFG2_GMODE_COMP_AC131 | \ 890 BGE_PHYCFG2_ACT_MASK_AC131 | \ 891 BGE_PHYCFG2_ACT_COMP_AC131 | \ 892 BGE_PHYCFG2_QUAL_MASK_AC131 | \ 893 BGE_PHYCFG2_QUAL_COMP_AC131) 894#define BGE_PHYCFG2_RTL8211C_LED_MODES \ 895 (BGE_PHYCFG2_EMODE_MASK_RT8211 | \ 896 BGE_PHYCFG2_EMODE_COMP_RT8211 | \ 897 BGE_PHYCFG2_FMODE_MASK_RT8211 | \ 898 BGE_PHYCFG2_FMODE_COMP_RT8211 | \ 899 BGE_PHYCFG2_GMODE_MASK_RT8211 | \ 900 BGE_PHYCFG2_GMODE_COMP_RT8211 | \ 901 BGE_PHYCFG2_ACT_MASK_RT8211 | \ 902 BGE_PHYCFG2_ACT_COMP_RT8211 | \ 903 BGE_PHYCFG2_QUAL_MASK_RT8211 | \ 904 BGE_PHYCFG2_QUAL_COMP_RT8211) 905#define BGE_PHYCFG2_RTL8201E_LED_MODES \ 906 (BGE_PHYCFG2_EMODE_MASK_RT8201 | \ 907 BGE_PHYCFG2_EMODE_COMP_RT8201 | \ 908 BGE_PHYCFG2_FMODE_MASK_RT8201 | \ 909 BGE_PHYCFG2_FMODE_COMP_RT8201 | \ 910 BGE_PHYCFG2_GMODE_MASK_RT8201 | \ 911 BGE_PHYCFG2_GMODE_COMP_RT8201 | \ 912 BGE_PHYCFG2_ACT_MASK_RT8201 | \ 913 BGE_PHYCFG2_ACT_COMP_RT8201 | \ 914 BGE_PHYCFG2_QUAL_MASK_RT8201 | \ 915 BGE_PHYCFG2_QUAL_COMP_RT8201) 916 917/* EXT_RGMII_MODE config */ 918#define BGE_RGMII_MODE_TX_ENABLE 0x00000001 919#define BGE_RGMII_MODE_TX_LOWPWR 0x00000002 920#define BGE_RGMII_MODE_TX_RESET 0x00000004 921#define BGE_RGMII_MODE_RX_INT_B 0x00000100 922#define BGE_RGMII_MODE_RX_QUALITY 0x00000200 923#define BGE_RGMII_MODE_RX_ACTIVITY 0x00000400 924#define BGE_RGMII_MODE_RX_ENG_DET 0x00000800 925 926/* SGDIG config (not documented) */ 927#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 928#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 929#define BGE_SGDIGCFG_SEND 0x40000000 930#define BGE_SGDIGCFG_AUTO 0x80000000 931 932/* SGDIG status (not documented) */ 933#define BGE_SGDIGSTS_DONE 0x00000002 934#define BGE_SGDIGSTS_IS_SERDES 0x00000100 935#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 936#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 937 938/* MI communication register */ 939#define BGE_MICOMM_DATA 0x0000FFFF 940#define BGE_MICOMM_REG 0x001F0000 941#define BGE_MICOMM_PHY 0x03E00000 942#define BGE_MICOMM_CMD 0x0C000000 943#define BGE_MICOMM_READFAIL 0x10000000 944#define BGE_MICOMM_BUSY 0x20000000 945 946#define BGE_MIREG(x) ((x & 0x1F) << 16) 947#define BGE_MIPHY(x) ((x & 0x1F) << 21) 948#define BGE_MICMD_WRITE 0x04000000 949#define BGE_MICMD_READ 0x08000000 950 951/* MI status register */ 952#define BGE_MISTS_LINK 0x00000001 953#define BGE_MISTS_10MBPS 0x00000002 954 955#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 956#define BGE_MIMODE_AUTOPOLL 0x00000010 957#define BGE_MIMODE_CLKCNT 0x001F0000 958#define BGE_MIMODE_500KHZ_CONST 0x00008000 959#define BGE_MIMODE_BASE 0x000C0000 960 961/* 962 * Send data initiator control registers. 963 */ 964#define BGE_SDI_MODE 0x0C00 965#define BGE_SDI_STATUS 0x0C04 966#define BGE_SDI_STATS_CTL 0x0C08 967#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 968#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 969#define BGE_ISO_PKT_TX 0x0C20 970#define BGE_LOCSTATS_COS0 0x0C80 971#define BGE_LOCSTATS_COS1 0x0C84 972#define BGE_LOCSTATS_COS2 0x0C88 973#define BGE_LOCSTATS_COS3 0x0C8C 974#define BGE_LOCSTATS_COS4 0x0C90 975#define BGE_LOCSTATS_COS5 0x0C84 976#define BGE_LOCSTATS_COS6 0x0C98 977#define BGE_LOCSTATS_COS7 0x0C9C 978#define BGE_LOCSTATS_COS8 0x0CA0 979#define BGE_LOCSTATS_COS9 0x0CA4 980#define BGE_LOCSTATS_COS10 0x0CA8 981#define BGE_LOCSTATS_COS11 0x0CAC 982#define BGE_LOCSTATS_COS12 0x0CB0 983#define BGE_LOCSTATS_COS13 0x0CB4 984#define BGE_LOCSTATS_COS14 0x0CB8 985#define BGE_LOCSTATS_COS15 0x0CBC 986#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 987#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 988#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 989#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 990#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 991#define BGE_LOCSTATS_IRQS 0x0CD4 992#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 993#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 994 995/* Send Data Initiator mode register */ 996#define BGE_SDIMODE_RESET 0x00000001 997#define BGE_SDIMODE_ENABLE 0x00000002 998#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 999 1000/* Send Data Initiator stats register */ 1001#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 1002 1003/* Send Data Initiator stats control register */ 1004#define BGE_SDISTATSCTL_ENABLE 0x00000001 1005#define BGE_SDISTATSCTL_FASTER 0x00000002 1006#define BGE_SDISTATSCTL_CLEAR 0x00000004 1007#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 1008#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 1009 1010/* 1011 * Send Data Completion Control registers 1012 */ 1013#define BGE_SDC_MODE 0x1000 1014#define BGE_SDC_STATUS 0x1004 1015 1016/* Send Data completion mode register */ 1017#define BGE_SDCMODE_RESET 0x00000001 1018#define BGE_SDCMODE_ENABLE 0x00000002 1019#define BGE_SDCMODE_ATTN 0x00000004 1020#define BGE_SDCMODE_CDELAY 0x00000010 1021 1022/* Send Data completion status register */ 1023#define BGE_SDCSTAT_ATTN 0x00000004 1024 1025/* 1026 * Send BD Ring Selector Control registers 1027 */ 1028#define BGE_SRS_MODE 0x1400 1029#define BGE_SRS_STATUS 0x1404 1030#define BGE_SRS_HWDIAG 0x1408 1031#define BGE_SRS_LOC_NIC_CONS0 0x1440 1032#define BGE_SRS_LOC_NIC_CONS1 0x1444 1033#define BGE_SRS_LOC_NIC_CONS2 0x1448 1034#define BGE_SRS_LOC_NIC_CONS3 0x144C 1035#define BGE_SRS_LOC_NIC_CONS4 0x1450 1036#define BGE_SRS_LOC_NIC_CONS5 0x1454 1037#define BGE_SRS_LOC_NIC_CONS6 0x1458 1038#define BGE_SRS_LOC_NIC_CONS7 0x145C 1039#define BGE_SRS_LOC_NIC_CONS8 0x1460 1040#define BGE_SRS_LOC_NIC_CONS9 0x1464 1041#define BGE_SRS_LOC_NIC_CONS10 0x1468 1042#define BGE_SRS_LOC_NIC_CONS11 0x146C 1043#define BGE_SRS_LOC_NIC_CONS12 0x1470 1044#define BGE_SRS_LOC_NIC_CONS13 0x1474 1045#define BGE_SRS_LOC_NIC_CONS14 0x1478 1046#define BGE_SRS_LOC_NIC_CONS15 0x147C 1047 1048/* Send BD Ring Selector Mode register */ 1049#define BGE_SRSMODE_RESET 0x00000001 1050#define BGE_SRSMODE_ENABLE 0x00000002 1051#define BGE_SRSMODE_ATTN 0x00000004 1052 1053/* Send BD Ring Selector Status register */ 1054#define BGE_SRSSTAT_ERROR 0x00000004 1055 1056/* Send BD Ring Selector HW Diagnostics register */ 1057#define BGE_SRSHWDIAG_STATE 0x0000000F 1058#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 1059#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 1060#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 1061 1062/* 1063 * Send BD Initiator Selector Control registers 1064 */ 1065#define BGE_SBDI_MODE 0x1800 1066#define BGE_SBDI_STATUS 0x1804 1067#define BGE_SBDI_LOC_NIC_PROD0 0x1808 1068#define BGE_SBDI_LOC_NIC_PROD1 0x180C 1069#define BGE_SBDI_LOC_NIC_PROD2 0x1810 1070#define BGE_SBDI_LOC_NIC_PROD3 0x1814 1071#define BGE_SBDI_LOC_NIC_PROD4 0x1818 1072#define BGE_SBDI_LOC_NIC_PROD5 0x181C 1073#define BGE_SBDI_LOC_NIC_PROD6 0x1820 1074#define BGE_SBDI_LOC_NIC_PROD7 0x1824 1075#define BGE_SBDI_LOC_NIC_PROD8 0x1828 1076#define BGE_SBDI_LOC_NIC_PROD9 0x182C 1077#define BGE_SBDI_LOC_NIC_PROD10 0x1830 1078#define BGE_SBDI_LOC_NIC_PROD11 0x1834 1079#define BGE_SBDI_LOC_NIC_PROD12 0x1838 1080#define BGE_SBDI_LOC_NIC_PROD13 0x183C 1081#define BGE_SBDI_LOC_NIC_PROD14 0x1840 1082#define BGE_SBDI_LOC_NIC_PROD15 0x1844 1083 1084/* Send BD Initiator Mode register */ 1085#define BGE_SBDIMODE_RESET 0x00000001 1086#define BGE_SBDIMODE_ENABLE 0x00000002 1087#define BGE_SBDIMODE_ATTN 0x00000004 1088 1089/* Send BD Initiator Status register */ 1090#define BGE_SBDISTAT_ERROR 0x00000004 1091 1092/* 1093 * Send BD Completion Control registers 1094 */ 1095#define BGE_SBDC_MODE 0x1C00 1096#define BGE_SBDC_STATUS 0x1C04 1097 1098/* Send BD Completion Control Mode register */ 1099#define BGE_SBDCMODE_RESET 0x00000001 1100#define BGE_SBDCMODE_ENABLE 0x00000002 1101#define BGE_SBDCMODE_ATTN 0x00000004 1102 1103/* Send BD Completion Control Status register */ 1104#define BGE_SBDCSTAT_ATTN 0x00000004 1105 1106/* 1107 * Receive List Placement Control registers 1108 */ 1109#define BGE_RXLP_MODE 0x2000 1110#define BGE_RXLP_STATUS 0x2004 1111#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1112#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1113#define BGE_RXLP_CFG 0x2010 1114#define BGE_RXLP_STATS_CTL 0x2014 1115#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1116#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1117#define BGE_RXLP_HEAD0 0x2100 1118#define BGE_RXLP_TAIL0 0x2104 1119#define BGE_RXLP_COUNT0 0x2108 1120#define BGE_RXLP_HEAD1 0x2110 1121#define BGE_RXLP_TAIL1 0x2114 1122#define BGE_RXLP_COUNT1 0x2118 1123#define BGE_RXLP_HEAD2 0x2120 1124#define BGE_RXLP_TAIL2 0x2124 1125#define BGE_RXLP_COUNT2 0x2128 1126#define BGE_RXLP_HEAD3 0x2130 1127#define BGE_RXLP_TAIL3 0x2134 1128#define BGE_RXLP_COUNT3 0x2138 1129#define BGE_RXLP_HEAD4 0x2140 1130#define BGE_RXLP_TAIL4 0x2144 1131#define BGE_RXLP_COUNT4 0x2148 1132#define BGE_RXLP_HEAD5 0x2150 1133#define BGE_RXLP_TAIL5 0x2154 1134#define BGE_RXLP_COUNT5 0x2158 1135#define BGE_RXLP_HEAD6 0x2160 1136#define BGE_RXLP_TAIL6 0x2164 1137#define BGE_RXLP_COUNT6 0x2168 1138#define BGE_RXLP_HEAD7 0x2170 1139#define BGE_RXLP_TAIL7 0x2174 1140#define BGE_RXLP_COUNT7 0x2178 1141#define BGE_RXLP_HEAD8 0x2180 1142#define BGE_RXLP_TAIL8 0x2184 1143#define BGE_RXLP_COUNT8 0x2188 1144#define BGE_RXLP_HEAD9 0x2190 1145#define BGE_RXLP_TAIL9 0x2194 1146#define BGE_RXLP_COUNT9 0x2198 1147#define BGE_RXLP_HEAD10 0x21A0 1148#define BGE_RXLP_TAIL10 0x21A4 1149#define BGE_RXLP_COUNT10 0x21A8 1150#define BGE_RXLP_HEAD11 0x21B0 1151#define BGE_RXLP_TAIL11 0x21B4 1152#define BGE_RXLP_COUNT11 0x21B8 1153#define BGE_RXLP_HEAD12 0x21C0 1154#define BGE_RXLP_TAIL12 0x21C4 1155#define BGE_RXLP_COUNT12 0x21C8 1156#define BGE_RXLP_HEAD13 0x21D0 1157#define BGE_RXLP_TAIL13 0x21D4 1158#define BGE_RXLP_COUNT13 0x21D8 1159#define BGE_RXLP_HEAD14 0x21E0 1160#define BGE_RXLP_TAIL14 0x21E4 1161#define BGE_RXLP_COUNT14 0x21E8 1162#define BGE_RXLP_HEAD15 0x21F0 1163#define BGE_RXLP_TAIL15 0x21F4 1164#define BGE_RXLP_COUNT15 0x21F8 1165#define BGE_RXLP_LOCSTAT_COS0 0x2200 1166#define BGE_RXLP_LOCSTAT_COS1 0x2204 1167#define BGE_RXLP_LOCSTAT_COS2 0x2208 1168#define BGE_RXLP_LOCSTAT_COS3 0x220C 1169#define BGE_RXLP_LOCSTAT_COS4 0x2210 1170#define BGE_RXLP_LOCSTAT_COS5 0x2214 1171#define BGE_RXLP_LOCSTAT_COS6 0x2218 1172#define BGE_RXLP_LOCSTAT_COS7 0x221C 1173#define BGE_RXLP_LOCSTAT_COS8 0x2220 1174#define BGE_RXLP_LOCSTAT_COS9 0x2224 1175#define BGE_RXLP_LOCSTAT_COS10 0x2228 1176#define BGE_RXLP_LOCSTAT_COS11 0x222C 1177#define BGE_RXLP_LOCSTAT_COS12 0x2230 1178#define BGE_RXLP_LOCSTAT_COS13 0x2234 1179#define BGE_RXLP_LOCSTAT_COS14 0x2238 1180#define BGE_RXLP_LOCSTAT_COS15 0x223C 1181#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1182#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1183#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1184#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1185#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1186#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1187#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1188 1189 1190/* Receive List Placement mode register */ 1191#define BGE_RXLPMODE_RESET 0x00000001 1192#define BGE_RXLPMODE_ENABLE 0x00000002 1193#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1194#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1195#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1196 1197/* Receive List Placement Status register */ 1198#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1199#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1200#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1201 1202/* 1203 * Receive Data and Receive BD Initiator Control Registers 1204 */ 1205#define BGE_RDBDI_MODE 0x2400 1206#define BGE_RDBDI_STATUS 0x2404 1207#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1208#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1209#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1210#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1211#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1212#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1213#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1214#define BGE_RX_STD_RCB_NICADDR 0x245C 1215#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1216#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1217#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1218#define BGE_RX_MINI_RCB_NICADDR 0x246C 1219#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1220#define BGE_RDBDI_STD_RX_CONS 0x2474 1221#define BGE_RDBDI_MINI_RX_CONS 0x2478 1222#define BGE_RDBDI_RETURN_PROD0 0x2480 1223#define BGE_RDBDI_RETURN_PROD1 0x2484 1224#define BGE_RDBDI_RETURN_PROD2 0x2488 1225#define BGE_RDBDI_RETURN_PROD3 0x248C 1226#define BGE_RDBDI_RETURN_PROD4 0x2490 1227#define BGE_RDBDI_RETURN_PROD5 0x2494 1228#define BGE_RDBDI_RETURN_PROD6 0x2498 1229#define BGE_RDBDI_RETURN_PROD7 0x249C 1230#define BGE_RDBDI_RETURN_PROD8 0x24A0 1231#define BGE_RDBDI_RETURN_PROD9 0x24A4 1232#define BGE_RDBDI_RETURN_PROD10 0x24A8 1233#define BGE_RDBDI_RETURN_PROD11 0x24AC 1234#define BGE_RDBDI_RETURN_PROD12 0x24B0 1235#define BGE_RDBDI_RETURN_PROD13 0x24B4 1236#define BGE_RDBDI_RETURN_PROD14 0x24B8 1237#define BGE_RDBDI_RETURN_PROD15 0x24BC 1238#define BGE_RDBDI_HWDIAG 0x24C0 1239 1240 1241/* Receive Data and Receive BD Initiator Mode register */ 1242#define BGE_RDBDIMODE_RESET 0x00000001 1243#define BGE_RDBDIMODE_ENABLE 0x00000002 1244#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1245#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1246#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1247 1248/* Receive Data and Receive BD Initiator Status register */ 1249#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1250#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1251#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1252 1253 1254/* 1255 * Receive Data Completion Control registers 1256 */ 1257#define BGE_RDC_MODE 0x2800 1258 1259/* Receive Data Completion Mode register */ 1260#define BGE_RDCMODE_RESET 0x00000001 1261#define BGE_RDCMODE_ENABLE 0x00000002 1262#define BGE_RDCMODE_ATTN 0x00000004 1263 1264/* 1265 * Receive BD Initiator Control registers 1266 */ 1267#define BGE_RBDI_MODE 0x2C00 1268#define BGE_RBDI_STATUS 0x2C04 1269#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1270#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1271#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1272#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1273#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1274#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1275 1276#define BGE_STD_REPL_LWM 0x2D00 1277#define BGE_JUMBO_REPL_LWM 0x2D04 1278 1279/* Receive BD Initiator Mode register */ 1280#define BGE_RBDIMODE_RESET 0x00000001 1281#define BGE_RBDIMODE_ENABLE 0x00000002 1282#define BGE_RBDIMODE_ATTN 0x00000004 1283 1284/* Receive BD Initiator Status register */ 1285#define BGE_RBDISTAT_ATTN 0x00000004 1286 1287/* 1288 * Receive BD Completion Control registers 1289 */ 1290#define BGE_RBDC_MODE 0x3000 1291#define BGE_RBDC_STATUS 0x3004 1292#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1293#define BGE_RBDC_STD_BD_PROD 0x300C 1294#define BGE_RBDC_MINI_BD_PROD 0x3010 1295 1296/* Receive BD completion mode register */ 1297#define BGE_RBDCMODE_RESET 0x00000001 1298#define BGE_RBDCMODE_ENABLE 0x00000002 1299#define BGE_RBDCMODE_ATTN 0x00000004 1300 1301/* Receive BD completion status register */ 1302#define BGE_RBDCSTAT_ERROR 0x00000004 1303 1304/* 1305 * Receive List Selector Control registers 1306 */ 1307#define BGE_RXLS_MODE 0x3400 1308#define BGE_RXLS_STATUS 0x3404 1309 1310/* Receive List Selector Mode register */ 1311#define BGE_RXLSMODE_RESET 0x00000001 1312#define BGE_RXLSMODE_ENABLE 0x00000002 1313#define BGE_RXLSMODE_ATTN 0x00000004 1314 1315/* Receive List Selector Status register */ 1316#define BGE_RXLSSTAT_ERROR 0x00000004 1317 1318#define BGE_CPMU_CTRL 0x3600 1319#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1320#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1321#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1322#define BGE_CPMU_HST_ACC 0x361C 1323#define BGE_CPMU_CLCK_ORIDE 0x3624 1324#define BGE_CPMU_CLCK_STAT 0x3630 1325#define BGE_CPMU_MUTEX_REQ 0x365C 1326#define BGE_CPMU_MUTEX_GNT 0x3660 1327#define BGE_CPMU_PHY_STRAP 0x3664 1328 1329/* Central Power Management Unit (CPMU) register */ 1330#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1331#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1332#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1333#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1334 1335/* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1336#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1337#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1338 1339/* Link Speed 1000MB Power Mode Clock Policy register */ 1340#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1341#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1342#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1343 1344/* Link Aware Power Mode Clock Policy register */ 1345#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1346#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1347 1348#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1349#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1350 1351/* Clock Speed Override Policy register */ 1352#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1353 1354/* CPMU Clock Status register */ 1355#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1356#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1357#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1358#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1359 1360/* CPMU Mutex Request register */ 1361#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1362#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1363 1364/* CPMU GPHY Strap register */ 1365#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1366 1367/* 1368 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1369 */ 1370#define BGE_MBCF_MODE 0x3800 1371#define BGE_MBCF_STATUS 0x3804 1372 1373/* Mbuf Cluster Free mode register */ 1374#define BGE_MBCFMODE_RESET 0x00000001 1375#define BGE_MBCFMODE_ENABLE 0x00000002 1376#define BGE_MBCFMODE_ATTN 0x00000004 1377 1378/* Mbuf Cluster Free status register */ 1379#define BGE_MBCFSTAT_ERROR 0x00000004 1380 1381/* 1382 * Host Coalescing Control registers 1383 */ 1384#define BGE_HCC_MODE 0x3C00 1385#define BGE_HCC_STATUS 0x3C04 1386#define BGE_HCC_RX_COAL_TICKS 0x3C08 1387#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1388#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1389#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1390#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1391#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1392#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1393#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1394#define BGE_HCC_STATS_TICKS 0x3C28 1395#define BGE_HCC_STATS_ADDR_HI 0x3C30 1396#define BGE_HCC_STATS_ADDR_LO 0x3C34 1397#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1398#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1399#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1400#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1401#define BGE_FLOW_ATTN 0x3C48 1402#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1403#define BGE_HCC_STD_BD_CONS 0x3C54 1404#define BGE_HCC_MINI_BD_CONS 0x3C58 1405#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1406#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1407#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1408#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1409#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1410#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1411#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1412#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1413#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1414#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1415#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1416#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1417#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1418#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1419#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1420#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1421#define BGE_HCC_TX_BD_CONS0 0x3CC0 1422#define BGE_HCC_TX_BD_CONS1 0x3CC4 1423#define BGE_HCC_TX_BD_CONS2 0x3CC8 1424#define BGE_HCC_TX_BD_CONS3 0x3CCC 1425#define BGE_HCC_TX_BD_CONS4 0x3CD0 1426#define BGE_HCC_TX_BD_CONS5 0x3CD4 1427#define BGE_HCC_TX_BD_CONS6 0x3CD8 1428#define BGE_HCC_TX_BD_CONS7 0x3CDC 1429#define BGE_HCC_TX_BD_CONS8 0x3CE0 1430#define BGE_HCC_TX_BD_CONS9 0x3CE4 1431#define BGE_HCC_TX_BD_CONS10 0x3CE8 1432#define BGE_HCC_TX_BD_CONS11 0x3CEC 1433#define BGE_HCC_TX_BD_CONS12 0x3CF0 1434#define BGE_HCC_TX_BD_CONS13 0x3CF4 1435#define BGE_HCC_TX_BD_CONS14 0x3CF8 1436#define BGE_HCC_TX_BD_CONS15 0x3CFC 1437 1438 1439/* Host coalescing mode register */ 1440#define BGE_HCCMODE_RESET 0x00000001 1441#define BGE_HCCMODE_ENABLE 0x00000002 1442#define BGE_HCCMODE_ATTN 0x00000004 1443#define BGE_HCCMODE_COAL_NOW 0x00000008 1444#define BGE_HCCMODE_MSI_BITS 0x00000070 1445#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1446 1447#define BGE_STATBLKSZ_FULL 0x00000000 1448#define BGE_STATBLKSZ_64BYTE 0x00000080 1449#define BGE_STATBLKSZ_32BYTE 0x00000100 1450 1451/* Host coalescing status register */ 1452#define BGE_HCCSTAT_ERROR 0x00000004 1453 1454/* Flow attention register */ 1455#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1456#define BGE_FLOWATTN_MEMARB 0x00000080 1457#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1458#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1459#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1460#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1461#define BGE_FLOWATTN_RDBDI 0x00080000 1462#define BGE_FLOWATTN_RXLS 0x00100000 1463#define BGE_FLOWATTN_RXLP 0x00200000 1464#define BGE_FLOWATTN_RBDC 0x00400000 1465#define BGE_FLOWATTN_RBDI 0x00800000 1466#define BGE_FLOWATTN_SDC 0x08000000 1467#define BGE_FLOWATTN_SDI 0x10000000 1468#define BGE_FLOWATTN_SRS 0x20000000 1469#define BGE_FLOWATTN_SBDC 0x40000000 1470#define BGE_FLOWATTN_SBDI 0x80000000 1471 1472/* 1473 * Memory arbiter registers 1474 */ 1475#define BGE_MARB_MODE 0x4000 1476#define BGE_MARB_STATUS 0x4004 1477#define BGE_MARB_TRAPADDR_HI 0x4008 1478#define BGE_MARB_TRAPADDR_LO 0x400C 1479 1480/* Memory arbiter mode register */ 1481#define BGE_MARBMODE_RESET 0x00000001 1482#define BGE_MARBMODE_ENABLE 0x00000002 1483#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1484#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1485#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1486#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1487#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1488#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1489#define BGE_MARBMODE_PCI_TRAP 0x00000100 1490#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1491#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1492#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1493#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1494#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1495#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1496#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1497#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1498#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1499#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1500#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1501#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1502#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1503#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1504#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1505#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1506#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1507 1508/* Memory arbiter status register */ 1509#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1510#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1511#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1512#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1513#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1514#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1515#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1516#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1517#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1518#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1519#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1520#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1521#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1522#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1523#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1524#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1525#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1526#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1527#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1528#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1529#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1530#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1531#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1532#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1533 1534/* 1535 * Buffer manager control registers 1536 */ 1537#define BGE_BMAN_MODE 0x4400 1538#define BGE_BMAN_STATUS 0x4404 1539#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1540#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1541#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1542#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1543#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1544#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1545#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1546#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1547#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1548#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1549#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1550#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1551#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1552#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1553#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1554#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1555#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1556#define BGE_BMAN_HWDIAG_1 0x444C 1557#define BGE_BMAN_HWDIAG_2 0x4450 1558#define BGE_BMAN_HWDIAG_3 0x4454 1559 1560/* Buffer manager mode register */ 1561#define BGE_BMANMODE_RESET 0x00000001 1562#define BGE_BMANMODE_ENABLE 0x00000002 1563#define BGE_BMANMODE_ATTN 0x00000004 1564#define BGE_BMANMODE_TESTMODE 0x00000008 1565#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1566#define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000 1567 1568/* Buffer manager status register */ 1569#define BGE_BMANSTAT_ERRO 0x00000004 1570#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1571 1572 1573/* 1574 * Read DMA Control registers 1575 */ 1576#define BGE_RDMA_MODE 0x4800 1577#define BGE_RDMA_STATUS 0x4804 1578#define BGE_RDMA_RSRVCTRL 0x4900 1579#define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 1580 1581/* Read DMA mode register */ 1582#define BGE_RDMAMODE_RESET 0x00000001 1583#define BGE_RDMAMODE_ENABLE 0x00000002 1584#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1585#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1586#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1587#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1588#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1589#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1590#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1591#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1592#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1593#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1594#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1595#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1596#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1597#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1598#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1599#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1600#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1601#define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000 1602 1603/* Read DMA status register */ 1604#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1605#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1606#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1607#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1608#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1609#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1610#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1611#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1612 1613/* Read DMA Reserved Control register */ 1614#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1615#define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00 1616#define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000 1617#define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1618#define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0 1619#define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000 1620#define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000 1621 1622#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000 1623#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1624#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 1625 1626/* 1627 * Write DMA control registers 1628 */ 1629#define BGE_WDMA_MODE 0x4C00 1630#define BGE_WDMA_STATUS 0x4C04 1631 1632/* Write DMA mode register */ 1633#define BGE_WDMAMODE_RESET 0x00000001 1634#define BGE_WDMAMODE_ENABLE 0x00000002 1635#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1636#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1637#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1638#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1639#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1640#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1641#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1642#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1643#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1644#define BGE_WDMAMODE_RX_ACCEL 0x00000400 1645#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1646#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1647 1648/* Write DMA status register */ 1649#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1650#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1651#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1652#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1653#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1654#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1655#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1656#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1657 1658 1659/* 1660 * RX CPU registers 1661 */ 1662#define BGE_RXCPU_MODE 0x5000 1663#define BGE_RXCPU_STATUS 0x5004 1664#define BGE_RXCPU_PC 0x501C 1665 1666/* RX CPU mode register */ 1667#define BGE_RXCPUMODE_RESET 0x00000001 1668#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1669#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1670#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1671#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1672#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1673#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1674#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1675#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1676#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1677#define BGE_RXCPUMODE_HALTCPU 0x00000400 1678#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1679#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1680#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1681 1682/* RX CPU status register */ 1683#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1684#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1685#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1686#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1687#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1688#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1689#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1690#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1691#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1692#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1693#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1694#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1695#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1696#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1697#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1698#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1699#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1700 1701 1702/* 1703 * V? CPU registers 1704 */ 1705#define BGE_VCPU_STATUS 0x5100 1706#define BGE_VCPU_EXT_CTRL 0x6890 1707 1708#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1709#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1710 1711#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1712#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1713 1714/* 1715 * TX CPU registers 1716 */ 1717#define BGE_TXCPU_MODE 0x5400 1718#define BGE_TXCPU_STATUS 0x5404 1719#define BGE_TXCPU_PC 0x541C 1720 1721/* TX CPU mode register */ 1722#define BGE_TXCPUMODE_RESET 0x00000001 1723#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1724#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1725#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1726#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1727#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1728#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1729#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1730#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1731#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1732#define BGE_TXCPUMODE_HALTCPU 0x00000400 1733#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1734#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1735 1736/* TX CPU status register */ 1737#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1738#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1739#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1740#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1741#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1742#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1743#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1744#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1745#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1746#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1747#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1748#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1749#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1750#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1751#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1752#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1753#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1754 1755 1756/* 1757 * Low priority mailbox registers 1758 */ 1759#define BGE_LPMBX_IRQ0_HI 0x5800 1760#define BGE_LPMBX_IRQ0_LO 0x5804 1761#define BGE_LPMBX_IRQ1_HI 0x5808 1762#define BGE_LPMBX_IRQ1_LO 0x580C 1763#define BGE_LPMBX_IRQ2_HI 0x5810 1764#define BGE_LPMBX_IRQ2_LO 0x5814 1765#define BGE_LPMBX_IRQ3_HI 0x5818 1766#define BGE_LPMBX_IRQ3_LO 0x581C 1767#define BGE_LPMBX_GEN0_HI 0x5820 1768#define BGE_LPMBX_GEN0_LO 0x5824 1769#define BGE_LPMBX_GEN1_HI 0x5828 1770#define BGE_LPMBX_GEN1_LO 0x582C 1771#define BGE_LPMBX_GEN2_HI 0x5830 1772#define BGE_LPMBX_GEN2_LO 0x5834 1773#define BGE_LPMBX_GEN3_HI 0x5828 1774#define BGE_LPMBX_GEN3_LO 0x582C 1775#define BGE_LPMBX_GEN4_HI 0x5840 1776#define BGE_LPMBX_GEN4_LO 0x5844 1777#define BGE_LPMBX_GEN5_HI 0x5848 1778#define BGE_LPMBX_GEN5_LO 0x584C 1779#define BGE_LPMBX_GEN6_HI 0x5850 1780#define BGE_LPMBX_GEN6_LO 0x5854 1781#define BGE_LPMBX_GEN7_HI 0x5858 1782#define BGE_LPMBX_GEN7_LO 0x585C 1783#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1784#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1785#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1786#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1787#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1788#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1789#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1790#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1791#define BGE_LPMBX_RX_CONS0_HI 0x5880 1792#define BGE_LPMBX_RX_CONS0_LO 0x5884 1793#define BGE_LPMBX_RX_CONS1_HI 0x5888 1794#define BGE_LPMBX_RX_CONS1_LO 0x588C 1795#define BGE_LPMBX_RX_CONS2_HI 0x5890 1796#define BGE_LPMBX_RX_CONS2_LO 0x5894 1797#define BGE_LPMBX_RX_CONS3_HI 0x5898 1798#define BGE_LPMBX_RX_CONS3_LO 0x589C 1799#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1800#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1801#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1802#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1803#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1804#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1805#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1806#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1807#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1808#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1809#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1810#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1811#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1812#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1813#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1814#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1815#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1816#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1817#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1818#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1819#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1820#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1821#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1822#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1823#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1824#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1825#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1826#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1827#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1828#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1829#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1830#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1831#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1832#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1833#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1834#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1835#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1836#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1837#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1838#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1839#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1840#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1841#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1842#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1843#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1844#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1845#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1846#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1847#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1848#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1849#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1850#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1851#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1852#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1853#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1854#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1855#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1856#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1857#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1858#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1859#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1860#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1861#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1862#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1863#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1864#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1865#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1866#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1867#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1868#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1869#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1870#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1871#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1872#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1873#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1874#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1875#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1876#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1877#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1878#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1879#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1880#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1881#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1882#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1883#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1884#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1885#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1886#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1887 1888/* 1889 * Flow throw Queue reset register 1890 */ 1891#define BGE_FTQ_RESET 0x5C00 1892 1893#define BGE_FTQRESET_DMAREAD 0x00000002 1894#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1895#define BGE_FTQRESET_DMADONE 0x00000010 1896#define BGE_FTQRESET_SBDC 0x00000020 1897#define BGE_FTQRESET_SDI 0x00000040 1898#define BGE_FTQRESET_WDMA 0x00000080 1899#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1900#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1901#define BGE_FTQRESET_SDC 0x00000400 1902#define BGE_FTQRESET_HCC 0x00000800 1903#define BGE_FTQRESET_TXFIFO 0x00001000 1904#define BGE_FTQRESET_MBC 0x00002000 1905#define BGE_FTQRESET_RBDC 0x00004000 1906#define BGE_FTQRESET_RXLP 0x00008000 1907#define BGE_FTQRESET_RDBDI 0x00010000 1908#define BGE_FTQRESET_RDC 0x00020000 1909#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1910 1911/* 1912 * Message Signaled Interrupt registers 1913 */ 1914#define BGE_MSI_MODE 0x6000 1915#define BGE_MSI_STATUS 0x6004 1916#define BGE_MSI_FIFOACCESS 0x6008 1917 1918/* MSI mode register */ 1919#define BGE_MSIMODE_RESET 0x00000001 1920#define BGE_MSIMODE_ENABLE 0x00000002 1921#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1922#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1923#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1924#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1925#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1926 1927/* MSI status register */ 1928#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1929#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1930#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1931#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1932#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1933 1934 1935/* 1936 * DMA Completion registers 1937 */ 1938#define BGE_DMAC_MODE 0x6400 1939 1940/* DMA Completion mode register */ 1941#define BGE_DMACMODE_RESET 0x00000001 1942#define BGE_DMACMODE_ENABLE 0x00000002 1943 1944 1945/* 1946 * General control registers. 1947 */ 1948#define BGE_MODE_CTL 0x6800 1949#define BGE_MISC_CFG 0x6804 1950#define BGE_MISC_LOCAL_CTL 0x6808 1951#define BGE_RX_CPU_EVENT 0x6810 1952#define BGE_TX_CPU_EVENT 0x6820 1953#define BGE_EE_ADDR 0x6838 1954#define BGE_EE_DATA 0x683C 1955#define BGE_EE_CTL 0x6840 1956#define BGE_MDI_CTL 0x6844 1957#define BGE_EE_DELAY 0x6848 1958#define BGE_FASTBOOT_PC 0x6894 1959 1960#define BGE_RX_CPU_DRV_EVENT 0x00004000 1961 1962/* 1963 * NVRAM Control registers 1964 */ 1965 1966#define BGE_NVRAM_CMD 0x7000 1967#define BGE_NVRAM_STAT 0x7004 1968#define BGE_NVRAM_WRDATA 0x7008 1969#define BGE_NVRAM_ADDR 0x700c 1970#define BGE_NVRAM_RDDATA 0x7010 1971#define BGE_NVRAM_CFG1 0x7014 1972#define BGE_NVRAM_CFG2 0x7018 1973#define BGE_NVRAM_CFG3 0x701c 1974#define BGE_NVRAM_SWARB 0x7020 1975#define BGE_NVRAM_ACCESS 0x7024 1976#define BGE_NVRAM_WRITE1 0x7028 1977 1978 1979#define BGE_NVRAMCMD_RESET 0x00000001 1980#define BGE_NVRAMCMD_DONE 0x00000008 1981#define BGE_NVRAMCMD_START 0x00000010 1982#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1983#define BGE_NVRAMCMD_ERASE 0x00000040 1984#define BGE_NVRAMCMD_FIRST 0x00000080 1985#define BGE_NVRAMCMD_LAST 0x00000100 1986 1987#define BGE_NVRAM_READCMD \ 1988 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1989 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1990#define BGE_NVRAM_WRITECMD \ 1991 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1992 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1993 1994#define BGE_NVRAMSWARB_SET0 0x00000001 1995#define BGE_NVRAMSWARB_SET1 0x00000002 1996#define BGE_NVRAMSWARB_SET2 0x00000003 1997#define BGE_NVRAMSWARB_SET3 0x00000004 1998#define BGE_NVRAMSWARB_CLR0 0x00000010 1999#define BGE_NVRAMSWARB_CLR1 0x00000020 2000#define BGE_NVRAMSWARB_CLR2 0x00000040 2001#define BGE_NVRAMSWARB_CLR3 0x00000080 2002#define BGE_NVRAMSWARB_GNT0 0x00000100 2003#define BGE_NVRAMSWARB_GNT1 0x00000200 2004#define BGE_NVRAMSWARB_GNT2 0x00000400 2005#define BGE_NVRAMSWARB_GNT3 0x00000800 2006#define BGE_NVRAMSWARB_REQ0 0x00001000 2007#define BGE_NVRAMSWARB_REQ1 0x00002000 2008#define BGE_NVRAMSWARB_REQ2 0x00004000 2009#define BGE_NVRAMSWARB_REQ3 0x00008000 2010 2011#define BGE_NVRAMACC_ENABLE 0x00000001 2012#define BGE_NVRAMACC_WRENABLE 0x00000002 2013 2014/* 2015 * TLP Control Register 2016 * Applicable to BCM5721 and BCM5751 only 2017 */ 2018#define BGE_TLP_CONTROL_REG 0x7c00 2019#define BGE_TLP_DATA_FIFO_PROTECT 0x02000000 2020 2021/* 2022 * PHY Test Control Register 2023 * Applicable to BCM5721 and BCM5751 only 2024 */ 2025#define BGE_PHY_TEST_CTRL_REG 0x7e2c 2026#define BGE_PHY_PCIE_SCRAM_MODE 0x0020 2027#define BGE_PHY_PCIE_LTASS_MODE 0x0040 2028 2029/* Mode control register */ 2030#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 2031#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 2032#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 2033#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 2034#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 2035#define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040 2036#define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080 2037#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 2038#define BGE_MODECTL_NO_RX_CRC 0x00000400 2039#define BGE_MODECTL_RX_BADFRAMES 0x00000800 2040#define BGE_MODECTL_NO_TX_INTR 0x00002000 2041#define BGE_MODECTL_NO_RX_INTR 0x00004000 2042#define BGE_MODECTL_FORCE_PCI32 0x00008000 2043#define BGE_MODECTL_B2HRX_ENABLE 0x00008000 2044#define BGE_MODECTL_STACKUP 0x00010000 2045#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 2046#define BGE_MODECTL_HTX2B_ENABLE 0x00040000 2047#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 2048#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 2049#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 2050#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 2051#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 2052#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 2053#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 2054#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 2055#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 2056 2057/* Misc. config register */ 2058#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 2059#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 2060#define BGE_MISCCFG_BOARD_ID_MASK 0x0001E000 2061#define BGE_MISCCFG_BOARD_ID_5704 0x00000000 2062#define BGE_MISCCFG_BOARD_ID_5704CIOBE 0x00004000 2063#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 2064#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 2065#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 2066#define BGE_MISCCFG_KEEP_GPHY_POWER 0x04000000 2067 2068#define BGE_32BITTIME_66MHZ (0x41 << 1) 2069 2070/* Misc. Local Control */ 2071#define BGE_MLC_INTR_STATE 0x00000001 2072#define BGE_MLC_INTR_CLR 0x00000002 2073#define BGE_MLC_INTR_SET 0x00000004 2074#define BGE_MLC_INTR_ONATTN 0x00000008 2075#define BGE_MLC_MISCIO_IN0 0x00000100 2076#define BGE_MLC_MISCIO_IN1 0x00000200 2077#define BGE_MLC_MISCIO_IN2 0x00000400 2078#define BGE_MLC_MISCIO_OUTEN0 0x00000800 2079#define BGE_MLC_MISCIO_OUTEN1 0x00001000 2080#define BGE_MLC_MISCIO_OUTEN2 0x00002000 2081#define BGE_MLC_MISCIO_OUT0 0x00004000 2082#define BGE_MLC_MISCIO_OUT1 0x00008000 2083#define BGE_MLC_MISCIO_OUT2 0x00010000 2084#define BGE_MLC_EXTRAM_ENB 0x00020000 2085#define BGE_MLC_SRAM_SIZE 0x001C0000 2086#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 2087#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 2088#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 2089#define BGE_MLC_AUTO_EEPROM 0x01000000 2090 2091#define BGE_SSRAMSIZE_256KB 0x00000000 2092#define BGE_SSRAMSIZE_512KB 0x00040000 2093#define BGE_SSRAMSIZE_1MB 0x00080000 2094#define BGE_SSRAMSIZE_2MB 0x000C0000 2095#define BGE_SSRAMSIZE_4MB 0x00100000 2096#define BGE_SSRAMSIZE_8MB 0x00140000 2097#define BGE_SSRAMSIZE_16M 0x00180000 2098 2099/* EEPROM address register */ 2100#define BGE_EEADDR_ADDRESS 0x0000FFFC 2101#define BGE_EEADDR_HALFCLK 0x01FF0000 2102#define BGE_EEADDR_START 0x02000000 2103#define BGE_EEADDR_DEVID 0x1C000000 2104#define BGE_EEADDR_RESET 0x20000000 2105#define BGE_EEADDR_DONE 0x40000000 2106#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 2107 2108#define BGE_EEDEVID(x) ((x & 7) << 26) 2109#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2110#define BGE_HALFCLK_384SCL 0x60 2111#define BGE_EE_READCMD \ 2112 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2113 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 2114#define BGE_EE_WRCMD \ 2115 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2116 BGE_EEADDR_START|BGE_EEADDR_DONE) 2117 2118/* EEPROM Control register */ 2119#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2120#define BGE_EECTL_CLKOUT 0x00000002 2121#define BGE_EECTL_CLKIN 0x00000004 2122#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2123#define BGE_EECTL_DATAOUT 0x00000010 2124#define BGE_EECTL_DATAIN 0x00000020 2125 2126/* MDI (MII/GMII) access register */ 2127#define BGE_MDI_DATA 0x00000001 2128#define BGE_MDI_DIR 0x00000002 2129#define BGE_MDI_SEL 0x00000004 2130#define BGE_MDI_CLK 0x00000008 2131 2132#define BGE_MEMWIN_START 0x00008000 2133#define BGE_MEMWIN_END 0x0000FFFF 2134 2135 2136#define BGE_MEMWIN_READ(pc, tag, x, val) \ 2137 do { \ 2138 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 2139 (0xFFFF0000 & x)); \ 2140 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 2141 } while(0) 2142 2143#define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 2144 do { \ 2145 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 2146 (0xFFFF0000 & x)); \ 2147 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 2148 } while(0) 2149 2150/* 2151 * This magic number is written to the firmware mailbox at 0xb50 2152 * before a software reset is issued. After the internal firmware 2153 * has completed its initialization it will write the opposite of 2154 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 2155 * driver to synchronize with the firmware. 2156 */ 2157#define BGE_MAGIC_NUMBER 0x4B657654 2158 2159typedef struct { 2160 u_int32_t bge_addr_hi; 2161 u_int32_t bge_addr_lo; 2162} bge_hostaddr; 2163#define BGE_HOSTADDR(x,y) \ 2164 do { \ 2165 (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 2166 if (sizeof(bus_addr_t) == 8) \ 2167 (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 2168 else \ 2169 (x).bge_addr_hi = 0; \ 2170 } while(0) 2171 2172/* Ring control block structure */ 2173struct bge_rcb { 2174 bge_hostaddr bge_hostaddr; 2175 u_int32_t bge_maxlen_flags; 2176 u_int32_t bge_nicaddr; 2177}; 2178 2179#define RCB_WRITE_4(sc, rcb, offset, val) \ 2180 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 2181 rcb + offsetof(struct bge_rcb, offset), val) 2182 2183#define RCB_WRITE_2(sc, rcb, offset, val) \ 2184 bus_space_write_2(sc->bge_btag, sc->bge_bhandle, \ 2185 rcb + offsetof(struct bge_rcb, offset), val) 2186 2187#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 2188 2189#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2190#define BGE_RCB_FLAG_RING_DISABLED 0x0002 2191 2192struct bge_tx_bd { 2193 bge_hostaddr bge_addr; 2194#if BYTE_ORDER == LITTLE_ENDIAN 2195 u_int16_t bge_flags; 2196 u_int16_t bge_len; 2197 u_int16_t bge_vlan_tag; 2198 u_int16_t bge_rsvd; 2199#else 2200 u_int16_t bge_len; 2201 u_int16_t bge_flags; 2202 u_int16_t bge_rsvd; 2203 u_int16_t bge_vlan_tag; 2204#endif 2205}; 2206 2207#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2208#define BGE_TXBDFLAG_IP_CSUM 0x0002 2209#define BGE_TXBDFLAG_END 0x0004 2210#define BGE_TXBDFLAG_IP_FRAG 0x0008 2211#define BGE_TXBDFLAG_JMB_PKT 0x0008 2212#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2213#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2214#define BGE_TXBDFLAG_COAL_NOW 0x0080 2215#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2216#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2217#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2218#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2219#define BGE_TXBDFLAG_NO_CRC 0x8000 2220 2221#define BGE_NIC_TXRING_ADDR(ringno, size) \ 2222 BGE_SEND_RING_1_TO_4 + \ 2223 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2224 2225struct bge_rx_bd { 2226 bge_hostaddr bge_addr; 2227#if BYTE_ORDER == LITTLE_ENDIAN 2228 u_int16_t bge_len; 2229 u_int16_t bge_idx; 2230 u_int16_t bge_flags; 2231 u_int16_t bge_type; 2232 u_int16_t bge_tcp_udp_csum; 2233 u_int16_t bge_ip_csum; 2234 u_int16_t bge_vlan_tag; 2235 u_int16_t bge_error_flag; 2236#else 2237 u_int16_t bge_idx; 2238 u_int16_t bge_len; 2239 u_int16_t bge_type; 2240 u_int16_t bge_flags; 2241 u_int16_t bge_ip_csum; 2242 u_int16_t bge_tcp_udp_csum; 2243 u_int16_t bge_error_flag; 2244 u_int16_t bge_vlan_tag; 2245#endif 2246 u_int32_t bge_rsvd; 2247 u_int32_t bge_opaque; 2248}; 2249 2250struct bge_ext_rx_bd { 2251 bge_hostaddr bge_addr1; 2252 bge_hostaddr bge_addr2; 2253 bge_hostaddr bge_addr3; 2254#if BYTE_ORDER == LITTLE_ENDIAN 2255 u_int16_t bge_len2; 2256 u_int16_t bge_len1; 2257 u_int16_t bge_rsvd; 2258 u_int16_t bge_len3; 2259#else 2260 u_int16_t bge_len1; 2261 u_int16_t bge_len2; 2262 u_int16_t bge_len3; 2263 u_int16_t bge_rsvd; 2264#endif 2265 struct bge_rx_bd bge_bd; 2266}; 2267 2268#define BGE_RXBDFLAG_END 0x0004 2269#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2270#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2271#define BGE_RXBDFLAG_ERROR 0x0400 2272#define BGE_RXBDFLAG_MINI_RING 0x0800 2273#define BGE_RXBDFLAG_IP_CSUM 0x1000 2274#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2275#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2276 2277#define BGE_RXERRFLAG_BAD_CRC 0x0001 2278#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2279#define BGE_RXERRFLAG_LINK_LOST 0x0004 2280#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2281#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2282#define BGE_RXERRFLAG_RUNT 0x0020 2283#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2284#define BGE_RXERRFLAG_GIANT 0x0080 2285 2286struct bge_sts_idx { 2287#if BYTE_ORDER == LITTLE_ENDIAN 2288 u_int16_t bge_rx_prod_idx; 2289 u_int16_t bge_tx_cons_idx; 2290#else 2291 u_int16_t bge_tx_cons_idx; 2292 u_int16_t bge_rx_prod_idx; 2293#endif 2294}; 2295 2296struct bge_status_block { 2297 u_int32_t bge_status; 2298 u_int32_t bge_rsvd0; 2299#if BYTE_ORDER == LITTLE_ENDIAN 2300 u_int16_t bge_rx_jumbo_cons_idx; 2301 u_int16_t bge_rx_std_cons_idx; 2302 u_int16_t bge_rx_mini_cons_idx; 2303 u_int16_t bge_rsvd1; 2304#else 2305 u_int16_t bge_rx_std_cons_idx; 2306 u_int16_t bge_rx_jumbo_cons_idx; 2307 u_int16_t bge_rsvd1; 2308 u_int16_t bge_rx_mini_cons_idx; 2309#endif 2310 struct bge_sts_idx bge_idx[16]; 2311}; 2312 2313#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 2314#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 2315 2316#define BGE_STATFLAG_UPDATED 0x00000001 2317#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2318#define BGE_STATFLAG_ERROR 0x00000004 2319 2320/* 2321 * SysKonnect Subsystem IDs 2322 */ 2323#define SK_SUBSYSID_9D41 0x4441 2324 2325/* 2326 * Dell PCI vendor ID 2327 */ 2328#define DELL_VENDORID 0x1028 2329 2330/* 2331 * Offset of MAC address inside EEPROM. 2332 */ 2333#define BGE_EE_MAC_OFFSET 0x7C 2334#define BGE_EE_MAC_OFFSET_5906 0x10 2335#define BGE_EE_HWCFG_OFFSET 0xC8 2336 2337#define BGE_HWCFG_VOLTAGE 0x00000003 2338#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2339#define BGE_HWCFG_MEDIA 0x00000030 2340#define BGE_HWCFG_ASF 0x00000080 2341 2342#define BGE_VOLTAGE_1POINT3 0x00000000 2343#define BGE_VOLTAGE_1POINT8 0x00000001 2344 2345#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2346#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2347#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2348 2349#define BGE_MEDIA_UNSPEC 0x00000000 2350#define BGE_MEDIA_COPPER 0x00000010 2351#define BGE_MEDIA_FIBER 0x00000020 2352 2353#define BGE_TICKS_PER_SEC 1000000 2354 2355/* 2356 * Ring size constants. 2357 */ 2358#define BGE_EVENT_RING_CNT 256 2359#define BGE_CMD_RING_CNT 64 2360#define BGE_STD_RX_RING_CNT 512 2361#define BGE_JUMBO_RX_RING_CNT 256 2362#define BGE_MINI_RX_RING_CNT 1024 2363#define BGE_RETURN_RING_CNT 1024 2364 2365/* 5705 has smaller return ring size */ 2366#define BGE_RETURN_RING_CNT_5705 512 2367 2368/* 2369 * Possible TX ring sizes. 2370 */ 2371#define BGE_TX_RING_CNT_128 128 2372#define BGE_TX_RING_BASE_128 0x3800 2373 2374#define BGE_TX_RING_CNT_256 256 2375#define BGE_TX_RING_BASE_256 0x3000 2376 2377#define BGE_TX_RING_CNT_512 512 2378#define BGE_TX_RING_BASE_512 0x2000 2379 2380#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2381#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2382 2383/* 2384 * Tigon III statistics counters. 2385 */ 2386/* Statistics maintained MAC Receive block. */ 2387struct bge_rx_mac_stats { 2388 bge_hostaddr ifHCInOctets; 2389 bge_hostaddr Reserved1; 2390 bge_hostaddr etherStatsFragments; 2391 bge_hostaddr ifHCInUcastPkts; 2392 bge_hostaddr ifHCInMulticastPkts; 2393 bge_hostaddr ifHCInBroadcastPkts; 2394 bge_hostaddr dot3StatsFCSErrors; 2395 bge_hostaddr dot3StatsAlignmentErrors; 2396 bge_hostaddr xonPauseFramesReceived; 2397 bge_hostaddr xoffPauseFramesReceived; 2398 bge_hostaddr macControlFramesReceived; 2399 bge_hostaddr xoffStateEntered; 2400 bge_hostaddr dot3StatsFramesTooLong; 2401 bge_hostaddr etherStatsJabbers; 2402 bge_hostaddr etherStatsUndersizePkts; 2403 bge_hostaddr inRangeLengthError; 2404 bge_hostaddr outRangeLengthError; 2405 bge_hostaddr etherStatsPkts64Octets; 2406 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2407 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2408 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2409 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2410 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2411 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2412 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2413 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2414 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2415}; 2416 2417/* Statistics maintained MAC Transmit block. */ 2418struct bge_tx_mac_stats { 2419 bge_hostaddr ifHCOutOctets; 2420 bge_hostaddr Reserved2; 2421 bge_hostaddr etherStatsCollisions; 2422 bge_hostaddr outXonSent; 2423 bge_hostaddr outXoffSent; 2424 bge_hostaddr flowControlDone; 2425 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2426 bge_hostaddr dot3StatsSingleCollisionFrames; 2427 bge_hostaddr dot3StatsMultipleCollisionFrames; 2428 bge_hostaddr dot3StatsDeferredTransmissions; 2429 bge_hostaddr Reserved3; 2430 bge_hostaddr dot3StatsExcessiveCollisions; 2431 bge_hostaddr dot3StatsLateCollisions; 2432 bge_hostaddr dot3Collided2Times; 2433 bge_hostaddr dot3Collided3Times; 2434 bge_hostaddr dot3Collided4Times; 2435 bge_hostaddr dot3Collided5Times; 2436 bge_hostaddr dot3Collided6Times; 2437 bge_hostaddr dot3Collided7Times; 2438 bge_hostaddr dot3Collided8Times; 2439 bge_hostaddr dot3Collided9Times; 2440 bge_hostaddr dot3Collided10Times; 2441 bge_hostaddr dot3Collided11Times; 2442 bge_hostaddr dot3Collided12Times; 2443 bge_hostaddr dot3Collided13Times; 2444 bge_hostaddr dot3Collided14Times; 2445 bge_hostaddr dot3Collided15Times; 2446 bge_hostaddr ifHCOutUcastPkts; 2447 bge_hostaddr ifHCOutMulticastPkts; 2448 bge_hostaddr ifHCOutBroadcastPkts; 2449 bge_hostaddr dot3StatsCarrierSenseErrors; 2450 bge_hostaddr ifOutDiscards; 2451 bge_hostaddr ifOutErrors; 2452}; 2453 2454/* Stats counters access through registers */ 2455struct bge_mac_stats_regs { 2456 u_int32_t ifHCOutOctets; 2457 u_int32_t Reserved0; 2458 u_int32_t etherStatsCollisions; 2459 u_int32_t outXonSent; 2460 u_int32_t outXoffSent; 2461 u_int32_t Reserved1; 2462 u_int32_t dot3StatsInternalMacTransmitErrors; 2463 u_int32_t dot3StatsSingleCollisionFrames; 2464 u_int32_t dot3StatsMultipleCollisionFrames; 2465 u_int32_t dot3StatsDeferredTransmissions; 2466 u_int32_t Reserved2; 2467 u_int32_t dot3StatsExcessiveCollisions; 2468 u_int32_t dot3StatsLateCollisions; 2469 u_int32_t Reserved3[14]; 2470 u_int32_t ifHCOutUcastPkts; 2471 u_int32_t ifHCOutMulticastPkts; 2472 u_int32_t ifHCOutBroadcastPkts; 2473 u_int32_t Reserved4[2]; 2474 u_int32_t ifHCInOctets; 2475 u_int32_t Reserved5; 2476 u_int32_t etherStatsFragments; 2477 u_int32_t ifHCInUcastPkts; 2478 u_int32_t ifHCInMulticastPkts; 2479 u_int32_t ifHCInBroadcastPkts; 2480 u_int32_t dot3StatsFCSErrors; 2481 u_int32_t dot3StatsAlignmentErrors; 2482 u_int32_t xonPauseFramesReceived; 2483 u_int32_t xoffPauseFramesReceived; 2484 u_int32_t macControlFramesReceived; 2485 u_int32_t xoffStateEntered; 2486 u_int32_t dot3StatsFramesTooLong; 2487 u_int32_t etherStatsJabbers; 2488 u_int32_t etherStatsUndersizePkts; 2489}; 2490 2491struct bge_stats { 2492 u_int8_t Reserved0[256]; 2493 2494 /* Statistics maintained by Receive MAC. */ 2495 struct bge_rx_mac_stats rxstats; 2496 2497 bge_hostaddr Unused1[37]; 2498 2499 /* Statistics maintained by Transmit MAC. */ 2500 struct bge_tx_mac_stats txstats; 2501 2502 bge_hostaddr Unused2[31]; 2503 2504 /* Statistics maintained by Receive List Placement. */ 2505 bge_hostaddr COSIfHCInPkts[16]; 2506 bge_hostaddr COSFramesDroppedDueToFilters; 2507 bge_hostaddr nicDmaWriteQueueFull; 2508 bge_hostaddr nicDmaWriteHighPriQueueFull; 2509 bge_hostaddr nicNoMoreRxBDs; 2510 bge_hostaddr ifInDiscards; 2511 bge_hostaddr ifInErrors; 2512 bge_hostaddr nicRecvThresholdHit; 2513 2514 bge_hostaddr Unused3[9]; 2515 2516 /* Statistics maintained by Send Data Initiator. */ 2517 bge_hostaddr COSIfHCOutPkts[16]; 2518 bge_hostaddr nicDmaReadQueueFull; 2519 bge_hostaddr nicDmaReadHighPriQueueFull; 2520 bge_hostaddr nicSendDataCompQueueFull; 2521 2522 /* Statistics maintained by Host Coalescing. */ 2523 bge_hostaddr nicRingSetSendProdIndex; 2524 bge_hostaddr nicRingStatusUpdate; 2525 bge_hostaddr nicInterrupts; 2526 bge_hostaddr nicAvoidedInterrupts; 2527 bge_hostaddr nicSendThresholdHit; 2528 2529 u_int8_t Reserved4[320]; 2530}; 2531 2532/* 2533 * Tigon general information block. This resides in host memory 2534 * and contains the status counters, ring control blocks and 2535 * producer pointers. 2536 */ 2537 2538struct bge_gib { 2539 struct bge_stats bge_stats; 2540 struct bge_rcb bge_tx_rcb[16]; 2541 struct bge_rcb bge_std_rx_rcb; 2542 struct bge_rcb bge_jumbo_rx_rcb; 2543 struct bge_rcb bge_mini_rx_rcb; 2544 struct bge_rcb bge_return_rcb; 2545}; 2546 2547/* 2548 * NOTE! On the Alpha, we have an alignment constraint. 2549 * The first thing in the packet is a 14-byte Ethernet header. 2550 * This means that the packet is misaligned. To compensate, 2551 * we actually offset the data 2 bytes into the cluster. This 2552 * aligns the packet after the Ethernet header to a 32-bit 2553 * boundary. 2554 */ 2555 2556#define BGE_JUMBO_FRAMELEN 9022 2557#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 2558#define BGE_PAGE_SIZE PAGE_SIZE 2559 2560/* 2561 * Other utility macros. 2562 */ 2563#define BGE_INC(x, y) (x) = (x + 1) % y 2564 2565/* 2566 * Vital product data and structures. 2567 */ 2568#define BGE_VPD_FLAG 0x8000 2569 2570#define VPD_RES_ID 0x82 /* ID string */ 2571#define VPD_RES_READ 0x90 /* start of read only area */ 2572#define VPD_RES_WRITE 0x81 /* start of read/write area */ 2573#define VPD_RES_END 0x78 /* end tag */ 2574 2575/* 2576 * Register access macros. The Tigon always uses memory mapped register 2577 * accesses and all registers must be accessed with 32 bit operations. 2578 */ 2579 2580#define CSR_WRITE_4(sc, reg, val) \ 2581 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2582 2583#define CSR_READ_4(sc, reg) \ 2584 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2585 2586#define BGE_SETBIT(sc, reg, x) \ 2587 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2588#define BGE_CLRBIT(sc, reg, x) \ 2589 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2590 2591#define PCI_SETBIT(pc, tag, reg, x) \ 2592 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 2593#define PCI_CLRBIT(pc, tag, reg, x) \ 2594 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 2595 2596/* 2597 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2598 * values are tuneable. They control the actual amount of buffers 2599 * allocated for the standard, mini and jumbo receive rings. 2600 */ 2601 2602#define BGE_SSLOTS 256 2603#define BGE_MSLOTS 256 2604#define BGE_JSLOTS 384 2605 2606#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2607#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2608 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2609 2610/* 2611 * Ring structures. Most of these reside in host memory and we tell 2612 * the NIC where they are via the ring control blocks. The exceptions 2613 * are the tx and command rings, which live in NIC memory and which 2614 * we access via the shared memory window. 2615 */ 2616struct bge_ring_data { 2617 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2618 struct bge_ext_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2619 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2620 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2621 struct bge_status_block bge_status_block; 2622 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2623 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2624 struct bge_gib bge_info; 2625}; 2626 2627#define BGE_RING_DMA_ADDR(sc, offset) \ 2628 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2629 offsetof(struct bge_ring_data, offset)) 2630 2631/* 2632 * Number of DMA segments in a TxCB. Note that this is carefully 2633 * chosen to make the total struct size an even power of two. It's 2634 * critical that no TxCB be split across a page boundary since 2635 * no attempt is made to allocate physically contiguous memory. 2636 * 2637 */ 2638#ifdef __LP64__ 2639#define BGE_NTXSEG 30 2640#else 2641#define BGE_NTXSEG 31 2642#endif 2643 2644/* 2645 * Mbuf pointers. We need these to keep track of the virtual addresses 2646 * of our mbuf chains since we can only convert from physical to virtual, 2647 * not the other way around. 2648 */ 2649struct bge_chain_data { 2650 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2651 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2652 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2653 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2654 bus_dmamap_t bge_tx_map[BGE_TX_RING_CNT]; 2655 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2656 bus_dmamap_t bge_rx_jumbo_map[BGE_JUMBO_RX_RING_CNT]; 2657}; 2658 2659struct bge_type { 2660 u_int16_t bge_vid; 2661 u_int16_t bge_did; 2662 char *bge_name; 2663}; 2664 2665#define BGE_TIMEOUT 100000 2666#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2667 2668struct txdmamap_pool_entry { 2669 bus_dmamap_t dmamap; 2670 SLIST_ENTRY(txdmamap_pool_entry) link; 2671}; 2672 2673#define ASF_ENABLE 1 2674#define ASF_NEW_HANDSHAKE 2 2675#define ASF_STACKUP 4 2676 2677struct bge_softc { 2678 struct device bge_dev; 2679 struct arpcom arpcom; /* interface info */ 2680 bus_space_handle_t bge_bhandle; 2681 bus_space_tag_t bge_btag; 2682 void *bge_intrhand; 2683 struct pci_attach_args bge_pa; 2684 struct mii_data bge_mii; 2685 struct ifmedia bge_ifmedia; /* media info */ 2686 u_int32_t bge_flags; 2687#define BGE_TXRING_VALID 0x00000001 2688#define BGE_RXRING_VALID 0x00000002 2689#define BGE_JUMBO_RXRING_VALID 0x00000004 2690#define BGE_RX_ALIGNBUG 0x00000008 2691#define BGE_NO_3LED 0x00000010 2692#define BGE_PCIX 0x00000020 2693#define BGE_PCIE 0x00000040 2694#define BGE_ASF_MODE 0x00000080 2695#define BGE_NO_EEPROM 0x00000100 2696#define BGE_JUMBO_CAPABLE 0x00000200 2697#define BGE_10_100_ONLY 0x00000400 2698#define BGE_PHY_FIBER_TBI 0x00000800 2699#define BGE_PHY_FIBER_MII 0x00001000 2700#define BGE_PHY_CRC_BUG 0x00002000 2701#define BGE_PHY_ADC_BUG 0x00004000 2702#define BGE_PHY_5704_A0_BUG 0x00008000 2703#define BGE_PHY_JITTER_BUG 0x00010000 2704#define BGE_PHY_BER_BUG 0x00020000 2705#define BGE_PHY_ADJUST_TRIM 0x00040000 2706#define BGE_NO_ETH_WIRE_SPEED 0x00080000 2707#define BGE_IS_5788 0x00100000 2708#define BGE_5705_PLUS 0x00200000 2709#define BGE_575X_PLUS 0x00400000 2710#define BGE_5755_PLUS 0x00800000 2711#define BGE_5714_FAMILY 0x01000000 2712#define BGE_5700_FAMILY 0x02000000 2713#define BGE_5717_PLUS 0x04000000 2714#define BGE_57765_PLUS 0x08000000 2715#define BGE_APE 0x10000000 2716#define BGE_CPMU_PRESENT 0x20000000 2717 2718 bus_dma_tag_t bge_dmatag; 2719 int bge_phy_addr; 2720 u_int32_t bge_chipid; 2721 struct bge_ring_data *bge_rdata; /* rings */ 2722 struct bge_chain_data bge_cdata; /* mbufs */ 2723 bus_dmamap_t bge_ring_map; 2724 u_int16_t bge_tx_saved_considx; 2725 u_int16_t bge_rx_saved_considx; 2726 u_int16_t bge_ev_saved_considx; 2727 u_int16_t bge_return_ring_cnt; 2728 u_int32_t bge_tx_prodidx; 2729 u_int16_t bge_std; /* current std ring head */ 2730 int bge_std_cnt; 2731 u_int16_t bge_jumbo; /* current jumo ring head */ 2732 int bge_jumbo_cnt; 2733 u_int32_t bge_stat_ticks; 2734 u_int32_t bge_rx_coal_ticks; 2735 u_int32_t bge_tx_coal_ticks; 2736 u_int32_t bge_rx_max_coal_bds; 2737 u_int32_t bge_tx_max_coal_bds; 2738 u_int32_t bge_tx_buf_ratio; 2739 u_int32_t bge_sts; 2740#define BGE_STS_LINK 0x00000001 /* MAC link status */ 2741#define BGE_STS_LINK_EVT 0x00000002 /* pending link event */ 2742#define BGE_STS_AUTOPOLL 0x00000004 /* PHY auto-polling */ 2743#define BGE_STS_BIT(sc, x) ((sc)->bge_sts & (x)) 2744#define BGE_STS_SETBIT(sc, x) ((sc)->bge_sts |= (x)) 2745#define BGE_STS_CLRBIT(sc, x) ((sc)->bge_sts &= ~(x)) 2746 int bge_flowflags; 2747 int bge_txcnt; 2748 struct timeout bge_timeout; 2749 struct timeout bge_rxtimeout; 2750 u_int32_t bge_rx_discards; 2751 u_int32_t bge_tx_discards; 2752 u_int32_t bge_rx_inerrors; 2753 u_int32_t bge_rx_overruns; 2754 u_int32_t bge_tx_collisions; 2755 SLIST_HEAD(, txdmamap_pool_entry) txdma_list; 2756 struct txdmamap_pool_entry *txdma[BGE_TX_RING_CNT]; 2757}; 2758