rv770d.h revision 1.1
1/* $OpenBSD: rv770d.h,v 1.1 2013/08/12 04:11:53 jsg Exp $ */ 2/* 3 * Copyright 2009 Advanced Micro Devices, Inc. 4 * Copyright 2009 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#ifndef RV770_H 29#define RV770_H 30 31#define R7XX_MAX_SH_GPRS 256 32#define R7XX_MAX_TEMP_GPRS 16 33#define R7XX_MAX_SH_THREADS 256 34#define R7XX_MAX_SH_STACK_ENTRIES 4096 35#define R7XX_MAX_BACKENDS 8 36#define R7XX_MAX_BACKENDS_MASK 0xff 37#define R7XX_MAX_SIMDS 16 38#define R7XX_MAX_SIMDS_MASK 0xffff 39#define R7XX_MAX_PIPES 8 40#define R7XX_MAX_PIPES_MASK 0xff 41 42/* Registers */ 43#define CB_COLOR0_BASE 0x28040 44#define CB_COLOR1_BASE 0x28044 45#define CB_COLOR2_BASE 0x28048 46#define CB_COLOR3_BASE 0x2804C 47#define CB_COLOR4_BASE 0x28050 48#define CB_COLOR5_BASE 0x28054 49#define CB_COLOR6_BASE 0x28058 50#define CB_COLOR7_BASE 0x2805C 51#define CB_COLOR7_FRAG 0x280FC 52 53#define CC_GC_SHADER_PIPE_CONFIG 0x8950 54#define CC_RB_BACKEND_DISABLE 0x98F4 55#define BACKEND_DISABLE(x) ((x) << 16) 56#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 57 58#define CGTS_SYS_TCC_DISABLE 0x3F90 59#define CGTS_TCC_DISABLE 0x9148 60#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 61#define CGTS_USER_TCC_DISABLE 0x914C 62 63#define CONFIG_MEMSIZE 0x5428 64 65#define CP_ME_CNTL 0x86D8 66#define CP_ME_HALT (1<<28) 67#define CP_PFP_HALT (1<<26) 68#define CP_ME_RAM_DATA 0xC160 69#define CP_ME_RAM_RADDR 0xC158 70#define CP_ME_RAM_WADDR 0xC15C 71#define CP_MEQ_THRESHOLDS 0x8764 72#define STQ_SPLIT(x) ((x) << 0) 73#define CP_PERFMON_CNTL 0x87FC 74#define CP_PFP_UCODE_ADDR 0xC150 75#define CP_PFP_UCODE_DATA 0xC154 76#define CP_QUEUE_THRESHOLDS 0x8760 77#define ROQ_IB1_START(x) ((x) << 0) 78#define ROQ_IB2_START(x) ((x) << 8) 79#define CP_RB_CNTL 0xC104 80#define RB_BUFSZ(x) ((x) << 0) 81#define RB_BLKSZ(x) ((x) << 8) 82#define RB_NO_UPDATE (1 << 27) 83#define RB_RPTR_WR_ENA (1 << 31) 84#define BUF_SWAP_32BIT (2 << 16) 85#define CP_RB_RPTR 0x8700 86#define CP_RB_RPTR_ADDR 0xC10C 87#define CP_RB_RPTR_ADDR_HI 0xC110 88#define CP_RB_RPTR_WR 0xC108 89#define CP_RB_WPTR 0xC114 90#define CP_RB_WPTR_ADDR 0xC118 91#define CP_RB_WPTR_ADDR_HI 0xC11C 92#define CP_RB_WPTR_DELAY 0x8704 93#define CP_SEM_WAIT_TIMER 0x85BC 94 95#define DB_DEBUG3 0x98B0 96#define DB_CLK_OFF_DELAY(x) ((x) << 11) 97#define DB_DEBUG4 0x9B8C 98#define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 99 100#define DCP_TILING_CONFIG 0x6CA0 101#define PIPE_TILING(x) ((x) << 1) 102#define BANK_TILING(x) ((x) << 4) 103#define GROUP_SIZE(x) ((x) << 6) 104#define ROW_TILING(x) ((x) << 8) 105#define BANK_SWAPS(x) ((x) << 11) 106#define SAMPLE_SPLIT(x) ((x) << 14) 107#define BACKEND_MAP(x) ((x) << 16) 108 109#define GB_TILING_CONFIG 0x98F0 110#define PIPE_TILING__SHIFT 1 111#define PIPE_TILING__MASK 0x0000000e 112 113#define DMA_TILING_CONFIG 0x3ec8 114#define DMA_TILING_CONFIG2 0xd0b8 115 116#define GC_USER_SHADER_PIPE_CONFIG 0x8954 117#define INACTIVE_QD_PIPES(x) ((x) << 8) 118#define INACTIVE_QD_PIPES_MASK 0x0000FF00 119#define INACTIVE_QD_PIPES_SHIFT 8 120#define INACTIVE_SIMDS(x) ((x) << 16) 121#define INACTIVE_SIMDS_MASK 0x00FF0000 122 123#define GRBM_CNTL 0x8000 124#define GRBM_READ_TIMEOUT(x) ((x) << 0) 125#define GRBM_SOFT_RESET 0x8020 126#define SOFT_RESET_CP (1<<0) 127#define GRBM_STATUS 0x8010 128#define CMDFIFO_AVAIL_MASK 0x0000000F 129#define GUI_ACTIVE (1<<31) 130#define GRBM_STATUS2 0x8014 131 132#define CG_MULT_THERMAL_STATUS 0x740 133#define ASIC_T(x) ((x) << 16) 134#define ASIC_T_MASK 0x3FF0000 135#define ASIC_T_SHIFT 16 136 137#define HDP_HOST_PATH_CNTL 0x2C00 138#define HDP_NONSURFACE_BASE 0x2C04 139#define HDP_NONSURFACE_INFO 0x2C08 140#define HDP_NONSURFACE_SIZE 0x2C0C 141#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 142#define HDP_TILING_CONFIG 0x2F3C 143#define HDP_DEBUG1 0x2F34 144 145#define MC_SHARED_CHMAP 0x2004 146#define NOOFCHAN_SHIFT 12 147#define NOOFCHAN_MASK 0x00003000 148#define MC_SHARED_CHREMAP 0x2008 149 150#define MC_ARB_RAMCFG 0x2760 151#define NOOFBANK_SHIFT 0 152#define NOOFBANK_MASK 0x00000003 153#define NOOFRANK_SHIFT 2 154#define NOOFRANK_MASK 0x00000004 155#define NOOFROWS_SHIFT 3 156#define NOOFROWS_MASK 0x00000038 157#define NOOFCOLS_SHIFT 6 158#define NOOFCOLS_MASK 0x000000C0 159#define CHANSIZE_SHIFT 8 160#define CHANSIZE_MASK 0x00000100 161#define BURSTLENGTH_SHIFT 9 162#define BURSTLENGTH_MASK 0x00000200 163#define CHANSIZE_OVERRIDE (1 << 11) 164#define MC_VM_AGP_TOP 0x2028 165#define MC_VM_AGP_BOT 0x202C 166#define MC_VM_AGP_BASE 0x2030 167#define MC_VM_FB_LOCATION 0x2024 168#define MC_VM_MB_L1_TLB0_CNTL 0x2234 169#define MC_VM_MB_L1_TLB1_CNTL 0x2238 170#define MC_VM_MB_L1_TLB2_CNTL 0x223C 171#define MC_VM_MB_L1_TLB3_CNTL 0x2240 172#define ENABLE_L1_TLB (1 << 0) 173#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 174#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 175#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 176#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 177#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 178#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 179#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 180#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 181#define MC_VM_MD_L1_TLB0_CNTL 0x2654 182#define MC_VM_MD_L1_TLB1_CNTL 0x2658 183#define MC_VM_MD_L1_TLB2_CNTL 0x265C 184#define MC_VM_MD_L1_TLB3_CNTL 0x2698 185#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 186#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 187#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 188 189#define PA_CL_ENHANCE 0x8A14 190#define CLIP_VTX_REORDER_ENA (1 << 0) 191#define NUM_CLIP_SEQ(x) ((x) << 1) 192#define PA_SC_AA_CONFIG 0x28C04 193#define PA_SC_CLIPRECT_RULE 0x2820C 194#define PA_SC_EDGERULE 0x28230 195#define PA_SC_FIFO_SIZE 0x8BCC 196#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 197#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 198#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 199#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) 200#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) 201#define PA_SC_LINE_STIPPLE 0x28A0C 202#define PA_SC_LINE_STIPPLE_STATE 0x8B10 203#define PA_SC_MODE_CNTL 0x28A4C 204#define PA_SC_MULTI_CHIP_CNTL 0x8B20 205#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 206 207#define SCRATCH_REG0 0x8500 208#define SCRATCH_REG1 0x8504 209#define SCRATCH_REG2 0x8508 210#define SCRATCH_REG3 0x850C 211#define SCRATCH_REG4 0x8510 212#define SCRATCH_REG5 0x8514 213#define SCRATCH_REG6 0x8518 214#define SCRATCH_REG7 0x851C 215#define SCRATCH_UMSK 0x8540 216#define SCRATCH_ADDR 0x8544 217 218#define SMX_SAR_CTL0 0xA008 219#define SMX_DC_CTL0 0xA020 220#define USE_HASH_FUNCTION (1 << 0) 221#define CACHE_DEPTH(x) ((x) << 1) 222#define FLUSH_ALL_ON_EVENT (1 << 10) 223#define STALL_ON_EVENT (1 << 11) 224#define SMX_EVENT_CTL 0xA02C 225#define ES_FLUSH_CTL(x) ((x) << 0) 226#define GS_FLUSH_CTL(x) ((x) << 3) 227#define ACK_FLUSH_CTL(x) ((x) << 6) 228#define SYNC_FLUSH_CTL (1 << 8) 229 230#define SPI_CONFIG_CNTL 0x9100 231#define GPR_WRITE_PRIORITY(x) ((x) << 0) 232#define DISABLE_INTERP_1 (1 << 5) 233#define SPI_CONFIG_CNTL_1 0x913C 234#define VTX_DONE_DELAY(x) ((x) << 0) 235#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 236#define SPI_INPUT_Z 0x286D8 237#define SPI_PS_IN_CONTROL_0 0x286CC 238#define NUM_INTERP(x) ((x)<<0) 239#define POSITION_ENA (1<<8) 240#define POSITION_CENTROID (1<<9) 241#define POSITION_ADDR(x) ((x)<<10) 242#define PARAM_GEN(x) ((x)<<15) 243#define PARAM_GEN_ADDR(x) ((x)<<19) 244#define BARYC_SAMPLE_CNTL(x) ((x)<<26) 245#define PERSP_GRADIENT_ENA (1<<28) 246#define LINEAR_GRADIENT_ENA (1<<29) 247#define POSITION_SAMPLE (1<<30) 248#define BARYC_AT_SAMPLE_ENA (1<<31) 249 250#define SQ_CONFIG 0x8C00 251#define VC_ENABLE (1 << 0) 252#define EXPORT_SRC_C (1 << 1) 253#define DX9_CONSTS (1 << 2) 254#define ALU_INST_PREFER_VECTOR (1 << 3) 255#define DX10_CLAMP (1 << 4) 256#define CLAUSE_SEQ_PRIO(x) ((x) << 8) 257#define PS_PRIO(x) ((x) << 24) 258#define VS_PRIO(x) ((x) << 26) 259#define GS_PRIO(x) ((x) << 28) 260#define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0 261#define SIMDA_RING0(x) ((x)<<0) 262#define SIMDA_RING1(x) ((x)<<8) 263#define SIMDB_RING0(x) ((x)<<16) 264#define SIMDB_RING1(x) ((x)<<24) 265#define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4 266#define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8 267#define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC 268#define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0 269#define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4 270#define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8 271#define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC 272#define ES_PRIO(x) ((x) << 30) 273#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 274#define NUM_PS_GPRS(x) ((x) << 0) 275#define NUM_VS_GPRS(x) ((x) << 16) 276#define DYN_GPR_ENABLE (1 << 27) 277#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 278#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 279#define NUM_GS_GPRS(x) ((x) << 0) 280#define NUM_ES_GPRS(x) ((x) << 16) 281#define SQ_MS_FIFO_SIZES 0x8CF0 282#define CACHE_FIFO_SIZE(x) ((x) << 0) 283#define FETCH_FIFO_HIWATER(x) ((x) << 8) 284#define DONE_FIFO_HIWATER(x) ((x) << 16) 285#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 286#define SQ_STACK_RESOURCE_MGMT_1 0x8C10 287#define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 288#define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 289#define SQ_STACK_RESOURCE_MGMT_2 0x8C14 290#define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 291#define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 292#define SQ_THREAD_RESOURCE_MGMT 0x8C0C 293#define NUM_PS_THREADS(x) ((x) << 0) 294#define NUM_VS_THREADS(x) ((x) << 8) 295#define NUM_GS_THREADS(x) ((x) << 16) 296#define NUM_ES_THREADS(x) ((x) << 24) 297 298#define SX_DEBUG_1 0x9058 299#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 300#define SX_EXPORT_BUFFER_SIZES 0x900C 301#define COLOR_BUFFER_SIZE(x) ((x) << 0) 302#define POSITION_BUFFER_SIZE(x) ((x) << 8) 303#define SMX_BUFFER_SIZE(x) ((x) << 16) 304#define SX_MISC 0x28350 305 306#define TA_CNTL_AUX 0x9508 307#define DISABLE_CUBE_WRAP (1 << 0) 308#define DISABLE_CUBE_ANISO (1 << 1) 309#define SYNC_GRADIENT (1 << 24) 310#define SYNC_WALKER (1 << 25) 311#define SYNC_ALIGNER (1 << 26) 312#define BILINEAR_PRECISION_6_BIT (0 << 31) 313#define BILINEAR_PRECISION_8_BIT (1 << 31) 314 315#define TCP_CNTL 0x9610 316#define TCP_CHAN_STEER 0x9614 317 318#define VC_ENHANCE 0x9714 319 320#define VGT_CACHE_INVALIDATION 0x88C4 321#define CACHE_INVALIDATION(x) ((x)<<0) 322#define VC_ONLY 0 323#define TC_ONLY 1 324#define VC_AND_TC 2 325#define AUTO_INVLD_EN(x) ((x) << 6) 326#define NO_AUTO 0 327#define ES_AUTO 1 328#define GS_AUTO 2 329#define ES_AND_GS_AUTO 3 330#define VGT_ES_PER_GS 0x88CC 331#define VGT_GS_PER_ES 0x88C8 332#define VGT_GS_PER_VS 0x88E8 333#define VGT_GS_VERTEX_REUSE 0x88D4 334#define VGT_NUM_INSTANCES 0x8974 335#define VGT_OUT_DEALLOC_CNTL 0x28C5C 336#define DEALLOC_DIST_MASK 0x0000007F 337#define VGT_STRMOUT_EN 0x28AB0 338#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 339#define VTX_REUSE_DEPTH_MASK 0x000000FF 340 341#define VM_CONTEXT0_CNTL 0x1410 342#define ENABLE_CONTEXT (1 << 0) 343#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 344#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 345#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 346#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 347#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 348#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 349#define VM_L2_CNTL 0x1400 350#define ENABLE_L2_CACHE (1 << 0) 351#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 352#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 353#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 354#define VM_L2_CNTL2 0x1404 355#define INVALIDATE_ALL_L1_TLBS (1 << 0) 356#define INVALIDATE_L2_CACHE (1 << 1) 357#define VM_L2_CNTL3 0x1408 358#define BANK_SELECT(x) ((x) << 0) 359#define CACHE_UPDATE_MODE(x) ((x) << 6) 360#define VM_L2_STATUS 0x140C 361#define L2_BUSY (1 << 0) 362 363#define WAIT_UNTIL 0x8040 364 365/* async DMA */ 366#define DMA_RB_RPTR 0xd008 367#define DMA_RB_WPTR 0xd00c 368 369/* async DMA packets */ 370#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 371 (((t) & 0x1) << 23) | \ 372 (((s) & 0x1) << 22) | \ 373 (((n) & 0xFFFF) << 0)) 374/* async DMA Packet types */ 375#define DMA_PACKET_WRITE 0x2 376#define DMA_PACKET_COPY 0x3 377#define DMA_PACKET_INDIRECT_BUFFER 0x4 378#define DMA_PACKET_SEMAPHORE 0x5 379#define DMA_PACKET_FENCE 0x6 380#define DMA_PACKET_TRAP 0x7 381#define DMA_PACKET_CONSTANT_FILL 0xd 382#define DMA_PACKET_NOP 0xf 383 384 385#define SRBM_STATUS 0x0E50 386 387/* DCE 3.2 HDMI */ 388#define HDMI_CONTROL 0x7400 389# define HDMI_KEEPOUT_MODE (1 << 0) 390# define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ 391# define HDMI_ERROR_ACK (1 << 8) 392# define HDMI_ERROR_MASK (1 << 9) 393#define HDMI_STATUS 0x7404 394# define HDMI_ACTIVE_AVMUTE (1 << 0) 395# define HDMI_AUDIO_PACKET_ERROR (1 << 16) 396# define HDMI_VBI_PACKET_ERROR (1 << 20) 397#define HDMI_AUDIO_PACKET_CONTROL 0x7408 398# define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 399# define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 400#define HDMI_ACR_PACKET_CONTROL 0x740c 401# define HDMI_ACR_SEND (1 << 0) 402# define HDMI_ACR_CONT (1 << 1) 403# define HDMI_ACR_SELECT(x) (((x) & 3) << 4) 404# define HDMI_ACR_HW 0 405# define HDMI_ACR_32 1 406# define HDMI_ACR_44 2 407# define HDMI_ACR_48 3 408# define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 409# define HDMI_ACR_AUTO_SEND (1 << 12) 410#define HDMI_VBI_PACKET_CONTROL 0x7410 411# define HDMI_NULL_SEND (1 << 0) 412# define HDMI_GC_SEND (1 << 4) 413# define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 414#define HDMI_INFOFRAME_CONTROL0 0x7414 415# define HDMI_AVI_INFO_SEND (1 << 0) 416# define HDMI_AVI_INFO_CONT (1 << 1) 417# define HDMI_AUDIO_INFO_SEND (1 << 4) 418# define HDMI_AUDIO_INFO_CONT (1 << 5) 419# define HDMI_MPEG_INFO_SEND (1 << 8) 420# define HDMI_MPEG_INFO_CONT (1 << 9) 421#define HDMI_INFOFRAME_CONTROL1 0x7418 422# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 423# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 424# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 425#define HDMI_GENERIC_PACKET_CONTROL 0x741c 426# define HDMI_GENERIC0_SEND (1 << 0) 427# define HDMI_GENERIC0_CONT (1 << 1) 428# define HDMI_GENERIC1_SEND (1 << 4) 429# define HDMI_GENERIC1_CONT (1 << 5) 430# define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 431# define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 432#define HDMI_GC 0x7428 433# define HDMI_GC_AVMUTE (1 << 0) 434#define AFMT_AUDIO_PACKET_CONTROL2 0x742c 435# define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) 436# define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) 437# define AFMT_60958_CS_SOURCE (1 << 4) 438# define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) 439# define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) 440#define AFMT_AVI_INFO0 0x7454 441# define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 442# define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) 443# define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) 444# define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) 445# define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) 446# define AFMT_AVI_INFO_Y_RGB 0 447# define AFMT_AVI_INFO_Y_YCBCR422 1 448# define AFMT_AVI_INFO_Y_YCBCR444 2 449# define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 450# define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) 451# define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) 452# define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) 453# define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 454# define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) 455# define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) 456# define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) 457# define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) 458# define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 459#define AFMT_AVI_INFO1 0x7458 460# define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 461# define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 462# define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 463#define AFMT_AVI_INFO2 0x745c 464# define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 465# define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 466#define AFMT_AVI_INFO3 0x7460 467# define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 468# define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) 469#define AFMT_MPEG_INFO0 0x7464 470# define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 471# define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 472# define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 473# define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 474#define AFMT_MPEG_INFO1 0x7468 475# define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 476# define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) 477# define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) 478#define AFMT_GENERIC0_HDR 0x746c 479#define AFMT_GENERIC0_0 0x7470 480#define AFMT_GENERIC0_1 0x7474 481#define AFMT_GENERIC0_2 0x7478 482#define AFMT_GENERIC0_3 0x747c 483#define AFMT_GENERIC0_4 0x7480 484#define AFMT_GENERIC0_5 0x7484 485#define AFMT_GENERIC0_6 0x7488 486#define AFMT_GENERIC1_HDR 0x748c 487#define AFMT_GENERIC1_0 0x7490 488#define AFMT_GENERIC1_1 0x7494 489#define AFMT_GENERIC1_2 0x7498 490#define AFMT_GENERIC1_3 0x749c 491#define AFMT_GENERIC1_4 0x74a0 492#define AFMT_GENERIC1_5 0x74a4 493#define AFMT_GENERIC1_6 0x74a8 494#define HDMI_ACR_32_0 0x74ac 495# define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 496#define HDMI_ACR_32_1 0x74b0 497# define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) 498#define HDMI_ACR_44_0 0x74b4 499# define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 500#define HDMI_ACR_44_1 0x74b8 501# define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) 502#define HDMI_ACR_48_0 0x74bc 503# define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 504#define HDMI_ACR_48_1 0x74c0 505# define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) 506#define HDMI_ACR_STATUS_0 0x74c4 507#define HDMI_ACR_STATUS_1 0x74c8 508#define AFMT_AUDIO_INFO0 0x74cc 509# define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 510# define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) 511# define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) 512#define AFMT_AUDIO_INFO1 0x74d0 513# define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 514# define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 515# define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 516# define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 517#define AFMT_60958_0 0x74d4 518# define AFMT_60958_CS_A(x) (((x) & 1) << 0) 519# define AFMT_60958_CS_B(x) (((x) & 1) << 1) 520# define AFMT_60958_CS_C(x) (((x) & 1) << 2) 521# define AFMT_60958_CS_D(x) (((x) & 3) << 3) 522# define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) 523# define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 524# define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 525# define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 526# define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 527# define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 528#define AFMT_60958_1 0x74d8 529# define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 530# define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 531# define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) 532# define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) 533# define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 534#define AFMT_AUDIO_CRC_CONTROL 0x74dc 535# define AFMT_AUDIO_CRC_EN (1 << 0) 536#define AFMT_RAMP_CONTROL0 0x74e0 537# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 538# define AFMT_RAMP_DATA_SIGN (1 << 31) 539#define AFMT_RAMP_CONTROL1 0x74e4 540# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 541# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) 542#define AFMT_RAMP_CONTROL2 0x74e8 543# define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 544#define AFMT_RAMP_CONTROL3 0x74ec 545# define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 546#define AFMT_60958_2 0x74f0 547# define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 548# define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 549# define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 550# define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 551# define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 552# define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 553#define AFMT_STATUS 0x7600 554# define AFMT_AUDIO_ENABLE (1 << 4) 555# define AFMT_AZ_FORMAT_WTRIG (1 << 28) 556# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 557# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 558#define AFMT_AUDIO_PACKET_CONTROL 0x7604 559# define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 560# define AFMT_AUDIO_TEST_EN (1 << 12) 561# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 562# define AFMT_60958_CS_UPDATE (1 << 26) 563# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 564# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 565# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 566# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 567#define AFMT_VBI_PACKET_CONTROL 0x7608 568# define AFMT_GENERIC0_UPDATE (1 << 2) 569#define AFMT_INFOFRAME_CONTROL0 0x760c 570# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */ 571# define AFMT_AUDIO_INFO_UPDATE (1 << 7) 572# define AFMT_MPEG_INFO_UPDATE (1 << 10) 573#define AFMT_GENERIC0_7 0x7610 574/* second instance starts at 0x7800 */ 575#define HDMI_OFFSET0 (0x7400 - 0x7400) 576#define HDMI_OFFSET1 (0x7800 - 0x7400) 577 578/* DCE3.2 ELD audio interface */ 579#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */ 580#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */ 581#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */ 582#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */ 583#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */ 584#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */ 585#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */ 586#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */ 587#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */ 588#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */ 589#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */ 590#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */ 591#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */ 592#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */ 593# define MAX_CHANNELS(x) (((x) & 0x7) << 0) 594/* max channels minus one. 7 = 8 channels */ 595# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 596# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 597# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 598/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 599 * bit0 = 32 kHz 600 * bit1 = 44.1 kHz 601 * bit2 = 48 kHz 602 * bit3 = 88.2 kHz 603 * bit4 = 96 kHz 604 * bit5 = 176.4 kHz 605 * bit6 = 192 kHz 606 */ 607 608#define AZ_HOT_PLUG_CONTROL 0x7300 609# define AZ_FORCE_CODEC_WAKE (1 << 0) 610# define PIN0_JACK_DETECTION_ENABLE (1 << 4) 611# define PIN1_JACK_DETECTION_ENABLE (1 << 5) 612# define PIN2_JACK_DETECTION_ENABLE (1 << 6) 613# define PIN3_JACK_DETECTION_ENABLE (1 << 7) 614# define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8) 615# define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9) 616# define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10) 617# define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11) 618# define CODEC_HOT_PLUG_ENABLE (1 << 12) 619# define PIN0_AUDIO_ENABLED (1 << 24) 620# define PIN1_AUDIO_ENABLED (1 << 25) 621# define PIN2_AUDIO_ENABLED (1 << 26) 622# define PIN3_AUDIO_ENABLED (1 << 27) 623# define AUDIO_ENABLED (1 << 31) 624 625 626#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 627#define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 628#define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 629#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 630#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c 631#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c 632 633/* PCIE link stuff */ 634#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 635#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 636# define LC_LINK_WIDTH_SHIFT 0 637# define LC_LINK_WIDTH_MASK 0x7 638# define LC_LINK_WIDTH_X0 0 639# define LC_LINK_WIDTH_X1 1 640# define LC_LINK_WIDTH_X2 2 641# define LC_LINK_WIDTH_X4 3 642# define LC_LINK_WIDTH_X8 4 643# define LC_LINK_WIDTH_X16 6 644# define LC_LINK_WIDTH_RD_SHIFT 4 645# define LC_LINK_WIDTH_RD_MASK 0x70 646# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 647# define LC_RECONFIG_NOW (1 << 8) 648# define LC_RENEGOTIATION_SUPPORT (1 << 9) 649# define LC_RENEGOTIATE_EN (1 << 10) 650# define LC_SHORT_RECONFIG_EN (1 << 11) 651# define LC_UPCONFIGURE_SUPPORT (1 << 12) 652# define LC_UPCONFIGURE_DIS (1 << 13) 653#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 654# define LC_GEN2_EN_STRAP (1 << 0) 655# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 656# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 657# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 658# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 659# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 660# define LC_CURRENT_DATA_RATE (1 << 11) 661# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 662# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 663# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 664# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 665#define MM_CFGREGS_CNTL 0x544c 666# define MM_WR_TO_CFG_EN (1 << 3) 667#define LINK_CNTL2 0x88 /* F0 */ 668# define TARGET_LINK_SPEED_MASK (0xf << 0) 669# define SELECTABLE_DEEMPHASIS (1 << 6) 670 671#endif 672