1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29#include <linux/seq_file.h> 30#include <linux/slab.h> 31 32#include <drm/drm_device.h> 33#include <drm/drm_file.h> 34 35#include "atom.h" 36#include "radeon.h" 37#include "radeon_asic.h" 38#include "rv515_reg_safe.h" 39#include "rv515d.h" 40 41/* This files gather functions specifics to: rv515 */ 42static void rv515_gpu_init(struct radeon_device *rdev); 43int rv515_mc_wait_for_idle(struct radeon_device *rdev); 44 45static const u32 crtc_offsets[2] = 46{ 47 0, 48 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 49}; 50 51void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 52{ 53 int r; 54 55 r = radeon_ring_lock(rdev, ring, 64); 56 if (r) { 57 return; 58 } 59 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); 60 radeon_ring_write(ring, 61 ISYNC_ANY2D_IDLE3D | 62 ISYNC_ANY3D_IDLE2D | 63 ISYNC_WAIT_IDLEGUI | 64 ISYNC_CPSCRATCH_IDLEGUI); 65 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 66 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 67 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 68 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 69 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); 70 radeon_ring_write(ring, 0); 71 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); 72 radeon_ring_write(ring, 0); 73 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); 74 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); 75 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); 76 radeon_ring_write(ring, 0); 77 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 78 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 79 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 80 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 81 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 82 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 83 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); 84 radeon_ring_write(ring, 0); 85 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 86 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 87 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 88 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 89 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); 90 radeon_ring_write(ring, 91 ((6 << MS_X0_SHIFT) | 92 (6 << MS_Y0_SHIFT) | 93 (6 << MS_X1_SHIFT) | 94 (6 << MS_Y1_SHIFT) | 95 (6 << MS_X2_SHIFT) | 96 (6 << MS_Y2_SHIFT) | 97 (6 << MSBD0_Y_SHIFT) | 98 (6 << MSBD0_X_SHIFT))); 99 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); 100 radeon_ring_write(ring, 101 ((6 << MS_X3_SHIFT) | 102 (6 << MS_Y3_SHIFT) | 103 (6 << MS_X4_SHIFT) | 104 (6 << MS_Y4_SHIFT) | 105 (6 << MS_X5_SHIFT) | 106 (6 << MS_Y5_SHIFT) | 107 (6 << MSBD1_SHIFT))); 108 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); 109 radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); 110 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); 111 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); 112 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); 113 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); 114 radeon_ring_write(ring, PACKET0(0x20C8, 0)); 115 radeon_ring_write(ring, 0); 116 radeon_ring_unlock_commit(rdev, ring, false); 117} 118 119int rv515_mc_wait_for_idle(struct radeon_device *rdev) 120{ 121 unsigned i; 122 uint32_t tmp; 123 124 for (i = 0; i < rdev->usec_timeout; i++) { 125 /* read MC_STATUS */ 126 tmp = RREG32_MC(MC_STATUS); 127 if (tmp & MC_STATUS_IDLE) { 128 return 0; 129 } 130 udelay(1); 131 } 132 return -1; 133} 134 135void rv515_vga_render_disable(struct radeon_device *rdev) 136{ 137 WREG32(R_000300_VGA_RENDER_CONTROL, 138 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 139} 140 141static void rv515_gpu_init(struct radeon_device *rdev) 142{ 143 unsigned pipe_select_current, gb_pipe_select, tmp; 144 145 if (r100_gui_wait_for_idle(rdev)) { 146 pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n"); 147 } 148 rv515_vga_render_disable(rdev); 149 r420_pipes_init(rdev); 150 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 151 tmp = RREG32(R300_DST_PIPE_CONFIG); 152 pipe_select_current = (tmp >> 2) & 3; 153 tmp = (1 << pipe_select_current) | 154 (((gb_pipe_select >> 8) & 0xF) << 4); 155 WREG32_PLL(0x000D, tmp); 156 if (r100_gui_wait_for_idle(rdev)) { 157 pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n"); 158 } 159 if (rv515_mc_wait_for_idle(rdev)) { 160 pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n"); 161 } 162} 163 164static void rv515_vram_get_type(struct radeon_device *rdev) 165{ 166 uint32_t tmp; 167 168 rdev->mc.vram_width = 128; 169 rdev->mc.vram_is_ddr = true; 170 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; 171 switch (tmp) { 172 case 0: 173 rdev->mc.vram_width = 64; 174 break; 175 case 1: 176 rdev->mc.vram_width = 128; 177 break; 178 default: 179 rdev->mc.vram_width = 128; 180 break; 181 } 182} 183 184static void rv515_mc_init(struct radeon_device *rdev) 185{ 186 187 rv515_vram_get_type(rdev); 188 r100_vram_init_sizes(rdev); 189 radeon_vram_location(rdev, &rdev->mc, 0); 190 rdev->mc.gtt_base_align = 0; 191 if (!(rdev->flags & RADEON_IS_AGP)) 192 radeon_gtt_location(rdev, &rdev->mc); 193 radeon_update_bandwidth_info(rdev); 194} 195 196uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) 197{ 198 unsigned long flags; 199 uint32_t r; 200 201 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 202 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); 203 r = RREG32(MC_IND_DATA); 204 WREG32(MC_IND_INDEX, 0); 205 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 206 207 return r; 208} 209 210void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 211{ 212 unsigned long flags; 213 214 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 215 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); 216 WREG32(MC_IND_DATA, (v)); 217 WREG32(MC_IND_INDEX, 0); 218 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 219} 220 221#if defined(CONFIG_DEBUG_FS) 222static int rv515_debugfs_pipes_info_show(struct seq_file *m, void *unused) 223{ 224 struct radeon_device *rdev = m->private; 225 uint32_t tmp; 226 227 tmp = RREG32(GB_PIPE_SELECT); 228 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 229 tmp = RREG32(SU_REG_DEST); 230 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); 231 tmp = RREG32(GB_TILE_CONFIG); 232 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 233 tmp = RREG32(DST_PIPE_CONFIG); 234 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 235 return 0; 236} 237 238static int rv515_debugfs_ga_info_show(struct seq_file *m, void *unused) 239{ 240 struct radeon_device *rdev = m->private; 241 uint32_t tmp; 242 243 tmp = RREG32(0x2140); 244 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); 245 radeon_asic_reset(rdev); 246 tmp = RREG32(0x425C); 247 seq_printf(m, "GA_IDLE 0x%08x\n", tmp); 248 return 0; 249} 250 251DEFINE_SHOW_ATTRIBUTE(rv515_debugfs_pipes_info); 252DEFINE_SHOW_ATTRIBUTE(rv515_debugfs_ga_info); 253#endif 254 255void rv515_debugfs(struct radeon_device *rdev) 256{ 257#if defined(CONFIG_DEBUG_FS) 258 struct dentry *root = rdev->ddev->primary->debugfs_root; 259 260 debugfs_create_file("rv515_pipes_info", 0444, root, rdev, 261 &rv515_debugfs_pipes_info_fops); 262 debugfs_create_file("rv515_ga_info", 0444, root, rdev, 263 &rv515_debugfs_ga_info_fops); 264#endif 265 r100_debugfs_rbbm_init(rdev); 266} 267 268void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 269{ 270 u32 crtc_enabled, tmp, frame_count, blackout; 271 int i, j; 272 273 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); 274 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); 275 276 /* disable VGA render */ 277 WREG32(R_000300_VGA_RENDER_CONTROL, 0); 278 /* blank the display controllers */ 279 for (i = 0; i < rdev->num_crtc; i++) { 280 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; 281 if (crtc_enabled) { 282 save->crtc_enabled[i] = true; 283 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 284 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { 285 radeon_wait_for_vblank(rdev, i); 286 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 287 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 288 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 289 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 290 } 291 /* wait for the next frame */ 292 frame_count = radeon_get_vblank_counter(rdev, i); 293 for (j = 0; j < rdev->usec_timeout; j++) { 294 if (radeon_get_vblank_counter(rdev, i) != frame_count) 295 break; 296 udelay(1); 297 } 298 299 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 300 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 301 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 302 tmp &= ~AVIVO_CRTC_EN; 303 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 304 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 305 save->crtc_enabled[i] = false; 306 /* ***** */ 307 } else { 308 save->crtc_enabled[i] = false; 309 } 310 } 311 312 radeon_mc_wait_for_idle(rdev); 313 314 if (rdev->family >= CHIP_R600) { 315 if (rdev->family >= CHIP_RV770) 316 blackout = RREG32(R700_MC_CITF_CNTL); 317 else 318 blackout = RREG32(R600_CITF_CNTL); 319 if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) { 320 /* Block CPU access */ 321 WREG32(R600_BIF_FB_EN, 0); 322 /* blackout the MC */ 323 blackout |= R600_BLACKOUT_MASK; 324 if (rdev->family >= CHIP_RV770) 325 WREG32(R700_MC_CITF_CNTL, blackout); 326 else 327 WREG32(R600_CITF_CNTL, blackout); 328 } 329 } 330 /* wait for the MC to settle */ 331 udelay(100); 332 333 /* lock double buffered regs */ 334 for (i = 0; i < rdev->num_crtc; i++) { 335 if (save->crtc_enabled[i]) { 336 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 337 if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) { 338 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 339 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); 340 } 341 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); 342 if (!(tmp & 1)) { 343 tmp |= 1; 344 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 345 } 346 } 347 } 348} 349 350void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 351{ 352 u32 tmp, frame_count; 353 int i, j; 354 355 /* update crtc base addresses */ 356 for (i = 0; i < rdev->num_crtc; i++) { 357 if (rdev->family >= CHIP_RV770) { 358 if (i == 0) { 359 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 360 upper_32_bits(rdev->mc.vram_start)); 361 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 362 upper_32_bits(rdev->mc.vram_start)); 363 } else { 364 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 365 upper_32_bits(rdev->mc.vram_start)); 366 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 367 upper_32_bits(rdev->mc.vram_start)); 368 } 369 } 370 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 371 (u32)rdev->mc.vram_start); 372 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 373 (u32)rdev->mc.vram_start); 374 } 375 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 376 377 /* unlock regs and wait for update */ 378 for (i = 0; i < rdev->num_crtc; i++) { 379 if (save->crtc_enabled[i]) { 380 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); 381 if ((tmp & 0x7) != 3) { 382 tmp &= ~0x7; 383 tmp |= 0x3; 384 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); 385 } 386 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 387 if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) { 388 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 389 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); 390 } 391 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); 392 if (tmp & 1) { 393 tmp &= ~1; 394 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 395 } 396 for (j = 0; j < rdev->usec_timeout; j++) { 397 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 398 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0) 399 break; 400 udelay(1); 401 } 402 } 403 } 404 405 if (rdev->family >= CHIP_R600) { 406 /* unblackout the MC */ 407 if (rdev->family >= CHIP_RV770) 408 tmp = RREG32(R700_MC_CITF_CNTL); 409 else 410 tmp = RREG32(R600_CITF_CNTL); 411 tmp &= ~R600_BLACKOUT_MASK; 412 if (rdev->family >= CHIP_RV770) 413 WREG32(R700_MC_CITF_CNTL, tmp); 414 else 415 WREG32(R600_CITF_CNTL, tmp); 416 /* allow CPU access */ 417 WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN); 418 } 419 420 for (i = 0; i < rdev->num_crtc; i++) { 421 if (save->crtc_enabled[i]) { 422 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 423 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 424 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 425 /* wait for the next frame */ 426 frame_count = radeon_get_vblank_counter(rdev, i); 427 for (j = 0; j < rdev->usec_timeout; j++) { 428 if (radeon_get_vblank_counter(rdev, i) != frame_count) 429 break; 430 udelay(1); 431 } 432 } 433 } 434 /* Unlock vga access */ 435 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 436 mdelay(1); 437 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 438} 439 440static void rv515_mc_program(struct radeon_device *rdev) 441{ 442 struct rv515_mc_save save; 443 444 /* Stops all mc clients */ 445 rv515_mc_stop(rdev, &save); 446 447 /* Wait for mc idle */ 448 if (rv515_mc_wait_for_idle(rdev)) 449 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 450 /* Write VRAM size in case we are limiting it */ 451 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 452 /* Program MC, should be a 32bits limited address space */ 453 WREG32_MC(R_000001_MC_FB_LOCATION, 454 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | 455 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); 456 WREG32(R_000134_HDP_FB_LOCATION, 457 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 458 if (rdev->flags & RADEON_IS_AGP) { 459 WREG32_MC(R_000002_MC_AGP_LOCATION, 460 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | 461 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 462 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 463 WREG32_MC(R_000004_MC_AGP_BASE_2, 464 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 465 } else { 466 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); 467 WREG32_MC(R_000003_MC_AGP_BASE, 0); 468 WREG32_MC(R_000004_MC_AGP_BASE_2, 0); 469 } 470 471 rv515_mc_resume(rdev, &save); 472} 473 474void rv515_clock_startup(struct radeon_device *rdev) 475{ 476 if (radeon_dynclks != -1 && radeon_dynclks) 477 radeon_atom_set_clock_gating(rdev, 1); 478 /* We need to force on some of the block */ 479 WREG32_PLL(R_00000F_CP_DYN_CNTL, 480 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); 481 WREG32_PLL(R_000011_E2_DYN_CNTL, 482 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); 483 WREG32_PLL(R_000013_IDCT_DYN_CNTL, 484 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); 485} 486 487static int rv515_startup(struct radeon_device *rdev) 488{ 489 int r; 490 491 rv515_mc_program(rdev); 492 /* Resume clock */ 493 rv515_clock_startup(rdev); 494 /* Initialize GPU configuration (# pipes, ...) */ 495 rv515_gpu_init(rdev); 496 /* Initialize GART (initialize after TTM so we can allocate 497 * memory through TTM but finalize after TTM) */ 498 if (rdev->flags & RADEON_IS_PCIE) { 499 r = rv370_pcie_gart_enable(rdev); 500 if (r) 501 return r; 502 } 503 504 /* allocate wb buffer */ 505 r = radeon_wb_init(rdev); 506 if (r) 507 return r; 508 509 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 510 if (r) { 511 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 512 return r; 513 } 514 515 /* Enable IRQ */ 516 if (!rdev->irq.installed) { 517 r = radeon_irq_kms_init(rdev); 518 if (r) 519 return r; 520 } 521 522 rs600_irq_set(rdev); 523 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 524 /* 1M ring buffer */ 525 r = r100_cp_init(rdev, 1024 * 1024); 526 if (r) { 527 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 528 return r; 529 } 530 531 r = radeon_ib_pool_init(rdev); 532 if (r) { 533 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 534 return r; 535 } 536 537 return 0; 538} 539 540int rv515_resume(struct radeon_device *rdev) 541{ 542 int r; 543 544 /* Make sur GART are not working */ 545 if (rdev->flags & RADEON_IS_PCIE) 546 rv370_pcie_gart_disable(rdev); 547 /* Resume clock before doing reset */ 548 rv515_clock_startup(rdev); 549 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 550 if (radeon_asic_reset(rdev)) { 551 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 552 RREG32(R_000E40_RBBM_STATUS), 553 RREG32(R_0007C0_CP_STAT)); 554 } 555 /* post */ 556 atom_asic_init(rdev->mode_info.atom_context); 557 /* Resume clock after posting */ 558 rv515_clock_startup(rdev); 559 /* Initialize surface registers */ 560 radeon_surface_init(rdev); 561 562 rdev->accel_working = true; 563 r = rv515_startup(rdev); 564 if (r) { 565 rdev->accel_working = false; 566 } 567 return r; 568} 569 570int rv515_suspend(struct radeon_device *rdev) 571{ 572 radeon_pm_suspend(rdev); 573 r100_cp_disable(rdev); 574 radeon_wb_disable(rdev); 575 rs600_irq_disable(rdev); 576 if (rdev->flags & RADEON_IS_PCIE) 577 rv370_pcie_gart_disable(rdev); 578 return 0; 579} 580 581void rv515_set_safe_registers(struct radeon_device *rdev) 582{ 583 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; 584 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); 585} 586 587void rv515_fini(struct radeon_device *rdev) 588{ 589 radeon_pm_fini(rdev); 590 r100_cp_fini(rdev); 591 radeon_wb_fini(rdev); 592 radeon_ib_pool_fini(rdev); 593 radeon_gem_fini(rdev); 594 rv370_pcie_gart_fini(rdev); 595 radeon_agp_fini(rdev); 596 radeon_irq_kms_fini(rdev); 597 radeon_fence_driver_fini(rdev); 598 radeon_bo_fini(rdev); 599 radeon_atombios_fini(rdev); 600 kfree(rdev->bios); 601 rdev->bios = NULL; 602} 603 604int rv515_init(struct radeon_device *rdev) 605{ 606 int r; 607 608 /* Initialize scratch registers */ 609 radeon_scratch_init(rdev); 610 /* Initialize surface registers */ 611 radeon_surface_init(rdev); 612 /* TODO: disable VGA need to use VGA request */ 613 /* restore some register to sane defaults */ 614 r100_restore_sanity(rdev); 615 /* BIOS*/ 616 if (!radeon_get_bios(rdev)) { 617 if (ASIC_IS_AVIVO(rdev)) 618 return -EINVAL; 619 } 620 if (rdev->is_atom_bios) { 621 r = radeon_atombios_init(rdev); 622 if (r) 623 return r; 624 } else { 625 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 626 return -EINVAL; 627 } 628 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 629 if (radeon_asic_reset(rdev)) { 630 dev_warn(rdev->dev, 631 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 632 RREG32(R_000E40_RBBM_STATUS), 633 RREG32(R_0007C0_CP_STAT)); 634 } 635 /* check if cards are posted or not */ 636 if (radeon_boot_test_post_card(rdev) == false) 637 return -EINVAL; 638 /* Initialize clocks */ 639 radeon_get_clock_info(rdev->ddev); 640 /* initialize AGP */ 641 if (rdev->flags & RADEON_IS_AGP) { 642 r = radeon_agp_init(rdev); 643 if (r) { 644 radeon_agp_disable(rdev); 645 } 646 } 647 /* initialize memory controller */ 648 rv515_mc_init(rdev); 649 rv515_debugfs(rdev); 650 /* Fence driver */ 651 radeon_fence_driver_init(rdev); 652 /* Memory manager */ 653 r = radeon_bo_init(rdev); 654 if (r) 655 return r; 656 r = rv370_pcie_gart_init(rdev); 657 if (r) 658 return r; 659 rv515_set_safe_registers(rdev); 660 661 /* Initialize power management */ 662 radeon_pm_init(rdev); 663 664 rdev->accel_working = true; 665 r = rv515_startup(rdev); 666 if (r) { 667 /* Somethings want wront with the accel init stop accel */ 668 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 669 r100_cp_fini(rdev); 670 radeon_wb_fini(rdev); 671 radeon_ib_pool_fini(rdev); 672 radeon_irq_kms_fini(rdev); 673 rv370_pcie_gart_fini(rdev); 674 radeon_agp_fini(rdev); 675 rdev->accel_working = false; 676 } 677 return 0; 678} 679 680void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) 681{ 682 int index_reg = 0x6578 + crtc->crtc_offset; 683 int data_reg = 0x657c + crtc->crtc_offset; 684 685 WREG32(0x659C + crtc->crtc_offset, 0x0); 686 WREG32(0x6594 + crtc->crtc_offset, 0x705); 687 WREG32(0x65A4 + crtc->crtc_offset, 0x10001); 688 WREG32(0x65D8 + crtc->crtc_offset, 0x0); 689 WREG32(0x65B0 + crtc->crtc_offset, 0x0); 690 WREG32(0x65C0 + crtc->crtc_offset, 0x0); 691 WREG32(0x65D4 + crtc->crtc_offset, 0x0); 692 WREG32(index_reg, 0x0); 693 WREG32(data_reg, 0x841880A8); 694 WREG32(index_reg, 0x1); 695 WREG32(data_reg, 0x84208680); 696 WREG32(index_reg, 0x2); 697 WREG32(data_reg, 0xBFF880B0); 698 WREG32(index_reg, 0x100); 699 WREG32(data_reg, 0x83D88088); 700 WREG32(index_reg, 0x101); 701 WREG32(data_reg, 0x84608680); 702 WREG32(index_reg, 0x102); 703 WREG32(data_reg, 0xBFF080D0); 704 WREG32(index_reg, 0x200); 705 WREG32(data_reg, 0x83988068); 706 WREG32(index_reg, 0x201); 707 WREG32(data_reg, 0x84A08680); 708 WREG32(index_reg, 0x202); 709 WREG32(data_reg, 0xBFF080F8); 710 WREG32(index_reg, 0x300); 711 WREG32(data_reg, 0x83588058); 712 WREG32(index_reg, 0x301); 713 WREG32(data_reg, 0x84E08660); 714 WREG32(index_reg, 0x302); 715 WREG32(data_reg, 0xBFF88120); 716 WREG32(index_reg, 0x400); 717 WREG32(data_reg, 0x83188040); 718 WREG32(index_reg, 0x401); 719 WREG32(data_reg, 0x85008660); 720 WREG32(index_reg, 0x402); 721 WREG32(data_reg, 0xBFF88150); 722 WREG32(index_reg, 0x500); 723 WREG32(data_reg, 0x82D88030); 724 WREG32(index_reg, 0x501); 725 WREG32(data_reg, 0x85408640); 726 WREG32(index_reg, 0x502); 727 WREG32(data_reg, 0xBFF88180); 728 WREG32(index_reg, 0x600); 729 WREG32(data_reg, 0x82A08018); 730 WREG32(index_reg, 0x601); 731 WREG32(data_reg, 0x85808620); 732 WREG32(index_reg, 0x602); 733 WREG32(data_reg, 0xBFF081B8); 734 WREG32(index_reg, 0x700); 735 WREG32(data_reg, 0x82608010); 736 WREG32(index_reg, 0x701); 737 WREG32(data_reg, 0x85A08600); 738 WREG32(index_reg, 0x702); 739 WREG32(data_reg, 0x800081F0); 740 WREG32(index_reg, 0x800); 741 WREG32(data_reg, 0x8228BFF8); 742 WREG32(index_reg, 0x801); 743 WREG32(data_reg, 0x85E085E0); 744 WREG32(index_reg, 0x802); 745 WREG32(data_reg, 0xBFF88228); 746 WREG32(index_reg, 0x10000); 747 WREG32(data_reg, 0x82A8BF00); 748 WREG32(index_reg, 0x10001); 749 WREG32(data_reg, 0x82A08CC0); 750 WREG32(index_reg, 0x10002); 751 WREG32(data_reg, 0x8008BEF8); 752 WREG32(index_reg, 0x10100); 753 WREG32(data_reg, 0x81F0BF28); 754 WREG32(index_reg, 0x10101); 755 WREG32(data_reg, 0x83608CA0); 756 WREG32(index_reg, 0x10102); 757 WREG32(data_reg, 0x8018BED0); 758 WREG32(index_reg, 0x10200); 759 WREG32(data_reg, 0x8148BF38); 760 WREG32(index_reg, 0x10201); 761 WREG32(data_reg, 0x84408C80); 762 WREG32(index_reg, 0x10202); 763 WREG32(data_reg, 0x8008BEB8); 764 WREG32(index_reg, 0x10300); 765 WREG32(data_reg, 0x80B0BF78); 766 WREG32(index_reg, 0x10301); 767 WREG32(data_reg, 0x85008C20); 768 WREG32(index_reg, 0x10302); 769 WREG32(data_reg, 0x8020BEA0); 770 WREG32(index_reg, 0x10400); 771 WREG32(data_reg, 0x8028BF90); 772 WREG32(index_reg, 0x10401); 773 WREG32(data_reg, 0x85E08BC0); 774 WREG32(index_reg, 0x10402); 775 WREG32(data_reg, 0x8018BE90); 776 WREG32(index_reg, 0x10500); 777 WREG32(data_reg, 0xBFB8BFB0); 778 WREG32(index_reg, 0x10501); 779 WREG32(data_reg, 0x86C08B40); 780 WREG32(index_reg, 0x10502); 781 WREG32(data_reg, 0x8010BE90); 782 WREG32(index_reg, 0x10600); 783 WREG32(data_reg, 0xBF58BFC8); 784 WREG32(index_reg, 0x10601); 785 WREG32(data_reg, 0x87A08AA0); 786 WREG32(index_reg, 0x10602); 787 WREG32(data_reg, 0x8010BE98); 788 WREG32(index_reg, 0x10700); 789 WREG32(data_reg, 0xBF10BFF0); 790 WREG32(index_reg, 0x10701); 791 WREG32(data_reg, 0x886089E0); 792 WREG32(index_reg, 0x10702); 793 WREG32(data_reg, 0x8018BEB0); 794 WREG32(index_reg, 0x10800); 795 WREG32(data_reg, 0xBED8BFE8); 796 WREG32(index_reg, 0x10801); 797 WREG32(data_reg, 0x89408940); 798 WREG32(index_reg, 0x10802); 799 WREG32(data_reg, 0xBFE8BED8); 800 WREG32(index_reg, 0x20000); 801 WREG32(data_reg, 0x80008000); 802 WREG32(index_reg, 0x20001); 803 WREG32(data_reg, 0x90008000); 804 WREG32(index_reg, 0x20002); 805 WREG32(data_reg, 0x80008000); 806 WREG32(index_reg, 0x20003); 807 WREG32(data_reg, 0x80008000); 808 WREG32(index_reg, 0x20100); 809 WREG32(data_reg, 0x80108000); 810 WREG32(index_reg, 0x20101); 811 WREG32(data_reg, 0x8FE0BF70); 812 WREG32(index_reg, 0x20102); 813 WREG32(data_reg, 0xBFE880C0); 814 WREG32(index_reg, 0x20103); 815 WREG32(data_reg, 0x80008000); 816 WREG32(index_reg, 0x20200); 817 WREG32(data_reg, 0x8018BFF8); 818 WREG32(index_reg, 0x20201); 819 WREG32(data_reg, 0x8F80BF08); 820 WREG32(index_reg, 0x20202); 821 WREG32(data_reg, 0xBFD081A0); 822 WREG32(index_reg, 0x20203); 823 WREG32(data_reg, 0xBFF88000); 824 WREG32(index_reg, 0x20300); 825 WREG32(data_reg, 0x80188000); 826 WREG32(index_reg, 0x20301); 827 WREG32(data_reg, 0x8EE0BEC0); 828 WREG32(index_reg, 0x20302); 829 WREG32(data_reg, 0xBFB082A0); 830 WREG32(index_reg, 0x20303); 831 WREG32(data_reg, 0x80008000); 832 WREG32(index_reg, 0x20400); 833 WREG32(data_reg, 0x80188000); 834 WREG32(index_reg, 0x20401); 835 WREG32(data_reg, 0x8E00BEA0); 836 WREG32(index_reg, 0x20402); 837 WREG32(data_reg, 0xBF8883C0); 838 WREG32(index_reg, 0x20403); 839 WREG32(data_reg, 0x80008000); 840 WREG32(index_reg, 0x20500); 841 WREG32(data_reg, 0x80188000); 842 WREG32(index_reg, 0x20501); 843 WREG32(data_reg, 0x8D00BE90); 844 WREG32(index_reg, 0x20502); 845 WREG32(data_reg, 0xBF588500); 846 WREG32(index_reg, 0x20503); 847 WREG32(data_reg, 0x80008008); 848 WREG32(index_reg, 0x20600); 849 WREG32(data_reg, 0x80188000); 850 WREG32(index_reg, 0x20601); 851 WREG32(data_reg, 0x8BC0BE98); 852 WREG32(index_reg, 0x20602); 853 WREG32(data_reg, 0xBF308660); 854 WREG32(index_reg, 0x20603); 855 WREG32(data_reg, 0x80008008); 856 WREG32(index_reg, 0x20700); 857 WREG32(data_reg, 0x80108000); 858 WREG32(index_reg, 0x20701); 859 WREG32(data_reg, 0x8A80BEB0); 860 WREG32(index_reg, 0x20702); 861 WREG32(data_reg, 0xBF0087C0); 862 WREG32(index_reg, 0x20703); 863 WREG32(data_reg, 0x80008008); 864 WREG32(index_reg, 0x20800); 865 WREG32(data_reg, 0x80108000); 866 WREG32(index_reg, 0x20801); 867 WREG32(data_reg, 0x8920BED0); 868 WREG32(index_reg, 0x20802); 869 WREG32(data_reg, 0xBED08920); 870 WREG32(index_reg, 0x20803); 871 WREG32(data_reg, 0x80008010); 872 WREG32(index_reg, 0x30000); 873 WREG32(data_reg, 0x90008000); 874 WREG32(index_reg, 0x30001); 875 WREG32(data_reg, 0x80008000); 876 WREG32(index_reg, 0x30100); 877 WREG32(data_reg, 0x8FE0BF90); 878 WREG32(index_reg, 0x30101); 879 WREG32(data_reg, 0xBFF880A0); 880 WREG32(index_reg, 0x30200); 881 WREG32(data_reg, 0x8F60BF40); 882 WREG32(index_reg, 0x30201); 883 WREG32(data_reg, 0xBFE88180); 884 WREG32(index_reg, 0x30300); 885 WREG32(data_reg, 0x8EC0BF00); 886 WREG32(index_reg, 0x30301); 887 WREG32(data_reg, 0xBFC88280); 888 WREG32(index_reg, 0x30400); 889 WREG32(data_reg, 0x8DE0BEE0); 890 WREG32(index_reg, 0x30401); 891 WREG32(data_reg, 0xBFA083A0); 892 WREG32(index_reg, 0x30500); 893 WREG32(data_reg, 0x8CE0BED0); 894 WREG32(index_reg, 0x30501); 895 WREG32(data_reg, 0xBF7884E0); 896 WREG32(index_reg, 0x30600); 897 WREG32(data_reg, 0x8BA0BED8); 898 WREG32(index_reg, 0x30601); 899 WREG32(data_reg, 0xBF508640); 900 WREG32(index_reg, 0x30700); 901 WREG32(data_reg, 0x8A60BEE8); 902 WREG32(index_reg, 0x30701); 903 WREG32(data_reg, 0xBF2087A0); 904 WREG32(index_reg, 0x30800); 905 WREG32(data_reg, 0x8900BF00); 906 WREG32(index_reg, 0x30801); 907 WREG32(data_reg, 0xBF008900); 908} 909 910struct rv515_watermark { 911 u32 lb_request_fifo_depth; 912 fixed20_12 num_line_pair; 913 fixed20_12 estimated_width; 914 fixed20_12 worst_case_latency; 915 fixed20_12 consumption_rate; 916 fixed20_12 active_time; 917 fixed20_12 dbpp; 918 fixed20_12 priority_mark_max; 919 fixed20_12 priority_mark; 920 fixed20_12 sclk; 921}; 922 923static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, 924 struct radeon_crtc *crtc, 925 struct rv515_watermark *wm, 926 bool low) 927{ 928 struct drm_display_mode *mode = &crtc->base.mode; 929 fixed20_12 a, b, c; 930 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 931 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 932 fixed20_12 sclk; 933 u32 selected_sclk; 934 935 if (!crtc->base.enabled) { 936 /* FIXME: wouldn't it better to set priority mark to maximum */ 937 wm->lb_request_fifo_depth = 4; 938 return; 939 } 940 941 /* rv6xx, rv7xx */ 942 if ((rdev->family >= CHIP_RV610) && 943 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 944 selected_sclk = radeon_dpm_get_sclk(rdev, low); 945 else 946 selected_sclk = rdev->pm.current_sclk; 947 948 /* sclk in Mhz */ 949 a.full = dfixed_const(100); 950 sclk.full = dfixed_const(selected_sclk); 951 sclk.full = dfixed_div(sclk, a); 952 953 if (crtc->vsc.full > dfixed_const(2)) 954 wm->num_line_pair.full = dfixed_const(2); 955 else 956 wm->num_line_pair.full = dfixed_const(1); 957 958 b.full = dfixed_const(mode->crtc_hdisplay); 959 c.full = dfixed_const(256); 960 a.full = dfixed_div(b, c); 961 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 962 request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 963 if (a.full < dfixed_const(4)) { 964 wm->lb_request_fifo_depth = 4; 965 } else { 966 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 967 } 968 969 /* Determine consumption rate 970 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 971 * vtaps = number of vertical taps, 972 * vsc = vertical scaling ratio, defined as source/destination 973 * hsc = horizontal scaling ration, defined as source/destination 974 */ 975 a.full = dfixed_const(mode->clock); 976 b.full = dfixed_const(1000); 977 a.full = dfixed_div(a, b); 978 pclk.full = dfixed_div(b, a); 979 if (crtc->rmx_type != RMX_OFF) { 980 b.full = dfixed_const(2); 981 if (crtc->vsc.full > b.full) 982 b.full = crtc->vsc.full; 983 b.full = dfixed_mul(b, crtc->hsc); 984 c.full = dfixed_const(2); 985 b.full = dfixed_div(b, c); 986 consumption_time.full = dfixed_div(pclk, b); 987 } else { 988 consumption_time.full = pclk.full; 989 } 990 a.full = dfixed_const(1); 991 wm->consumption_rate.full = dfixed_div(a, consumption_time); 992 993 994 /* Determine line time 995 * LineTime = total time for one line of displayhtotal 996 * LineTime = total number of horizontal pixels 997 * pclk = pixel clock period(ns) 998 */ 999 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 1000 line_time.full = dfixed_mul(a, pclk); 1001 1002 /* Determine active time 1003 * ActiveTime = time of active region of display within one line, 1004 * hactive = total number of horizontal active pixels 1005 * htotal = total number of horizontal pixels 1006 */ 1007 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 1008 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 1009 wm->active_time.full = dfixed_mul(line_time, b); 1010 wm->active_time.full = dfixed_div(wm->active_time, a); 1011 1012 /* Determine chunk time 1013 * ChunkTime = the time it takes the DCP to send one chunk of data 1014 * to the LB which consists of pipeline delay and inter chunk gap 1015 * sclk = system clock(Mhz) 1016 */ 1017 a.full = dfixed_const(600 * 1000); 1018 chunk_time.full = dfixed_div(a, sclk); 1019 read_delay_latency.full = dfixed_const(1000); 1020 1021 /* Determine the worst case latency 1022 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 1023 * WorstCaseLatency = worst case time from urgent to when the MC starts 1024 * to return data 1025 * READ_DELAY_IDLE_MAX = constant of 1us 1026 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 1027 * which consists of pipeline delay and inter chunk gap 1028 */ 1029 if (dfixed_trunc(wm->num_line_pair) > 1) { 1030 a.full = dfixed_const(3); 1031 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 1032 wm->worst_case_latency.full += read_delay_latency.full; 1033 } else { 1034 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; 1035 } 1036 1037 /* Determine the tolerable latency 1038 * TolerableLatency = Any given request has only 1 line time 1039 * for the data to be returned 1040 * LBRequestFifoDepth = Number of chunk requests the LB can 1041 * put into the request FIFO for a display 1042 * LineTime = total time for one line of display 1043 * ChunkTime = the time it takes the DCP to send one chunk 1044 * of data to the LB which consists of 1045 * pipeline delay and inter chunk gap 1046 */ 1047 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 1048 tolerable_latency.full = line_time.full; 1049 } else { 1050 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 1051 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 1052 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 1053 tolerable_latency.full = line_time.full - tolerable_latency.full; 1054 } 1055 /* We assume worst case 32bits (4 bytes) */ 1056 wm->dbpp.full = dfixed_const(2 * 16); 1057 1058 /* Determine the maximum priority mark 1059 * width = viewport width in pixels 1060 */ 1061 a.full = dfixed_const(16); 1062 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 1063 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 1064 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 1065 1066 /* Determine estimated width */ 1067 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 1068 estimated_width.full = dfixed_div(estimated_width, consumption_time); 1069 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 1070 wm->priority_mark.full = wm->priority_mark_max.full; 1071 } else { 1072 a.full = dfixed_const(16); 1073 wm->priority_mark.full = dfixed_div(estimated_width, a); 1074 wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 1075 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 1076 } 1077} 1078 1079static void rv515_compute_mode_priority(struct radeon_device *rdev, 1080 struct rv515_watermark *wm0, 1081 struct rv515_watermark *wm1, 1082 struct drm_display_mode *mode0, 1083 struct drm_display_mode *mode1, 1084 u32 *d1mode_priority_a_cnt, 1085 u32 *d2mode_priority_a_cnt) 1086{ 1087 fixed20_12 priority_mark02, priority_mark12, fill_rate; 1088 fixed20_12 a, b; 1089 1090 *d1mode_priority_a_cnt = MODE_PRIORITY_OFF; 1091 *d2mode_priority_a_cnt = MODE_PRIORITY_OFF; 1092 1093 if (mode0 && mode1) { 1094 if (dfixed_trunc(wm0->dbpp) > 64) 1095 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); 1096 else 1097 a.full = wm0->num_line_pair.full; 1098 if (dfixed_trunc(wm1->dbpp) > 64) 1099 b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); 1100 else 1101 b.full = wm1->num_line_pair.full; 1102 a.full += b.full; 1103 fill_rate.full = dfixed_div(wm0->sclk, a); 1104 if (wm0->consumption_rate.full > fill_rate.full) { 1105 b.full = wm0->consumption_rate.full - fill_rate.full; 1106 b.full = dfixed_mul(b, wm0->active_time); 1107 a.full = dfixed_const(16); 1108 b.full = dfixed_div(b, a); 1109 a.full = dfixed_mul(wm0->worst_case_latency, 1110 wm0->consumption_rate); 1111 priority_mark02.full = a.full + b.full; 1112 } else { 1113 a.full = dfixed_mul(wm0->worst_case_latency, 1114 wm0->consumption_rate); 1115 b.full = dfixed_const(16 * 1000); 1116 priority_mark02.full = dfixed_div(a, b); 1117 } 1118 if (wm1->consumption_rate.full > fill_rate.full) { 1119 b.full = wm1->consumption_rate.full - fill_rate.full; 1120 b.full = dfixed_mul(b, wm1->active_time); 1121 a.full = dfixed_const(16); 1122 b.full = dfixed_div(b, a); 1123 a.full = dfixed_mul(wm1->worst_case_latency, 1124 wm1->consumption_rate); 1125 priority_mark12.full = a.full + b.full; 1126 } else { 1127 a.full = dfixed_mul(wm1->worst_case_latency, 1128 wm1->consumption_rate); 1129 b.full = dfixed_const(16 * 1000); 1130 priority_mark12.full = dfixed_div(a, b); 1131 } 1132 if (wm0->priority_mark.full > priority_mark02.full) 1133 priority_mark02.full = wm0->priority_mark.full; 1134 if (wm0->priority_mark_max.full > priority_mark02.full) 1135 priority_mark02.full = wm0->priority_mark_max.full; 1136 if (wm1->priority_mark.full > priority_mark12.full) 1137 priority_mark12.full = wm1->priority_mark.full; 1138 if (wm1->priority_mark_max.full > priority_mark12.full) 1139 priority_mark12.full = wm1->priority_mark_max.full; 1140 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1141 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1142 if (rdev->disp_priority == 2) { 1143 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1144 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1145 } 1146 } else if (mode0) { 1147 if (dfixed_trunc(wm0->dbpp) > 64) 1148 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); 1149 else 1150 a.full = wm0->num_line_pair.full; 1151 fill_rate.full = dfixed_div(wm0->sclk, a); 1152 if (wm0->consumption_rate.full > fill_rate.full) { 1153 b.full = wm0->consumption_rate.full - fill_rate.full; 1154 b.full = dfixed_mul(b, wm0->active_time); 1155 a.full = dfixed_const(16); 1156 b.full = dfixed_div(b, a); 1157 a.full = dfixed_mul(wm0->worst_case_latency, 1158 wm0->consumption_rate); 1159 priority_mark02.full = a.full + b.full; 1160 } else { 1161 a.full = dfixed_mul(wm0->worst_case_latency, 1162 wm0->consumption_rate); 1163 b.full = dfixed_const(16); 1164 priority_mark02.full = dfixed_div(a, b); 1165 } 1166 if (wm0->priority_mark.full > priority_mark02.full) 1167 priority_mark02.full = wm0->priority_mark.full; 1168 if (wm0->priority_mark_max.full > priority_mark02.full) 1169 priority_mark02.full = wm0->priority_mark_max.full; 1170 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1171 if (rdev->disp_priority == 2) 1172 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1173 } else if (mode1) { 1174 if (dfixed_trunc(wm1->dbpp) > 64) 1175 a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); 1176 else 1177 a.full = wm1->num_line_pair.full; 1178 fill_rate.full = dfixed_div(wm1->sclk, a); 1179 if (wm1->consumption_rate.full > fill_rate.full) { 1180 b.full = wm1->consumption_rate.full - fill_rate.full; 1181 b.full = dfixed_mul(b, wm1->active_time); 1182 a.full = dfixed_const(16); 1183 b.full = dfixed_div(b, a); 1184 a.full = dfixed_mul(wm1->worst_case_latency, 1185 wm1->consumption_rate); 1186 priority_mark12.full = a.full + b.full; 1187 } else { 1188 a.full = dfixed_mul(wm1->worst_case_latency, 1189 wm1->consumption_rate); 1190 b.full = dfixed_const(16 * 1000); 1191 priority_mark12.full = dfixed_div(a, b); 1192 } 1193 if (wm1->priority_mark.full > priority_mark12.full) 1194 priority_mark12.full = wm1->priority_mark.full; 1195 if (wm1->priority_mark_max.full > priority_mark12.full) 1196 priority_mark12.full = wm1->priority_mark_max.full; 1197 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1198 if (rdev->disp_priority == 2) 1199 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1200 } 1201} 1202 1203void rv515_bandwidth_avivo_update(struct radeon_device *rdev) 1204{ 1205 struct drm_display_mode *mode0 = NULL; 1206 struct drm_display_mode *mode1 = NULL; 1207 struct rv515_watermark wm0_high, wm0_low; 1208 struct rv515_watermark wm1_high, wm1_low; 1209 u32 tmp; 1210 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; 1211 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; 1212 1213 if (rdev->mode_info.crtcs[0]->base.enabled) 1214 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1215 if (rdev->mode_info.crtcs[1]->base.enabled) 1216 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1217 rs690_line_buffer_adjust(rdev, mode0, mode1); 1218 1219 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); 1220 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); 1221 1222 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); 1223 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); 1224 1225 tmp = wm0_high.lb_request_fifo_depth; 1226 tmp |= wm1_high.lb_request_fifo_depth << 16; 1227 WREG32(LB_MAX_REQ_OUTSTANDING, tmp); 1228 1229 rv515_compute_mode_priority(rdev, 1230 &wm0_high, &wm1_high, 1231 mode0, mode1, 1232 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt); 1233 rv515_compute_mode_priority(rdev, 1234 &wm0_low, &wm1_low, 1235 mode0, mode1, 1236 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt); 1237 1238 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 1239 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); 1240 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 1241 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); 1242} 1243 1244void rv515_bandwidth_update(struct radeon_device *rdev) 1245{ 1246 uint32_t tmp; 1247 struct drm_display_mode *mode0 = NULL; 1248 struct drm_display_mode *mode1 = NULL; 1249 1250 if (!rdev->mode_info.mode_config_initialized) 1251 return; 1252 1253 radeon_update_display_priority(rdev); 1254 1255 if (rdev->mode_info.crtcs[0]->base.enabled) 1256 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1257 if (rdev->mode_info.crtcs[1]->base.enabled) 1258 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1259 /* 1260 * Set display0/1 priority up in the memory controller for 1261 * modes if the user specifies HIGH for displaypriority 1262 * option. 1263 */ 1264 if ((rdev->disp_priority == 2) && 1265 (rdev->family == CHIP_RV515)) { 1266 tmp = RREG32_MC(MC_MISC_LAT_TIMER); 1267 tmp &= ~MC_DISP1R_INIT_LAT_MASK; 1268 tmp &= ~MC_DISP0R_INIT_LAT_MASK; 1269 if (mode1) 1270 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); 1271 if (mode0) 1272 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); 1273 WREG32_MC(MC_MISC_LAT_TIMER, tmp); 1274 } 1275 rv515_bandwidth_avivo_update(rdev); 1276} 1277